Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises data lines and sub-pixel groups. The data lines are arranged along a first direction and extend along a second direction. Each sub-pixel group comprises a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. In a same sub-pixel group, a light-emitting area of the first color sub-pixel extends along a third direction, the second color sub-pixel and the third color sub-pixel are arranged along the third direction, and an included angle of 20-70 degrees is formed between the third direction and the second direction. In adjacent sub-pixel groups arranged along the second direction, the orthographic projection of a light-emitting area of at least one of the second color sub-pixel and the third color sub-pixel in one sub-pixel group overlaps with the orthographic projection of a light-emitting area of the first color sub-pixel in the other sub-pixel group on a straight line extending along a fourth direction. The relative positional relationships between light-emitting areas of sub-pixels in different sub-pixel groups are set while extension directions of light-emitting areas of first color sub-pixels are set, so that the image quality can be optimized.

Description

Array substrate and display device Technical Field

[0001] This disclosure relates to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are self-emissive devices. Unlike traditional light-emitting devices, they do not require a backlight. OLEDs are injection-type light-emitting devices and offer advantages such as rich colors, fast response time, and foldability. OLED display devices utilize a tandem structure, which improves the lifespan and brightness of the light-emitting device by adding at least one light-emitting layer and a charge-generating layer to the organic light-emitting element, while reducing power consumption. This meets users' requirements for power consumption and lifespan of display devices. Summary of the Invention

[0003] This disclosure provides an array substrate and a display device.

[0004] This disclosure provides an array substrate, comprising: a substrate and a plurality of data lines and a plurality of sub-pixel groups located on the substrate. The plurality of data lines are arranged along a first direction and extend along a second direction, the first direction intersecting the second direction; the plurality of sub-pixel groups are arranged in an array along the first and second directions, each sub-pixel group including at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. In the same sub-pixel group, at least the light-emitting area of ​​the first color sub-pixel extends along a third direction, the second color sub-pixel and the third color sub-pixel are arranged along the third direction, and the arrangement direction of the second color sub-pixel and the first color sub-pixel intersects the third direction, the angle between the third direction and the second direction being 20 to 70 degrees; in adjacent sub-pixel groups arranged along the second direction, the light-emitting area of ​​at least one of the second color sub-pixel and the third color sub-pixel in one sub-pixel group overlaps with the orthographic projection of the light-emitting area of ​​the first color sub-pixel in another sub-pixel group onto a straight line extending along a fourth direction, the fourth direction being perpendicular to the third direction.

[0005] For example, according to an embodiment of this disclosure, in the same sub-pixel group, the area of ​​the light-emitting region of the second color sub-pixel and the area of ​​the light-emitting region of the third color sub-pixel are both smaller than the area of ​​the light-emitting region of the first color sub-pixel; the light-emitting regions of the second color sub-pixel and the light-emitting regions of the third color sub-pixel both extend along the third direction.

[0006] For example, according to an embodiment of this disclosure, the array substrate further includes: a defining structure located at least between the light-emitting areas of two adjacent sub-pixels. The defining structure includes a first defining structure located between the light-emitting area of ​​at least one of the second color sub-pixel and the third color sub-pixel and the light-emitting area of ​​the first color sub-pixel, the first defining structure extending along the third direction.

[0007] For example, according to an embodiment of this disclosure, in the same sub-pixel group, the light-emitting area of ​​the first color sub-pixel includes a first side and a second side extending along the third direction, the length of the first side is greater than the length of the second side, and the first side is located between the second side and the light-emitting area of ​​the second color sub-pixel; the light-emitting area of ​​the first color sub-pixel also includes a third side extending along the second direction, and the light-emitting area of ​​one of the second color sub-pixel and the third color sub-pixel includes a fourth side extending along the second direction; the third side and the fourth side are adjacent to each other in two sub-pixel groups that are adjacent in the first direction.

[0008] For example, according to an embodiment of this disclosure, in adjacent sub-pixel groups arranged along the second direction, the center line of the light-emitting area of ​​the first color sub-pixel in one sub-pixel group extending along the third direction passes through the light-emitting areas of the second color sub-pixel and the third color sub-pixel in another sub-pixel group.

[0009] For example, according to an embodiment of this disclosure, in adjacent sub-pixel groups arranged along the first direction, the light-emitting area of ​​one of the second color sub-pixels and the third color sub-pixels in one sub-pixel group overlaps with the orthographic projection of the light-emitting area of ​​the first color sub-pixel in another sub-pixel group on a straight line extending along the third direction.

[0010] For example, according to an embodiment of this disclosure, each sub-pixel in the at least part of the sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked together. The first electrode is located between the light-emitting functional layer and the substrate, and an insulating layer is disposed between the first electrode and the pixel circuit. The first electrode is electrically connected to the pixel circuit through a via in the insulating layer. The first electrode of the first color sub-pixel includes an electrode center located in its central region, and the electrode center overlaps with the via along a direction perpendicular to the substrate.

[0011] For example, according to an embodiment of this disclosure, the first electrode includes multiple electrode layers, with at least one electrode layer overlapping the via along a direction perpendicular to the substrate.

[0012] For example, according to an embodiment of this disclosure, in at least one sub-pixel group, the light-emitting area of ​​the first color sub-pixel includes a plurality of sub-light-emitting areas, and the sub-light-emitting areas do not overlap with the via along a direction perpendicular to the substrate.

[0013] For example, according to an embodiment of this disclosure, in the same first color sub-pixel, the orthogonal projection of the light-emitting area on the substrate surrounds the orthogonal projection of the via on the substrate.

[0014] For example, according to an embodiment of this disclosure, in the same first color sub-pixel, the plurality of sub-light-emitting regions are spaced apart, and the orthogonal projection of the via on the substrate is located within the interval between the orthogonal projections of the plurality of sub-light-emitting regions on the substrate.

[0015] For example, according to an embodiment of this disclosure, in the same first color sub-pixel, the plurality of sub-light-emitting areas include two sub-light-emitting areas, the interval between the two sub-light-emitting areas is elongated, and the width of the interval is equal at different positions.

[0016] For example, according to an embodiment of this disclosure, in the same first color sub-pixel, the plurality of sub-light-emitting areas include two sub-light-emitting areas, and the interval between the two sub-light-emitting areas includes at least a first sub-interval and a second sub-interval, the maximum size of the first sub-interval in the first direction is greater than the maximum size of the second sub-interval in the first direction, and the orthographic projection of the via on the substrate is located within the orthographic projection of the first sub-interval on the substrate.

[0017] For example, according to an embodiment of this disclosure, the interval includes two second sub-intervals, the first sub-interval is located between the two second sub-intervals, and the first sub-interval and the second sub-intervals are arranged along the second direction.

[0018] For example, according to an embodiment of this disclosure, the multilayer electrode layer includes a light-transmitting electrode layer along a direction perpendicular to the substrate, wherein only the light-transmitting electrode layer overlaps with the via in the multilayer electrode layer, and the light-transmitting electrode layer is electrically connected to the pixel circuit through the via.

[0019] For example, according to an embodiment of this disclosure, the light-emitting area of ​​the first color sub-pixel further includes a fifth side extending along the first direction, and the light-emitting area of ​​the other of the second color sub-pixel and the third color sub-pixel includes a sixth side extending along the first direction; the fifth side and the sixth side are respectively located in two adjacent sub-pixel groups in the second direction.

[0020] For example, according to an embodiment of this disclosure, each sub-pixel in the at least partial sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked together. The first electrode is located between the light-emitting functional layer and the substrate and is electrically connected to the pixel circuit. The first electrode of the first color sub-pixel includes a first main electrode and a first connecting electrode connected to each other. The first main electrode overlaps with the light-emitting area of ​​the first color sub-pixel. At least a portion of the first connecting electrode extends along the second direction. In the same sub-pixel group, the light-emitting areas of one of the second color sub-pixels and the third color sub-pixel overlap with the orthographic projection of the first connecting electrode on a straight line extending along the second direction.

[0021] For example, according to an embodiment of this disclosure, the first electrode of the third color sub-pixel includes a second main electrode and a second connecting electrode connected to each other. The second main electrode overlaps with the light-emitting area of ​​the third color sub-pixel. At least a portion of the second connecting electrode extends along the second direction. In the same sub-pixel group, the light-emitting area of ​​the second color sub-pixel overlaps with the orthographic projection of the second connecting electrode on a straight line extending along the second direction.

[0022] For example, according to an embodiment of this disclosure, in the same sub-pixel group, the distance between the first connecting electrode and the second connecting electrode is greater than the maximum size of the third main electrode of the second color sub-pixel in the first direction.

[0023] For example, according to an embodiment of this disclosure, an insulating layer is provided between the first electrode and the pixel circuit, and the first electrode is electrically connected to the pixel circuit through a via in the insulating layer; a plurality of vias corresponding to the first electrodes of a plurality of sub-pixels in the same sub-pixel group are arranged along the first direction, and the plurality of vias are located between the light-emitting areas of adjacent sub-pixel groups arranged along the second direction.

[0024] For example, according to an embodiment of this disclosure, at least one of the number of edges included in the luminous region of the first color sub-pixel, the number of edges included in the luminous region of the second color sub-pixel, and the number of edges included in the luminous region of the third color sub-pixel is greater than 4.

[0025] For example, according to an embodiment of this disclosure, the maximum size of the light-emitting area of ​​one of the second color sub-pixels and the third color sub-pixel in the second direction is greater than the maximum size in the first direction.

[0026] For example, according to an embodiment of this disclosure, in the same sub-pixel group, the light-emitting area of ​​the second color sub-pixel includes two sides extending along the third direction and having different lengths, wherein the longer side is located between the other side and the light-emitting area of ​​the first color sub-pixel; in the same sub-pixel group, the light-emitting area of ​​the third color sub-pixel includes two sides extending along the third direction and having different lengths, wherein the longer side is located between the other side and the light-emitting area of ​​the first color sub-pixel.

[0027] For example, according to an embodiment of this disclosure, the limiting structure further includes a second limiting structure located between the light-emitting area of ​​one of the second color sub-pixels and the third color sub-pixel and the light-emitting area of ​​the first color sub-pixel, and the second limiting structure extends along the fourth direction.

[0028] For example, according to an embodiment of this disclosure, each sub-pixel in the at least part of the sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked together. The first electrode is located between the light-emitting functional layer and the substrate, and an insulating layer is disposed between the first electrode and the pixel circuit. The first electrode is electrically connected to the pixel circuit through a via in the insulating layer. Along a direction perpendicular to the substrate, the defining structure does not overlap with the via.

[0029] For example, according to an embodiment of this disclosure, the defining structure includes a first annular defining structure surrounding the light-emitting area of ​​the first color sub-pixel, the first annular defining structure being a non-closed ring with a first notch.

[0030] For example, according to an embodiment of this disclosure, the defining structure further includes a second annular defining structure surrounding the light-emitting areas of the second color sub-pixel and the third color sub-pixel in the same sub-pixel group. The second annular defining structure is shaped as a non-closed ring with a second notch, and the first annular defining structure is disposed between the second notch and the light-emitting area of ​​the first color sub-pixel.

[0031] For example, according to an embodiment of this disclosure, the defining structure includes a third annular defining structure surrounding the light-emitting area of ​​the second color sub-pixel and a fourth annular defining structure surrounding the light-emitting area of ​​the third color sub-pixel. The third annular defining structure is a non-closed ring with a third notch, and the fourth annular defining structure is a non-closed ring with a fourth notch. The third notch faces at least one of the first annular defining structure and the fourth annular defining structure, and the fourth notch faces at least one of the first annular defining structure and the third annular defining structure.

[0032] For example, according to an embodiment of this disclosure, each sub-pixel in the at least partial sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked together, with the first electrode located between the light-emitting functional layer and the substrate. The array substrate further includes: a planarization layer located between the first electrode and the substrate; and a pixel defining pattern located on the side of the first electrode away from the substrate. The pixel defining pattern includes a plurality of pixel defining openings and a pixel defining portion surrounding the plurality of pixel defining openings. One sub-pixel corresponds to at least one pixel defining opening. The light-emitting element of the sub-pixel is at least partially located in the pixel defining opening corresponding to the sub-pixel, and the pixel defining opening is configured to define the light-emitting area of ​​the sub-pixel. The defining structure is located on the side of one of the pixel defining portion and the planarization layer away from the substrate.

[0033] For example, according to an embodiment of this disclosure, each sub-pixel in the at least partial sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked together, with the first electrode located between the light-emitting functional layer and the substrate. The array substrate further includes: a planarization layer located between the first electrode and the substrate; and a pixel defining pattern located on the side of the first electrode away from the substrate. The pixel defining pattern includes a plurality of pixel defining openings and a pixel defining portion surrounding the plurality of pixel defining openings. One sub-pixel corresponds to at least one pixel defining opening. The light-emitting element of the sub-pixel is at least partially located in the pixel defining opening corresponding to the sub-pixel, and the pixel defining opening is configured to define the light-emitting area of ​​the sub-pixel. The defining structure includes a groove located in the pixel defining portion, or the defining structure includes an opening penetrating the pixel defining portion.

[0034] For example, according to an embodiment of this disclosure, the light-emitting functional layer includes a plurality of film layers, and the defining structure is configured to isolate at least one of the light-emitting functional layers, or the defining structure is configured to increase the length of the conductive path of at least one of the light-emitting functional layers.

[0035] For example, according to an embodiment of this disclosure, the array substrate further includes a plurality of spacers located on the side of the first electrode of the light-emitting element in the sub-pixel group away from the substrate. The ratio of the plurality of sub-pixel groups to the plurality of spacers is 4:1 or 2:1.

[0036] For example, according to an embodiment of this disclosure, a spacer is surrounded by four sub-pixel groups, the four sub-pixel groups including a first sub-pixel group and a second sub-pixel group located on both sides of the spacer in the third direction, the straight line passing through the center of the spacer and extending along the third direction passing through the light-emitting area of ​​the first color sub-pixel in the first sub-pixel group and the light-emitting area of ​​the second color sub-pixel and the light-emitting area of ​​the third color sub-pixel in the second sub-pixel group.

[0037] Another embodiment of this disclosure provides a display device including any of the array substrates described above. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0039] Figure 1 is a partial planar structure schematic diagram of an array substrate provided according to an embodiment of the present disclosure.

[0040] Figure 2 is a partial planar structure schematic diagram of an array substrate provided according to an example of an embodiment of the present disclosure.

[0041] Figure 3 is a schematic diagram of a partial cross-sectional structure cut along line AA' shown in Figure 2.

[0042] Figure 4 is a partial planar structure schematic diagram of an array substrate provided according to another example of an embodiment of the present disclosure.

[0043] Figure 5 is a schematic diagram of a partial cross-sectional structure cut along line BB' shown in Figure 4.

[0044] Figures 6 to 8 are schematic diagrams of partial planar structures of array substrates provided according to different examples of embodiments of the present disclosure.

[0045] Figure 9 is a pixel layout diagram provided according to an example of an embodiment of the present disclosure.

[0046] Figure 10 is a stacking diagram of the pixel arrangement shown in Figure 9 and the film layer where the data lines are located.

[0047] Figure 11 is an equivalent circuit diagram of a pixel circuit.

[0048] Figure 12 is a partial planar schematic diagram of an array substrate provided according to another example of an embodiment of the present disclosure.

[0049] Figures 13 to 15 are schematic diagrams of local cross-sectional structures cut along line CC' shown in Figure 12 in different examples.

[0050] Figure 16 is a partial planar schematic diagram of an array substrate provided according to yet another example of an embodiment of the present disclosure.

[0051] Figures 17 and 18 are partial planar schematic diagrams of array substrates provided according to different examples of embodiments of the present disclosure.

[0052] Figure 19 is a schematic diagram of a partial cross-sectional structure along DD' shown in Figure 17.

[0053] Figure 20 is a schematic block diagram of a display device provided according to another embodiment of the present disclosure. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0056] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of said value. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component is implied to mean that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two.

[0057] This disclosure provides an array substrate and a display device. The array substrate includes a substrate and multiple data lines and multiple sub-pixel groups located on the substrate. The multiple data lines are arranged along a first direction and extend along a second direction, the first direction intersecting the second direction; the multiple sub-pixel groups are arranged in an array along the first and second directions, each sub-pixel group including at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. In the same sub-pixel group, the light-emitting area of ​​at least the first color sub-pixel extends along a third direction, the second color sub-pixel and the third color sub-pixel are arranged along the third direction, and the arrangement direction of the second color sub-pixel and the first color sub-pixel intersects the third direction, the angle between the third direction and the second direction is 20 to 70 degrees; in adjacent sub-pixel groups arranged along the second direction, the light-emitting area of ​​at least one of the second color sub-pixel and the third color sub-pixel in one sub-pixel group overlaps with the orthographic projection of the light-emitting area of ​​the first color sub-pixel in another sub-pixel group on a straight line extending along a fourth direction, the fourth direction being perpendicular to the third direction.

[0058] The array substrate provided in this disclosure, by setting the light-emitting area of ​​at least the first color sub-pixel to extend along a direction having an angle of 20 to 70 degrees with the extension direction of the data line, and setting the relative positional relationship of the light-emitting areas of the sub-pixels in different sub-pixel groups, is beneficial to improve the aperture ratio of the array substrate, improve the oblique jaggedness, optimize the image quality, and enhance the image quality uniformity and smoothness of the display device including the array substrate.

[0059] The array substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0060] Figure 1 is a partial planar structure schematic diagram of an array substrate provided according to an embodiment of the present disclosure.

[0061] As shown in Figure 1, the array substrate includes a substrate 01, multiple data lines 110, and multiple sub-pixel groups 20 located on the substrate 01. The multiple data lines 110 are arranged along a first direction and extend along a second direction, with the first and second directions intersecting. For example, the first direction can be the X direction, the second direction can be the Y direction, and the first and second directions are perpendicular. For example, the first direction can be a row direction, and the second direction can be a column direction. However, this is not limited to the above; the first and second directions can be interchanged; or the angle between the first and second directions is not limited to 90 degrees, but can be 85 to 95 degrees. Figure 1 schematically shows that the data lines 110 are straight lines, but this is not limited to the above; the data lines 110 can also have a curved shape, but the overall extension direction is the second direction.

[0062] As shown in Figure 1, multiple sub-pixel groups 20 are arranged in an array along a first direction and a second direction. At least some of the sub-pixel groups 20 include a first color sub-pixel 210, a second color sub-pixel 220, and a third color sub-pixel 230. For example, each sub-pixel group 20 includes a first color sub-pixel 210, a second color sub-pixel 220, and a third color sub-pixel 230.

[0063] As shown in Figure 1, in the same sub-pixel group 20, at least the luminous area 200 of the first color sub-pixel 210 extends along a third direction, and the second color sub-pixel 220 and the third color sub-pixel 230 are arranged along a third direction. The arrangement directions of the second color sub-pixel 220 and the first color sub-pixel 210 intersect with the third direction, and the angle between the third direction and the second direction is 20 to 70 degrees. For example, the third direction can be the V direction. The phrase "luminous area 200 extends along a third direction" means that the luminous area 200 has its maximum size in the third direction, which can be the extension direction of the luminous area 200. The extension direction of the luminous area 200 of subsequent sub-pixels can also refer to the luminous area 200 having its maximum size in its extension direction. Figure 1 uses square boxes to illustrate the luminous area 200 of each sub-pixel.

[0064] For example, as shown in Figure 1, the light-emitting area 200 of each first color sub-pixel 210 extends along a third direction. For example, the angle between the extension direction of the light-emitting area 200 of the first color sub-pixel 210 and the extension direction of the data line 110 is 20 to 70 degrees.

[0065] For example, as shown in Figure 1, the angle between the third direction and the second direction can be 20 degrees or 70 degrees. For example, the angle between the third direction and the second direction can be 30 to 60 degrees. For example, the angle between the third direction and the second direction can be 45 to 65 degrees. For example, the angle between the third direction and the second direction can be 40 to 50 degrees. This embodiment of the present disclosure will not list all the angles between the third direction and the second direction; the angle between the third direction and the second direction can be any angle between 20 and 70 degrees.

[0066] As shown in Figure 1, in adjacent sub-pixel groups 20 arranged along the second direction, the light-emitting area 200 of at least one of the second-color sub-pixel 220 and the third-color sub-pixel 230 in one sub-pixel group 20 overlaps with the orthographic projection of the light-emitting area 200 of the first-color sub-pixel 210 in another sub-pixel group 20 onto a straight line extending along a fourth direction, where the fourth direction is perpendicular to the third direction. For example, the fourth direction can be the W direction. For example, the first-color sub-pixel 210 and the second-color sub-pixel 220 can be arranged along the fourth direction.

[0067] The array substrate provided in this disclosure, by setting the light-emitting area 200 of at least the first color sub-pixel 210 to extend along a direction having an angle of 20 to 70 degrees with the extension direction of the data line 110, and setting the relative positional relationship of the light-emitting areas 200 of different color sub-pixels in different sub-pixel groups 20, is beneficial to improve the aperture ratio of the array substrate, improve the oblique jaggedness, optimize the image quality, and enhance the image quality uniformity and smoothness of the array substrate.

[0068] For example, as shown in Figure 1, a straight line extending along a third direction may pass through the light-emitting area 200 of at least one of the second-color sub-pixel 220 and the third-color sub-pixel 230 in one sub-pixel group 20, and the light-emitting area 200 of the first-color sub-pixel 210 in another sub-pixel group 20. For example, the orthographic projections of the light-emitting area 200 of the second-color sub-pixel 220 in one sub-pixel group 20 and the light-emitting area 200 of the first-color sub-pixel 210 in another sub-pixel group 20 overlap on a straight line extending along a fourth direction. For example, the orthographic projections of the light-emitting area 200 of the third-color sub-pixel 230 in one sub-pixel group 20 and the light-emitting area 200 of the first-color sub-pixel 210 in another sub-pixel group 20 overlap on a straight line extending along a fourth direction. For example, the light-emitting areas 200 of both the second-color sub-pixel 220 and the third-color sub-pixel 230 in one sub-pixel group 20 overlap with the orthographic projections of the light-emitting area 200 of the first-color sub-pixel 210 in another sub-pixel group 20 on a straight line extending along a fourth direction.

[0069] In some examples, as shown in Figure 1, within the same sub-pixel group 20, the areas of the luminous regions 200 of the second color sub-pixel 220 and the third color sub-pixel 230 are both smaller than the area of ​​the luminous region 200 of the first color sub-pixel 210. The luminous regions 200 of both the second color sub-pixel 220 and the third color sub-pixel 230 extend along a third direction. For example, the first color sub-pixel 210 can be a blue sub-pixel, the second color sub-pixel 220 can be a red sub-pixel, and the third color sub-pixel 230 can be a green sub-pixel; however, this is not a limitation, and the colors of the second color sub-pixel 220 and the third color sub-pixel 230 can be interchanged. For example, the area of ​​the luminous region 200 of the third color sub-pixel 230 is smaller than the area of ​​the luminous region 200 of the second color sub-pixel 220.

[0070] While setting the extension direction of the light-emitting area 200 of the first color sub-pixel 210 to have an angle of 20 to 70 degrees with the extension direction of the data line 110, the extension directions of the light-emitting areas 200 of the second color sub-pixel 220 and the third color sub-pixel 230 are both set to have an angle of 20 to 70 degrees with the extension direction of the data line 110, which is beneficial to maximizing the area of ​​the light-emitting areas 200 of the second color sub-pixel 220 and the third color sub-pixel 230.

[0071] In some examples, as shown in Figure 1, in adjacent sub-pixel groups 20 arranged along the second direction, the center line of the light-emitting area 200 of the first color sub-pixel 210 in one sub-pixel group 20 extends along the third direction through the light-emitting areas 200 of the second color sub-pixel 220 and the third color sub-pixel 230 in another sub-pixel group 20.

[0072] In some examples, as shown in Figure 1, in adjacent sub-pixel groups 20 arranged along a first direction, the light-emitting area 200 of one of the second color sub-pixels 220 and the third color sub-pixels 230 in one sub-pixel group 20 overlaps with the orthographic projection of the light-emitting area 200 of the first color sub-pixel 210 in another sub-pixel group 20 on a straight line extending along a third third direction.

[0073] By setting the relative positional relationships between the first color sub-pixel 210 in one of two adjacent sub-pixel groups 20 in the first and second directions and the second color sub-pixel 220 and the third color sub-pixel 230 in the other of the two adjacent sub-pixel groups 20, it is beneficial to reduce color shift and improve display uniformity.

[0074] For example, as shown in Figure 1, in adjacent sub-pixel groups 20 arranged along the first direction, the light-emitting area 200 of the second color sub-pixel 220 in one sub-pixel group 20 overlaps with the orthographic projection of the light-emitting area 200 of the first color sub-pixel 210 in another sub-pixel group 20 on a straight line extending along a third direction. For example, in adjacent sub-pixel groups 20 arranged along the first direction, the light-emitting area 200 of the third color sub-pixel 230 in one sub-pixel group 20 does not overlap with the orthographic projection of the light-emitting area 200 of the first color sub-pixel 210 in another sub-pixel group 20 on a straight line extending along a third direction.

[0075] For example, as shown in Figure 1, the shape of the light-emitting area 200 of each color sub-pixel can be a quadrilateral, such as a standard quadrilateral or a rounded quadrilateral. For example, the shape of the light-emitting area 200 of each sub-pixel can be a rectangle, and the long side of the rectangle extends along a third direction.

[0076] Figure 2 is a partial planar structure schematic diagram of an array substrate provided according to an example of an embodiment of the present disclosure, and Figure 3 is a partial cross-sectional structure schematic diagram cut along line AA' shown in Figure 2.

[0077] In some examples, as shown in Figures 2 and 3, each sub-pixel in at least some sub-pixel groups 20 includes a light-emitting element 240 and a pixel circuit 250 electrically connected to the light-emitting element 240. The light-emitting element 240 includes a first electrode 241, a light-emitting functional layer 243, and a second electrode 242 stacked together. The first electrode 241 is located between the light-emitting functional layer 243 and the substrate 01, and an insulating layer 400, such as a planarization layer 500, is disposed between the first electrode 241 and the pixel circuit 250. The first electrode 241 is electrically connected to the pixel circuit 250 through a via 401 in the insulating layer 400.

[0078] In some examples, as shown in Figures 2 and 3, the planarization layer 500 is located between the first electrode 241 and the substrate 01. The array substrate also includes a pixel defining pattern 600 located on the side of the first electrode 241 away from the substrate 01. The pixel defining pattern 600 includes a plurality of pixel defining openings 610 and pixel defining portions 620 surrounding the plurality of pixel defining openings 610. A sub-pixel corresponds to at least one pixel defining opening 610. The light-emitting element 240 of the sub-pixel is at least partially located in the pixel defining opening 610 corresponding to the sub-pixel, and the pixel defining opening 610 is configured to define the light-emitting area 200 of the sub-pixel.

[0079] For example, as shown in Figures 2 and 3, each sub-pixel in sub-pixel group 20 includes a light-emitting element 240 and a pixel circuit 250 electrically connected to the light-emitting element 240. For example, the light-emitting functional layer 243 may include a light-emitting layer and a functional layer, such as a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, the first electrode 241 may be an anode, and the second electrode 242 may be a cathode.

[0080] For example, as shown in FIG3, when the light-emitting functional layer 243 is formed in the pixel-defining opening 610 of the pixel-defining pattern 600, the first electrode 241 and the second electrode 242 located on both sides of the light-emitting functional layer 243 can drive the light-emitting functional layer 243 in the pixel-defining opening 610 to emit light. For example, the pixel-defining opening 610 of the pixel-defining pattern 600 is used to define the light-emitting area 200 of the sub-pixel. The light-emitting area 200 can refer to the effective light-emitting area of ​​the sub-pixel, and the shape of the light-emitting area 200 refers to a two-dimensional shape. For example, the shape of the light-emitting area 200 can be the same as the shape of the pixel-defining opening 610 of the pixel-defining pattern 600.

[0081] For example, as shown in FIG3, the material of the pixel limiting part 620 may include polyimide, acrylic or polyethylene terephthalate, etc.

[0082] In some examples, as shown in Figures 2 and 3, the first electrode 241 of the first color sub-pixel 210 includes an electrode center portion 2410 located in its central region, which overlaps with the via 401 along a direction perpendicular to the substrate 01. The central region of the first electrode 241 can refer to the area exposed by the pixel opening of the first electrode 241; for example, the electrode center portion 2410 can be the portion of the first electrode 241 exposed by the pixel-defined opening 610. In Figure 2, the area of ​​the pixel opening is indicated by a dashed box, and the first electrode 241 is indicated by a solid box.

[0083] For example, as shown in Figures 2 and 3, along the direction perpendicular to the substrate 01, the light-emitting area 200 of the first color sub-pixel 210 overlaps with the via 401, while the light-emitting areas 200 of the second color sub-pixel 220 and the third color sub-pixel 230 do not overlap with the via 401.

[0084] By setting the relative positional relationship between the light-emitting area 200 of different color sub-pixels and the via 401, it is beneficial to ensure that the first electrode 241 of each sub-pixel is electrically connected to the pixel circuit 250 through the via 401, while achieving compact pixel arrangement.

[0085] In some examples, as shown in Figures 2 and 3, the first electrode 241 includes a multilayer electrode layer 2400, with at least one electrode layer 2400 overlapping with the via 401 along a direction perpendicular to the substrate 01. For example, the aforementioned at least one electrode layer 2400 may include silver (Ag) and indium tin oxide (ITO), or the multilayer electrode layer 2400 may include two layers of indium tin oxide and silver disposed between the two layers of indium tin oxide.

[0086] By overlapping at least one electrode layer 2400 with the via 401, the first electrode 241 can be electrically connected to the pixel circuit 250 through the via 401.

[0087] In some examples, as shown in FIG3, the multilayer electrode layer 2400 includes a light-transmitting electrode layer 2401. Along a direction perpendicular to the substrate 01, only the light-transmitting electrode layer 2401 overlaps with the via 401, and the light-transmitting electrode layer 2401 is electrically connected to the pixel circuit 250 through the via 401. For example, the multilayer electrode layer 2400 may include multiple light-transmitting electrode layers 2401, with at least one light-transmitting electrode layer 2401 electrically connected to the pixel circuit 250 through the via 401. For example, in a direction perpendicular to the substrate 01, the silver layer in the multilayer electrode layer 2400 does not overlap with the via 401.

[0088] By setting only the light-transmitting electrode layer in the multilayer electrode layer 2400 to overlap with the via 401 to achieve electrical connection between the light-transmitting electrode layer 2400 and the pixel circuit 250, the other electrode layers 2400 in the first electrode 241 avoid the via 401, which helps to improve the flatness of the first electrode 241.

[0089] For example, the multilayer electrodes included in the first electrode 241 of the second color sub-pixel 220 and the third color sub-pixel 230 can all be electrically connected to the pixel circuit 250 through the via 401.

[0090] Figure 3 schematically shows that the light-transmitting electrode layer in the first electrode 241 that is only close to the substrate 01 is electrically connected to the pixel circuit 250 through the via 401. However, it is not limited to this. The light-transmitting electrode layer in the first electrode 241 that is far from the substrate 01 can also be electrically connected to the pixel circuit 250 through the via 401.

[0091] Figure 4 is a partial planar structural schematic diagram of an array substrate provided according to another example of an embodiment of the present disclosure. Figure 5 is a partial cross-sectional structural schematic diagram taken along line BB' shown in Figure 4.

[0092] In some examples, as shown in Figures 4 and 5, in at least one sub-pixel group 20, the light-emitting area 200 of the first color sub-pixel 210 includes a plurality of sub-light-emitting areas 2000, and the sub-light-emitting areas 2000 do not overlap with the via 401 along a direction perpendicular to the substrate 01.

[0093] For example, as shown in Figures 4 and 5, in at least one sub-pixel group 20, the number of light-emitting areas 200 of the second color sub-pixel 220 is one, that is, the light-emitting area 200 of the second color sub-pixel 220 includes one sub-light-emitting area 2000; the number of light-emitting areas 200 of the third color sub-pixel 230 is one, that is, the light-emitting area 200 of the third color sub-pixel 230 includes one sub-light-emitting area 2000.

[0094] The array substrate provided in this disclosure sets the light-emitting area 200 in the first color sub-pixel 210 that overlaps with the first electrode 241 and the via 401 as a plurality of sub-light-emitting areas 2000, and the plurality of sub-light-emitting areas 2000 do not overlap with the via 401. This helps to reduce the influence of the via 401 on the sub-light-emitting areas 2000 of the first color sub-pixel 210 and prevent color shift.

[0095] For example, as shown in Figures 4 and 5, in each sub-pixel group 20, the light-emitting area 200 of the first color sub-pixel 210 includes multiple sub-light-emitting areas 2000. For example, the number of sub-light-emitting areas 2000 included in the light-emitting area 200 of the first color sub-pixel 210 in different sub-pixel groups 20 may be the same, but it is not limited to this. The number of sub-light-emitting areas 2000 in the first color sub-pixel 210 in some sub-pixel groups 20 may be different according to the position of the first color sub-pixel 210.

[0096] In some examples, as shown in FIG4, the multiple sub-light-emitting areas 2000 included in the same first color sub-pixel 210 are spaced apart, and the orthographic projection of the via 401 on the substrate 01 is located within the interval between the orthographic projections of the multiple sub-light-emitting areas 2000 on the substrate 01.

[0097] For example, as shown in Figures 4 and 5, the via 401 overlaps with the pixel defining portion 620 along a direction perpendicular to the substrate 01. For example, the same first color sub-pixel 210 may include two sub-light-emitting areas 2000, with the via 401 located between the two sub-light-emitting areas 2000. For example, the shape and area of ​​the two sub-light-emitting areas 2000 included in the same first color sub-pixel 210 can be set according to the position of the via 401; for example, the shapes of the two sub-light-emitting areas 2000 may be the same or different; the areas of the two sub-light-emitting areas 2000 may be the same or different.

[0098] For example, as shown in Figure 4, the two sub-light-emitting regions 2000 are located on either side of the via 401 in the third direction. For example, the two sub-light-emitting regions 2000 are arranged along the third direction. For example, the edges of the sub-light-emitting regions 2000 may be approximately parallel to the edge of the first electrode 241.

[0099] For example, as shown in Figure 5, the first electrode 241 in the first color sub-pixel 210 includes multiple electrode layers 2400. Only the light-transmitting electrode layer is electrically connected to the pixel circuit 250 through a via 401, and the other electrode layers 2400 do not overlap with the via 401. For example, only one electrode layer 2400 closest to the substrate 01 is electrically connected to the pixel circuit 250 through the via 401. However, this is not the case; all electrode layers 2400 in the first electrode 241 can be electrically connected to the pixel circuit 250 through the via 401.

[0100] Figure 4 schematically shows that the dimensions of each first electrode 241 are equal in the direction perpendicular to its extension, but it is not limited thereto. At least one first electrode 241 may be provided with a smaller dimension, such as a smaller width, between adjacent sub-light-emitting areas 2000. That is, the first electrode 241 is provided only at the location of the via 401, so that the first electrode 241 forms a concave shape at the corresponding edge of the via 401.

[0101] Figures 6 to 8 are schematic diagrams of partial planar structures of array substrates provided according to different examples of embodiments of the present disclosure. The array substrates shown in Figures 6 to 8 differ from the array substrate shown in Figure 4 in that the shape and arrangement of the sub-light-emitting regions 2000 included in the light-emitting region 200 of the first color sub-pixel 210 are different. Other structures in the array substrates shown in Figures 6 to 8, except for the sub-light-emitting regions 2000 of the first color sub-pixel 210, can have the same features as the corresponding structures in the array substrate shown in Figure 4, and will not be described again here.

[0102] In some examples, as shown in Figure 6, within the same first color sub-pixel 210, multiple sub-light-emitting areas 2000 include two sub-light-emitting areas 2000, with a strip-shaped interval 260 between the two sub-light-emitting areas 2000, and the interval 260 having the same width at different positions. For example, the interval 260 may extend along a second direction.

[0103] For example, as shown in Figure 6, in the same first color sub-pixel 210, two sub-light-emitting areas 2000 are arranged along a first direction. For example, the size of the spacing 260 in the first direction is larger than the size of the via 401 in the first direction. For example, in the same first color sub-pixel 210, the shapes of the two sub-light-emitting areas 2000 can be different to better accommodate the position of the via 401.

[0104] In some examples, as shown in Figure 7, within the same first color sub-pixel 210, multiple sub-light-emitting areas 2000 include two sub-light-emitting areas 2000. The interval 260 between the two sub-light-emitting areas 2000 includes at least a first sub-interval 261 and a second sub-interval 262. The maximum dimension D1 of the first sub-interval 261 in a first direction is greater than the maximum dimension D2 of the second sub-interval 262 in the first direction, and the orthographic projection of the via 401 on the substrate 01 lies within the orthographic projection of the first sub-interval 261 on the substrate 01. The aforementioned first sub-interval 261 and second sub-interval 262 are connected.

[0105] By setting the interval between two sub-light-emitting areas 2000 in the same first color sub-pixel 210 to a first sub-interval 261 and a second sub-interval 262 with different sizes, the area of ​​each sub-light-emitting area 2000 can be increased while avoiding the via 401.

[0106] For example, as shown in Figure 7, the first sub-spacement 261 and the second sub-spacement 262 are arranged in the second direction.

[0107] For example, as shown in Figure 7, in the first direction, the size of the first sub-space 261 is larger than the size of the via 401; in the second direction, the size of the first sub-space 261 is larger than the size of the via 401.

[0108] In some examples, as shown in Figure 7, the interval between two sub-light-emitting regions 2000 includes two second sub-intervals 262, with a first sub-interval 261 located between the two second sub-intervals 262.

[0109] By setting the larger first sub-space 261 between two smaller second sub-spaces 262, it is beneficial to further increase the area of ​​the sub-light-emitting region 2000.

[0110] Of course, the embodiments disclosed herein are not limited to the interval between the two sub-light-emitting regions 2000 including two second sub-intervals 262, and the aforementioned interval may also include one second sub-interval 262.

[0111] For example, as shown in Figure 7, in the first direction, the size of the second sub-space 262 can be larger than the size of the via 401. For example, the width of each second sub-space 262 in the first direction can be equal at all locations. However, it is not limited to this; the width of the second sub-space 262 can also be gradual, such as gradually increasing the width of the second sub-space 262 from the direction away from the first sub-space 261 to the direction closer to the first sub-space 261.

[0112] In some examples, as shown in Figure 8, in the same first color sub-pixel 210, the orthogonal projection of the light-emitting area 200 on the substrate 01 surrounds the orthogonal projection of the via 401 on the substrate 01.

[0113] By setting the light-emitting area 200 of the first color sub-pixel 210 to surround the via 401, it is beneficial to further increase the area of ​​the light-emitting area 200.

[0114] Figure 9 is a pixel arrangement diagram provided according to an example embodiment of the present disclosure. Figure 10 is a stack-up diagram of the pixel arrangement shown in Figure 9 and the film layer containing the data lines. The substrate 01 is omitted in Figures 9 and 10, and the substrate 01 in the examples shown in Figures 9 and 10 has the same features as the substrate 01 shown in Figure 1.

[0115] Figures 9 and 10 show the relationship between the number and type of subpixels included in subpixel group 20, the size of the light-emitting area 200, the extension direction of the light-emitting area 200 of the first color subpixel 210 and the extension direction of the data line 110, and the orthographic projection overlap relationship between the light-emitting area 200 of at least one of the second color subpixel 220 and the third color subpixel 230 in one subpixel group 20 arranged along the second direction and the light-emitting area 200 of the first color subpixel 210 in another subpixel group 20 on a straight line extending along the fourth direction, as shown in Figure 1. The number and type of sub-pixels included in pixel group 20, the size relationship of the light-emitting area 200, the extension direction of the light-emitting area 200 of the first color sub-pixel 210 and the extension direction of the data line 110, and the orthographic projection overlap relationship between the light-emitting area 200 of at least one of the second color sub-pixel 220 and the third color sub-pixel 230 in one sub-pixel group 20 arranged along the second direction and the light-emitting area 200 of the first color sub-pixel 210 in another sub-pixel group 20 on a straight line extending along the fourth direction, have the same characteristics, and will not be described in detail here.

[0116] In some examples, as shown in Figure 9, in the same sub-pixel group 20, the light-emitting area 200 of the first color sub-pixel 210 includes a first side 201 and a second side 202 extending along a third direction. The length of the first side 201 is greater than the length of the second side 202, and the first side 201 is located between the second side 202 and the light-emitting area 200 of the second color sub-pixel 220. The light-emitting area 200 of the first color sub-pixel 210 also includes a third side 203 extending along a second direction. The light-emitting area 200 of one of the second color sub-pixel 220 and the third color sub-pixel 230 includes a fourth side 204 extending along the second direction. The third side 203 and the fourth side 204 are adjacent in two sub-pixel groups 20 that are adjacent in the first direction.

[0117] By setting the lengths of the first side 201 and the second side 202 in the light-emitting area 200 of the first color sub-pixel 210 and their positional relationship relative to the light-emitting area 200 of the second color sub-pixel 220, and by setting the relative positional relationship between the fourth side 204 of the light-emitting area 200 of one of the second color sub-pixel 220 and the third side 203 of the first color sub-pixel 210, it is beneficial to increase the area of ​​the light-emitting area 200 of each color sub-pixel.

[0118] For example, as shown in FIG9, the light-emitting area 200 of the third color sub-pixel 230 includes a fourth side 204 extending along the second direction; in adjacent sub-pixel groups 20 in the first direction, the first color sub-pixel 210 in one sub-pixel group 20 is adjacent to the third color sub-pixel 230 in another sub-pixel group 20.

[0119] In some examples, as shown in FIG9, the light-emitting area 200 of the first color sub-pixel 210 further includes a fifth side 205 extending along the first direction, and the light-emitting area 200 of the other of the second color sub-pixel 220 and the third color sub-pixel 230 includes a sixth side 206 extending along the first direction; the fifth side 205 and the sixth side 206 are respectively located in two adjacent sub-pixel groups 20 in the second direction.

[0120] By setting the shape of the light-emitting area 200 of the sub-pixel adjacent to the first color sub-pixel 210 in the sub-pixel groups 20 that are adjacent to the first color sub-pixel 210 in the first and second directions respectively, it is beneficial to achieve a compact arrangement of multiple sub-pixel groups 20 and increase the area of ​​the light-emitting area 200 of each sub-pixel.

[0121] For example, as shown in FIG9, the light-emitting area 200 of the second color sub-pixel 220 includes a sixth side 206 extending along the first direction; in adjacent sub-pixel groups 20 in the second direction, the first color sub-pixel 210 in one sub-pixel group 20 is adjacent to the second color sub-pixel 220 in another sub-pixel group 20.

[0122] For example, as shown in FIG9, in the same sub-pixel group 20, the second color sub-pixel 220 and the third color sub-pixel 230 include an edge that is adjacent to the first edge 201 of the first color sub-pixel 210 and extends along a third direction. For example, in the same sub-pixel group 20, the adjacent edges of the second color sub-pixel 220 and the third color sub-pixel 230 are arranged parallel to each other.

[0123] In some examples, as shown in Figures 9 and 10, at least one of the following is greater than 4: the number of edges included in the luminous area 200 of the first color sub-pixel 210, the number of edges included in the luminous area 200 of the second color sub-pixel 220, and the number of edges included in the luminous area 200 of the third color sub-pixel 230.

[0124] By setting the number of edges included in the light-emitting area 200 of each color sub-pixel, it is beneficial to improve the compactness of the pixel arrangement and increase the area of ​​the light-emitting area 200 of each color sub-pixel while avoiding the position of the via 401 connected to the first electrode 241.

[0125] For example, as shown in Figure 9, the number of edges in the luminous area 200 of the first color sub-pixel 210 is greater than 4, the number of edges in the luminous area 200 of the second color sub-pixel 220 is greater than 4, and the number of edges in the luminous area 200 of the third color sub-pixel 230 is greater than 4. For example, the number of edges in the luminous area 200 of different color sub-pixels can be the same or different. For example, the number of edges in the luminous area 200 of the first color sub-pixel 210 is 6, the number of edges in the luminous area 200 of the second color sub-pixel 220 is 5, and the number of edges in the luminous area 200 of the third color sub-pixel 230 is 7. However, this embodiment does not limit the number of edges in the luminous area 200 of each color sub-pixel; it can be any value greater than 4.

[0126] In some examples, as shown in Figure 9, the maximum size D3 of the light-emitting area 200 of one of the second color sub-pixels 220 and the third color sub-pixel 230 in the second direction is greater than the maximum size D4 in the first direction. For example, the light-emitting area 200 of one of the second color sub-pixels 220 and the third color sub-pixel 230 extends along the second direction.

[0127] By setting the light-emitting area 200 of the first color sub-pixel 210 to extend along a third direction, and setting the light-emitting area 200 of one of the light-emitting areas 200 of the second color sub-pixel 220 and the third color sub-pixel 230 to extend along a second direction, it is beneficial to maximize the area of ​​the light-emitting area 200 of each color sub-pixel.

[0128] In some examples, as shown in Figure 9, in the same sub-pixel group 20, the light-emitting area 200 of the second color sub-pixel 220 includes two sides extending along a third direction with different lengths, and the longer side 2071 is located between the other side 2072 and the light-emitting area 200 of the first color sub-pixel 210; in the same sub-pixel group 20, the light-emitting area 200 of the third color sub-pixel 230 includes two sides extending along a third direction with different lengths, and the longer side 2081 is located between the other side 2082 and the light-emitting area 200 of the first color sub-pixel 210.

[0129] By setting the number, length, and relative position of the edges extending along the third direction in the light-emitting area 200 of the second color sub-pixel 220 and the third color sub-pixel 230, it is beneficial to further improve the compactness of the pixel arrangement.

[0130] The light-emitting element 240 of the sub-pixel shown in Figures 9 and 10 can have the same features as the light-emitting element 240 shown in Figure 3, such as including a first electrode 241, a light-emitting functional layer 243 and a second electrode 242 stacked together. The first electrode 241 is located between the light-emitting functional layer 243 and the substrate 01, and the first electrode 241 is electrically connected to the pixel circuit 250.

[0131] Figure 11 is an equivalent circuit diagram of a pixel circuit. As shown in Figure 11, the pixel circuit 250 may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. The pixel circuit 250 is connected to the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the light emission signal line EM, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the data line DATA (data line 110 as shown in Figures 1 and 10), and the first power supply line VDD. However, it is not limited to this. The pixel circuit 250 provided in this embodiment may also be a 7T1C, 9T1C, 8T2C pixel circuit, etc., and this embodiment does not limit it.

[0132] For example, as shown in Figure 11, the pixel circuit 250 may include a first node N1, a second node N2, a third node N3, and a fourth node N4. For example, the first node N1 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the storage capacitor C, respectively; the second node N2 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5, and the second terminal of the eighth transistor T8, respectively; the third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively; and the fourth node N4 is connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7, respectively.

[0133] For example, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power line VDD.

[0134] For example, as shown in Figure 11, the first transistor T1 can be called the first initialization transistor. The gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1.

[0135] For example, as shown in Figure 11, the second transistor T2 can be called a compensation transistor. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0136] For example, as shown in Figure 11, the third transistor T3 can be called the driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0137] For example, as shown in Figure 11, the fourth transistor T4 can be called the data writing transistor. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0138] For example, as shown in Figure 11, the fifth transistor T5 can be called the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0139] For example, as shown in Figure 11, the sixth transistor T6 can be called the second light-emitting control transistor. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0140] For example, as shown in Figure 11, the seventh transistor T7 can be called the second initialization transistor. The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0141] For example, as shown in Figure 11, the eighth transistor T8 can be called the third initialization transistor. The gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0142] For example, as shown in Figure 11, the first electrode of the light-emitting element EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS.

[0143] For example, as shown in Figure 11, the signal of the first power line VDD is a continuously supplied high-level signal, and the signal of the second power line VSS is a continuously supplied low-level signal.

[0144] For example, as shown in Figure 11, the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel circuit 250 can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0145] For example, as shown in Figure 11, the first transistor T1 to the eighth transistor T8 can be low-temperature polycrystalline silicon (LTPS) transistors, or oxide transistors, or a combination of both. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor. LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and oxide transistors onto a single array substrate to form a low-temperature polycrystalline oxide (LTPO) array substrate allows for the utilization of both advantages to achieve low-frequency driving, thereby reducing power consumption and improving display quality.

[0146] The array substrates in the examples shown in Figures 1 to 8 and the examples shown in Figures 9 to 10 can all adopt the pixel circuit 250 shown in Figure 11. As shown in Figure 5, the pixel circuit 250 can have the equivalent circuit shown in Figure 11. The specific layer structure of the pixel circuit 250 can be any specific layer structure that satisfies the equivalent circuit shown in Figure 11.

[0147] For example, as shown in Figures 10 and 11, a metal layer 100 is disposed between the first electrode 241 of the light-emitting element 240 and the substrate 01. The metal layer 100 includes a data line 110, a first power line 120 (i.e., the first power line VDD), an initial signal line 130 (i.e., one of the first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3), a signal line 140, and a connection portion 150. For example, the signal line 140 can transmit a low-level signal VSS, or it can serve as an adapter to transmit a data signal.

[0148] For example, as shown in Figure 10, the first power line 120, the initial signal line 130, and the signal line 140 extend along a second direction. For example, between two adjacent initial signal lines 130, there are first power lines 120, signal lines 140, and data lines 110 arranged sequentially along a first direction.

[0149] For example, as shown in FIG10, the first electrode 241 of the light-emitting element 240 is connected to the connection portion 150 in the metal layer 100 through the via 401. The connection portion 150 is connected to the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6 located between it and the substrate 01, so as to realize the electrical connection between the first electrode of the light-emitting element 240 and the pixel circuit 250.

[0150] Figure 10 schematically shows that the metal layer 100 includes a data line 110, a first power line 120, an initial signal line 130, a signal line 140, and a connection portion 150. However, it is not limited to this; the metal layer 100 may also include only the data line 110, the first power line 120, the signal line 140, and the connection portion 150, or it may only include the data line 110, the first power line 120, and the connection portion 150. The film layer between the metal layer 100 and the substrate 01 shown in Figure 10 includes at least one semiconductor layer, multiple metal layers, and multiple insulating layers. The semiconductor layer may include active layers of multiple transistors, and the multiple metal layers may include transistor gates, storage capacitor plates, light-emitting signal lines, scan signal lines, initial signal lines, connection electrodes, and other structures. The film layer between the metal layer 100 and the substrate 01 can be configured in various different ways according to the pixel circuit 250, all of which are included in the technical solutions of this application.

[0151] In some examples, as shown in FIG10, the first electrode 241 of the first color sub-pixel 210 includes a first main electrode 2411 and a first connecting electrode 2421 connected to each other. The first main electrode 2411 overlaps with the light-emitting area 200 of the first color sub-pixel 210. At least a portion of the first connecting electrode 2421 extends along a second direction. In the same sub-pixel group 20, the light-emitting area 200 of one of the second color sub-pixel 220 and the third color sub-pixel 230 overlaps with the orthographic projection of the first connecting electrode 2421 on a straight line extending along the second direction.

[0152] By setting the positional relationship between the first connecting electrode 2421 of the first color sub-pixel 210 and the light-emitting area 200 of one of the second color sub-pixel 220 and the third color sub-pixel 230, the compactness of the pixel arrangement can be improved while preventing interference between the first electrodes 241 of the light-emitting elements 240 of each sub-pixel.

[0153] For example, as shown in Figure 10, in the same first color sub-pixel 210, the first main electrode 2411 and the first connecting electrode 2421 are integrally formed. For example, along the direction perpendicular to the substrate 01, the first connecting electrode 2421 does not overlap with the light-emitting area 200. For example, the shape of the first main electrode 2411 is similar to that of the light-emitting area 200 of the first color sub-pixel 210.

[0154] For example, as shown in Figure 10, in the same sub-pixel group 20, the light-emitting area 200 of the second color sub-pixel 220 overlaps with the orthographic projection of the first connecting electrode 2421 on a straight line extending along the second direction.

[0155] For example, as shown in Figure 10, the first main electrode 2411 of the first color sub-pixel 210 overlaps with the first power line 120 and the two data lines 110, and the first power line 120 is located between the two data lines 110, which helps to improve the flatness and symmetry of the first main electrode 2411 and prevent the first color sub-pixel 210 from color shifting.

[0156] For example, as shown in Figure 10, the edge of the first power line 120 extending along the second direction is recessed inward at the position of the corresponding connection portion 150, so as to provide placement space for the connection portion 150 while achieving a larger overall width for the first power line 120.

[0157] For example, as shown in FIG10, the initial signal line 130 has a bend to provide placement space for the adapter provided on the data line 110 for electrical connection with the first pole of the fourth transistor T4.

[0158] For example, as shown in FIG10, a third power line extending in a first direction is provided between the metal layer 100 and the substrate 01 to be electrically connected to the first power line extending in a second direction in the metal layer 100, forming a grid-like first power line, reducing resistance and improving signal transmission efficiency.

[0159] In some examples, as shown in FIG10, the first electrode 241 of the third color sub-pixel 230 includes a second main electrode 2412 and a second connecting electrode 2422 connected to each other. The second main electrode 2412 overlaps with the light-emitting area 200 of the third color sub-pixel 230. At least a portion of the second connecting electrode 2422 extends along a second direction. In the same sub-pixel group 20, the light-emitting area 200 of the second color sub-pixel 220 overlaps with the orthographic projection of the second connecting electrode 2422 on a straight line extending along the second direction.

[0160] By setting the positional relationship between the second connecting electrode 2422 of the third color sub-pixel 230 and the light-emitting area 200 of the second color sub-pixel 220, interference between the first electrode 241 of the light-emitting element 240 of each sub-pixel can be further prevented, while improving the compactness of the pixel arrangement.

[0161] For example, as shown in Figure 10, in the same third color sub-pixel 230, the second main electrode 2412 and the second connecting electrode 2422 are integrally formed. For example, along the direction perpendicular to the substrate 01, the second connecting electrode 2422 does not overlap with the light-emitting area 200. For example, the shape of the second main electrode 2412 is similar to that of the light-emitting area 200 of the third color sub-pixel 230.

[0162] For example, as shown in Figure 10, the second main electrode 2412 of the third color sub-pixel 230 overlaps with the first power line 120, the data line 110 and the initial signal line 130, and the initial signal line 130 is located between the first power line 120 and the data line 110, which helps to improve the flatness and symmetry of the second main electrode 2412 and prevent the third color sub-pixel 230 from color shifting.

[0163] In some examples, as shown in FIG10, within the same sub-pixel group 20, the distance between the first connecting electrode 2421 and the second connecting electrode 2422 is greater than the maximum dimension of the third main electrode 2413 of the second color sub-pixel 220 in the first direction. For example, the minimum distance between the second connecting electrode 2422 and the third main electrode 2413 is greater than the minimum distance between the connecting portion 150 connected to the second connecting electrode 2422 and the third main electrode 2413 in the first direction, to prevent interference between the second connecting electrode 2422 and the third main electrode 2413.

[0164] For example, as shown in Figure 10, the third main electrode 2413 overlaps with the light-emitting area 200 of the second color sub-pixel 220, and the shape of the third main electrode 2413 is similar to the shape of the light-emitting area 200 of the second color sub-pixel 220. For example, the first electrode 241 of the second color sub-pixel 220 also includes a third connecting electrode, which does not overlap with the light-emitting area 200 of the second color sub-pixel 220, and the third connecting electrode and the third main electrode 2413 are integrally formed.

[0165] The insulating layer 400 disposed between the first electrode 241 of the light-emitting element 240 shown in Figure 10 and the pixel circuit 250 can have the same features as the insulating layer 400 disposed between the first electrode 241 and the pixel circuit 250 shown in Figure 5. For example, the first electrode 241 is electrically connected to the connecting part through the through hole 401 in the insulating layer 400, thereby realizing the electrical connection between the first electrode 241 and the pixel circuit 250.

[0166] In some examples, as shown in FIG10, a plurality of vias 401 corresponding to the first electrodes 241 of a plurality of sub-pixels in the same sub-pixel group 20 are arranged along a first direction, and the plurality of vias 401 are located between the light-emitting areas 200 of adjacent sub-pixel groups 20 arranged along a second direction.

[0167] By setting multiple vias 401 between the light-emitting areas 200 of two adjacent rows of sub-pixel groups 20, it is possible to prevent the light-emitting areas 200 from overlapping with the vias 401 and affecting the light emission effect.

[0168] Figure 12 is a partial planar schematic diagram of an array substrate provided according to another example of an embodiment of the present disclosure. Figures 13 to 15 are partial cross-sectional schematic diagrams taken along line CC' shown in Figure 12 in different examples. Figure 12 schematically uses the pixel arrangement structure shown in Figure 4 as an example of setting a limiting structure, but it is not limited thereto. The limiting structure can also be set in any pixel arrangement structure shown in Figure 2 and Figures 6 to 8. Other structures in the array substrate shown in Figure 12, except for the limiting structure, can have the same features as the corresponding structures in the array substrates in the foregoing examples, and will not be described again here.

[0169] In some examples, as shown in Figures 12 to 15, the array substrate further includes a defining structure 300, the light-emitting functional layer 243 includes multiple film layers, the defining structure 300 is configured to block at least one of the light-emitting functional layers 243, or the defining structure 300 is configured to increase the length of the conductive path of at least one of the light-emitting functional layers 243.

[0170] For example, as shown in Figures 12 to 15, the light-emitting functional layer 243 includes two stacked light-emitting layers and a charge-generating layer located between the two light-emitting layers, thus the array substrate adopts a tandem structure. For example, a tandem structure involves stacking and connecting the light-emitting layers of sub-pixels in series, and placing a full-layer charge-generating layer between the stacked light-emitting layers, such as a P-type doped charge-generating layer P-CGL and an N-type doped charge-generating layer N-CGL. Compared to an array substrate without a tandem structure, the tandem structure uses N / P-CGL as a heterojunction to connect the two light-emitting layers in series. This structure realizes the series connection of two light-emitting devices, significantly reducing the luminous current of the light-emitting devices under the same luminous intensity, improving the lifetime of the organic light-emitting element, and reducing power consumption.

[0171] However, in the Tandem structure, the charge generation layers of two adjacent sub-pixels are continuous film layers, which can lead to lateral charge migration. This can cause monochromatic color shift in low grayscale levels of the display device, and may also cause crosstalk between adjacent sub-pixels, resulting in color deviation in the display device.

[0172] For example, in the same sub-pixel, the two light-emitting layers can be light-emitting layers that emit the same color of light, but they are not limited to this; the two light-emitting layers can also be light-emitting layers that emit different colors of light.

[0173] For example, in each sub-pixel, the light-emitting functional layer 243 may also include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0174] For example, the hole injection layer, hole transport layer, electron transport layer, electron injection layer, charge generation layer, and second electrode 242 are all shared film layers for multiple sub-pixels, and can be referred to as common layers. For example, the aforementioned common layer and second electrode 242 can be film layers formed using an open mask.

[0175] For example, the charge generation layer can include N-type charge generation layers and P-type charge generation layers. For example, the material of the electron transport layer can include aromatic heterocyclic compounds, such as imidazole derivatives, imidazopyridine derivatives, benzimidazole-phenanthridine derivatives, and other imidazole derivatives; pyrimidine derivatives, triazine derivatives, and other azine derivatives; quinoline derivatives, isoquinoline derivatives, phenanthreneroline derivatives, and other compounds containing a nitrogen-containing six-membered ring structure (including compounds with phosphine oxide substituents on the heterocycle), etc.

[0176] For example, the material of the charge-generating layer can be a material containing phospho groups or a material containing triazine. For example, the ratio of the electron mobility of the charge-generating layer material to the electron mobility of the electron transport layer is 10⁻² to 10².

[0177] In some examples, as shown in Figures 12 and 13, the defining structure 300 is located at least between the light-emitting areas 200 of two adjacent sub-pixels. The defining structure 300 includes a first defining structure 310 located between the light-emitting area 200 of at least one of the second color sub-pixel 220 and the third color sub-pixel 230 and the light-emitting area 200 of the first color sub-pixel 210, the first defining structure 310 extending in a third direction.

[0178] A first limiting structure 310, which extends in the same direction as the light-emitting area 200 of the first color sub-pixel 210, is provided between the light-emitting area 200 of at least one of the second color sub-pixel 220 and the third color sub-pixel 230 and the light-emitting area 200 of the first color sub-pixel 210. This helps to improve the isolation effect of the first limiting structure 310 on the portion of the common layer of the first color sub-pixel 210 located between the light-emitting area 200 of the first color sub-pixel 210 and the light-emitting area 200 of at least one of the second color sub-pixel 220 and the third color sub-pixel 230, and reduces crosstalk between the first color sub-pixel 210 and other color sub-pixels.

[0179] For example, as shown in Figure 12, the length of the first defining structure 310 is greater than the total length of the light-emitting area 200 of the first color sub-pixel 210 in the third direction. For example, the distance between the first defining structure 310 and the light-emitting area 200 of the first color sub-pixel 210 is less than the distance between the first defining structure 310 and the light-emitting areas 200 of other color sub-pixels.

[0180] In some examples, as shown in FIG13, the array substrate further includes a planarization layer 500 located between the first electrode 241 and the substrate 01, with the defining structure located on the side of the pixel defining portion 620 and the planarization layer 500 away from the substrate 01. FIG13 schematically shows the defining structure 300 located on the side of the pixel defining portion 620 away from the substrate 01, but is not limited thereto. The defining structure 300 may also be located on the side of the planarization layer 500 away from the substrate 01, such as when the pixel defining pattern 600 may include an opening, and the defining structure 300 is located on the side of the planarization layer 500 away from the substrate 01 and is located in the opening.

[0181] For example, as shown in FIG13, the limiting structure 300 may include a multilayer structure stacked on top of each other, such as a first isolation layer, a second isolation layer, and a third isolation layer stacked sequentially. The first isolation layer is located between the second isolation layer and the substrate 01, and the edge of the third isolation layer protrudes relative to the edge of the second isolation layer to isolate at least one layer of the light-emitting functional layer 243. For example, the edge of the first isolation layer also protrudes relative to the edge of the second isolation layer. For example, the limiting structure 300 may be formed of a metallic material, such as titanium for the first and third isolation layers, and aluminum for the second isolation layer.

[0182] Of course, the embodiments disclosed herein are not limited to the three-layer structure described above, but may also include a two-layer structure or a four-layer structure, etc.

[0183] For example, in other examples, the defining structure 300 may also employ at least one of organic and inorganic materials. For instance, the defining structure 300 may consist only of a first isolation layer and a second isolation layer stacked together, with the first isolation layer located between the second isolation layer and the substrate 01. The first isolation layer may be an organic layer, such as a portion of the pixel defining portion 620, and the second isolation layer may be an inorganic layer, with its edge protruding relative to the edge of the first isolation layer. For example, the material of the inorganic layer may include inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0184] For example, as shown in Figure 13, the defined structure 300 blocks all the film layers included in the light-emitting functional layer 243 and the second electrode 242.

[0185] For example, in other examples, the light-emitting functional layer 243 may include only one light-emitting layer, such as excluding the charge generation layer. The above-described defined structure can isolate at least one of the common layers between adjacent sub-pixels, such as the electron transport layer and / or the electron injection layer, to reduce leakage current between sub-pixels of different colors.

[0186] For example, as shown in FIG14, the limiting structure 300 can also be a single-layer structure, such as a protrusion on the surface of the pixel limiting portion 620 away from the substrate 01. This limiting structure 300 can not block the light-emitting functional layer 243 and the second electrode 242, but only increase the conductive path of the common layer in the light-emitting functional layer 243, so as to reduce the conductivity of the common layer while ensuring that the second electrode 242 has good conductivity.

[0187] For example, as shown in FIG14, the limiting structure 300 may be made of a different material than the pixel limiting portion 620, but is not limited thereto; the limiting structure 300 may also be formed of the same material as the pixel limiting portion 620.

[0188] In some examples, as shown in FIG15, the defining structure 300 includes a groove located in the pixel defining portion 620, or the defining structure 300 includes an opening through the pixel defining portion 620.

[0189] For example, as shown in FIG15, the limiting structure 300 can be a groove in the pixel limiting part 620. This groove can not block the light-emitting functional layer 243 and the second electrode 242, but only increase the conductive path of the common layer in the light-emitting functional layer 243, so as to reduce the conductivity of the common layer while ensuring that the second electrode 242 has good conductivity.

[0190] Figure 15 schematically shows the limiting structure 300 as a groove in the pixel limiting portion 620, but it is not limited thereto. The limiting structure 300 can also be an opening in the pixel limiting portion 620, which exposes the planarization layer 500. For example, the opening can block the light-emitting functional layer 243, or it can simply extend the conductive path of the common layer in the light-emitting functional layer 243.

[0191] In some examples, as shown in FIG12, the limiting structure 300 further includes a second limiting structure 320, which is located between the light-emitting area 200 of one of the second color sub-pixels 220 and the third color sub-pixels 230 and the light-emitting area 200 of the first color sub-pixel 210, and the second limiting structure 320 extends along a fourth direction.

[0192] For example, as shown in Figure 12, the distance between the second defining structure 320 and the light-emitting area 200 of one of the second color sub-pixels 220 and the third color sub-pixel 230 is less than the distance between the second defining structure 320 and the light-emitting area 200 of the first color sub-pixel 210. For example, the distance between the second defining structure 320 and the light-emitting area 200 of the third color sub-pixel 230 is less than the distance between the second defining structure 320 and the light-emitting area 200 of the first color sub-pixel 210.

[0193] By setting the light-emitting area 200 of one of the second color sub-pixels 220 and the third color sub-pixel 230 to extend along the arrangement direction of the first color sub-pixel 210 and the second color sub-pixel 220, and setting the distance between the second limiting structure 320 and different color sub-pixels, it is beneficial to reduce the crosstalk between the common layer in the light-emitting functional layer 243 of one of the second color sub-pixels 220 and the third color sub-pixel 230 and the common layer of the first color sub-pixel 210.

[0194] For example, as shown in Figure 12, a first limiting structure 310 and a second limiting structure 320 can be simultaneously provided between the light-emitting areas 200 of a first color sub-pixel 210 in a sub-pixel group 20 and a third color sub-pixel 230 in an adjacent sub-pixel group 20, and the first limiting structure 310 and the second limiting structure 320 can also be simultaneously provided between the light-emitting areas 200 of a first color sub-pixel 210 in a sub-pixel group 20 and a second color sub-pixel 220 in an adjacent sub-pixel group 20. However, this is not limited to this; only the first limiting structure 310 or only the second limiting structure 320 can be provided between the light-emitting areas 200 of the first color sub-pixel 210 and the third color sub-pixel 230, and / or only the first limiting structure 310 or only the second limiting structure 320 can be provided between the light-emitting areas 200 of the first color sub-pixel 210 and the second color sub-pixel 220, in order to increase the width of the conductive path of the second electrode 242 located between the first color sub-pixel 210 and other colors.

[0195] In some examples, as shown in FIG12, the defining structure 300 includes a first annular defining structure 330 surrounding the light-emitting region 200 of the first color sub-pixel 210, the first annular defining structure 330 being a non-closed ring with a first notch 331.

[0196] By setting the shape of the first annular defining structure 330 to a non-closed ring with a first notch 331, the second electrode 242 of the first color sub-pixel 210 can be prevented from being completely disconnected at the position of the first annular defining structure 330, thus affecting signal transmission.

[0197] For example, as shown in Figure 12, the first notch 331 can be located on the side of the light-emitting area 200 of the first color sub-pixel 210 away from the light-emitting area 200 of the second color sub-pixel 220 located in the same sub-pixel group 20 as the first color sub-pixel 210. However, it is not limited to this; the first notch 331 can also be located in other positions. For example, the position of the first notch 331 can be set with a limiting structure between the light-emitting areas 200 of the first color sub-pixel 210 and other color sub-pixels. For example, the first notch 331 can be located between the light-emitting area 200 of the first color sub-pixel 210 and the second limiting structure 320.

[0198] For example, Figure 12 schematically shows a first annular defining structure 330 including a first notch 331, but is not limited thereto, and the number of first notches 331 can be set as needed.

[0199] For example, as shown in Figure 12, the distance between the first annular defining structure 330 and the light-emitting area 200 of the first color sub-pixel 210 is greater than the distance between the first annular defining structure 330 and the light-emitting areas 200 of other color sub-pixels.

[0200] In some examples, as shown in Figure 12, the structure 300 and the via 401 do not overlap along a direction perpendicular to the substrate 01.

[0201] By staggering the positions of the limiting structure and the via 401, interference between the limiting structure and the via 401 can be avoided.

[0202] In some examples, as shown in FIG12, the defining structure 300 includes a second annular defining structure 340 surrounding the light-emitting areas 200 of the second color sub-pixel 220 and the third color sub-pixel 230 in the same sub-pixel group 20. The second annular defining structure 340 is shaped as a non-closed ring with a second notch 341, and a first annular defining structure 330 is disposed between the second notch 341 and the light-emitting area 200 of the first color sub-pixel 210.

[0203] By setting a second annular defining structure 340 around the light-emitting area 200 of the second color sub-pixel 220 and the third color sub-pixel 230, it is beneficial to further reduce crosstalk between the first color sub-pixel 210 and other color sub-pixels, such as reducing crosstalk between the blue sub-pixel and other color sub-pixels.

[0204] For example, as shown in Figure 12, the second notch 341 of the second annular limiting structure 340 can be provided at the position of the through hole 401 to avoid the through hole 401.

[0205] For example, as shown in Figure 12, the distance between the second annular defining structure 340 and the light-emitting area 200 of the first color sub-pixel 210 is greater than the distance between the second annular defining structure 340 and the light-emitting areas 200 of other color sub-pixels.

[0206] For example, as shown in Figure 12, a first annular defining structure 330 and a second notch 341, or a first annular defining structure 330 and a second annular defining structure 340, or a first notch 331 and a second annular defining structure 340, can be provided between the light-emitting area 200 of the first color sub-pixel 210 and the light-emitting area 200 of the third color sub-pixel 230. For example, a first annular defining structure 330 and a second notch 341, or a first annular defining structure 330 and a second annular defining structure 340, or a first notch 331 and a second annular defining structure 340, can be provided between the light-emitting area 200 of the first color sub-pixel 210 and the light-emitting area 200 of the third color sub-pixel 230.

[0207] By setting the relative positional relationships between the light-emitting areas 200 of the first color sub-pixel 210, the second color sub-pixel 220, and the third color sub-pixel 230 and the first annular limiting structure 330, the second annular limiting structure 340, the first notch 331, and the second notch 341, it is beneficial to reduce crosstalk between different color sub-pixels while achieving a larger conductive path for the second electrode 242.

[0208] Figure 16 is a partial planar schematic diagram of an array substrate provided according to another example of an embodiment of the present disclosure. The array substrate shown in Figure 16 differs from the array substrate shown in Figure 12 in that the shape of the defining structure 300 surrounding the light-emitting area 200 of the second color sub-pixel 220 and the light-emitting area 200 of the third color sub-pixel 230 is different. The defining structure 300 shown in Figure 16 may have the cross-sectional shape shown in any of the examples shown in Figures 13 to 15.

[0209] In some examples, as shown in FIG16, the defining structure 300 includes a third annular defining structure 350 surrounding the light-emitting area 200 of the second color sub-pixel 220 and a fourth annular defining structure 360 ​​surrounding the light-emitting area 200 of the third color sub-pixel 230. The third annular defining structure 350 is shaped as a non-closed ring with a third notch 351, and the fourth annular defining structure 360 ​​is shaped as a non-closed ring with a fourth notch 361. The third notch 351 faces at least one of the first annular defining structure 330 and the fourth annular defining structure 360, and the fourth notch 361 faces at least one of the first annular defining structure 330 and the third annular defining structure 350.

[0210] By setting a third annular defining structure 350 around the light-emitting area 200 of the second color sub-pixel 220 and a fourth annular defining structure 360 ​​around the light-emitting area 200 of the third color sub-pixel 230, and each annular defining structure includes a notch that faces other annular defining structures, it is beneficial to reduce crosstalk between the second color sub-pixel 220 and the third color sub-pixel 230, while also reducing crosstalk between the second color sub-pixel 220 and the third color sub-pixel 230 and the first color sub-pixel 210, and ensuring that the second electrode 242 has a large conductive path.

[0211] For example, as shown in Figure 16, the distance between the third annular defining structure 350 and the light-emitting area 200 of the second color sub-pixel 220 is smaller than the distance between the third annular defining structure 350 and the light-emitting area 200 of other color sub-pixels, and the distance between the fourth annular defining structure 360 ​​and the light-emitting area 200 of the third color sub-pixel 230 is smaller than the distance between the fourth annular defining structure 360 ​​and the light-emitting area 200 of other color sub-pixels.

[0212] For example, as shown in Figure 16, a first annular defining structure 330 and a third annular defining structure 350, or a first annular defining structure 330 and a third notch 351, or a first notch 331 and a third annular defining structure 350, can be provided between the light-emitting area 200 of the first color sub-pixel 210 and the light-emitting area 200 of the third color sub-pixel 230. For example, a first annular defining structure 330 and a fourth annular defining structure 360, or a first annular defining structure 330 and a fourth notch 361, or a first notch 331 and a fourth annular defining structure 360, can be provided between the light-emitting area 200 of the first color sub-pixel 210 and the light-emitting area 200 of the third color sub-pixel 230.

[0213] For example, as shown in Figure 16, both the third notch 351 and the fourth notch 361 can be set at the via 401 to avoid the via 401.

[0214] Figures 17 and 18 are partial planar schematic diagrams of array substrates provided according to different examples of embodiments of the present disclosure. Figure 19 is a partial cross-sectional schematic diagram along DD' shown in Figure 17.

[0215] Figures 17 and 18 are described using the arrangement of the light-emitting areas 200 shown in Figure 1 as an example, but are not limited thereto. The arrangement of the light-emitting areas 200 shown in Figures 17 and 18 can also be replaced by the arrangements of the light-emitting areas 200 shown in Figures 4 and 6 to 9. The difference between the array substrates shown in Figures 17 and 18 is the ratio of the number of sub-pixel groups 20 to spacers 700.

[0216] In some examples, as shown in Figures 17 to 19, the array substrate further includes a plurality of spacers 700 (PS) located on the side of the first electrode 241 of the light-emitting element 240 in the sub-pixel group 20 away from the substrate 01. For example, the spacers 700 are located on the side of the pixel defining portion 620 away from the substrate 01. For example, the spacers 700 are used to support the fine metal mask when a non-common layer, such as a light-emitting layer, is deposited to form the light-emitting functional layer 243 of the sub-pixel.

[0217] In some examples, as shown in Figures 17 and 18, the ratio of the number of multiple sub-pixel groups 20 to the number of multiple spacers 700 is 4:1 or 2:1.

[0218] By setting the ratio of sub-pixel group 20 to spacer 700 to 4:1 or 2:1, it is beneficial to ensure the supporting effect of spacer 700 on fine metal mask while preventing excessive spacer 700 from scratching and affecting the display.

[0219] For example, as shown in Figures 17 to 19, the spacer 700 and the pixel limiting portion 620 can be formed of different materials or the same material, and there is no clear boundary between them.

[0220] In some examples, as shown in Figures 17 and 18, a spacer 700 is surrounded by four sub-pixel groups 20, which include a first sub-pixel group 21 and a second sub-pixel group 22 located on both sides of a spacer 700 in the third direction. A straight line passing through the center of the spacer 700 and extending in the third direction passes through the light-emitting area 200 of the first color sub-pixel 210 in the first sub-pixel group 21 and the light-emitting areas 200 of the second color sub-pixel 220 and the third color sub-pixel 230 in the second sub-pixel group 22.

[0221] A large distance is set between the first sub-pixel group 21 and the second sub-pixel group 22 arranged in a third direction, such as a large distance is set between the light-emitting area 200 of the first color sub-pixel 210 in the first sub-pixel group 21 and the light-emitting area 200 of the second color sub-pixel 220 in the second sub-pixel group 22, so as to set the spacer 700.

[0222] For example, as shown in Figure 17, the spacers 700 are arranged in an array along a first direction and a second direction. For example, two columns of sub-pixel groups 20 are arranged between two adjacent spacers 700 in the first direction, and two rows of sub-pixel groups 20 are arranged between two adjacent spacers 700 in the second direction, such as the spacers 700 being spaced apart. In this embodiment, the sub-pixel groups 20 arranged along the first direction are taken as a row of sub-pixel groups 20, and the sub-pixel groups 20 arranged along the second direction are taken as a column of sub-pixel groups 20.

[0223] For example, as shown in Figure 18, a row of spacers 700 is provided between any two rows of sub-pixel groups 20, and a column of spacers 700 is provided between any two columns of sub-pixel groups 20. The adjacent rows of spacers 700 are staggered in the first direction, such as the spacers 700 being staggered.

[0224] Figure 20 is a schematic block diagram of a display device according to another embodiment of the present disclosure. As shown in Figure 20, a display device provided in an embodiment of the present disclosure includes any of the array substrates described above.

[0225] For example, a display device may or may not have a color filter layer.

[0226] For example, the display device also includes a cover plate located on the light-emitting side of the array substrate.

[0227] For example, the display device can be an organic light-emitting diode display device or other display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator that includes the display device. This embodiment is not limited to this.

[0228] The following points need to be explained:

[0229] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0230] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0231] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. An array substrate, comprising: Substrate; Multiple data lines are located on the substrate, the multiple data lines are arranged along a first direction and extend along a second direction, the first direction and the second direction intersect; Multiple sub-pixel groups are located on the substrate and are arranged in an array along the first direction and the second direction. At least some of the sub-pixel groups include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel in each sub-pixel group. In the same sub-pixel group, at least the light-emitting area of ​​the first color sub-pixel extends along a third direction, the second color sub-pixel and the third color sub-pixel are arranged along the third direction, and the arrangement direction of the second color sub-pixel and the first color sub-pixel intersects with the third direction, and the angle between the third direction and the second direction is 20 to 70 degrees. In adjacent sub-pixel groups arranged along the second direction, the light-emitting area of ​​at least one of the second color sub-pixel and the third color sub-pixel in one sub-pixel group overlaps with the orthographic projection of the light-emitting area of ​​the first color sub-pixel in another sub-pixel group on a straight line extending along the fourth direction, which is perpendicular to the third direction.

2. The array substrate according to claim 1, wherein, In the same sub-pixel group, the area of ​​the light-emitting region of the second color sub-pixel and the area of ​​the light-emitting region of the third color sub-pixel are both smaller than the area of ​​the light-emitting region of the first color sub-pixel; The light-emitting areas of the second color sub-pixel and the third color sub-pixel both extend along the third direction.

3. The array substrate according to claim 1, further comprising: The defined structure must be located at least between the light-emitting areas of two adjacent sub-pixels. The defining structure includes a first defining structure located between the light-emitting area of ​​at least one of the second color sub-pixel and the third color sub-pixel and the light-emitting area of ​​the first color sub-pixel, the first defining structure extending along the third direction.

4. The array substrate according to claim 1, wherein, In the same sub-pixel group, the light-emitting area of ​​the first color sub-pixel includes a first side and a second side extending along the third direction, the length of the first side is greater than the length of the second side, and the first side is located between the second side and the light-emitting area of ​​the second color sub-pixel; The light-emitting area of ​​the first color sub-pixel further includes a third side extending along the second direction, and the light-emitting area of ​​one of the second color sub-pixel and the third color sub-pixel includes a fourth side extending along the second direction; The third side and the fourth side are respectively located in two adjacent sub-pixel groups in the first direction.

5. The array substrate according to claim 2 or 3, wherein, In adjacent sub-pixel groups arranged along the second direction, the center line of the light-emitting area of ​​the first color sub-pixel in one sub-pixel group extending along the third direction passes through the light-emitting areas of the second color sub-pixel and the third color sub-pixel in another sub-pixel group.

6. The array substrate according to any one of claims 2-3 and 5, wherein, In adjacent sub-pixel groups arranged along the first direction, the light-emitting area of ​​one of the second color sub-pixels and the third color sub-pixels in one sub-pixel group overlaps with the orthographic projection of the light-emitting area of ​​the first color sub-pixel in another sub-pixel group onto a straight line extending along the third direction.

7. The array substrate according to any one of claims 2-3 and 5-6, wherein, Each sub-pixel in the at least part of the sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer and a second electrode stacked together. The first electrode is located between the light-emitting functional layer and the substrate, and an insulating layer is disposed between the first electrode and the pixel circuit. The first electrode is electrically connected to the pixel circuit through a via in the insulating layer. The first electrode of the first color sub-pixel includes an electrode center located in its central region, which overlaps with the via along a direction perpendicular to the substrate.

8. The array substrate according to claim 7, wherein, The first electrode includes multiple electrode layers, with at least one electrode layer overlapping the via along a direction perpendicular to the substrate.

9. The array substrate according to claim 8, wherein, In at least one sub-pixel group, the light-emitting area of ​​the first color sub-pixel includes multiple sub-light-emitting areas, and the sub-light-emitting areas do not overlap with the via along a direction perpendicular to the substrate.

10. The array substrate according to claim 9, wherein, In the same first color sub-pixel, the orthogonal projection of the light-emitting area on the substrate surrounds the orthogonal projection of the via on the substrate.

11. The array substrate according to claim 9, wherein, In the same first color sub-pixel, the plurality of sub-light-emitting areas are spaced apart, and the orthogonal projection of the via on the substrate is located within the interval between the orthogonal projections of the plurality of sub-light-emitting areas on the substrate.

12. The array substrate according to claim 11, wherein, Within the same first color sub-pixel, the plurality of sub-light-emitting regions include two sub-light-emitting regions, the interval between the two sub-light-emitting regions is elongated, and the width of the interval is equal at different positions.

13. The array substrate according to claim 11, wherein, In the same first color sub-pixel, the plurality of sub-light-emitting areas include two sub-light-emitting areas, and the interval between the two sub-light-emitting areas includes at least a first sub-interval and a second sub-interval. The maximum size of the first sub-interval in the first direction is greater than the maximum size of the second sub-interval in the first direction, and the orthographic projection of the via on the substrate is located within the orthographic projection of the first sub-interval on the substrate.

14. The array substrate according to claim 13, wherein, The interval includes two second sub-intervals, the first sub-interval is located between the two second sub-intervals, and the first sub-interval and the second sub-intervals are arranged along the second direction.

15. The array substrate according to any one of claims 8-14, wherein, The multilayer electrode layer includes a light-transmitting electrode layer along a direction perpendicular to the substrate. Only the light-transmitting electrode layer overlaps with the via in the multilayer electrode layer, and the light-transmitting electrode layer is electrically connected to the pixel circuit through the via.

16. The array substrate according to claim 4, wherein, The light-emitting area of ​​the first color sub-pixel also includes a fifth side extending along the first direction, and the light-emitting area of ​​the other of the second color sub-pixel and the third color sub-pixel includes a sixth side extending along the first direction; The fifth side and the sixth side are respectively located in two adjacent sub-pixel groups in the second direction.

17. The array substrate according to claim 4 or 16, wherein, Each sub-pixel in the at least part of the sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer and a second electrode stacked together. The first electrode is located between the light-emitting functional layer and the substrate and is electrically connected to the pixel circuit. The first electrode of the first color sub-pixel includes a first main electrode and a first connecting electrode connected to each other. The first main electrode overlaps with the light-emitting area of ​​the first color sub-pixel. At least a portion of the first connecting electrode extends along the second direction. In the same sub-pixel group, the light-emitting area of ​​one of the second color sub-pixel and the third color sub-pixel overlaps with the orthographic projection of the first connecting electrode on a straight line extending along the second direction.

18. The array substrate according to claim 17, wherein, The first electrode of the third color sub-pixel includes a second main electrode and a second connecting electrode connected to each other. The second main electrode overlaps with the light-emitting area of ​​the third color sub-pixel. At least a portion of the second connecting electrode extends along the second direction. In the same sub-pixel group, the light-emitting area of ​​the second color sub-pixel overlaps with the orthographic projection of the second connecting electrode on a straight line extending along the second direction.

19. The array substrate according to claim 18, wherein, In the same sub-pixel group, the distance between the first connecting electrode and the second connecting electrode is greater than the maximum size of the third main electrode of the second color sub-pixel in the first direction.

20. The array substrate according to any one of claims 17-19, wherein, An insulating layer is provided between the first electrode and the pixel circuit, and the first electrode is electrically connected to the pixel circuit through a via in the insulating layer. Multiple vias corresponding to the first electrodes of multiple sub-pixels in the same sub-pixel group are arranged along the first direction, and the multiple vias are located between the light-emitting areas of adjacent sub-pixel groups arranged along the second direction.

21. The array substrate according to any one of claims 4 and 16-20, wherein, At least one of the following is greater than 4: the number of edges included in the luminous region of the first color sub-pixel, the number of edges included in the luminous region of the second color sub-pixel, and the number of edges included in the luminous region of the third color sub-pixel.

22. The array substrate according to any one of claims 4 and 16-21, wherein, The maximum size of the light-emitting area of ​​one of the second color sub-pixels and the third color sub-pixel in the second direction is greater than the maximum size in the first direction.

23. The array substrate according to any one of claims 4 and 16-22, wherein, In the same sub-pixel group, the light-emitting area of ​​the second color sub-pixel includes two sides extending along the third direction and having different lengths, wherein the longer side is located between the other side and the light-emitting area of ​​the first color sub-pixel. In the same sub-pixel group, the light-emitting area of ​​the third color sub-pixel includes two sides extending along the third direction and having different lengths, wherein the longer side is located between the other side and the light-emitting area of ​​the first color sub-pixel.

24. The array substrate according to claim 3, wherein, The limiting structure further includes a second limiting structure, which is located between the light-emitting area of ​​one of the second color sub-pixels and the third color sub-pixel and the light-emitting area of ​​the first color sub-pixel, and the second limiting structure extends along the fourth direction.

25. The array substrate according to claim 3 or 24, wherein, Each sub-pixel in the at least part of the sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer and a second electrode stacked together. The first electrode is located between the light-emitting functional layer and the substrate, and an insulating layer is disposed between the first electrode and the pixel circuit. The first electrode is electrically connected to the pixel circuit through a via in the insulating layer. Along a direction perpendicular to the substrate, the defining structure does not overlap with the via.

26. The array substrate according to any one of claims 3 and 24-25, wherein, The defining structure includes a first annular defining structure surrounding the light-emitting area of ​​the first color sub-pixel, wherein the first annular defining structure is a non-closed ring with a first notch.

27. The array substrate according to claim 26, wherein, The defining structure further includes a second annular defining structure surrounding the light-emitting areas of the second color sub-pixel and the third color sub-pixel in the same sub-pixel group. The second annular defining structure is a non-closed ring with a second notch, and the first annular defining structure is disposed between the second notch and the light-emitting area of ​​the first color sub-pixel.

28. The array substrate according to claim 26, wherein, The defining structure includes a third annular defining structure surrounding the light-emitting area of ​​the second color sub-pixel and a fourth annular defining structure surrounding the light-emitting area of ​​the third color sub-pixel. The third annular defining structure is a non-closed ring with a third notch, and the fourth annular defining structure is a non-closed ring with a fourth notch. The third notch faces at least one of the first annular defining structure and the fourth annular defining structure, and the fourth notch faces at least one of the first annular defining structure and the third annular defining structure.

29. The array substrate according to claim 3, wherein, Each sub-pixel in the at least part of the sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer and a second electrode stacked together. The first electrode is located between the light-emitting functional layer and the substrate. The array substrate further includes: A planarization layer is located between the first electrode and the substrate. The pixel-defined pattern is located on the side of the first electrode away from the substrate. The pixel-defined pattern includes a plurality of pixel-defined openings and a pixel-defined portion surrounding the plurality of pixel-defined openings. Each sub-pixel corresponds to at least one pixel-defined opening. The light-emitting element of the sub-pixel is at least partially located in the pixel-defined opening corresponding to the sub-pixel, and the pixel-defined opening is configured to define the light-emitting area of ​​the sub-pixel. The defining structure is located on the side of the pixel defining portion and the planarization layer away from the substrate.

30. The array substrate according to claim 3, wherein, Each sub-pixel in the at least part of the sub-pixel group includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The light-emitting element includes a first electrode, a light-emitting functional layer and a second electrode stacked together. The first electrode is located between the light-emitting functional layer and the substrate. The array substrate further includes: A planarization layer is located between the first electrode and the substrate. The pixel-defined pattern is located on the side of the first electrode away from the substrate. The pixel-defined pattern includes a plurality of pixel-defined openings and a pixel-defined portion surrounding the plurality of pixel-defined openings. Each sub-pixel corresponds to at least one pixel-defined opening. The light-emitting element of the sub-pixel is at least partially located in the pixel-defined opening corresponding to the sub-pixel, and the pixel-defined opening is configured to define the light-emitting area of ​​the sub-pixel. The defining structure includes a groove located in the pixel defining portion, or the defining structure includes an opening extending through the pixel defining portion.

31. The array substrate according to claim 29 or 30, wherein, The light-emitting functional layer includes multiple film layers, and the defining structure is configured to isolate at least one of the light-emitting functional layers, or the defining structure is configured to increase the length of the conductive path of at least one of the light-emitting functional layers.

32. The array substrate according to any one of claims 1-31, further comprising: Multiple spacers are located on the side of the sub-pixel group where the first electrode of the light-emitting element is away from the substrate. The ratio of the number of the plurality of sub-pixel groups to the plurality of spacers is 4:1 or 2:

1.

33. The array substrate according to claim 32, wherein, A spacer is surrounded by four sub-pixel groups, the four sub-pixel groups including a first sub-pixel group and a second sub-pixel group located on both sides of the spacer in the third direction, a straight line passing through the center of the spacer and extending along the third direction, passing through the light-emitting area of ​​the first color sub-pixel in the first sub-pixel group and the light-emitting area of ​​the second color sub-pixel and the light-emitting area of ​​the third color sub-pixel in the second sub-pixel group.

34. A display device comprising an array substrate as described in any one of claims 1-33.

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