Display panel and display device

Abstract

The present application relates to a display panel and a display device. The display panel is provided with a plurality of first contact holes corresponding to a plurality of first data lines, the first data lines extend into the first contact holes and are connected to pixel driving circuits, and first fan-out lines extend into the first contact holes and are connected to the corresponding first data lines.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202411930453.4, filed with the Chinese Patent Office on December 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] To better achieve narrow bezels in display products, related technologies employ a technique of placing some fanout traces in the display area (Fanout In AA, FIAA). FIAA places some fanout traces in the display area, structurally saving the fanout area wiring space required for the bottom bezel and further compressing the bottom bezel.

[0004] Currently, as shown in Figure 1, in display panels with a FIAA architecture, in order to connect the horizontally extending fan-out traces FIAA with the data lines DATA, overlapping protrusions TU are often reserved on the data lines DATA and connected to the horizontally extending fan-out traces FIAA through sleeve holes. Furthermore, the data lines DATA are connected to the semiconductor layer BA through contact holes KO at the position of the switching transistors. This increases the load on the horizontally extending fan-out traces FIAA and reduces the spacing between traces, increasing the risk of short circuits between traces. Invention Overview

[0005] This application provides a display panel and display device that reduces the load on the first fan-outline, increases wiring space, and reduces the probability of short circuits.

[0006] This application provides a display panel, which includes multiple pixel areas and multiple pixel driving circuits disposed corresponding to the multiple pixel areas;

[0007] The display panel also includes:

[0008] substrate;

[0009] A first metal layer is disposed on one side of the substrate, and the first metal layer includes a plurality of first fan-out lines located in the display area of ​​the display panel;

[0010] A second metal layer is disposed on the side of the first metal layer away from the substrate, and the second metal layer includes a plurality of first data lines that are connected to at least a portion of the plurality of first fan-out lines.

[0011] The display panel has multiple first contact holes corresponding to the multiple first data lines. The first data lines extend into the first contact holes and are connected to the pixel driving circuit. The first fan-out line extends into the first contact hole and is connected to the corresponding first data line.

[0012] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display device, the display device including a display panel, the display panel including a plurality of pixel areas and a plurality of pixel driving circuits disposed corresponding to the plurality of pixel areas;

[0013] The display panel also includes:

[0014] substrate;

[0015] A first metal layer is disposed on one side of the substrate, and the first metal layer includes a plurality of first fan-out lines located in the display area of ​​the display panel;

[0016] A second metal layer is disposed on the side of the first metal layer away from the substrate, and the second metal layer includes a plurality of first data lines that are connected to at least a portion of the plurality of first fan-out lines.

[0017] The display panel has multiple first contact holes corresponding to the multiple first data lines. The first data lines extend into the first contact holes and are connected to the pixel driving circuit. The first fan-out line extends into the first contact hole and is connected to the corresponding first data line. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 is a schematic diagram of the planar wiring distribution structure of a display panel provided in one embodiment;

[0021] Figure 2 is a schematic diagram of a planar distribution structure of a display panel provided in an embodiment of this application;

[0022] Figure 3 is a schematic diagram of a connection structure between the first fan-out line and the first data line provided in an embodiment of this application;

[0023] Figure 4 is a schematic diagram of the cross-sectional structure obtained along line aa in Figure 3 according to an embodiment of this application;

[0024] Figure 5 is a circuit structure diagram of a pixel driving circuit provided in an embodiment of this application;

[0025] Figure 6 is a schematic diagram of a planar distribution structure of the pixel driving circuit at point Z in Figure 2 provided in an embodiment of this application;

[0026] Figure 7 is a schematic diagram of a planar distribution structure of a semiconductor layer provided in an embodiment of this application;

[0027] Figure 8 is a schematic diagram of a planar distribution structure of the second metal layer and the third metal layer provided in an embodiment of this application;

[0028] Figure 9 is a schematic diagram of a connection structure between the first fan-out line and the second data line in an embodiment of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 10. Substrate; 101. Display area; 102. Non-display area; 1101. Pixel area; 11. Pixel driving circuit; 12. First spacer layer; 13. Second spacer layer; 14. Third spacer layer;

[0031] 20. Semiconductor layer; 201. First contact hole; 202. Second contact hole; 21. Switch active part; 22. Drive active part; 23. First light emission control active part; 24. First reset active part; 25. Second light emission control active part; 26. Second reset active part; 27. Third reset active part;

[0032] 30. First metal layer; 31. First sector outgoing line; 311. First sector outgoing line segment; 312. Second sector outgoing line segment; 32. First control signal line; 33. First reset signal line; 34. Second reset signal line; 35. Second control signal line; 36. Power signal line;

[0033] 40. Second metal layer; 41. First data line;

[0034] 50. Third metal layer; 51. Second fan-out cable; 52. Second data cable; 53. Adapter section;

[0035] 60. Gate layer; 61. Light emission control signal line; 62. Gate; 63. Connector;

[0036] 70. Signal terminal. Embodiments of the present invention

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0038] Referring to Figures 2, 3, and 4, this application embodiment provides a display panel, which includes a plurality of pixel areas 1011 and a plurality of pixel driving circuits 11 disposed corresponding to the plurality of pixel areas 1011.

[0039] The display panel further includes a substrate 10, a first metal layer 30, and a second metal layer 40; the first metal layer 30 is disposed on one side of the substrate 10, and the first metal layer 30 includes a plurality of first fan-out lines 31 located in the display area 101 of the display panel; the second metal layer 40 is disposed on the side of the first metal layer 30 away from the substrate 10, and the second metal layer 40 includes a plurality of first data lines 41 corresponding to and connected to the plurality of first fan-out lines 31.

[0040] The display panel has multiple first contact holes 201 corresponding to multiple first data lines 41. The first data lines 41 extend into the first contact holes 201 and are connected to the pixel driving circuit 11. The first fan-out line 31 extends into the first contact holes 201 and is connected to the corresponding first data line 41.

[0041] In the implementation process, this embodiment of the application extends the first fan-out line 31 into the first contact hole 201 of the first data line 41 and the pixel driving circuit 11, and connects it with the first data line 41 to realize signal transmission. It does not require additional overlapping protrusions and sleeve holes for the corresponding data lines, which can reduce the load on the first fan-out line 31 and increase the wiring space in the display panel. This increases the spacing between signal lines, reduces the probability of short circuits between signal lines, and improves the stability of the display panel.

[0042] In one embodiment of this application, the pixel driving circuit includes a switching transistor, and the display panel further includes:

[0043] A semiconductor layer is disposed between the substrate and the first metal layer. The semiconductor layer includes a switching active portion of the switching transistor. The first data line extends into the first contact hole and connects to the switching active portion.

[0044] In one embodiment of this application, a plurality of pixel regions are arranged along a first direction and a second direction, the first direction and the second direction intersect, a plurality of first data lines are arranged along the first direction, the first data lines extend along the second direction, and the active part of the switch extends along the second direction.

[0045] The fan-out line includes a first fan-out line segment extending along the first direction. The orthographic projection of the first fan-out line segment on the substrate overlaps with the orthographic projection of the corresponding first data line on the substrate. The orthographic projection of the active switch portion on the substrate partially overlaps with the orthographic projection of the corresponding first data line on the substrate.

[0046] In one embodiment of this application, the fan-out line further includes a second fan-out line segment extending along the second direction, one end of the second fan-out line segment being connected to the first fan-out line segment, and the other end of the second fan-out line segment extending into the first contact hole and being connected to the corresponding first data line.

[0047] In one embodiment of this application, the second fan-out line segment at least partially overlaps with the active portion of the switch along the second direction, and the orthographic projection of the second fan-out line segment on the substrate partially overlaps with the orthographic projection of the first data line on the substrate.

[0048] In one embodiment of this application, the pixel driving circuit further includes a driving transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first node, a second node, a third node, and a fourth node.

[0049] The semiconductor layer includes a driving active portion of the driving transistor, a first light-emitting control active portion of the first light-emitting control transistor, a second light-emitting control active portion of the second light-emitting control transistor, a first reset active portion of the first reset transistor, a second reset active portion of the second reset transistor, and a third reset active portion of the third reset transistor.

[0050] In this configuration, the first light-emitting control active portion extends along the second direction and is connected to the switching active portion at the first node. One end of the driving active portion is connected to the first node, and the other end of the driving active portion along the first direction is connected to the second node. The first reset active portion and the second light-emitting control active portion are located on opposite sides of the second node along the second direction and are both connected to the second node. The side of the second light-emitting control active portion away from the second node is connected to the third node. The third reset active portion is connected to the third node. The second reset active portion is located along the second direction on the side of the first reset active portion away from the second node, and the end of the first reset active portion away from the second node is connected to the second reset active portion and connected to the fourth node. The gate of the driving active portion is electrically connected to the fourth node.

[0051] In one embodiment of this application, the first metal layer further includes a first control signal line extending along the first direction, wherein the orthographic projection of the first control signal line on the substrate overlaps with the orthographic projection of the active switch portion on the substrate, and the orthographic projection of the first control signal line on the substrate overlaps with the orthographic projection of the first reset active portion on the substrate.

[0052] Wherein, the orthographic projection of the first contact hole on the substrate is located between the orthographic projection of the first fan-out line segment on the substrate and the orthographic projection of the first control signal line on the substrate.

[0053] In one embodiment of this application, the first metal layer further includes a first reset signal line extending along the first direction, the first reset signal line being connected to the second reset active portion, and the first fan-out segment being located between the first control signal line and the first reset signal line.

[0054] In one embodiment of this application, the display panel further includes:

[0055] A third metal layer is disposed between the second metal layer and the first metal layer. The third metal layer includes a second fan-out line. One end of the first fan-out line segment is connected to the second fan-out line segment, and the other end of the first fan-out line segment is connected to the second fan-out line.

[0056] The signal terminal is located in the non-display area of ​​the display panel. One end of the second fan-out line is connected to the first fan-out line segment, and the other end of the second fan-out line is connected to the signal terminal.

[0057] The second fan-out line extends along the second direction, and the orthographic projection of the second fan-out line on the substrate is located between the orthographic projection of the switch active part on the substrate and the orthographic projection of the first reset active part on the substrate.

[0058] In one embodiment of this application, corresponding to the same pixel area, the first node and the second node are located on opposite sides of the second fan-out line, and the second node, the third node, and the fourth node are located on the same side of the second fan-out line.

[0059] In one embodiment of this application, the third metal layer further includes a second data line extending along the second direction, with a portion of the active switch portion in the pixel driving circuit connected to the first data line and another portion of the active switch portion in the pixel driving circuit connected to the second data line.

[0060] In one embodiment of this application, a portion of the plurality of first fan-out lines is connected to the second data line;

[0061] The display panel also includes a second contact hole corresponding to the second data line. The second data line is connected to the active part of the switch through the second contact hole, and the first fan-out line extends into the second contact hole and is connected to the second data line.

[0062] In one embodiment of this application, within the second contact hole, the first fan-out line covers the side of the active switch portion away from the substrate, and the second data line covers the side of the first fan-out line away from the active switch portion.

[0063] In one embodiment of this application, within the first contact hole, the first fan-out line covers the side of the active switch portion away from the substrate, and the first data line covers the side of the first fan-out line away from the active switch portion.

[0064] In one embodiment of this application, the two pixel driving circuits in two adjacent pixel regions along the first direction are arranged symmetrically.

[0065] Specifically, referring to Figures 2, 3, and 4, the display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101; the display area 101 contains a plurality of pixel areas 1011, and the plurality of pixel areas 1011 can be arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect.

[0066] In some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0067] Furthermore, the display panel includes a substrate 10 and a thin-film transistor layer disposed on the substrate 10. The thin-film transistor layer includes a semiconductor layer 20, a gate layer, a first metal layer 30, a second metal layer 40, and a third metal layer 50 disposed on the substrate 10.

[0068] In some embodiments, the first metal layer 30 is located on the side of the semiconductor layer 20 away from the substrate 10, the second metal layer 40 is located on the side of the first metal layer 30 away from the semiconductor layer 20, and the third metal layer 50 is located between the first metal layer 30 and the second metal layer 40; the display panel further includes a first spacer layer 12 disposed between the semiconductor layer 20 and the first metal layer 30, a second spacer layer 13 disposed between the first metal layer 30 and the third metal layer 50, and a third spacer layer 14 disposed between the third metal layer 50 and the second metal layer 40.

[0069] It is understood that the gate layer may be located between the semiconductor layer 20 and the substrate 10; or the gate layer may be located between the semiconductor layer 20 and the first metal layer 30; or the gate layer may include a first gate sub-layer and a second gate sub-layer, with the first gate sub-layer located between the semiconductor layer 20 and the substrate 10, and the second gate sub-layer located between the semiconductor layer 20 and the first metal layer 30; or the gate layer may include a first gate sub-layer and a second gate sub-layer, with both the first gate sub-layer and the second gate sub-layer located between the semiconductor layer 20 and the first metal layer 30.

[0070] In this embodiment of the application, the second metal layer 40 includes a plurality of first data lines 41 arranged along the first direction, each first data line 41 extending along the second direction Y, and each data line 41 transmitting a signal to a corresponding column of pixel areas 1011 arranged along the second direction Y.

[0071] It should be noted that the display panel provided in this application embodiment adopts the FIAA architecture, that is, the fan-out traces connected to the first data line 41 are set within the display area 101 to achieve a narrow bezel; wherein, the first metal layer 30 includes multiple first fan-out traces 31, the third metal layer 50 includes multiple second fan-out traces 51, and at least a portion of the first fan-out traces 31 extend along the first direction X, the second fan-out traces 51 can extend along the second direction Y, and one first fan-out trace 31 is connected to one second fan-out trace 52, and the connected first fan-out trace 31 and one second fan-out trace 52 are connected to a corresponding first data line 41.

[0072] In some embodiments, the display panel further includes a signal terminal 70 disposed in the non-display area 102, and one end of the second fan-out line 52 is connected to the signal terminal 61, the other end of the second fan-out line 51 is connected to the first fan-out line 31, one end of the first fan-out line 31 is connected to the second fan-out line 51, and the other end of the first fan-out line 31 is connected to the corresponding first data line 41; so as to transmit the data signal to the corresponding first data line 41, and further transmit the data signal to the corresponding pixel area 1011 through the first data line 41.

[0073] The display panel includes pixel driving circuits 11 corresponding to multiple pixel areas 101, and the first data line 41 is connected to the pixel driving circuit 11 in the corresponding pixel area 1011 to transmit data signals to the corresponding pixel driving circuit 11; for example, each pixel area 101 is provided with a pixel driving circuit 11, and the pixel driving circuit 11 is provided with multiple thin film transistors located in the thin film transistor layer, and the thin film transistor layer also includes signal lines connecting the multiple thin film transistors.

[0074] The gate layer 60 includes a light emission control signal line 61 extending along the first direction X, and the first metal layer 30 includes a first control signal line 32 extending along the first direction X, a first reset signal line 33 extending along the first direction X, a second reset signal line 34 extending along the first direction X, a second control signal line 35 extending along the first direction X, and a power signal line 36 extending along the first direction X.

[0075] Specifically, referring to Figure 5, the pixel driving circuit 11 includes a switching transistor T1, a driving transistor T2, a first reset transistor T3, a second reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a third reset transistor T7, a first node A, a second node B, a third node C, and a fourth node Q.

[0076] The display panel includes a light-emitting device layer disposed in each of the pixel areas 101, and the light-emitting device layer is located on the side of the thin film transistor layer away from the substrate 10. The light-emitting device layer includes an anode, a light-emitting layer and a cathode stacked together, and the anode is connected to the thin film transistor.

[0077] The gate of the switching transistor T1 is connected to the first control signal line 32 and is connected to the first control signal SCAN. The switching transistor T1 is also connected to the first data line 41 and the first node A.

[0078] The gate of the driving transistor T2 is connected to the fourth node Q, and the driving transistor T2 is also connected to the first node A and the second node B.

[0079] The gate of the first reset transistor T3 is connected to the first control signal line 32 and is connected to the first control signal SCAN. The first reset transistor T3 is also connected to the second node B and the fourth node Q.

[0080] The gate of the second reset transistor T4 is connected to the second control signal line 35 and is connected to the second control signal SCAN_RST. The second reset transistor T4 is also connected to the fourth node Q and the first reset signal line 33, and the first reset signal VI_Gate is input through the first reset signal line 33.

[0081] The gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line 61 and is connected to the light-emitting control signal EM. The first light-emitting control transistor T5 is also connected to the power signal line 36 and the first node, and the power signal VDD is input through the power signal line 36.

[0082] The gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal 61 and is also connected to the light-emitting control signal EM. The second light-emitting control transistor T6 is also connected to the second node B and the third node C.

[0083] The gate of the third reset transistor T7 is connected to the second control signal line 35 and is connected to the second control signal SCAN_RST. The third reset transistor T7 is also connected to the second reset signal line 34 and the third node C, and the second reset signal VI_Ano is input from the second reset signal line 34.

[0084] The anode is connected to the third node C.

[0085] The pixel driving circuit 11 also includes a storage capacitor Cst connected between the power signal VDD and the fourth node Q.

[0086] In some embodiments, the first reset transistor T3 and the second reset transistor T4 may be dual-gate thin-film transistors to reduce the leakage current of the first reset transistor T3 and the second reset transistor T4.

[0087] Furthermore, please refer to Figures 5, 6, 7 and 8 for a detailed description of the wiring structure of the pixel driving circuit 11 in the embodiments of this application.

[0088] The semiconductor layer 20 includes a switching active portion 21 of the switching transistor T1, a driving active portion 22 of the driving transistor T2, a first light-emitting active portion 25 of the first light-emitting control transistor T5, a second light-emitting active portion 26 of the second light-emitting control transistor T6, a first reset active portion 23 of the first reset transistor T3, a second reset active portion 24 of the second reset transistor T4, and a third reset active portion 27 of the third reset transistor T7.

[0089] Both the active switching portion 21 and the first active light-emitting control portion 25 extend along the second direction Y, and are connected at the first node A. The orthographic projection of the first control signal line 32 on the substrate 10 overlaps with the orthographic projection of the active switching portion 21 on the substrate 10, and the overlapping portion of the first control signal line 32 is multiplexed as the gate of the switching transistor T1; the light-emitting control signal line 61 overlaps with the first active light-emitting control portion 25, and the overlapping portion of the light-emitting control signal line 61 is multiplexed as the gate of the first active light-emitting control transistor T5.

[0090] The active part of the switch 21, away from the first node A, is connected to the first data line 41 and inputs a data signal.

[0091] The end of the first light-emitting active unit 25 away from the first node A is connected to the power signal line 36 and inputs the power signal VDD.

[0092] One end of the driving active portion 22 is connected to the first node A, and the other end of the driving active portion 22 along the first direction X is connected to the second node B. The portion of the driving active portion 22 located between the first node A and the second node B is arranged in a U-shape. The gate layer 60 includes the gate 62 of the driving transistor T1. The U-shaped portion can be aligned with the gate 62 of the driving transistor T1 to form a channel. The gate 62 of the driving transistor T1 is connected to the fourth node Q.

[0093] The first reset active portion 23 and the second light-emitting control active portion 26 are located on opposite sides of the second node B along the second direction Y, and are both connected to the second node B. The first reset active portion 23 is connected between the second node B and the fourth node Q, and the first reset active portion 23 has a U-shaped portion. The orthographic projection of the U-shaped portion of the first reset active portion 23 on the substrate 10 overlaps with the orthographic projection of the first control signal line 32 on the substrate 10. The overlapping portion of the first control signal line 32 is multiplexed as the gate of the first reset transistor T3. Since the first control signal line 32 and the U-shaped first reset active portion 23 have two overlapping portions, the first reset transistor T3 has a dual-gate structure.

[0094] The side of the second light-emitting control active part 26 away from the second node B is connected to the third node C, and the orthographic projection of the second light-emitting control active part 26 on the substrate 10 overlaps with the orthographic projection of the light-emitting control signal line 61 on the substrate 10. The overlapping portion of the light-emitting control signal line 61 is multiplexed as the gate of the second light-emitting control transistor T6.

[0095] The third reset active part 27 is connected to the third node C. The third reset active part 27 is located along the second direction Y on the side of the second light-emitting control active part 26 away from the second node B. The orthographic projection of the third reset active part 27 on the substrate 10 overlaps with the orthographic projection of the second control signal line 35 on the substrate 10. The overlapping portion of the second control signal line 35 is multiplexed as the gate of the third reset transistor T7.

[0096] The end of the third reset active unit 27 away from the fourth node Q is connected to the second reset signal line 34 and inputs the second reset signal VI_Ano.

[0097] The first reset active portion 23, at one end away from the second node B, is connected to the second reset active portion 24 and to the fourth node Q. The second reset active portion 24 is located on the side of the first reset active portion 23 away from the fourth node Q. The gate layer 60 also includes a connection portion 63, one end of which is connected to the second control signal line 35. The other end of the connection portion 63 extends along the first direction X and overlaps with the second reset active portion 23. The portion of the connection portion 63 that overlaps with the second reset active portion 24 is multiplexed as the gate of the second reset transistor T4. Furthermore, a portion of the second reset active portion 24 is U-shaped, and the U-shaped second reset active portion 24 overlaps with the connection portion 63 in two places. Therefore, the second reset transistor T4 is a dual-gate structure.

[0098] One end of the second active reset unit 24 is connected to the first active reset unit 23, and the other end of the second active reset unit 24 is connected to the first reset signal line 33, so as to input the first reset signal VI_Gate to the second active reset unit 24.

[0099] The gate 62 of the driving active part 22 is electrically connected to the fourth node Q.

[0100] It should be noted that in some embodiments, the third metal layer 50 further includes a second data line 52 extending along the second direction Y, and for the plurality of pixel driving circuits 11, the active switching portion 21 in some of the pixel driving circuits 11 is connected to the first data line 41, and the active switching portion 21 in some of the pixel driving circuits 11 is connected to the second data line 52; for example, the plurality of pixel regions 1011 include red pixel regions, green pixel regions and blue pixel regions, wherein the active switching portion 21 of the pixel driving circuits 11 in the red pixel regions and green pixel regions is connected to the first data line 41, and the active switching portion 21 of the pixel driving circuits 11 in the blue pixel regions is connected to the second data line 52; thereby saving the wiring space of the second metal layer 40, increasing the spacing between adjacent traces in the second metal layer 40, and reducing signal interference and the probability of short circuits; and the following description in this application embodiment takes the first data line 41 as an example for description.

[0101] In this embodiment of the application, both the first data line 41 and the second data line 52 receive signal inputs through the first fan-out line 31 and the second fan-out line 51.

[0102] For the wiring connection structure of the first data line 41, the display panel includes a plurality of first contact holes 201 corresponding to the plurality of first data lines 41, and the first data line 41 extends into the corresponding first contact hole 201 and connects to the active switch part 21 in the pixel driving circuit 11.

[0103] Further, the first fan-out line 31 includes a first fan-out line segment 311 extending along the first direction X and a second fan-out line segment 312 extending along the second direction Y. One end of the first fan-out line segment 311 is connected to the second fan-out line 51, and the other end of the first fan-out line segment 311 is connected to the second fan-out line segment 312. One end of the second fan-out line segment 312 is connected to the first fan-out line segment 311, and the other end of the second fan-out line segment 312 extends into the first contact hole 201 and is connected to the first data line 41. That is, in this embodiment of the application, by changing the position of the first fan-out line 31, the first fan-out line 51... Line 31 is positioned close to the first contact hole 201, and can be connected to the first contact hole 201 by adding a second fan-out line segment 312 extending along the second direction Y, sharing the first contact hole 201 of the first data line 41 and the first contact hole 201 of the active part of the switch 21, thereby realizing the connection between the first fan-out line 31 and the first data line 41. Compared with the prior art, it can reduce the setting of vias, reduce the signal transmission path, and reduce the load of the first fan-out line 31; it can also reduce the setting of overlapping protrusions, increase wiring space, increase the spacing between signal lines, reduce the probability of short circuits between signal lines, and improve the stability of the display panel.

[0104] It should be noted that within the first contact hole 201, the first fan-out line 31 covers the side of the active switch portion 21 away from the substrate 10, and the first data line 41 covers the side of the first fan-out line 31 away from the active switch portion 21.

[0105] In some embodiments, the third metal layer 50 is located between the first metal layer 30 and the second metal layer 40, and the third metal layer 50 further includes a transition portion 53 extending into the first contact hole 201. Within the first contact hole 201, the first fan-out line 31 covers the side of the active switch portion 21 away from the substrate 10, the transition portion 53 covers the side of the first fan-out line 31 away from the active switch portion 21, and the first data line 41 covers the side of the transition portion 53 away from the first fan-out line 31. In this embodiment, the addition of the transition portion 53 can improve the overlap yield of the first data line 41 within the first contact hole 201 and reduce the probability of defects such as wire breakage due to the depth of the first contact hole 201.

[0106] In some embodiments, the orthographic projection of the first fan-out line segment 311 on the substrate 10 overlaps with the orthographic projection of the corresponding first data line 41 on the substrate 10; the second fan-out line segment 312 at least partially overlaps with the active switch portion 21 along the second direction Y, and the orthographic projection of the second fan-out line segment 312 on the substrate 10 partially overlaps with the orthographic projection of the first data line 41 on the substrate 10. That is, one end of the first fan-out line 31 is connected to the second fan-out line 51, and the other end of the first fan-out line 31 first extends along the first direction X to the point of intersection with the first data line 41, and then extends along the second direction Y into the first contact hole 201 to connect with the first data line 41.

[0107] In some embodiments, the orthographic projection of the first data line 41 on the substrate 10 partially overlaps with the orthographic projection of the active switch portion 21 on the substrate 10.

[0108] In some embodiments, the orthographic projection of the first contact hole 201 on the substrate 10 is located between the orthographic projection of the first fan-out segment 311 on the substrate 10 and the orthographic projection of the first control signal line 32 on the substrate 10; the first fan-out segment 311 is located between the first control signal line 32 and the first reset signal line 33.

[0109] In some embodiments, for the position of the second fan-out line 51, the second fan-out line 51 extends along the second direction Y, and the orthographic projection of the second fan-out line 51 on the substrate 10 is located between the orthographic projection of the switch active part 21 on the substrate 10 and the orthographic projection of the first reset active part 23 on the substrate 10. Further, corresponding to the same pixel region 101, the first node A and the second node B are located on opposite sides of the second fan-out line 52, and the second node B, the third node C, and the fourth node Q are located on the same side of the second fan-out line 52.

[0110] Furthermore, in some embodiments, please refer to Figure 9 for the connection between the first fan-out line 31 and the second data line 52; similarly, the display panel includes a second contact hole 202 corresponding to the second data line 52, and the second data line 52 is connected to the active switch portion 21 through the second contact hole 202; wherein, the second fan-out line 52 extends along the second direction Y and is connected to the first fan-out line 31, and the first fan-out line 31 can extend to the second data line 52 through the first fan-out line segment 311 extending along the first direction X, and extend into the second contact hole 202 where the second data line 52 is connected to the active switch portion 21 by the second fan-out line segment 312 extending along the second direction Y, so as to realize that the first fan-out line 31 is connected to the second data line 52 in the second contact hole 202.

[0111] Within the second contact hole 202, the first fan-out line 31 covers the side of the active switch portion 21 away from the substrate 10, and the second data line 52 covers the side of the first fan-out line 31 away from the active switch portion 21.

[0112] In some embodiments, two pixel driving circuits 11 are arranged symmetrically in two adjacent pixel regions 101 along the first direction X; further, two pixel driving circuits 11 that are adjacent along the first direction X and both connected to the first data line 41 are arranged symmetrically.

[0113] In this application embodiment, comparative examples and embodiments are provided to verify the pixel driving circuit structure shown in FIG1 and the pixel driving circuit structure shown in FIG6. The comparative example is the pixel driving circuit structure shown in FIG1, and the embodiment is the pixel driving circuit 11 shown in FIG6. The load and line spacing of the fan-out lines (first fan-out line 31, second fan-out line 51 or FIAA trace) in the comparative example and embodiment are verified to obtain the following Table 1.

[0114] Table 1

[0115] Comparative Example: Fan-out line load 16fF 14.8fF; Line spacing of the film layer containing the fan-out line 3µm 3.8µm

[0116] As can be seen from Table 1, the embodiments of this application can effectively reduce the load on the first fan-out line 31 and the second fan-out line 51, and can increase the wiring space and increase the line spacing in the first metal layer 30 and the third metal layer 50.

[0117] In summary, the embodiments of this application extend the first fan-out line 31 into the first contact hole 201 of the first data line 41 and the active part of the switch 21, and connect it to the first data line 41 to achieve signal transmission. This eliminates the need for additional overlapping protrusions and sleeve holes on the corresponding data lines, reduces the load on the first fan-out line 31, increases the wiring space in the display panel, increases the spacing between signal lines, reduces the probability of short circuits between signal lines, and improves the stability of the display panel.

[0118] In addition, this application embodiment also provides a display device, which includes the display panel described in the above embodiments.

[0119] It is understood that since the display device has the same display panel as the one described in the above embodiments, the display device has the same beneficial effects as the display panel described in the above embodiments, and will not be repeated here.

[0120] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0121] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0122] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0123] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

A display panel, comprising a plurality of pixel regions and a plurality of pixel driving circuits arranged corresponding to the plurality of pixel regions; The display panel further comprises: a substrate; a first metal layer arranged on one side of the substrate, the first metal layer comprising a plurality of first fan-out lines located in a display area of the display panel; a second metal layer arranged on a side of the first metal layer away from the substrate, the second metal layer comprising a plurality of first data lines connected corresponding to at least part of the plurality of first fan-out lines; wherein a plurality of first contact holes corresponding to the plurality of first data lines are formed in the display panel, the first data lines extend into the first contact holes and are connected with the pixel driving circuits, and the first fan-out lines extend into the first contact holes and are connected with the corresponding first data lines. The display panel of claim 1, wherein, The pixel driving circuit comprises a switching transistor, and the display panel further comprises: a semiconductor layer arranged between the substrate and the first metal layer, the semiconductor layer comprising a switching active part of the switching transistor, and the first data lines extend into the first contact holes and are connected with the switching active part. The display panel according to claim 2, wherein, The plurality of pixel regions are arranged along a first direction and a second direction, the first direction and the second direction intersect, the plurality of first data lines are arranged along the first direction, the first data lines extend along the second direction, and the switching active part extends along the second direction; The fan-out line comprises a first fan-out line segment extending along the first direction, a projection of the first fan-out line segment on the substrate and a projection of the corresponding first data line on the substrate overlap, and a projection of the switching active part on the substrate and a projection of the corresponding first data line on the substrate partially overlap. The display panel according to claim 3, wherein, The fan-out line further comprises a second fan-out line segment extending along the second direction, one end of the second fan-out line segment is connected with the first fan-out line segment, and the other end of the second fan-out line segment extends into the first contact hole and is connected with the corresponding first data line. The display panel according to claim 4, wherein, The second fan-out line segment and the switching active part at least partially overlap along the second direction, and a projection of the second fan-out line segment on the substrate and a projection of the first data line on the substrate partially overlap. The display panel according to claim 5, wherein, The pixel driving circuit further comprises a driving transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first node, a second node, a third node, and a fourth node; The semiconductor layer comprises a driving active part of the driving transistor, a first light-emitting control active part of the first light-emitting control transistor, a second light-emitting control active part of the second light-emitting control transistor, a first reset active part of the first reset transistor, a second reset active part of the second reset transistor, and a third reset active part of the third reset transistor; The first light-emitting control active part extends along the second direction and is connected to the switch active part at the first node, one end of the drive active part is connected to the first node, the opposite end of the drive active part along the first direction is connected to the second node, the first reset active part and the second light-emitting control active part are located on the opposite sides of the second node along the second direction and are connected to the second node, the second light-emitting control active part is connected to the third node on the side away from the second node, the third reset active part is connected to the third node, the second reset active part is located on the side of the first reset active part away from the second node along the second direction, and one end of the first reset active part away from the second node is connected to the second reset active part and the fourth node. The display panel according to claim 6, wherein The first metal layer further comprises a first control signal line extending along the first direction, a projection of the first control signal line on the substrate intersects with a projection of the switch active part on the substrate, and a projection of the first control signal line on the substrate intersects with a projection of the first reset active part on the substrate. A projection of the first contact hole on the substrate is located between a projection of the first fan-out line segment on the substrate and a projection of the first control signal line on the substrate. The display panel according to claim 7, wherein The first metal layer further comprises a first reset signal line extending along the first direction, the first reset signal line is connected to the second reset active part, and the first fan-out line segment is located between the first control signal line and the first reset signal line. The display panel according to claim 6, wherein The display panel further comprises: A third metal layer is arranged between the second metal layer and the first metal layer, the third metal layer comprises a second fan-out line, one end of the first fan-out line segment is connected to the second fan-out line segment, and the other end of the first fan-out line segment is connected to the second fan-out line. A signal terminal is arranged in a non-display area of the display panel, one end of the second fan-out line is connected to the first fan-out line segment, and the other end of the second fan-out line is connected to the signal terminal. The second fan-out line extends along the second direction, and a projection of the second fan-out line on the substrate is located between a projection of the switch active part on the substrate and a projection of the first reset active part on the substrate. The display panel according to claim 9, wherein, Corresponding to the same pixel area, the first node and the second node are located on opposite sides of the second fan-out line, and the second node, the third node and the fourth node are located on the same side of the second fan-out line. The display panel according to claim 9, wherein The third metal layer further comprises a second data line extending along the second direction, the switch active part in part of the pixel driving circuits is connected to the first data line, and the switch active part in another part of the pixel driving circuits is connected to the second data line. The display panel according to claim 11, wherein, Part of the first fan-out lines are connected to the second data line. The display panel further comprises a second contact hole corresponding to the second data line, the second data line is connected with the switch active part through the second contact hole, and the first fan-out line extends into the second contact hole and is connected with the second data line. The display panel according to claim 12, wherein, In the second contact hole, the first fan-out line covers one side of the switch active part away from the substrate, and the second data line covers one side of the first fan-out line away from the switch active part. The display panel according to claim 2, wherein, In the first contact hole, the first fan-out line covers one side of the switch active part away from the substrate, and the first data line covers one side of the first fan-out line away from the switch active part. The display panel according to any one of claims 3 to 14, wherein In the two pixel regions adjacent in the first direction, the two pixel drive circuits corresponding to the two pixel regions are arranged in axial symmetry. A display device comprises a display panel, the display panel comprises a plurality of pixel regions and a plurality of pixel drive circuits corresponding to the plurality of pixel regions; The display panel further comprises: a substrate; a first metal layer arranged on one side of the substrate, the first metal layer comprises a plurality of first fan-out lines in the display area of the display panel; a second metal layer arranged on one side of the first metal layer away from the substrate, the second metal layer comprises a plurality of first data lines connected with at least part of the plurality of first fan-out lines; wherein the display panel is provided with a plurality of first contact holes corresponding to the plurality of first data lines, the first data line extends into the first contact hole and is connected with the pixel drive circuit, and the first fan-out line extends into the first contact hole and is connected with the corresponding first data line. The display device according to claim 16, wherein The pixel drive circuit comprises a switch transistor, and the display panel further comprises: a semiconductor layer arranged between the substrate and the first metal layer, the semiconductor layer comprises a switch active part of the switch transistor, and the first data line extends into the first contact hole and is connected with the switch active part. The display device according to claim 17, wherein The plurality of pixel regions are arranged along a first direction and a second direction, the first direction and the second direction intersect, the plurality of first data lines are arranged along the first direction, the first data line extends along the second direction, and the switch active part extends along the second direction; The fan-out line comprises the first fan-out line segment extending along the first direction, the orthographic projection of the first fan-out line segment on the substrate and the orthographic projection of the corresponding first data line on the substrate overlap, and the orthographic projection of the switch active part on the substrate and the orthographic projection of the corresponding first data line on the substrate partially overlap. The display device according to claim 18, wherein The fan-out line further comprises a second fan-out line segment extending along the second direction, one end of the second fan-out line segment is connected with the first fan-out line segment, and the other end of the second fan-out line segment extends into the first contact hole and is connected with the corresponding first data line. The display device according to claim 19, wherein The second fan-out line segment and the switch active part at least partially overlap along the second direction, and the orthographic projection of the second fan-out line segment on the substrate and the orthographic projection of the first data line on the substrate partially overlap.

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