Display panel and display device

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display device. Non-display regions include first non-display regions and a second non-display region, wherein the second non-display region is located on one side of a display region in a first direction, and the first non-display regions are located on two opposite sides of the display region in a second direction. The display panel comprises: a plurality of drive control lines, the drive control lines extending in the first direction and being arranged in the second direction, wherein the first direction intersects the second direction; a plurality of data lines, the data lines extending in the second direction and being arranged in the first direction; and a plurality of multiplexing units located in the first non-display regions. Each multiplexing unit comprises one input terminal and N output terminals, the N output terminals being connected to N data lines, respectively, where N≥2. The input terminals of the multiplexing units are connected to first input lines; and the first input lines are at least partially located in the display region. The first input lines are configured to acquire data signals from bond pads. Thus, the narrow bezel design can be achieved for display products.

Description

A display panel and display device

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202411911603.7, filed on December 23, 2024, entitled “A Display Panel and Display Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0004] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0005] At present, how to reduce the bezel width of display products and increase the screen ratio has become one of the urgent technical problems to be solved. Summary of the Invention

[0006] To address the aforementioned technical issues, this disclosure provides a display panel and display device, aiming to achieve a narrow bezel design for the display panel and increase the screen-to-body ratio.

[0007] In a first aspect, this disclosure provides a display panel, including a display area and a non-display area located around the display area. The non-display area includes a first non-display area and a second non-display area, the second non-display area being located on one side of the display area along a first direction, and the first non-display area being located on opposite sides of the display area along a second direction. The second non-display area includes a bonding area, and the bonding area includes bonding pads. The display panel includes:

[0008] Multiple drive control lines extend along a first direction and are arranged along a second direction, with the first and second directions intersecting.

[0009] Multiple data lines, which extend along a second direction and are arranged along a first direction;

[0010] Multiple multiplexing units are located in the first non-display area. Each multiplexing unit includes one input terminal and N output terminals. The N output terminals are connected to N data lines, where N ≥ 2. The input terminal of the multiplexing unit is connected to a first input line. At least a portion of the first input line is located in the display area. The first input line is configured to acquire data signals from bonding pads.

[0011] Secondly, based on the same inventive concept, this disclosure provides a display device, including the display panel provided in the first aspect of this disclosure. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0013] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 is a plan view of a display panel provided in an embodiment of this disclosure;

[0015] Figure 2 shows a detailed view of the display panel described in Figure 1;

[0016] Figure 3 shows a schematic diagram of a pixel driving circuit applicable to an embodiment of the present disclosure.

[0017] Figure 4 shows a driving timing diagram corresponding to the pixel driving circuit in Figure 3;

[0018] Figure 5 is a schematic diagram of a film layer of a display panel provided in an embodiment of this disclosure;

[0019] Figure 6 shows a planar schematic diagram of a display panel in the related art;

[0020] Figure 7 shows a schematic diagram of the pixel driving circuit layout in an embodiment of this disclosure;

[0021] Figure 8 shows a relative positional relationship between the pixel driving circuit, driving control line, data line, and sub-pixels.

[0022] Figure 9 shows another plan view of the display panel provided in an embodiment of this disclosure;

[0023] Figure 10 shows a relative positional reference diagram of some of the first auxiliary lines and some of the first connecting lines in the display panel;

[0024] Figure 11 shows another planar schematic diagram of the display panel provided in an embodiment of this disclosure;

[0025] Figure 12 shows a relative positional reference diagram of some of the second auxiliary lines and some of the second connecting lines in the display panel;

[0026] Figure 13 shows a schematic diagram of a connection between a multiplexing unit and a data line;

[0027] Figure 14 shows a timing diagram of one of the multiplexing units in Figure 13.

[0028] Figure 15 shows a schematic diagram of a connection between a multiplexing unit and a data line;

[0029] Figure 16 shows a timing diagram of one of the multiplexing units in Figure 15.

[0030] Figure 17 shows another plan view of the display panel provided in an embodiment of this disclosure;

[0031] Figure 18 shows a schematic diagram of one arrangement of the second input line and the third auxiliary line L3;

[0032] Figure 19 shows a schematic diagram of a layout of the first and second input lines in the display panel;

[0033] Figure 20 shows another plan view of the display panel provided in an embodiment of this disclosure;

[0034] Figure 21 shows another plan view of the display panel provided in an embodiment of this disclosure;

[0035] Figure 22 shows another plan view of the display panel provided in an embodiment of this disclosure;

[0036] Figure 23 shows another plan view of the display panel provided in an embodiment of this disclosure;

[0037] Figure 24 shows a schematic diagram of a layout of power signal lines and gate drive circuit in a display panel.

[0038] Figure 25 shows a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0039] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0040] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0041] Figure 1 is a plan view of a display panel provided in an embodiment of this disclosure, illustrating the relative positions of the drive control line SL, data line DL, and multiplexing unit 90 included in the display panel. Figure 2 is a detailed view of the display panel shown in Figure 1, specifically detailing the structure and connection of the multiplexing unit 90 in Figure 1. Figure 3 is a circuit diagram of a pixel driving circuit applicable to an embodiment of this disclosure, and Figure 4 is a driving timing diagram corresponding to the pixel driving circuit in Figure 3.

[0042] Referring to Figures 1 and 2, this embodiment of the present disclosure provides a display panel 100, including a display area A0 and a non-display area A1 located around the display area A0. The non-display area A1 includes a first non-display area A11 and a second non-display area A12. The second non-display area A12 is located on one side of the display area A0 along a first direction D1, and the first non-display area A11 is located on opposite sides of the display area A0 along a second direction D2. The second display area A12 includes a bonding area A13, which includes bonding pads P0. Optionally, the display panel includes a plurality of pixel driving circuits as shown in Figure 3. Referring to Figures 3 and 4, the pixel driving circuits are used to electrically connect with the light-emitting element 30 to drive the light-emitting element 30 to emit light. Optionally, the pixel driving circuit includes a driving transistor DT, a first reset module 41 (described with transistor T1 as an example), and a data writing module 42 (described with transistor T5 as an example). The gate of the driving transistor DT is connected to a first node N1, its first terminal is connected to a second node N2, and its second terminal is connected to a third node N3. The two ends of the first reset module 41 are connected to a first reset signal line Vref1 and the first node N1, respectively, and its control terminal is connected to a first scan line S1. The two ends of the data writing module 42 are connected to a data signal line DL and the second node N2, respectively, and its control terminal is connected to a second scan line S2. The third node N3 is used for electrical connection with the light-emitting element 30. The pixel driving circuit also includes a first light-emitting control module 43 (described with transistor T3 as an example) and a second light-emitting control module 44 (described with transistor T4 as an example). The first light-emitting control module 43 is connected between the first power supply signal terminal PVDD and the second node N2, and the second light-emitting control module 44 is connected between the third node N3 and the light-emitting element 30. The control terminals of the first light-emitting control module 43 and the second light-emitting control module 44 are connected to the light-emitting control signal line EM. Optionally, the pixel driving circuit also includes a threshold compensation module 45 (for example, including transistor T6), the threshold compensation module 45 is connected between the first node N1 and the third node N3, and the control terminal of the threshold compensation module 45 is connected to the second scan line S2.

[0043] The operation of this pixel driving circuit includes:

[0044] First reset stage: The first scan line S1 provides a valid level signal to the first reset module 41, the first reset module 41 is turned on, and the reset signal on the first reset signal line Vref1 is transmitted to the first node N1 to reset the first node N1.

[0045] Data writing and threshold compensation stage: The second scan line S2 provides a valid level signal to the data writing module 42 and the threshold compensation module 45. The data writing module 42 and the threshold compensation module 45 are turned on, and the data signal on the data signal line DL is transmitted to the second node N2. The threshold compensation module 45 performs threshold compensation on the driving transistor DT.

[0046] Light emission stage: The light emission control signal line EM sends an effective level signal to the first light emission control module 43 and the second light emission control module 44 to control the first light emission control module 43 and the second light emission control module 44 to be turned on. The signal of the first power supply signal terminal PVDD is transmitted to the driving transistor DT to form the current driving the light emission element 30 to emit light.

[0047] It should be noted that the above embodiments are illustrated using P-type transistors in the pixel driving circuit as an example, but this disclosure is not limited thereto. In some other embodiments of this disclosure, at least one transistor in FIG3 may be configured as an N-type transistor. Furthermore, the above embodiments are illustrated using a pixel driving circuit comprising 7 transistors as an example. In some other embodiments of this disclosure, the pixel driving circuit may also include other numbers of transistors, such as 8 or even more transistors, all of which are applicable to the design concept of this disclosure.

[0048] Please continue to refer to Figures 1 to 5. The display panel 100 in this embodiment of the present disclosure further includes:

[0049] Multiple drive control lines SL extend along a first direction D1 and are arranged along a second direction D2, with the first direction D1 and the second direction D2 intersecting. The drive control lines SL provide control signals to the pixel driving circuit in the display panel. These drive control lines SL may include, for example, at least one of the first scan line S1, the second scan line S2, and the light emission control signal line EM mentioned in the foregoing embodiments. When the display panel is a rectangular structure or a rounded rectangular structure, in this disclosure, the extension direction of the drive control lines SL is the same as the extension direction of the long side of the display panel, and the bonding area A13 is located in the second non-display area A12 along the extension direction of the drive control lines SL.

[0050] Multiple data lines DL extend along a second direction D2 and are arranged along a first direction D1. The data lines DL are used to provide data signals to the pixel driving circuit in the display panel. When the display panel is a rectangular structure or a rounded rectangular structure, in this disclosure, the extension direction of the data lines DL is the same as the extension direction of the short side of the display panel.

[0051] Multiple multiplexing units 90 are located in the first non-display area A11, that is, in the non-display area A1 located in the extension direction of the data lines DL. Each multiplexing unit 90 includes one input terminal and N output terminals. The N output terminals are respectively connected to N data lines DL, where N≥2. The input terminal of the multiplexing unit 90 is connected to the first input line 20. At least a portion of the first input line 20 is located in the display area A0. The first input line 20 is configured to obtain data signals from the bonding pad P0.

[0052] It should be noted that Figure 1 is only illustrated using a rectangular display panel as an example and does not limit the actual shape of the display panel. In some other embodiments of this disclosure, the display panel can also be any other feasible shape, such as a rounded rectangle. When the display panel is a rectangular or rounded rectangle, the first non-display area A11 of the display panel can be, for example, a non-display area adjacent to the long edge of the display panel, and the second non-display area A12 of the display panel can be, for example, a non-display area adjacent to the short edge of the display panel. The bonding area is located in the second non-display area A12, and the bonding area A13 is provided with multiple bonding pads P0. The bonding pads P0 are electrically connected to the signal lines in the display panel, such as data lines SL. It should be noted that the electrical connection mentioned in this disclosure can be a direct connection or a connection through intermediate connectors such as switches, and this disclosure does not specifically limit this. In the bonding area A13, the bonding pads P0 can be used to bond to the control chip or flexible circuit board, thereby realizing the transmission of signals between the control chip or flexible circuit board and the display panel.

[0053] Optionally, the display panel provided in this embodiment can be a display panel using organic light-emitting diode (OLED) display technology. For example, please refer to Figure 5, which shows a schematic diagram of a film layer of the display panel provided in this embodiment. In this embodiment, the pixels of the display panel may include the light-emitting element 30 in Figure 5 and a pixel driving circuit connected to the light-emitting element 30. Referring to Figure 5, the basic structure of the light-emitting element 30 of the OLED display panel includes an anode 301, a light-emitting material layer 302, and a cathode 303. When a suitable voltage is supplied, the holes generated by the anode 301 and the electrons generated by the cathode 303 combine in the light-emitting material layer 302 to produce light. Compared with liquid crystal displays, OLED display panels have high visibility and high brightness, and are more energy-efficient, lightweight, and thin. Of course, in some other embodiments of the present invention, the display panel may also be a display panel using inorganic light-emitting diode (OLED) display technology, such as a Micro LED display panel, or a Mini LED display panel, etc., and this disclosure is not limited thereto.

[0054] Taking the display panel in Figure 5 as an example, the display panel includes a substrate 00, a driving layer 40, and a display layer 10. The display layer 10 includes a pixel definition layer 19, which defines multiple pixel openings. A light-emitting material layer 302 is located at least within the pixel openings. Along a direction perpendicular to the substrate 00, an anode 301 and a cathode 303 are located on opposite sides of the light-emitting material layer 302, with the anode 301 located on the side of the cathode 303 facing the substrate 00. Optionally, an encapsulation layer 50 is also provided on the side of the cathode 303 away from the anode 301. Optionally, the encapsulation layer 50 includes a first inorganic layer 51, an organic layer 52, and a second organic layer 53 stacked together. A pixel driving circuit is provided in the driving layer 40 to provide a driving voltage to the light-emitting element, driving the light-emitting element to emit light. The pixel driving circuit includes multiple transistors M. The driving control line SL and data line DL mentioned in the embodiments of this disclosure are both used for electrical connection with the pixel driving circuit, and are used to provide control signals and data signals to the pixel driving circuit, respectively. Optionally, in the driving layer 40, the gate of the transistor is disposed in the first metal layer m1, and the source and drain of the transistor are disposed in the second metal layer m2. The array substrate 10 also includes a semiconductor layer poly disposed on the side of the first metal layer m1 facing the substrate 00, and an auxiliary metal layer m0 disposed on the side of the semiconductor layer poly facing the substrate 00. It should be noted that the display panel may include transistors with a dual-gate structure. In this case, one gate of the transistor may be located in the first metal layer m1, and the other gate may be located in the auxiliary metal layer m0. Along the direction perpendicular to the plane where the substrate 00 is located, both the first metal layer m1 and the auxiliary metal layer m0 overlap with the semiconductor layer poly. The auxiliary metal layer m0 also has a light-shielding function to prevent light from affecting the semiconductor layer poly. Optionally, a capacitor metal layer mc is further included between the first metal layer m1 and the second metal layer m2. The capacitor metal layer mc can form a capacitor structure with the second metal layer m2. Optionally, a third metal layer m3 is also included on the side of the second metal layer m2 away from the substrate 00. Another metal layer can be provided on the side of the third metal layer m3 away from the substrate as needed. This disclosure does not make specific limitations in this regard. Signal lines can be laid in each metal layer.

[0055] Figure 6 shows a planar schematic diagram of a display panel 100' in the related art. The side length of the display panel along the first direction D1 is greater than its side length along the second direction D2. The scan lines SL' extend along the second direction D2 and are arranged along the first direction D1, and the data lines DL' extend along the first direction D1 and are arranged along the second direction D2. During data refresh, one scanning method is to scan the scan lines SL' line by line along the vertical direction (first direction D1) row by row, which is equivalent to vertical screen scanning. When the number of pixel circuits connected to a scan line SL' is less than the number of pixel circuits in a column, the number of pixel circuits scanned by the scan line SL' in a single scan is small and the number of scans is large, which is not conducive to improving refresh efficiency. If the extension and arrangement directions of scan line SL' and data line DL' are interchanged, so that scan line SL' extends along the first direction D1 and is arranged along the second direction D2, and data line DL' extends along the second direction and is arranged along the first direction, then during data refresh, the scanning method is that scan line SL' scans column by column horizontally, which is equivalent to landscape scanning. In this case, the scan line scans a column of pixel driving circuits with a larger number of pixels at a time, and the number of scans is smaller, which helps to improve refresh efficiency. However, for display panels with landscape scanning, the number of data lines is usually large. If all data lines enter from the bottom bezel area of ​​the display panel, it will result in a large number of wirings in the bottom bezel area of ​​the display panel, which is not conducive to achieving a narrow bezel design. Even if multiplexing units are introduced in the bottom bezel area of ​​the display panel, the multiplexing units and the bonding pads connected to the multiplexing units will still occupy space in the bottom bezel, making it difficult to achieve a narrow bottom bezel design.

[0056] Based on the problems existing in related technologies, this disclosure introduces a horizontal scanning method. Referring to Figures 1 and 2, the drive control line SL extends along the first direction D1 and is arranged along the second direction D2, while the data line DL extends along the second direction D2 and is arranged along the first direction D1. It should be noted that the viewing angle and display method of the display panel in the horizontal scanning method are the same as those of a conventional display panel, but the arrangement of the drive control line SL and the data line DL is different. Taking a mobile phone as an example, its vertical length is greater than its horizontal length. In the horizontal scanning display panel, the drive control line SL extends vertically, and the data line DL extends horizontally. The number of data lines DL is relatively large, and the number of pixel circuit columns is less than the number of pixel circuit rows. During data refresh, the drive control line SL scans one column of pixel drive circuits at a time. Because the number of pixel circuit columns is small, the number of pixel circuit columns that need to be scanned in one frame is small, thus improving the overall refresh efficiency and facilitating high-frequency driving. Figure 7 shows a schematic diagram of the pixel driving circuit arrangement in an embodiment of this disclosure, and Figure 8 shows a relative positional relationship diagram of the pixel driving circuit, driving control line, data line, and sub-pixels. Referring to Figures 7 and 8, for a horizontally scanning display panel, optionally, the display panel 100 includes multiple pixel circuit rows L0 arranged along a first direction D1 and multiple pixel circuit columns L1 arranged along a second direction D2. Both pixel circuit rows L0 and pixel circuit columns L1 include multiple pixel driving circuits 19. The number of pixel circuit rows L0 in the display panel is greater than the number of pixel circuit columns L1. The pixel driving circuit 19 corresponding to each pixel circuit row L0 is electrically connected to the same data line DL, and the pixel driving circuit 19 in each pixel column L1 is electrically connected to the driving control line SL. For a horizontally scanning display panel, the number of pixel circuit rows L0 is relatively large, and the number of data lines DL required will also be relatively large; when the number of pixel circuit columns L1 is small, the driving control line SL only needs to scan a small number of pixel circuit columns L1, which is beneficial for achieving high-frequency driving. Optionally, referring to Figure 8, the display panel includes alternating first pixel columns L11 and second pixel columns L12 along the second direction D2. The first pixel column L12 includes alternating first color sub-pixels P1 and second color sub-pixels P2 along the first direction D1, and the second pixel column L12 includes third color sub-pixels P3 arranged along the first direction D1. Assuming that adjacent first pixel columns L11 and second pixel columns L12 along the second direction D2 constitute a pixel column group L00, optionally, the pixel circuits 19 corresponding to the sub-pixels in the same pixel column group L00 are located in the same pixel circuit column L1. Optionally, different pixel circuits 19 in the same pixel circuit column L1 can be scanned through the same drive control line SL.

[0057] Please continue to refer to Figures 1 and 2. This disclosure further adjusts the positions of the multiplexing unit 90 and the bonding pad P0 in the non-display area. Specifically, when the drive control line SL extends along the first direction D1 and is arranged along the second direction D2, and the data line DL extends along the second direction D2 and is arranged along the first direction D1, the multiplexing unit 90 and the bonding pad P0 are respectively placed in the non-display area A1 on different sides of the display area A0. The multiplexing unit 90 is located in the first non-display area A11 in the extension direction of the data line DL, and the bonding pad P0 is located in the second non-display area A12 in the extension direction of the drive control line SL. In this way, placing the bonding pad P0 and the multiplexing unit 90 in different non-display areas A1 avoids their concentrated arrangement in the same non-display area A1, thus facilitating the narrow bezel design of the display panel. Furthermore, the separate arrangement of the multiplexing unit 90 and the bonding pad P0 in this embodiment means that even if the number of data lines DL and multiplexing units 90 is increased, the drive control line SL will not extend to the second non-display area A12, and the multiplexing unit 90 will not occupy the space of the second non-display area A12. Therefore, it will not have a significant impact on the space of the bezel area where the second non-display area A12 is located. This is also conducive to realizing the narrow bezel design of the display product and improving the screen ratio of the display product.

[0058] In this disclosure, when the multiplexing unit 90 and the bonding pad P0 are respectively located in the non-display area A1 on different sides of the display area A0, a first input line 20 is introduced into the display panel to achieve electrical connection between the multiplexing unit 90 and the bonding pad P0. At least a portion of the first input line 20 is located in the display area A0. That is, the first input line 20 is electrically connected to the multiplexing unit 90 in the first non-display area A11, extends to the display area A0, and is wired in the display area A0, and then extends further from the display area A0 to the second non-display area A12 to be electrically connected to the bonding pad P0. In this way, most of the line segments in the first input line 20 will not occupy the width space of the first non-display area A11 of the display panel, thus not affecting the bezel width of the first non-display area A11, which is also conducive to achieving a narrow bezel design in the area where the first non-display area A11 is located.

[0059] Optionally, referring to Figures 1 and 2, the display panel also includes at least two gating control lines Mux corresponding to the multiplexing unit 90. A single multiplexing unit 90 includes at least N switching elements T. The control terminals of different switching elements T in the same multiplexing unit 90 are connected to different gating control lines Mux. The output terminals of the switching elements T are electrically connected one-to-one with the data lines DL, used to transmit data signals to the data lines DL. The input terminals of different switching elements in the same multiplexing unit 90 are connected to the same first input line 20. The first input line 20 is electrically connected to the bonding pads P0 in the bonding area A13, and data signals are obtained through the bonding pads P0. The number of first input lines 20 is 1 / N of the total number of data lines DL. Compared to directly connecting the data signal lines to the bonding pads P0, the introduction of the multiplexing unit 90 can greatly reduce the number of bonding pads P0, thereby simplifying the design of the control chip or flexible circuit board bonded to the bonding pads P0, and simplifying the overall design of the display product.

[0060] Please continue to refer to Figure 1. In one optional embodiment of this disclosure, the first input line 20 includes a first connection line 21 and a second connection line 22 that are electrically connected. The first connection line 21 extends along the second direction D2 and is connected to the input terminal of the multiplexing unit 90. The second connection line 22 extends along the first direction D1 and is connected to the bonding pad P0 in the bonding area A13.

[0061] This embodiment further describes the wiring method of the first input line 20 in the display panel. Specifically, the first connecting line 21 included in the first input line 20 is used to directly connect to the input terminal of the multiplexing unit 90, and its extension direction is the same as that of the data line DL. The extension direction of the second connecting line 22 included in the first input line 20 is the same as that of the drive control line SL. One end of the second connecting line 22 is connected to the first connecting line 21, and the other end is connected to the bonding pad P0. Optionally, in this embodiment, some segments of the first connecting line 21 are located in the first non-display area A11, and some segments are located in the display area A0. Some segments of the second connecting line 22 are located in the display area A0, and some segments are located in the second non-display area A12. Optionally, the second non-display area A12 may also include a fan-out line (not shown in the figure) located between the bonding area A13 and the display area A0. The second connecting line 22 can be further electrically connected to the bonding pad P0 in the bonding area A13 through the fan-out line. Optionally, the first connecting line 21 and the second connecting line 22 in the first input line 20 may be located in the same film layer or in different film layers; this disclosure does not specifically limit this. In this embodiment, when the first connecting line 21 and the second connecting line 22 are introduced into the display area A0, the extension directions of the first connecting line 21 and the second connecting line 22 are adapted to the extension directions of the existing signal lines in the display area A0, which helps simplify the overall wiring difficulty and improve the visual effect of the display panel. Furthermore, wiring the first connecting line 21 and the second connecting line 22 in the display area A0 to connect to the second non-display area A12, compared to routing from the first non-display area A11 of the display panel along the non-display area A1 to the second non-display area A12, helps reduce the wiring in the non-display area A1, achieving a narrow bezel design in the non-display area A1.

[0062] Referring to Figures 1 and 5, in one optional embodiment of this disclosure, when the extension direction of the first connecting line 21 is the same as the extension direction of the data line DL, i.e., both extend along the second direction D2, the first connecting line 21 and the data line DL are disposed on the same layer. Thus, the fabrication of the first connecting line 21 and the data line DL can be completed in the same manufacturing process, eliminating the need for separate manufacturing processes for the first connecting line 21 and the data line DL. This simplifies the manufacturing process of the display panel and improves production efficiency. Optionally, the first connecting line 21 and the data line DL can be located in the second metal layer m2 mentioned in the embodiment shown in Figure 5. Alternatively, they can be disposed in the third metal layer m3 or other feasible metal layers as needed; this disclosure does not specifically limit this.

[0063] Please continue referring to Figures 1 and 5. In one optional embodiment of this disclosure, when the extension direction of the first connecting line 21 is the same as the extension direction of the data line DL, i.e., both extend along the second direction D2, the first connecting line 21 and the data line DL can be disposed in different layers, and the first connecting line 21 and the data line DL do not overlap in the direction perpendicular to the light-emitting surface of the display panel. For example, the data line DL can be disposed in the second metal layer m2 in the film layer shown in Figure 5, and the first connecting line 21 can be disposed in the third metal layer m3 or the capacitor metal layer mc, etc. When the data line DL and the first connecting line 21 are disposed in different film layers, this embodiment further limits that the two do not overlap in the direction perpendicular to the light-emitting surface of the display panel, which helps to reduce or avoid signal coupling between the data line DL and the first connecting line 21, thereby helping to improve the stability of the signals transmitted on the first connecting line 21 and the data line DL.

[0064] Figure 9 shows another planar schematic diagram of the display panel provided in an embodiment of this disclosure. Figure 10 shows a relative positional reference schematic diagram of a portion of the first auxiliary lines L1 and a portion of the first connecting lines 21 in the display panel. It should be noted that, in order to clearly distinguish the first auxiliary lines L1 and the first connecting lines 21, the embodiment shown in Figure 10 uses dashed lines to illustrate the first auxiliary lines L1, which does not represent the actual structure of the first auxiliary lines L1. Referring to Figures 9 and 10, in an optional embodiment of this disclosure, the display panel further includes multiple first auxiliary lines L1 extending along the second direction D2. The first auxiliary lines L1 and the first connecting lines 21 are on the same layer and insulated from each other. Along the first direction D1, the spacing between adjacent first auxiliary lines L1 is S01, and the spacing between adjacent first auxiliary lines L1 and first connecting lines 21 is S02, where S01 = S02.

[0065] In this disclosure, when the multiplexing unit 90 and the bonding pad P0 are located in the non-display area A1 on different sides of the display area A0, a first input line 20 needs to be introduced into the display panel to achieve electrical connection between the multiplexing unit 90 and the bonding pad P0 in the bonding area A13. The first input line 20 includes a first connecting line 21 extending along the second direction D2. This first connecting line 21 is equivalent to a newly introduced signal line in the display area A0. When the first connecting line 21 is introduced only in a part of the display area A0, it may cause uneven metal distribution in the display panel, affecting the display effect. Therefore, in this embodiment, a first auxiliary line L1 is introduced into the display panel in the same layer as the first connecting line 21 and is insulated from it. The first connecting line 21 and the first auxiliary line L1 are evenly arranged in the film layer in which they are located. That is, in the corresponding film layer, the spacing between adjacent traces is equal. Thus, even if the first connecting line 21 is introduced into the display area A0, it will not affect the overall wiring uniformity of the display area A0, thereby improving the overall display uniformity of the display panel. In actual production, the first connecting line 21 and the first auxiliary line L1 can be formed simultaneously in the same process, avoiding the introduction of different manufacturing processes for the first connecting line 21 and the first auxiliary line L1, which helps to simplify the manufacturing process of the display panel and improve production efficiency.

[0066] Please continue referring to Figures 9 and 10. To improve the uniformity of metal distribution, in one optional embodiment of this disclosure, when introducing the first auxiliary line L1 along with the first connecting line 21, at least a portion of the first auxiliary line L1 is electrically connected to a fixed potential signal. When the first auxiliary line L1 is introduced into the display panel, if the first auxiliary line L1 is floating (not connected to other signals), static electricity may be introduced, affecting the display reliability of the display panel. Therefore, in this embodiment, when at least a portion of the first auxiliary line L1 is connected to the fixed potential signal line, the first auxiliary signal line receives a constant potential signal, which helps to avoid the impact of static electricity on the display panel through the first auxiliary line L1.

[0067] It should be noted that the first auxiliary line can be connected to an existing fixed potential signal line in the display panel, such as a power supply voltage signal line or a reset signal line, etc. This disclosure does not specifically limit it in this regard.

[0068] Referring to Figures 1 and 3, when a first input line 20 is introduced into the display panel to electrically connect the multiplexing unit 90 to the bonding pad P0 in the bonding area A13, the first input line 20 includes a second connecting line 22 extending along a first direction D1. In an optional embodiment of this disclosure, the second connecting line 22 is disposed on the same layer as the drive control line SL, or the second connecting line 22 is disposed on a different layer from the drive control line SL, and the second connecting line 22 and the drive control line SL do not overlap in a direction perpendicular to the light-emitting surface of the display panel.

[0069] Since the second connecting line 22 and the driving control line SL extend in the same direction, when the second connecting line 22 and the driving control line SL are arranged in the same layer, they can be manufactured in the same process without introducing different manufacturing processes. This simplifies the manufacturing process of the display panel and improves production efficiency. When the second connecting line 22 and the driving control line SL are arranged in the same layer, they can both be located in the first metal layer m1 in the film layer structure shown in Figure 5, or both be located in the capacitor metal layer mc, or other feasible metal film layers. This disclosure does not specifically limit them in this regard.

[0070] In addition, the second connecting line 22 and the drive control line SL can be set on different film layers according to actual needs, and the second connecting line 22 and the drive control line SL can be controlled to not overlap along the direction perpendicular to the display panel. This helps to avoid coupling interference on the second connecting line 22 and the drive control line SL, and helps to improve the stability of the signals transmitted on the second connecting line 22 and the drive control line SL.

[0071] Figure 11 shows another planar schematic diagram of the display panel provided in an embodiment of this disclosure. Figure 12 shows a relative positional reference diagram of a portion of the second auxiliary lines L2 and a portion of the second connecting lines 22 in the display panel. It should be noted that, in order to clearly distinguish the second auxiliary lines L2 and the second connecting lines 22, the embodiment shown in Figure 12 represents the second auxiliary lines L2 in the form of dashed lines, but does not represent the actual structure of the second auxiliary lines L2. Referring to Figures 11 and 12, in an optional embodiment of this disclosure, the display panel further includes a plurality of second auxiliary lines L2 extending along the first direction D1, and the second auxiliary lines L2 and the second connecting lines 22 are disposed on the same layer; along the second direction D2, the spacing between adjacent second auxiliary lines L2 is S11, and the spacing between adjacent second auxiliary lines L2 and the second connecting lines 22 is S12, where S11 = S12.

[0072] In this disclosure, when the multiplexing unit 90 and the bonding pad P0 are located in the non-display area A1 on different sides of the display area A0, a first input line 20 needs to be introduced into the display panel to achieve electrical connection between the multiplexing unit 90 and the bonding pad P0 in the bonding area A13. The first input line 20 includes a second connecting line 22 extending along the first direction D1. This second connecting line 22 is equivalent to a newly introduced signal line in the display area A0. When the second connecting line 22 is introduced only in a part of the display area A0, it may cause uneven metal distribution in the display panel, affecting the display effect. Therefore, in this embodiment, a second auxiliary line L2 is introduced into the display panel in the same layer as the second connecting line 22 and is insulated from it. The second connecting line 22 and the second auxiliary line L2 are evenly arranged in the film layers in which they are located. That is, the spacing between adjacent traces is equal in the corresponding film layers. Thus, even if the second connecting line 22 is introduced into the display area A0, it will not affect the overall wiring uniformity of the display area A0, thereby improving the overall display uniformity of the display panel. In actual production, the second connecting line 22 and the second auxiliary line L2 can be formed simultaneously in the same process, avoiding the introduction of different manufacturing processes for the second connecting line 22 and the second auxiliary line L2, which helps to simplify the manufacturing process of the display panel and improve production efficiency.

[0073] To improve the uniformity of metal distribution, in one optional embodiment of this disclosure, when introducing the second auxiliary line L2 along with the second connecting line 22, at least one of the second auxiliary lines L2 is electrically connected to a fixed potential signal. When the second auxiliary line L2 is introduced into the display panel, if it is floating (not connected to other signals), static electricity may be introduced, affecting the display reliability of the display panel. Therefore, in this embodiment, connecting at least a portion of the second auxiliary line L2 to the fixed potential signal line ensures that the second auxiliary signal line receives a constant potential signal, which helps to prevent static electricity from affecting the display panel through the second auxiliary line L2.

[0074] It should be noted that the second auxiliary line can be connected to an existing fixed potential signal line in the display panel, such as a power supply voltage signal line or a reset signal line, etc. This disclosure does not specifically limit this connection.

[0075] Please continue referring to Figures 1 and 2. In the multiple multiplexing units 90 provided in this disclosure, each multiplexing unit 90 includes N output terminals, that is, N switching elements T. The output terminals of the switching elements T are electrically connected to the data lines DL one-to-one. The input terminals of the N switching elements T in a single multiplexing unit 90 are connected to the same first input line 20, and data signals are obtained through the first input line 20. The ratio of the number of first input lines 20 to the number of data lines DL is 1:N, which reduces the number of bonding pads P0 coupled to the data lines DL in the bonding area A13. In an optional embodiment of this disclosure, N≤5. The larger the value of N, the fewer the number of first input lines 20 introduced into the display panel, which is more conducive to simplifying the overall manufacturing process. However, research has found that if N≥6, under high-frequency driving, it will reduce the time for the data lines DL to write data signals to the pixel driving circuit, resulting in insufficient charging, which may affect the display effect. Therefore, in this embodiment, the value of N is set to be greater than or equal to 2 and less than or equal to 5. This not only helps to reduce the number of first input lines 20 and simplify the overall panel manufacturing process, but also helps to ensure the normal transmission of data signals and improve the display accuracy of the display panel. This embodiment uses N=4 as an example for illustration. In some other embodiments, N can also be 2, 3, or 5.

[0076] Figure 13 shows a schematic diagram of a connection between the multiplexing unit 90 and the data lines DL. It also illustrates an example of a pixel arrangement of the display panel. Referring to Figure 13, in an optional embodiment of this disclosure, the multiplexing unit 90 is connected to N data lines DL arranged continuously along the first direction D1.

[0077] In this embodiment, the display panel includes a first pixel row L01 and a second pixel row L02 arranged alternately along a first direction D1. The first pixel row L01 includes a first color sub-pixel P1 and a second color sub-pixel P2. Along a second direction D2, the first color sub-pixels P1 and P2 are arranged alternately in the first pixel row L01. The second pixel row L02 includes only a third color sub-pixel P3, which is arranged along the second direction D2. The total number of data lines DL in the display panel is the same as the total number of the first pixel row L01 and the second pixel row L02. The data lines DL include a first type of data line DL1 and a second type of data line DL2. The first type of data line DL1 is electrically connected to the pixel driving circuit corresponding to the first pixel row L01 and is used to provide data signals to the pixel driving circuits corresponding to the first color sub-pixel P1 and the second color sub-pixel P2. The second data line DL2 is electrically connected to the pixel driving circuit corresponding to the second pixel row L02 and is used to provide data signals to the pixel driving circuit corresponding to the third color sub-pixel P3. The first type of data lines DL and the second type of data lines DL are arranged alternately along the first direction D1. Optionally, the first color sub-pixel P1 is a red sub-pixel, the second color sub-pixel P2 is a blue sub-pixel, and the third color sub-pixel P3 is a green sub-pixel. It should be noted that the embodiment shown in Figure 13 is only an example of one feasible way of pixel arrangement and does not limit the actual arrangement or the shape of the sub-pixels. In some other embodiments of this disclosure, other feasible arrangement methods can also be used.

[0078] Referring to Figures 1, 2, 8, and 13, when multiple multiplexing units 90 are introduced into the display panel, each multiplexing unit 90 is electrically connected to at least two data lines DL arranged continuously along the first direction D1. Figure 13 illustrates an example using multiplexing units 90 and four continuously arranged data lines DL. For instance, the first to fourth data lines DL arranged along the first direction D1 are connected to the first multiplexing unit 90, the fifth to eighth data lines DL arranged along the first direction D1 are connected to the second multiplexing unit 90, and so on. This connection method simplifies the connection complexity between the multiplexing units 90 and the data lines DL. Figure 14 shows a timing diagram of one operation of the multiplexing unit 90 in Figure 13. Referring to Figures 13 and 14, in this embodiment, the display panel is provided with four gating control lines, namely Mux1, Mux2, Mux3, and Mux4. The control terminals of the four switching elements T in the multiplexing unit 90 are respectively connected to different gating control lines Mux1, Mux2, Mux3, and Mux4. In the display panel, a sub-pixel P is electrically connected to a corresponding pixel driving circuit 19. To clearly show the correspondence between the sub-pixel and the data line DL, Figure 13 illustrates the connection between the sub-pixel P and the data line DL. In reality, the pixel driving circuit 19 corresponding to the corresponding sub-pixel P is connected to the data line DL. Referring to Figures 13 and 14, during data refresh, the four gating control lines can send valid level signals in a time-division manner, causing the four switching elements T in the multiplexing unit 90 to be turned on sequentially, thereby causing the first input line 20 to be electrically connected to the corresponding data line DL in a time-division manner.

[0079] For example, when the control line Mux1 outputs a valid level signal, the first switching element T in the two multiplexing units 90 is turned on. In the two first input lines 20 in Figure 13, the first input line Source1 is electrically connected to the first data line DL arranged along the first direction D1, and the second input line Source2 is electrically connected to the fifth data line DL arranged along the first direction D1. At this time, the signals transmitted on each first input line 20 are data signals transmitted to the pixel circuit in the first pixel column L11. In the first pixel column L11, the first color sub-pixel P1 and the second color sub-pixel P2 are arranged alternately along the first direction D1. Correspondingly, in the first pixel column L11, the two input lines Source1 and Source2 transmit data signals to the data line DL corresponding to the first color sub-pixel P1.

[0080] Similarly, when the control line Mux2 receives a valid input signal, the first input line Source1 is electrically connected to the second data line DL arranged along the first direction D1, and the second input line Source2 is electrically connected to the sixth data line DL arranged along the first direction D1. Correspondingly, in the second pixel column L12, both input lines Source1 and Source2 transmit data signals to the data line DL connected to the third color sub-pixel P3. In the second pixel column L12, multiple third color sub-pixels P3 are alternately arranged along the first direction D1.

[0081] When the control line Mux3 receives a valid input signal, the first input line Source1 will be electrically connected to the third data line DL arranged along the first direction D1, and the second input line Source2 will be electrically connected to the seventh data line DL arranged along the first direction D1. Corresponding to the first pixel column L11, both input lines Source1 and Source2 transmit data signals to the data line DL connected to the second color sub-pixel P2.

[0082] When the control line Mux4 receives a valid input signal, the first input line Source1 will be electrically connected to the fourth data line DL arranged along the first direction D1, and the second input line Source2 will be electrically connected to the eighth data line DL arranged along the first direction D1. Corresponding to the second pixel column L12, both the second input lines Source1 and Source2 transmit data signals to the data line DL corresponding to the remaining third color sub-pixel P3.

[0083] In this way, data signals are sequentially provided to the data lines DL corresponding to the first color sub-pixel P1, the third color sub-pixel P3, the second color sub-pixel P2, and the third color sub-pixel P3 in the first pixel column L11 and the second pixel column L12. After the data signal is written to the corresponding data line DL, the data writing module in the pixel driving circuit can be turned on by the control signal Scan1 or Scan2, thereby writing the data signal into the corresponding pixel driving circuit. Here, Scan1 is the control signal to control whether the data writing module in the pixel driving circuit corresponding to the first pixel column L11 is turned on or off, and Scan2 is the control signal to control whether the data writing module in the pixel driving circuit corresponding to the second pixel column L12 is turned on or off. It should be noted that the timing of writing data to the pixel driving circuit can be set according to actual needs. The embodiment shown in Figure 14 is illustrated by sending the valid level signal of Scan1 or Scan2 after the start time of sending the valid level signal of the selection control line Mux4, but it is not limited to this.

[0084] Figure 15 shows a schematic diagram of a connection between the multiplexing unit 90 and the data lines DL. It also illustrates an example of a pixel arrangement for the display panel. The pixel arrangement in Figure 15 is the same as in Figure 13, and will not be described again in this embodiment. In an optional embodiment of this disclosure, the multiple multiplexing units 90 include a first multiplexing unit 91 and a second multiplexing unit 92. The first multiplexing unit 91 is connected to N odd-numbered data lines DL arranged adjacent to each other along the first direction D1, and the second multiplexing unit 92 is connected to N even-numbered data lines DL arranged adjacent to each other along the first direction D1.

[0085] The difference between the embodiment shown in Figure 15 and the embodiment shown in Figure 13 lies in the arrangement of the data lines DL connected to the multiplexing unit 90. In the embodiment shown in Figure 15, the first multiplexing unit 91 and the second multiplexing unit 92 are arranged alternately along the first direction D1. The first multiplexing unit 91 is connected to N consecutive odd-numbered data lines DL. For example, the embodiment shown in Figure 15 shows the first multiplexing unit 91 connected to the 1st, 3rd, 5th, and 7th data lines DL arranged along the first direction D1. The second multiplexing unit 92 is connected to N consecutive even-numbered data lines DL. For example, the embodiment shown in Figure 15 shows the second multiplexing unit 92 connected to the 2nd, 4th, 6th, and 8th data lines DL arranged along the first direction D1. Figure 16 shows a timing diagram of one operation of the multiplexing unit 90 in Figure 15. The difference between this timing diagram and Figure 15 lies in the start time of data writing; however, the timing diagram shown in Figure 14 can also be used. The embodiment corresponding to Figure 13 can also use the timing diagram of Figure 16. This disclosure does not specifically limit this. In the display panel, a sub-pixel P is electrically connected to a corresponding pixel driving circuit 19. To clearly illustrate the correspondence between the sub-pixel and the data line DL, Figure 15 uses the connection between the sub-pixel P and the data line DL for illustration. In reality, the pixel driving circuit 19 corresponding to the corresponding sub-pixel P is connected to the data line DL.

[0086] Referring to Figures 15 and 16, in this embodiment, the display panel is provided with four gating control lines, namely Mux1, Mux2, Mux3, and Mux4. The control terminals of the four switching elements in the multiplexing unit 90 are respectively connected to different gating control lines. The four gating control lines can send valid level signals in a time-division manner, causing the four switching elements in the multiplexing unit 90 to be turned on sequentially, thereby enabling the first input line 20 to be electrically connected to the corresponding data line DL in a time-division manner.

[0087] For example, when the control line Mux1 outputs a valid level signal, the first switching element T in the two multiplexing units 90 is turned on. The first data line DL connected to the first multiplexing unit 91 and the second data line DL connected to the second multiplexing unit 92 respectively receive the data signals transmitted by the first input lines Source1 and Source2. Taking the first pixel column L11 and the second pixel column L22 as examples, the data lines DL corresponding to the first color sub-pixel P1 in the first row of the first pixel column L11 and the third color sub-pixel P3 in the first row of the second pixel column L12 receive the data signals. It should be noted that n in the nth data line DL mentioned in the embodiments of this disclosure refers to the sequence number of the data lines DL arranged from top to bottom along the first direction D1 based on Figure 13 or Figure 15. The data lines DL arranged from top to bottom are the 1st, 2nd, ... 8th.

[0088] Similarly, when the control line Mux2 outputs a valid level signal, the second switching element T in the two multiplexing units 90 is turned on. The third data line DL connected to the first multiplexing unit 91 and the fourth data line DL connected to the second multiplexing unit 92 receive the data signals transmitted by the first input lines Source1 and Source2, respectively. Taking the first pixel column L11 and the second pixel column L22 as an example, the data lines DL corresponding to the second color sub-pixel P2 in the second row of the first pixel column L11 and the third color sub-pixel P3 in the second row of the second pixel column L12 receive the data signals.

[0089] When the selected control line Mux3 outputs a valid level signal, the third switching element T in the two multiplexing units 90 is turned on. The fifth data line DL connected to the first multiplexing unit 91 and the sixth data line DL connected to the second multiplexing unit 92 receive the data signals transmitted by the first input lines Source1 and Source2, respectively. Taking the first pixel column L11 and the second pixel column L22 as an example, the data lines DL corresponding to the first color sub-pixel P1 in the third row of the first pixel column L11 and the third color sub-pixel P3 in the third row of the second pixel column L12 receive the data signals.

[0090] When the selected control line Mux4 outputs a valid level signal, the fourth switching element T in the two multiplexing units 90 is turned on. The seventh data line DL connected to the first multiplexing unit 91 and the eighth data line DL connected to the second multiplexing unit 92 receive the data signals transmitted by the first input lines Source1 and Source2, respectively. Taking the first pixel column L11 and the second pixel column L22 as an example, the data lines DL corresponding to the second color sub-pixel P2 located in the fourth row of the first pixel column L11 and the third color sub-pixel P3 located in the fourth row of the second pixel column L12 receive the data signals.

[0091] Thus, the first input line Source1 connected to the first multiplexing unit 91 is only used to transmit data signals to the first color sub-pixel P1 or the second color sub-pixel P2, and the first input line Source2 connected to the second multiplexing unit 92 is only used to transmit data signals to the third color sub-pixel P3. This method helps to reduce the overall power consumption of the display panel.

[0092] Figure 17 shows another planar schematic diagram of the display panel provided in an embodiment of the present disclosure. Referring to Figure 17, in an optional embodiment of the present disclosure, the display panel further includes a gate driving circuit 80, which is electrically connected to a driving control line SL. The gate driving circuit 80 is located in the first non-display area A11. The gate driving circuit 80 is electrically connected to the driving control line SL through a second input line 82. The second input line 82 extends along the second direction D2 and is disposed on a different layer from the driving control line SL. The second input line 82 is at least partially located in the display area A0.

[0093] In this embodiment, the gate driving circuit 80 is located in the first non-display area A11, which is located on both sides of the display area A0 along the second direction D2. Considering that the driving control line SL extends along the first direction D1, the gate driving circuit 80 is not located in the extension direction of the driving control line SL. Therefore, in this embodiment, a second input line 82 extending along the second direction D2 is introduced into the display panel to connect the corresponding driving control line SL and the gate driving circuit 80. The second input line 82 is at least partially located in the display area A0. Since the purpose of the second input line 82 is to electrically connect the driving control line SL extending along the first direction D1 and the gate driving circuit 80 located in the first non-display area A11, most of the line segment of the second input line 82 is located in the display area A0, occupying less space in the first non-display area A11. Therefore, even if the second input line 82 is introduced into the display panel, it will not affect the width of the first non-display area A11, thus facilitating the narrow bezel design of the display panel.

[0094] It should be noted that the number of drive control lines SL and gate drive circuits 80 shown in the accompanying drawings of this disclosure is only schematic and does not limit the actual number of drive control lines SL and gate drive circuits 80 included in the display panel.

[0095] Referring to Figures 17 and 5, when a second input line 82 is introduced into the display panel to achieve electrical connection between the drive control line SL and the gate drive circuit 80, in an optional embodiment of this disclosure, the second input line 82 and the data line DL are disposed on the same layer. Considering that the extension direction of the second input line 82 is the same as the extension direction of the data line DL, when they are disposed on the same metal layer, the second input line 82 and the data line DL can be formed in the same manufacturing process, without the need to introduce different manufacturing processes for them, nor the need to introduce a new film layer structure for the second input line 82. Therefore, it is beneficial to simplify the manufacturing process and film layer structure of the display panel and to improve production efficiency. Optionally, the second input line 82 and the data line DL can both be located in the second metal layer m2 or the third metal layer m3, or they can be located in other feasible metal film layers. This disclosure does not specifically limit them in this regard. It should be noted that when the second input line 82 and the data line DL are set on the same film layer, the second input line 82 is set between adjacent data lines DL. Optionally, the number of data lines DL contained between each pair of second input lines 82 is the same or nearly the same, so that the second input line 82 and the data line DL are distributed as evenly as possible, which helps to improve the overall display uniformity of the display panel.

[0096] Of course, in some other embodiments of this disclosure, when the second input line 82 is introduced into the display panel to realize the electrical connection between the drive control line SL and the gate drive circuit 80, the second input line 82 and the data line DL can also be disposed in different layers, and the second input line 82 and the data line DL do not overlap along the direction perpendicular to the light-emitting surface of the display panel. In this way, it is beneficial to avoid signal coupling between the second input line 82 and the data line DL, and to improve the accuracy of signal transmission on the second input line 82 and the data line DL. When the second input line 82 and the data line DL are disposed in different film layers, the data line DL can be disposed in the second metal layer m2 in the film layer shown in FIG. 5, and the second input line 82 can be disposed in the third metal layer m3 or the capacitor metal layer mc, or other feasible film layers. This disclosure does not specifically limit this.

[0097] It should be noted that when the second input line 82 and the data line DL are set on different layers, a third auxiliary line L3 can also be introduced on the same layer as the second input line 82. For example, please refer to Figure 18, which shows a schematic diagram of the arrangement of the second input line 82 and the third auxiliary line L3. To clearly distinguish the second input line 82 and the third auxiliary line L3, the third auxiliary line L3 is represented by a dashed line in this embodiment, but the actual structure of the third auxiliary line L3 is not limited. Both the second input line 82 and the third auxiliary line L3 extend along the second direction D2 and are arranged along the first direction D1. The interval between adjacent second input lines 82 and third auxiliary lines L3, and the interval between adjacent third auxiliary lines L3, are equal, so that the second input line 82 and the third auxiliary line L3 are evenly distributed in the metal film layer, which helps to improve the overall display uniformity of the display panel.

[0098] Figure 19 shows a schematic diagram of a layout of the first input line 20 and the second input line 82 in the display panel. Referring to Figure 19, in an optional embodiment of this disclosure, the second input line 82 is arranged on the same layer as the first connecting line 21; at least a portion of the second input line 82 is located in the extension direction of the first connecting line 21, and along the second direction D2, there is a first interval JG between the first connecting line 21 and the second input line 82 located in its extension direction.

[0099] When a first input line 20 is introduced into the display panel to realize the electrical connection between the multiplexing unit 90 and the bonding pad P0, and a second input line 82 is introduced to realize the electrical connection between the gate drive circuit 80 and the drive control line SL, both the second input line 82 and the first connecting line 21 in the first input line 20 extend along the second direction D2. At this time, when laying out the second input line 82 and the first connecting line 21, part of the second input line 82 can be laid out in the extension direction of the first connecting line 21. In actual manufacturing, a signal line extending along the second direction D2 can be broken to obtain two line segments. The two line segments are insulated and isolated by a first gap. The two line segments are the second input line 82 and the first connecting line 21, respectively. This setting method can complete the manufacturing of the second input line 82 and the first connecting line 21 in one manufacturing process, which is beneficial to simplify the manufacturing process and can also make reasonable use of the wiring space of the display panel and improve the space utilization rate.

[0100] Figures 20 and 21 show another planar schematic diagram of the display panel provided in the embodiments of this disclosure. Referring to Figures 20 and 21, in an optional embodiment of this disclosure, the display area A0 includes a first display area A01, a third display area A03, and a second display area A02 arranged sequentially along a direction away from the second non-display area A12; the gate driving circuit 80 is located in the first non-display area A11 adjacent to the third display area A03 and / or the second display area A02.

[0101] In this embodiment, the display area A0 is divided into three sequentially arranged display areas A0 along the first direction D1. The display area A0 adjacent to the second non-display area A12 is the first display area A01, the display area A0 farthest from the second non-display area A12 is the second display area A02, and the display area A0 located between the first display area A01 and the second display area A02 is the third display area A03. That is to say, the second display area A02 and the third display area A03 are both located on the side of the first display area A01 that is far away from the second non-display area A12. The first non-display area A11, which is adjacent to the second display area A02 and the third display area A03, is also far away from the second non-display area A12. The embodiment shown in Figure 20 illustrates a scheme in which the gate driving circuit 80 is disposed in the first non-display area A11 adjacent to the second display area A02. In this way, the gate driving circuit 80 does not occupy the space of the first non-display area A11 adjacent to the first display area A01 and the third display area A03. This space can be used for the layout of other structures; for example, global signal lines for transmitting global signals, such as power signal lines, can be placed in this space. This will be explained in detail in subsequent embodiments. The embodiment shown in Figure 21 illustrates a scheme in which the gate driving circuit 80 is disposed in the first non-display area A11 adjacent to the second display area A02 and the third display area A03. In this way, the gate driving circuit 80 does not occupy the space of the first non-display area A11 adjacent to the first display area A01. This space can be used for global signal lines for transmitting global signals, such as power signal lines. When the gate drive circuit 80 is avoided in the first non-display area A11 adjacent to the first display area A01, or in the first non-display area A11 adjacent to both the first display area A01 and the third display area A03, the freed-up space can be used to set up global signal lines as described above, thereby increasing the area occupied by this type of signal line in the display panel and reducing the impedance of this part of the signal line, which is beneficial to increasing the voltage drop of the signal transmitted by this part of the signal line. It should be noted that Figures 20 and 21 respectively show the schemes where the gate drive unit 80 is located in the first non-display area A11 adjacent to the second display area A02 and the first non-display area A11 adjacent to the third display area A03. In some other embodiments of this disclosure, the gate drive unit 80 may also be located in both the first non-display area A11 adjacent to the second display area A02 and the first non-display area A11 adjacent to the third display area A03.

[0102] Referring again to Figures 20 and 21, in one optional embodiment of this disclosure, at least a portion of the second input line 82 is located in the third display area A03 and / or the second display area A02. When the gate driving circuit 80 is located only in the first non-display area A11 adjacent to the second display area A02, the second input line 82 can be routed in the second display area A02 and extended from the second display area A02 to the first non-display area A11 adjacent to the second display area A02 to achieve connection with the gate driving circuit 80. In this way, the second input line 82 can achieve connection without winding or with minimal winding, which simplifies the manufacturing process. Similarly, when the gate driving circuit 80 is located in the first non-display area A11 adjacent to the second display area A02 and the third display area A03, the second input line 82 can be wired in the second display area A02 and the third display area A03 respectively, and extended from the second display area A02 and the third display area A03 to the first non-display area A11 adjacent to the second display area A02 and the third display area A03 to achieve connection with the gate driving circuit 80. This also helps to reduce the winding of the second input line 82, and thus also helps to simplify the manufacturing process.

[0103] Referring to Figures 20 and 21, in one optional embodiment of this disclosure, the gate driving circuit 80 and the multiplexing unit 90 are disposed opposite to each other in different first non-display areas A11 along the second direction D2. When the gate driving circuit 80 is introduced into the display panel, the gate driving circuit 80 can be disposed in the first non-display area A11 while the gate driving circuit 80 and the multiplexing unit 90 are disposed on opposite sides of the display area A0 along the second direction D2. This facilitates a reasonable layout of the space of the first non-display areas A11 on both sides of the display area A0, making the widths of the two first non-display areas A11 consistent or nearly consistent, which helps to improve the overall visual effect of the display panel.

[0104] The above embodiments illustrate a method in which a drive control line SL is electrically connected to a gate drive circuit 80. In some other embodiments of this disclosure, a drive control line SL can also be electrically connected to two gate drive circuits 80, with the two gate drive circuits 80 providing drive signals to the same drive control line SL. For example, please refer to FIG22, which shows another planar schematic diagram of a display panel provided in an embodiment of this disclosure. Optionally, the gate drive circuit 80 includes a first drive circuit group Z1 and a second drive circuit group Z2. The first drive circuit group Z1 includes a plurality of first drive circuits 801, and the second drive circuit group Z2 includes a plurality of second drive circuits 802. At least one drive control line SL is electrically connected to both the first drive circuit 801 and the second drive circuit 802. Specifically, this embodiment illustrates a scheme of introducing two sets of drive circuits in the display panel. The drive control line SL is connected to both the first drive circuit 801 and the second drive circuit 802. The first drive circuit 801 and the second drive circuit 802 can simultaneously provide drive signals to the corresponding drive control line SL, which is beneficial to improving the overall driving capability of the gate drive circuit 80.

[0105] Please continue to refer to Figure 22. In one optional embodiment of this disclosure, the display area A0 includes a first display area A01, a third display area A03, and a second display area A02 arranged sequentially along a direction away from the second non-display area A12; the first driving circuit group Z1 and the second driving circuit group Z2 are respectively located in the first non-display area A11, which is arranged opposite to the third display area A03 and / or the second display area A02 along the second direction D2. When the first driving circuit group Z1 and the second driving circuit group Z2 are introduced into the display panel, the first driving circuit group Z1 and the second driving circuit group Z2 can be respectively set on opposite sides of the display area A0 along the second direction D2. For example, the first driving circuit group Z1 is located in the first non-display area A11 opposite to the multiplexing unit 90, and the second driving circuit group Z2 is set in the first non-display area A11 on the same side of the display area A0 as the multiplexing unit 90. The method of setting the first driving circuit group Z1 and the second driving circuit group Z2 on opposite sides of the display area is conducive to the rational layout of the space of the first non-display area A11 and avoids setting more peripheral circuits in the first non-display area A11 on one side, which would affect the narrow bezel design. Furthermore, when the first driving circuit group Z1 and the second driving circuit group Z2 are introduced, the first non-display area A11 where the first driving circuit 801 and the second driving circuit group Z2 are located is adjacent to the second display area A02 and / or the third display area A03, while avoiding the first display area A01. Other circuit structures can be laid out in the first non-display area A11 adjacent to the first display area A01 to make reasonable use of the space of the first non-display area A11 of the display panel and improve the space utilization rate of the display panel.

[0106] Figure 23 shows another planar schematic diagram of the display panel provided in the embodiment of this disclosure. The difference between this panel and the one shown in Figure 22 is that the gate driving circuit 80 is located in a different area in the first non-display area A11.

[0107] Please refer to Figure 23. In one optional embodiment of this disclosure, the display area A0 includes a first display area A01, a third display area A03, and a second display area A02 arranged sequentially along a direction away from the second non-display area A12. The first driving circuit group Z1 is located on one side of the second display area A02 along the second direction D2. Along the second direction D2, the first driving circuit group Z1 and the multiplexing unit 90 are disposed opposite each other on different sides of the display area A0. The second driving circuit group Z2 is located on one side of the first display area A01 along the second direction D2. Along the second direction D2, the second driving circuit group Z2 and the multiplexing unit 90 are located on the same side of the display area A0.

[0108] When a first driving circuit group Z1 and a second driving circuit group Z2 are introduced into the display panel, and the driving control line SL is electrically connected to the first driving circuit 801 in the first driving circuit group Z1 and the second driving circuit 802 in the second driving circuit group Z2, this embodiment shows that the first driving circuit group Z1 is disposed in the first non-display area A11 adjacent to the second display area A02 and disposed on a different side of the display area A0 opposite to the multiplexing unit 90, and the second driving circuit group Z2 is disposed in the first non-display area A11 adjacent to the first display area A01 and located in the same first non-display area A11 as the multiplexing unit 90. At this time, the second input line 82 connected to the first driving circuit group Z1 is located in the second display area A02, which allows the second input line 82 to be electrically connected to the end of the driving control line SL away from the second non-display area A12. The second input line 82 connected to the second driving circuit group Z2 is located in the first display area A01, which allows the second input line 82 to be electrically connected to the end of the driving control line SL close to the second non-display area A12. In this way, the first driving circuit 801 in the first driving circuit group Z1 transmits a driving signal to the driving control line SL from the end of the driving control line SL away from the second non-display area A12, and the second driving circuit 802 in the second driving circuit group Z2 transmits a driving signal to the driving control line SL from the end of the driving control line SL close to the second non-display area A12. This helps to reduce the difference in driving signals received by different areas on the driving control line SL and improves the consistency of the driving effect of the driving control line SL on the pixel driving circuit connected to it.

[0109] Referring to Figure 23, in one optional embodiment of this disclosure, the second input line 82 includes a first sub-line 821 and a second sub-line 822. The first driving circuit 801 is electrically connected to the driving control line SL through the first sub-line 821, and the second driving circuit 802 is electrically connected to the driving control line SL through the second sub-line 822. The first sub-line 821 is at least partially located in the second display area A02, and the second sub-line 822 is at least partially located in the first display area A01. When the first driving circuit group Z1 is located in the first non-display area A11 adjacent to the second display area A02, routing at least a portion of the first sub-line 821 in the second display area A02 simplifies the connection between the first sub-line 821 and the first driving circuit 801, reduces or avoids the winding of the first sub-line 821, and also allows the first sub-line 821 to be connected to the end of the driving control line SL away from the second non-display area A12, so that a driving signal can be input to the driving control line SL from the end of the driving control line SL away from the second non-display area A12. Similarly, when the second driving circuit group Z2 is located in the first non-display area A11 adjacent to the first display area A01, routing at least a portion of the second sub-line 822 in the first display area A01 simplifies the connection between the second sub-line 822 and the second driving circuit 802, reduces or avoids the winding of the second sub-line 822, and allows the second sub-line 822 to be connected to the end of the driving control line SL near the second non-display area A12, enabling the input of driving signals from the end of the driving control line SL near the second non-display area A12. Thus, the first sub-line 821 and the second sub-line 822 work together to provide driving signals from both ends of the driving control line SL, thereby improving the uniformity of the driving signals transmitted on the driving control line SL and enhancing the driving uniformity of the driving control line SL for the pixel driving circuits connected to it.

[0110] Figure 24 shows a schematic diagram of a layout of power signal lines and gate drive circuit 80 in a display panel. Referring to Figure 24, in an optional embodiment of this disclosure, display area A0 includes a first display area A01, a third display area A03, and a second display area A02 arranged sequentially along a direction away from the second non-display area A12; at least a portion of the gate drive circuit 80 is located in the first non-display area A11 adjacent to the second display area A02 and / or the third display area A03, and along the second direction D2, the gate drive circuit 80 and the multiplexing unit 90 are disposed opposite each other on both sides of the display area A0; the display panel also includes a power sub-line 71 and a power bus 72 electrically connected to the power sub-line 71, at least a portion of the power sub-line 71 is located in the display area A0, and the power bus 72 is located in the non-display area A1; at least a portion of the power bus 72 and the gate drive circuit 80 are located in the same first non-display area A11, and along the first direction D1, the power bus 72 is located between the gate drive circuit 80 and the second non-display area A12. Optionally, the power bus 72 and power sub-line 71 mentioned in this embodiment can correspond to the positive power signal line PVDD in the display panel. Optionally, the display panel also includes a negative power signal line PVEE. It should be noted that when the negative power signal line PVEE is introduced into the display panel, in the non-display area, the negative power signal line PVEE can be located on the side of the power bus 72 near the edge of the display panel.

[0111] The power sub-line 71 mentioned in this embodiment can be wired in the display area A0 to form a grid-like wiring structure, which is used to provide power signals to the pixel driving circuit. The grid-like wiring structure helps to reduce the total impedance of the power lines and reduce the difference in power signals transmitted by the power sub-lines 71 in different areas of the display panel. This disclosure further introduces a power bus 72 in the non-display area A1 to provide power signals to the power sub-line 71 in the display area A0. The line width of the power bus 72 is greater than that of the power sub-line 71. When the gate driving circuit 80 is located in the first non-display area A11 adjacent to the second display area A02 and / or the third display area A03, there will be spare space between the gate driving circuit 80 and the second non-display area A12 to set up the power bus 72. In this way, a larger area power bus 72 can be arranged in the non-display area A1, which helps to reduce the overall impedance of the power bus 72 and the power sub-line 71, increase the rate of power signal transmission from the power bus 72 to the power sub-line 71, reduce the difference in power signals received by the pixel driving circuits in different areas, and help to improve the overall display uniformity of the display panel.

[0112] Based on the same inventive concept, this disclosure also provides a display device. Figure 25 shows a structural schematic diagram of a display device provided in an embodiment of this disclosure. Referring to Figure 25, the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in the embodiments of this disclosure can be any electronic device with display function, such as a tablet computer with touch and display functions, a display cabinet product, a mobile phone, a television, or an in-vehicle display device. The display device 200 provided in the embodiments of this disclosure has the beneficial effects of the display panel 100 provided in the embodiments of this disclosure. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments, which will not be repeated here.

[0113] Optionally, in addition to the display panel 100, the display device 200 may also include a mid-frame, which is at least partially disposed around the periphery of the display panel 100 to protect it. Furthermore, depending on actual needs, the display device 200 may also include components such as a battery and a photosensitive element. The battery provides power to the display panel 100, while the photosensitive element enables functions such as fingerprint recognition in the display device 200.

[0114] It is understood that Figure 25 only illustrates the display device with a rectangular structure. In some other embodiments of this disclosure, the display device 200 may also be embodied in any other feasible shape such as a rounded rectangle, and this disclosure does not specifically limit it in this regard.

[0115] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0116] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, comprising a display area and a non-display area located around the display area, the non-display area comprising a first non-display area and a second non-display area, the second non-display area being located on one side of the display area along a first direction, and the first non-display area being located on opposite sides of the display area along a second direction; the second non-display area comprising a bonding area, the bonding area comprising bonding pads; the display panel comprising: Multiple drive control lines, which extend along a first direction and are arranged along a second direction, the first direction and the second direction intersecting; Multiple data lines, which extend along the second direction and are arranged along the first direction; Multiple multiplexing units are located in the first non-display area. Each multiplexing unit includes one input terminal and N output terminals. The N output terminals are connected to N data lines, where N ≥ 2. The input terminal of each multiplexing unit is connected to a first input line. At least a portion of the first input line is located in the display area. The first input line is configured to acquire data signals from the bonding pads.

2. The display panel of claim 1, wherein, The first input line includes a first connection line and a second connection line that are electrically connected. The first connection line extends along the second direction and is connected to the input terminal of the multiplexing unit. The second connection line extends along the first direction and is connected to the bonding pad of the bonding area.

3. The display panel of claim 2, wherein, The first connecting line is arranged on the same layer as the data line.

4. The display panel of claim 2, wherein, The first connecting line and the data line are disposed on different layers and are arranged in a direction perpendicular to the light-emitting surface of the display panel, and the first connecting line and the data line do not overlap.

5. The display panel of claim 2, wherein, It also includes a plurality of first auxiliary lines extending along the second direction, wherein the first auxiliary lines and the first connecting lines are in the same layer and are insulated from each other; along the first direction, the spacing between adjacent first auxiliary lines is S01, and the spacing between adjacent first auxiliary lines and the first connecting lines is S02, where S01 = S02.

6. The display panel of claim 5, wherein, At least a portion of the first auxiliary line is electrically connected to a fixed potential signal.

7. The display panel of claim 2, wherein, The second connecting line is disposed on the same layer as the driving control line, or the second connecting line is disposed on a different layer from the driving control line. Along the direction perpendicular to the light-emitting surface of the display panel, the second connecting line and the driving control line do not overlap.

8. The display panel according to claim 7 further includes a plurality of second auxiliary lines extending along the first direction, wherein the second auxiliary lines and the second connecting lines are disposed on the same layer; along the second direction, the spacing between adjacent second auxiliary lines is S11, and the spacing between adjacent second auxiliary lines and the second connecting lines is S12, wherein S11 = S12.

9. The display panel of claim 8, wherein, At least one of the second auxiliary lines is electrically connected to a fixed potential signal.

10. The display panel of claim 1, wherein, N≤5。 11. The display panel of claim 10, wherein, The multiplexing unit is connected to N data lines arranged continuously along the first direction.

12. The display panel of claim 10, wherein, The plurality of multiplexing units include a first multiplexing unit and a second multiplexing unit. The first multiplexing unit is connected to N odd-numbered data lines arranged adjacent to each other along the first direction, and the second multiplexing unit is connected to N even-numbered data lines arranged adjacent to each other along the first direction.

13. The display panel according to claim 2 further includes a gate driving circuit, the gate driving circuit being electrically connected to the driving control line, and the gate driving circuit being located in the first non-display area; The gate driving circuit is electrically connected to the driving control line through a second input line. The second input line extends along the second direction and is disposed on a different layer from the driving control line. The second input line is at least partially located in the display area.

14. The display panel of claim 13, wherein, The second input line is disposed on the same layer as the data line, or the second input line is disposed on a different layer from the data line. Along the direction perpendicular to the light-emitting surface of the display panel, the second input line and the data line do not overlap.

15. The display panel of claim 13, wherein, The second input line is disposed on the same layer as the first connecting line; at least a portion of the second input line is located in the extension direction of the first connecting line, and along the second direction, there is a first gap between the first connecting line and the second input line located in its extension direction.

16. The display panel of claim 13, wherein, The display area includes a first display area, a third display area, and a second display area arranged sequentially in a direction away from the second non-display area; the gate driving circuit is located in the first non-display area adjacent to the third display area and / or the second display area.

17. The display panel of claim 16, wherein, At least a portion of the second input line is located in the third display area and / or the second display area.

18. The display panel of claim 13, wherein, The gate driving circuit includes a first driving circuit group and a second driving circuit group. The first driving circuit group includes a plurality of first driving circuits, and the second driving circuit group includes a plurality of second driving circuits. At least one driving control line is electrically connected to both the first driving circuit and the second driving circuit.

19. The display panel of claim 18, wherein, The display area includes a first display area, a third display area, and a second display area arranged sequentially along a direction away from the second non-display area; The first driving circuit group and the second driving circuit group are respectively located in the first non-display area, which is arranged opposite to the third display area and / or the second display area along the second direction.

20. The display panel of claim 18, wherein, The display area includes a first display area, a third display area, and a second display area arranged sequentially along a direction away from the second non-display area; The first driving circuit group is located on one side of the second display area along the second direction. Along the second direction, the first driving circuit group and the multiplexing unit are disposed opposite to each other on different sides of the display area. The second driving circuit group is located on one side of the first display area along the second direction, and along the second direction, the second driving circuit group and the multiplexing unit are located on the same side of the display area.

21. The display panel of claim 20, wherein, The second input line includes a first sub-line and a second sub-line. The first driving circuit is electrically connected to the driving control line through the first sub-line, and the second driving circuit is electrically connected to the driving control line through the second sub-line. The first sub-line is at least partially located in the second display area, and the second sub-line is at least partially located in the first display area.

22. The display panel of claim 13, wherein, Along the second direction, the gate driving circuit and the multiplexing unit are disposed opposite to each other in different first non-display areas.

23. The display panel of claim 13, wherein, The display area includes a first display area, a third display area, and a second display area arranged sequentially along a direction away from the second non-display area; at least a portion of the gate driving circuit is located in the first non-display area adjacent to the second display area and / or the third display area, and along the second direction, the gate driving circuit and the multiplexing unit are disposed opposite to each other on both sides of the display area; The display panel further includes a power sub-line and a power bus electrically connected to the power sub-line. At least a portion of the power sub-line is located in the display area, and the power bus is located in the non-display area. At least a portion of the power bus is located in the same first non-display area as the gate driving circuit, and along the first direction, the power bus is located between the gate driving circuit and the second non-display area.

24. The display panel of claim 1, wherein, The display panel includes multiple rows of pixel circuits arranged along the first direction and multiple columns of pixel circuits arranged along the second direction. Each row and column of pixel circuits includes multiple pixel driving circuits, and the number of rows of pixel circuits is greater than the number of columns of pixel circuits.

25. A display device comprising a display panel as described in any one of claims 1 to 24.

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