Video synchronization method and apparatus, electronic device, and storage medium

Abstract

The present disclosure relates to the technical field of videos, and provides a video synchronization method and apparatus, an electronic device, and a storage medium. The method comprises: measuring a reference frame synchronization signal by using a master clock, and calculating a first frequency multiple between a video clock of a video interface and the master clock on the basis of the measurement result; generating two frequency multiples closest to the first frequency multiple, and generating a first adjustment clock and a second adjustment clock of different frequencies on the basis of the two frequency multiples; generating a first target synchronization signal of the master clock and a second target synchronization signal of the video clock on the basis of the reference frame synchronization signal and a video parameter of the video interface; comparing the phase of the first target synchronization signal with the phase of the second target synchronization signal; and switching, on the basis of the comparison result, the video clock to the first adjustment clock or the second adjustment clock when a switchable moment is reached, so that a first frame synchronization signal generated on the basis of the master clock is synchronized with a second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal. The present disclosure can achieve complete synchronization between video data of a plurality of video interfaces.

Description

Video synchronization methods and apparatus, electronic devices and storage media

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202411950455X, filed on December 27, 2024, entitled “Video Synchronization Method and Apparatus, Electronic Device and Storage Medium”, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to the field of video technology, and in particular to a video synchronization method and apparatus, electronic device and storage medium. Background Technology

[0004] When outputting video data from multiple video interfaces (which can originate from the same device or different devices), the video frame is divided into multiple screen regions. Each video interface corresponds one-to-one with a specific screen region, and each interface outputs video data for its corresponding region. Since the video data output by each interface is only used to display a portion of the video frame, it is essential to ensure complete synchronization of the video data across all interfaces to guarantee proper video display.

[0005] In practice, it is difficult to ensure that the clock frequencies of multiple video interfaces are consistent, which makes it difficult to fully synchronize the video data of multiple video interfaces. Summary of the Invention

[0006] This disclosure provides a video synchronization method, apparatus, electronic device, and storage medium to solve the defect in the prior art where the video data of multiple video interfaces are not completely synchronized when outputting video data of the same video frame based on multiple video interfaces, and to achieve complete synchronization between the video data of multiple video interfaces.

[0007] This disclosure provides a video synchronization method, including the following steps:

[0008] The reference frame synchronization signal is measured based on the master clock. The first multiplier between the video clock of the video interface and the master clock is calculated based on the measurement result. Based on the first multiplier, a first adjustment clock and a second adjustment clock of different frequencies are generated. The first adjustment clock is generated based on a second multiplier less than the first multiplier, and the second adjustment clock is generated based on a third multiplier greater than the first multiplier. The second and third multipliers are two adjacent multipliers after being ordered in ascending order of magnitude. Based on the reference frame synchronization signal and the video parameters of the video interface, a first target synchronization signal for the master clock and a second target synchronization signal for the video clock are generated. Both the first and second target synchronization signals are either row synchronization signals or column synchronization signals. The phases of the first and second target synchronization signals are compared. Based on the phase comparison result, when a switchable time is reached, the video clock is switched to either the first or second adjustment clock, so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

[0009] This disclosure also provides a video synchronization device, including the following modules:

[0010] The master clock measurement module is used to measure the reference frame synchronization signal according to the master clock, and calculate the first multiplication factor between the video clock of the video interface and the master clock based on the measurement results;

[0011] The clock generation module is used to generate a first adjusted clock and a second adjusted clock of different frequencies based on the first multiplier; wherein, the first adjusted clock is generated based on a second multiplier that is less than the first multiplier, and the second adjusted clock is generated based on a third multiplier that is greater than the first multiplier, and the second multiplier and the third multiplier are two adjacent multipliers after multiple available multipliers are sorted in order of magnitude;

[0012] The synchronization signal generation module is used to generate a first target synchronization signal for the master clock and a second target synchronization signal for the video clock based on the reference frame synchronization signal and the video parameters of the video interface; the first target synchronization signal and the second target synchronization signal are row synchronization signals, or the first target synchronization signal and the second target synchronization signal are column synchronization signals;

[0013] The phase comparison module is used to compare the phases of the first target synchronization signal and the second target synchronization signal;

[0014] The clock control module is used to switch the video clock to a first adjustment clock or a second adjustment clock when the switchable time is reached, based on the phase comparison result, so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

[0015] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement any of the video synchronization methods described above.

[0016] This disclosure also provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements any of the video synchronization methods described above.

[0017] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements any of the video synchronization methods described above. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a flowchart illustrating one of the video synchronization methods provided in this embodiment of the present disclosure.

[0020] Figure 2 is a flowchart of the data processing of the video synchronization method provided in the embodiments of this disclosure.

[0021] Figure 3 is a diagram of VESA standard parameters.

[0022] Figure 4 is a schematic diagram of the number of intermediate cycles and the number of residual pixels in the video synchronization method provided in the embodiments of this disclosure.

[0023] Figure 5 is a schematic diagram of the video synchronization method provided in this embodiment of the present disclosure, which adjusts the synchronization signal based on the phase comparison result.

[0024] Figure 6 is a second schematic flowchart of the video synchronization method provided in this embodiment of the present disclosure.

[0025] Figure 7 is a schematic diagram of an example of a period count value in the video synchronization method provided in the embodiments of this disclosure.

[0026] Figure 8 is a schematic diagram of the structure of the video synchronization device provided in the embodiments of this disclosure.

[0027] Figure 9 is a schematic diagram of the structure of the electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] In related technologies, when outputting video data of a single video frame based on multiple video interfaces, it is difficult to ensure the consistency of the video clock frequencies of multiple video interfaces due to the involvement of multiple devices and multiple video interface video clocks, which makes it difficult to fully synchronize the video data of multiple video interfaces.

[0030] For example, in some solutions, in order to make the video clock frequency of multiple video interfaces consistent, multiple video interfaces can use the same source clock. In this case, if the multiple video interfaces come from multiple different devices, multiple traces need to be set up to couple a clock (i.e., the same source clock) to multiple devices through the traces.

[0031] In practice, the wiring between clock and video equipment is often quite long. Excessive wiring leads to poor quality clock signals received by the equipment, making it difficult to guarantee the consistency of video clock frequencies across multiple video interfaces, and also increases costs. For example, some solutions use a single frame synchronization signal for frame synchronization, but this only considers frame-to-frame synchronization, neglecting line-to-line synchronization. This results in a half-frame to a full-frame discrepancy between different video interfaces, making it difficult to guarantee complete synchronization of video data across multiple interfaces, leading to poor video quality and a negative user experience. Furthermore, some solutions use phase interpolators to frequency-modulate multiple video interfaces to achieve complete synchronization. However, devices supporting phase interpolators are generally high-end, and the adjustable clock frequency range of phase interpolators is limited, making it difficult to meet millisecond-level adjustment requirements. When the clock frequencies of multiple video interfaces are outside the adjustable range of the phase interpolator, complete synchronization cannot be guaranteed. This method has poor versatility, is expensive, and is difficult to popularize.

[0032] On the other hand, some video interfaces (such as BT1120 / LVDS, see the next paragraph for details) have high requirements for the stability of the video clock. If the clock frequency of the video clock is adjusted arbitrarily, it will cause the video to have a black screen, blue screen, etc., and thus the ideal adjustment effect cannot be obtained.

[0033] BT.1120 typically refers to a video interface standard, part of the ITU-R BT.1120 standard, used for the transmission of Ultra High Definition (UHD) and High Dynamic Range (HDR) video signals. The ITU-R BT.1120 standard, developed by the International Telecommunication Union (ITU), aims to define and standardize parameters for UHD video, including resolution, frame rate, color space, and bit depth. Similar video transmission interfaces include Low Voltage Differential Signaling (LVDS) and Mobile Industry Processor Interface (MIPI), all of which have high requirements for clock stability.

[0034] In view of the above-mentioned problems, this disclosure provides a video synchronization method to solve the problem that the video data of multiple video interfaces are not completely synchronized when outputting video data of the same video frame based on multiple video interfaces in the prior art.

[0035] The video synchronization method disclosed herein is described below with reference to Figures 1-7.

[0036] The embodiments disclosed herein can achieve complete synchronization of multiple video interfaces. These multiple video interfaces can originate from a single device (single device) or from multiple different devices.

[0037] Figure 1 is a flowchart of one of the video synchronization methods provided in this disclosure. As shown in Figure 1, the method includes the following steps S110 to S150.

[0038] S110: Measure the reference frame synchronization signal according to the master clock, and calculate the first multiplication factor between the video clock of the video interface and the master clock based on the measurement result.

[0039] As shown in Figure 2, the execution process of S110 is carried out in the master clock measurement module.

[0040] Specifically, the master clock measurement module can receive a reference frame synchronization signal from an external source. It then measures the master clock based on the reference frame synchronization signal to obtain the measurement result.

[0041] The above measurement results represent the number of master clock cycles contained within one cycle of the reference frame synchronization signal, or they can be understood as the ratio of the frequency of the reference frame synchronization signal to the frequency of the master clock.

[0042] In some embodiments, a counter C1 can be set, with the master clock as the driving clock of the counter C1. When a frame synchronization pulse in the reference frame synchronization signal is detected, the counter C1 is controlled to start counting, and when the next frame synchronization pulse arrives, the counting ends. The counting result of the counter C1 is the measurement result described above.

[0043] In some embodiments, referring to Figure 2, video parameters can also be received synchronously when receiving a reference frame synchronization signal from an external source. When measuring the reference frame synchronization signal according to the master clock, video parameters can be introduced as a unit of measurement, and two measurement results are measured (see the corresponding description below; the specific meaning of these two measurement results is not explained here), and these two measurement results are used as the measurement result. The measurement process may include: receiving the reference frame synchronization signal and video parameters of the video interface, the video parameters including: the number of first pixels in a first direction and the number of second pixels in a second direction of the video interface. After that, based on the master clock, the reference frame synchronization signal, and the number of first pixels, the number of cycles in which the number of first pixels is fully displayed based on the master clock within one cycle of the frame synchronization signal, and the number of residual pixels that cannot fully display the number of first pixels are obtained; finally, the first frequency multiplication factor is calculated based on the number of first pixels, the number of second pixels, the number of cycles, and the number of residual pixels.

[0044] The first direction mentioned above can be a row direction, in which case the second direction is a column direction; alternatively, the first direction can also be a column direction, in which case the second direction is a row direction. The first direction is the refresh direction when the video image is displayed.

[0045] The video parameters can be standard video parameters defined by the Video Electronics Standards Association (VESA) (hereinafter referred to as VESA standard parameters), as shown in Figure 3. Of course, it is understood that the video parameters can also be user-defined custom video parameters. In this embodiment, for ease of understanding, VESA standard parameters are used as an example for illustration.

[0046] As shown in Figure 3, in the VESA standard parameters, the total number of rows in the video, V = 1125 (see the 1125lines box at the bottom of Figure 3, indicating that the total number of rows in the video is 1125), and the total number of columns, H = 2200 (see the 2200Pixels box in the middle of Figure 3, indicating that the total number of columns in the video is 2200). When the refresh direction is column-oriented, the video frame rate has a vertical frequency (corresponding to Ver Frequency in Figure 3) of 60Hz (see the 60.000 box at the top of Figure 3). In this case, the number of first pixels is 1125, and the number of second pixels is 2200. The first direction is column-oriented, and the number of first pixels equals the total number of rows in the video. The second direction is row-oriented, and the number of second pixels equals the total number of columns in the video.

[0047] It should be noted that the other parameters in Figure 3 have no substantial impact on the solution in the embodiments of this disclosure, and the embodiments of this disclosure will not provide further explanation of the other parameters in Figure 3.

[0048] When measuring two measurement results based on video parameters, two counters can be set, such as counter C2 and counter C3. The master clock is used as the driving clock for counter C2. When a frame synchronization pulse in the reference frame synchronization signal is detected, counter C2 starts counting. Each time the count reaches the target value, counter C2 is reset to zero, and counter C3 is incremented by 1. Counting ends when the next frame synchronization pulse of the reference frame synchronization signal arrives, and the count results from counters C2 and C3 are obtained.

[0049] The target value can be obtained from either the total number of rows or the total number of columns of video pixels in the video standard. The smaller of these two values ​​is selected as the target value.

[0050] In practice, if the total number of rows is less than the total number of columns, the total number of rows is reduced by 1 (because the counter starts counting from 0, so the final maximum value to be counted is reduced by 1) to obtain the target value. If the total number of columns is less than the total number of rows, the total number of columns is reduced by 1 to obtain the target value.

[0051] As shown in Figure 3, the number of first pixels = the total number of rows in the video V = 1125, and the number of second pixels = the total number of columns in the video H = 2200. In this case, if the refresh direction when the video is displayed is the column direction, the total number of rows in the video 1125 is used to determine the target value, and the target value = 1125 - 1 = 1124.

[0052] Two counting results can be obtained by using the counting methods of the two counters mentioned above, namely the counting result 1 of counter C2 and the counting result 2 of counter C3.

[0053] The mathematical relationship between the counting result 1 and the frequency of the master clock, the frequency of the reference frame synchronization signal, and the number of first pixels is shown in Formula 1 below.

[0054] Formula 1:

[0055] Among the symbols This indicates the floor function.

[0056] The mathematical relationship between count result 2 and the frequency of the master clock, the frequency of the reference frame synchronization signal, the number of first pixels, and count result 1 is shown in Formula 2 below.

[0057] Formula 2:

[0058] For example, if the frequency of the master clock is set to 25MHz, the number of first pixels = the total number of lines in the video V = 1125, and the frequency of the reference frame synchronization signal is 60Hz, then the following counting results 1 and 2 can be obtained.

[0059] Referring to Figure 4, counting result 1 involves displaying one pixel of a video frame every master clock cycle within one cycle of the reference frame synchronization signal, with a fixed number of 1125 rows. Based on this, the number of cycles in the first direction can be obtained, which is the number of pixels per row. Counting result 2 involves displaying one pixel every master clock cycle within one cycle of the reference frame synchronization signal. If a column of pixels is not fully displayed by the end of that cycle, the number of undisplayed pixels in the column where some pixels were displayed is the number of residual pixels, which is the number of pixels in the shaded area of ​​Figure 4.

[0060] The measurement result is actually the number of master clock cycles that pass within one cycle of the reference frame synchronization signal. In essence, the measurement result is the ratio of the master clock frequency to the reference frame synchronization signal frequency. That is, the master clock frequency = measurement result × reference frame synchronization signal frequency.

[0061] The process described above involves measuring the reference frame synchronization signal based on the master clock and obtaining the measurement result. The following describes the process of calculating the first multiplication factor between the video interface's video clock and the master clock based on the measurement result.

[0062] According to the definition of frequency multiplication, the first frequency multiplication can be obtained as: video clock frequency / master clock frequency.

[0063] For the video clock frequency, in the VESA standard parameters, the video clock frequency = F1 × V × H, where F1 is the video frame rate. As shown in Figure 3, F1 = 60Hz, and the video clock frequency = F1 × V × H = 148.5MHz.

[0064] For ease of calculation, the video frame rate F1 is adjusted to be consistent with the frequency F2 of the reference frame synchronization signal. The first multiplication factor between the video clock of the video interface and the master clock can be calculated using the following formula.

[0065] B1 represents the first harmonic frequency, and K represents the measurement result.

[0066] Of course, it is understandable that in specific implementations, the video frame rate F1 and the frequency F2 of the reference frame synchronization signal may not be the same. In this disclosure, the example given is that the video frame rate F1 and the frequency F2 of the reference frame synchronization signal are the same.

[0067] Given the number of cycles and the number of residual pixels based on video parameters, assuming the refresh direction during video display is column-oriented, K = V × Z + P; where Z is the number of cycles and P is the number of residual pixels. Based on this, the first harmonic can be calculated using the following formula.

[0068] Based on the count result 1 of 370 (i.e., number of cycles) and count result 2 of 416 (i.e., number of residual pixels) obtained in the above example, substituting V=1125, H=2200, Z=370, P=416 into the above formula, we can obtain the following calculation results.

[0069] S120: Generate a first adjustment clock and a second adjustment clock with different frequencies based on the first multiplier; wherein, the first adjustment clock is generated based on the second multiplier which is less than the first multiplier, and the second adjustment clock is generated based on the third multiplier which is greater than the first multiplier, and the second multiplier and the third multiplier are two adjacent multipliers after multiple available multipliers are sorted in order of size.

[0070] As shown in Figure 2, the execution process of S120 can be performed in the clock generation and control module.

[0071] Specifically, based on the first harmonic frequency B1 obtained in S110, the second harmonic frequency B2 and the third harmonic frequency B3 that are closest to the first harmonic frequency B1 can be determined from among multiple available harmonic frequencies. The magnitude relationship of B1, B2, and B3 satisfies: B2 <B1<B3。

[0072] In some embodiments, multiple available frequency multipliers are obtained based on multiple frequency multiplication parameters and multiple frequency division parameters in the phase-locked loop.

[0073] Specifically, when multiple frequency multiplication parameters and multiple frequency division parameters are used in combination in a phase-locked loop, clocks of various frequencies can be obtained. Based on this, the frequency multiplication parameters and frequency division parameters corresponding to the second frequency multiplication and the third frequency multiplication can be selected from among the multiple frequency multiplication parameters and multiple frequency division parameters, according to the first frequency multiplication, to obtain the second frequency multiplication and the third frequency multiplication.

[0074] For example, B1 = 5.94. Since the frequency multiplication parameter in the phase-locked loop can only be set to an integer, the frequency multiplication parameter can be 59 or 60, and the frequency division parameter is 10. Therefore, B2 = 59 / 10 = 5.9, and B3 = 60 / 10 = 6. A first adjustment clock can be generated based on B2, and a second adjustment clock can be generated based on B3. The first and second adjustment clocks are the clocks that are closest to the video clock of the video interface that can be generated.

[0075] Taking a master clock frequency of 25MHz as an example, the frequency of the first adjustment clock is 25MHz × 5.9 = 147.5MHz, and the frequency of the second adjustment clock is 25MHz × 6 = 150MHz. The frequency of the first adjustment clock is less than the frequency of the second adjustment clock. Based on the example above where the video clock frequency obtained from VESA standard parameters is 148.5MHz, it can be seen that the frequency of the first adjustment clock is less than the frequency of the video clock, and the frequency of the second adjustment clock is greater than the frequency of the video clock.

[0076] Of course, it is understood that the above-listed methods for obtaining the second and third harmonics are merely exemplary. In specific implementations, the methods for obtaining the second and third harmonics in this disclosure include, but are not limited to, the methods listed above. For example, multiple available harmonics can be preset, and when selecting the second and third harmonics, they can be directly selected from the multiple available harmonics, as long as the second harmonic is less than the first harmonic and the third harmonic is greater than the first harmonic.

[0077] S130: Generate a first target synchronization signal for the master clock and a second target synchronization signal for the video clock based on the reference frame synchronization signal and the video parameters of the video interface; both the first target synchronization signal and the second target synchronization signal are row synchronization signals, or both the first target synchronization signal and the second target synchronization signal are column synchronization signals.

[0078] Referring to Figure 2, the execution process of S130 can be performed in the synchronization signal generation module.

[0079] Specifically, the number of cycles and the number of residual pixels can be obtained based on the reference frame synchronization signal and the video parameters of the video interface (see the corresponding description in S110, which will not be repeated here), and the first target synchronization signal can be generated based on the number of cycles and the number of residual pixels.

[0080] When the number of first pixels equals the total number of lines in the video, both the first target synchronization signal and the second target synchronization signal are line synchronization signals. In this case, the first line synchronization signal and the first frame synchronization signal under the master clock are generated based on the number of cycles, the number of residual pixels, and the number of first pixels. The second line synchronization signal and the second frame synchronization signal under the video clock are generated based on the video parameters.

[0081] When the number of first pixels equals the total number of columns in the video, both the first target synchronization signal and the second target synchronization signal are column synchronization signals. In this case, the first column synchronization signal and the first frame synchronization signal under the master clock are generated based on the number of periods, the number of residual pixels, and the number of first pixels. The second column synchronization signal and the second frame synchronization signal under the video clock are generated based on the video parameters.

[0082] Referring to Figure 2, the process of generating the second line synchronization signal and the second frame synchronization signal under the video clock based on the video parameters can be performed in the video output module.

[0083] S140: Compare the phases of the first target synchronization signal and the second target synchronization signal.

[0084] The phase comparison results include: the second target synchronization signal is ahead of the first target synchronization signal in phase, or the second target synchronization signal is behind the first target synchronization signal in phase.

[0085] For example, when the first target synchronization signal and the second target synchronization signal are line synchronization signals, in S130, the first line synchronization signal and the first frame synchronization signal under the master clock are generated, and the second line synchronization signal and the second frame synchronization signal under the video clock are generated according to the video parameters. In this case, comparing the phases of the first target synchronization signal and the second target synchronization signal specifically involves: determining a first line synchronization pulse in the first line synchronization signal and determining a second line synchronization pulse that matches the first line synchronization pulse in the second line synchronization signal based on the first line synchronization signal, the first frame synchronization signal, the second line synchronization signal, and the second frame synchronization signal; if the second line synchronization pulse leads the first line synchronization pulse, it is determined that the second target synchronization signal leads the first target synchronization signal; if the second line synchronization pulse lags the first line synchronization pulse, it is determined that the second target synchronization signal lags the first target synchronization signal.

[0086] Referring to Figure 5, Vsync1 is the first frame synchronization signal, Hsync1 is the first line synchronization signal, Vsync2 is the second frame synchronization signal, and Hsync2 is the second line synchronization signal. Pulse E1 is the first line synchronization pulse, and pulse E2 is the second line synchronization pulse matched with pulse E1. Pulse E3 is the first line synchronization pulse, and pulse E4 is the second line synchronization pulse matched with pulse E3.

[0087] The first and second line of synchronization pulses correspond to the first frame synchronization pulse in the first frame synchronization signal and the second frame synchronization pulse in the second frame synchronization signal, respectively. Therefore, only by finding the matching frame synchronization pulses can the first line of synchronization pulses and the matching second line of synchronization pulses be determined.

[0088] In practice, two counters can be set up. One counter corresponds to the first frame synchronization signal and the first line synchronization signal, while the other counter corresponds to the second frame synchronization signal and the second line synchronization signal. When a frame synchronization pulse arrives in the first frame synchronization signal, the counter corresponding to the first frame synchronization signal is reset to zero. Afterward, for each subsequent line synchronization pulse in the first line synchronization signal, the counter corresponding to the first line synchronization signal is incremented by 1. Similarly, when a frame synchronization pulse arrives in the second frame synchronization signal, the counter corresponding to the second frame synchronization signal is reset to zero. Afterward, for each subsequent line synchronization pulse in the second line synchronization signal, the counter corresponding to the second line synchronization signal is incremented by 1. When the count results of the two counters are the same, the pulse corresponding to the count result is the matching line synchronization pulse, thus determining the first and second line synchronization pulses.

[0089] After determining the first and second synchronization pulses, as shown in Figure 5, pulse E2 arrives earlier than pulse E1, indicating that the second target synchronization signal is ahead of the first target synchronization signal in phase. Pulse E4 arrives later than pulse E3, indicating that the second target synchronization signal is behind the first target synchronization signal in phase.

[0090] S150: Based on the phase comparison result, when the switchable moment is reached, the video clock is switched to the first adjustment clock or the second adjustment clock so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

[0091] Referring to Figure 5, if the phase comparison result shows that the second target synchronization signal is ahead of the first target synchronization signal, it indicates that the video clock of the video interface is too fast and needs to be slowed down. The video clock of the video interface should be adjusted to the first adjustment clock with a lower frequency. Conversely, if the phase comparison result shows that the second target synchronization signal is behind the first target synchronization signal, it indicates that the video clock of the video interface is too slow and needs to be speeded up. The video clock of the video interface should be adjusted to the second adjustment clock with a higher frequency.

[0092] In some embodiments, the switchable time can be determined by testing, and then, based on the phase comparison results, the video clock can be switched to a first adjustment clock or a second adjustment clock when the switchable time is reached.

[0093] In some embodiments, the moment when the phase deviation of the first adjustment clock or the second adjustment clock is the smallest can be obtained, and this moment can be determined as the switchable moment. Based on this, before executing S150, as shown in FIG6, the following S610 to S620 can also be executed.

[0094] S610: Calculates the cycle count value based on the second multiplier, the third multiplier, and the master clock.

[0095] Since the second and third harmonics are generated based on the same harmonic (i.e., the first harmonic), for the first adjusted clock generated based on the second harmonic and the second adjusted clock generated based on the third harmonic, an offset period can always be calculated based on the first and second adjusted clocks, ensuring that the phase offset patterns of the two clocks are consistent within this offset period. In other words, within the offset period, there is one and only one cycle count value N such that the number of cycles for the first adjusted clock differs from the number of cycles for the second adjusted clock by 1.

[0096] In some embodiments, the counting clock is determined as the second adjustment clock, and the cycle count N value can be calculated using the following formula.

[0097] Among them, F 主 The frequency of the master clock.

[0098] For example, F 主 =25MHz, B2=5.9, B3=6. Substituting these parameters into the formula above, we can obtain... Solving for N, we get N = 60.

[0099] As shown in Figure 7, T0 is the offset period. Within T0, there are 59 periods T1 of the first adjustment clock and 60 periods T2 of the second adjustment clock. The number of periods of the first and second adjustment clocks within T0 differs by 1. Under these circumstances, there can be a moment within T0 at which the phase deviation between the first and second adjustment clocks is minimized. This moment can be determined as the switchable moment. For details on how to determine the switchable moment based on the period count value and the counting clock, please refer to the description in S620.

[0100] S620: Determine the switchable time based on the period count value and the counting clock; wherein the counting clock is either the first adjustment clock or the second adjustment clock.

[0101] For example, a counter 4 can be set up. If N is calculated using a second adjustment clock as the counting clock, then the second adjustment clock is used as the driving clock for counter 4. Counter 4 starts counting from 0 and restarts every time it counts to N-1. During the counting process from 0 to N-1, each count of counter 4 corresponds to a moment within the counting clock T0. Similarly, if N is calculated using a first adjustment clock as the counting clock, then the first adjustment clock is used as the driving clock for counter 4. Counter 4 starts counting from 0 and restarts every time it counts to N-1.

[0102] While counter 4 is counting, a video clock is input to the clock generation unit, where the video clock is obtained by switching between the first adjustment clock and the second adjustment clock. At any point within the counting time range of counter 4 up to T0, the video clock is switched, and the clock generation unit is checked for lockout. If the clock generation unit is lockout, it indicates that the phase deviation between the first and second adjustment clocks is large at the time corresponding to that count of counter 4, and that the time corresponding to that count of counter 4 is not a switchable time. If the clock generation unit is not lockout, it indicates that the phase deviation between the first and second adjustment clocks is small at the time corresponding to that count of counter 4, and that time is a switchable time.

[0103] In practice, after inputting the first adjustment clock and the second adjustment clock into the clock generation unit, the process of counter 4 counting from 0 to N-1 can be repeated multiple times to find the moment when the phase deviation between the first adjustment clock and the second adjustment clock is the smallest, which is the switchable moment.

[0104] In practice, after each power-on, steps S610 to S620 can be executed to re-determine the moment when the phase deviation between the first and second adjustment clocks is minimal, and this moment is designated as the switchable moment. This ensures that the clock switching process does not affect the smoothness of the video viewing process.

[0105] For the switchable time determined in S610-S620, a clock control signal (see clock control signal in Figure 5) can be generated based on the phase comparison result and the switchable time. In this case, referring to Figure 2, the execution process of S140-S150, S610-S620 is performed in the phase comparison module. The clock generation and control module receives the above clock control signal, and before reaching the Nc time (i.e., the switchable time, such as Nc1 or Nc2 in Figure 5) where the phase deviation between the first adjustment clock and the second adjustment clock is the smallest, it can set the level of the next Nc time to come to a high level or a low level according to the phase comparison result. For example, referring to Figure 5, if pulse E2 arrives earlier than pulse E1, it is determined that the second target synchronization signal is ahead of the first target synchronization signal in phase. In this case, the video clock needs to be adjusted to the first adjustment clock. Therefore, the level of the next Nc moment (i.e., Nc1 moment in Figure 5) is set to a high level. The clock control module adjusts the video clock to the first adjustment clock when the level in the clock control signal changes from the current low level to a high level, according to the clock control signal. After this, referring to Figure 5 again, if pulse E4 arrives later than pulse E3, it is determined that the second target synchronization signal is behind the first target synchronization signal in phase. In this case, the video clock needs to be adjusted to the second adjustment clock. The level of the next Nc moment (i.e., Nc2 moment in Figure 5) is set to a low level. The clock control module adjusts the video clock to the second adjustment clock when the level in the clock control signal changes from the current high level to a low level, according to the clock control signal.

[0106] It should be noted that, as shown in Figure 5, the purpose of synchronizing the first and second line synchronization signals is to synchronize the first and second frame synchronization signals. The first frame synchronization signal is generated based on the reference frame synchronization signal, and the first frame synchronization signal is synchronized with the reference frame synchronization signal. When the first and second frame synchronization signals are synchronized, the second frame synchronization signal of all video interfaces is synchronized with the reference frame synchronization signal. This allows the video clocks of all video interfaces to be adjusted to be consistent, thus achieving synchronization of multiple video clocks.

[0107] Referring to Figure 2, the clock generation and control module outputs the adjusted video clock to the video output module based on the adjustment result of the video clock of the video interface. The video output module outputs the required video timing according to the video data and video parameters, driven by the adjusted video clock. This includes the second frame synchronization signal and the second line synchronization signal of the video interface. The first second frame synchronization signal of the video interface is synchronized with the reference frame synchronization signal. Subsequently, the second frame synchronization signal and the second line synchronization signal must be generated in accordance with the above S110 to S150.

[0108] In some embodiments, referring to Figure 2, other functional modules may be provided to facilitate video processing of video data, such as video scaling, video cropping, etc.

[0109] The video synchronization method disclosed herein can measure the reference frame synchronization signal according to the master clock, calculate the first multiplier between the video clock of the video interface and the master clock based on the measurement result; generate a first adjustment clock and a second adjustment clock of different frequencies based on the first multiplier; wherein the first adjustment clock is generated based on a second multiplier less than the first multiplier, and the second adjustment clock is generated based on a third multiplier greater than the first multiplier, and the second and third multipliers are two adjacent multipliers after multiple available multipliers are sorted in order of magnitude; generate a first target synchronization signal of the master clock and a second target synchronization signal of the video clock according to the reference frame synchronization signal and the video parameters of the video interface; both the first target synchronization signal and the second target synchronization signal are row synchronization signals, or both are column synchronization signals; compare the phases of the first target synchronization signal and the second target synchronization signal; and, based on the phase comparison result, switch the video clock to the first adjustment clock or the second adjustment clock when a switchable time is reached, so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal. Therefore, this disclosure can adjust the second frame synchronization signal of the video clock of multiple video interfaces to synchronize with the reference frame synchronization signal, so that the second frame synchronization signal of the video clock of all video interfaces is synchronized, thereby realizing the synchronization of the video clock of all video interfaces. This solves the defect in the prior art that the video data of multiple video interfaces are not completely synchronized when outputting video data of the same video frame based on multiple video interfaces, and realizes complete synchronization between the video data of multiple video interfaces.

[0110] The video synchronization method of this disclosure can achieve complete synchronization of multiple video interfaces using only one frame synchronization pulse signal, which is highly versatile and low in cost.

[0111] The video synchronization device provided in this disclosure is described below. The video synchronization device described below and the video synchronization method described above can be referred to in correspondence.

[0112] Figure 8 is a schematic diagram of the structure of a video synchronization device provided in an embodiment of this disclosure. As shown in Figure 8, the video synchronization device 800 includes the following modules.

[0113] The master clock measurement module 801 is used to measure the reference frame synchronization signal according to the master clock, and calculate the first multiplication factor between the video clock of the video interface and the master clock based on the measurement results.

[0114] The clock generation module 802 is used to generate a first adjusted clock and a second adjusted clock of different frequencies based on the first multiplier; wherein the first adjusted clock is generated based on a second multiplier that is less than the first multiplier, and the second adjusted clock is generated based on a third multiplier that is greater than the first multiplier, and the second multiplier and the third multiplier are two available multipliers in adjacent positions after being sorted in order of magnitude from multiple available multipliers.

[0115] The synchronization signal generation module 803 is used to generate a first target synchronization signal for the master clock and a second target synchronization signal for the video clock according to the video parameters of the video interface; the first target synchronization signal and the second target synchronization signal are row synchronization signals, or the first target synchronization signal and the second target synchronization signal are column synchronization signals.

[0116] The phase comparison module 804 is used to compare the phases of the first target synchronization signal and the second target synchronization signal.

[0117] The clock control module 805 is used to switch the video clock to a first adjustment clock or a second adjustment clock when the switchable time is reached, based on the phase comparison result, so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

[0118] The video synchronization device provided in this disclosure can measure the reference frame synchronization signal according to the master clock, calculate the first multiplier between the video clock of the video interface and the master clock according to the measurement result; generate a first adjustment clock and a second adjustment clock of different frequencies according to the first multiplier; wherein, the first adjustment clock is generated based on a second multiplier less than the first multiplier, and the second adjustment clock is generated based on a third multiplier greater than the first multiplier, and the second and third multipliers are two adjacent multipliers after multiple available multipliers are sorted in order of magnitude; generate a first target synchronization signal of the master clock and a second target synchronization signal of the video clock according to the reference frame synchronization signal and the video parameters of the video interface; the first target synchronization signal and the second target synchronization signal are both row synchronization signals, or both are column synchronization signals; compare the phases of the first target synchronization signal and the second target synchronization signal; according to the phase comparison result, when the switchable time is reached, switch the video clock to the first adjustment clock or the second adjustment clock, so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal. Therefore, this disclosure can adjust the second frame synchronization signal of the video clock of multiple video interfaces to synchronize with the reference frame synchronization signal, so that the second frame synchronization signal of the video clock of all video interfaces is synchronized, thereby realizing the synchronization of the video clock of all video interfaces. This solves the defect in the prior art that the video data of multiple video interfaces are not completely synchronized when outputting video data of the same video frame based on multiple video interfaces, and realizes complete synchronization between the video data of multiple video interfaces.

[0119] The video synchronization device in this embodiment can achieve complete synchronization of multiple video interfaces using only one frame synchronization pulse signal, which is highly versatile and low in cost.

[0120] Figure 9 illustrates a schematic diagram of the physical structure of an electronic device. As shown in Figure 9, the electronic device may include: a processor 910, a communication interface 920, a memory 930, and a communication bus 940, wherein the processor 910, the communication interface 920, and the memory 930 communicate with each other through the communication bus 940. The processor 910 can call logic instructions in the memory 930 to execute a video synchronization method, which includes: measuring a reference frame synchronization signal according to a master clock; calculating a first multiplier between the video clock of the video interface and the master clock based on the measurement result; generating a first adjustment clock and a second adjustment clock of different frequencies based on the first multiplier; wherein the first adjustment clock is generated based on a second multiplier less than the first multiplier, and the second adjustment clock is generated based on a third multiplier greater than the first multiplier, and the second and third multipliers are two adjacent multipliers after being sorted in order of magnitude from multiple available multipliers; generating a first target synchronization signal of the master clock and a second target synchronization signal of the video clock according to the reference frame synchronization signal and the video parameters of the video interface; both the first target synchronization signal and the second target synchronization signal are row synchronization signals, or both are column synchronization signals; comparing the phases of the first target synchronization signal and the second target synchronization signal; and, based on the phase comparison result, switching the video clock to the first adjustment clock or the second adjustment clock when a switchable time is reached, so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

[0121] Furthermore, the logical instructions in the aforementioned memory 930 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] On the other hand, this disclosure also provides a computer program product, which includes a computer program that can be stored on a computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the video synchronization method provided by the above methods. The video synchronization method includes: measuring a reference frame synchronization signal based on a master clock; calculating a first multiplier between the video clock of the video interface and the master clock based on the measurement result; generating a first adjustment clock and a second adjustment clock of different frequencies based on the first multiplier; wherein the first adjustment clock is generated based on a second multiplier less than the first multiplier, and the second adjustment clock is generated based on a third multiplier greater than the first multiplier, and the second and third multipliers are multiple multipliers. The available multipliers are sorted in order of magnitude, and two adjacent available multipliers are selected. Based on the reference frame synchronization signal and the video parameters of the video interface, a first target synchronization signal for the master clock and a second target synchronization signal for the video clock are generated. Both the first target synchronization signal and the second target synchronization signal are row synchronization signals, or both are column synchronization signals. The phases of the first target synchronization signal and the second target synchronization signal are compared. Based on the phase comparison result, when the switchable time is reached, the video clock is switched to a first adjustment clock or a second adjustment clock so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

[0123] In another aspect, this disclosure also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the video synchronization method provided by the methods described above. The video synchronization method includes: measuring a reference frame synchronization signal according to a master clock; calculating a first multiplier between the video clock of the video interface and the master clock based on the measurement result; generating a first adjustment clock and a second adjustment clock of different frequencies based on the first multiplier; wherein the first adjustment clock is generated based on a second multiplier less than the first multiplier, and the second adjustment clock is generated based on a third multiplier greater than the first multiplier, and the second and third multipliers are multiple available multipliers ordered in ascending order. Two available frequency multipliers at adjacent positions; based on the reference frame synchronization signal and the video parameters of the video interface, a first target synchronization signal for the master clock and a second target synchronization signal for the video clock are generated; both the first target synchronization signal and the second target synchronization signal are row synchronization signals, or both are column synchronization signals; the phases of the first target synchronization signal and the second target synchronization signal are compared; based on the phase comparison result, when the switchable time is reached, the video clock is switched to a first adjustment clock or a second adjustment clock so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

[0124] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A video synchronization method, comprising: The synchronization signal of the reference frame is measured based on the master clock, and the first multiplication factor between the video clock of the video interface and the master clock is calculated based on the measurement results. Based on the first multiplier, a first adjustment clock and a second adjustment clock of different frequencies are generated; wherein, the first adjustment clock is generated based on a second multiplier that is less than the first multiplier, and the second adjustment clock is generated based on a third multiplier that is greater than the first multiplier, and the second multiplier and the third multiplier are two adjacent multipliers after multiple available multipliers are sorted in order of magnitude; Based on the reference frame synchronization signal and the video parameters of the video interface, a first target synchronization signal for the master clock and a second target synchronization signal for the video clock are generated; both the first target synchronization signal and the second target synchronization signal are row synchronization signals, or both the first target synchronization signal and the second target synchronization signal are column synchronization signals. Compare the phases of the first target synchronization signal and the second target synchronization signal; Based on the phase comparison result, when the switchable moment is reached, the video clock is switched to the first adjustment clock or the second adjustment clock so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

2. The video synchronization method according to claim 1, wherein, The step of measuring the reference frame synchronization signal based on the master clock and calculating the first frequency multiplication between the video clock of the video interface and the master clock based on the measurement results includes: The system receives the reference frame synchronization signal and the video parameters of the video interface, the video parameters including: the number of first pixels in a first direction and the number of second pixels in a second direction of the video interface; Based on the master clock, the reference frame synchronization signal, and the number of first pixels, obtain the number of cycles in which the number of first pixels is fully displayed based on the master clock within one cycle of the frame synchronization signal, and the number of residual pixels that cannot be fully displayed; The first frequency multiplication is calculated based on the first number of pixels, the second number of pixels, the number of periods, and the number of residual pixels.

3. The video synchronization method according to claim 1, wherein, The multiple available frequency multipliers are obtained based on multiple frequency multiplication parameters and multiple frequency division parameters in the phase-locked loop.

4. The video synchronization method according to claim 1, wherein, Before switching the video clock to the first adjustment clock or the second adjustment clock when the switchable time is reached, based on the comparison result of the phase, the method further includes: Calculate the cycle count value based on the second frequency multiplier, the third frequency multiplier, and the master clock; The switchable time is determined based on the cycle count value and the counting clock; wherein the counting clock is either the first adjustment clock or the second adjustment clock.

5. The video synchronization method according to any one of claims 1-4, wherein, The phase comparison results include: the second target synchronization signal is ahead of the first target synchronization signal in phase, or the second target synchronization signal is behind the first target synchronization signal in phase. The step of switching the video clock to the first adjustment clock or the second adjustment clock when the switchable time is reached, based on the comparison result of the phase, includes: If the phase comparison result is that the second target synchronization signal is ahead of the first target synchronization signal, the video clock is adjusted to the first adjusted clock; If the phase comparison result shows that the second target synchronization signal lags behind the first target synchronization signal, the video clock is adjusted to the second adjustment clock.

6. The video synchronization method according to claim 5, wherein, The first direction is the column direction, the first target synchronization signal includes a first row synchronization signal, and before comparing the phases of the first target synchronization signal of the master clock and the second target synchronization signal of the video clock, the method further includes: Based on the number of cycles, the number of residual pixels, and the number of first pixels, the first line synchronization signal and the first frame synchronization signal under the master clock are generated; The second line synchronization signal and the second frame synchronization signal under the video clock are generated according to the video parameters of the video interface; The step of comparing the phase of the first target synchronization signal of the master clock and the second target synchronization signal of the video clock includes: determining a first line synchronization pulse in the first line synchronization signal and determining a second line synchronization pulse that matches the first line synchronization pulse in the second line synchronization signal based on the first line synchronization signal, the first frame synchronization signal, the second line synchronization signal, and the second frame synchronization signal; If the second row of synchronization pulses leads the phase of the first row of synchronization pulses, it is determined that the second target synchronization signal leads the phase of the first target synchronization signal. If the second row of synchronization pulses lags behind the first row of synchronization pulses in phase, it is determined that the second target synchronization signal lags behind the first target synchronization signal in phase.

7. A video synchronization device, comprising: The master clock measurement module is used to measure the reference frame synchronization signal according to the master clock, and calculate the first multiplication factor between the video clock of the video interface and the master clock based on the measurement results; The clock generation module is used to generate a first adjusted clock and a second adjusted clock of different frequencies based on the first multiplier; wherein the first adjusted clock is generated based on a second multiplier that is less than the first multiplier, and the second adjusted clock is generated based on a third multiplier that is greater than the first multiplier, and the second multiplier and the third multiplier are two adjacent multipliers after multiple available multipliers are sorted in order of magnitude; A synchronization signal generation module is used to generate a first target synchronization signal for the master clock and a second target synchronization signal for the video clock based on the reference frame synchronization signal and the video parameters of the video interface; the first target synchronization signal and the second target synchronization signal are row synchronization signals, or the first target synchronization signal and the second target synchronization signal are column synchronization signals; A phase comparison module is used to compare the phases of the first target synchronization signal and the second target synchronization signal; The clock control module is used to switch the video clock to the first adjustment clock or the second adjustment clock when the switchable time is reached, based on the phase comparison result, so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor, when executing the computer program, implements the video synchronization method as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the video synchronization method as described in any one of claims 1 to 6.

10. A computer program product comprising a computer program that, when executed by a processor, implements the video synchronization method as described in any one of claims 1 to 6.

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