Data transmission method and communication device

Abstract

Embodiments of the present application relate to the technical field of communications, and provide a data transmission method and a communication device, for use in reducing the power consumption of a first communication apparatus. The method comprises: at a first clock tick, sending a first target code block corresponding to a first data code block, wherein the first target code block is obtained by using a first scrambling code to perform scrambling processing on the first data code block, and the first clock tick is located in a first transmission period; and at a second clock tick, sending a second target code block corresponding to a second data code block, wherein the second data code block comprises invalid data, the second target code block is obtained by using the first scrambling code to perform scrambling processing on the second data code block, the second clock tick is a clock tick following the first clock tick in the first transmission period, and the code pattern of the first data code block is the same as the code pattern of the second data code block. When the second data code block is invalid data, the first scrambling code is used as a scrambling code corresponding to the second data code block, such that the first target code block and the second target code block which are obtained after scrambling processing are the same, thereby reducing power consumption.

Description

A data transmission method and communication device

[0001] This application claims priority to Chinese Patent Application No. 202411923976.6, filed on December 23, 2024, entitled "A Data Transmission Method and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data transmission method and communication device. Background Technology

[0003] A chiplet is a pre-manufactured, functionally specific die that can be assembled and integrated. Chiplet interconnect refers to the connection of two chiplets through an interface, such as the Universal Chiplet Interconnect Express (UCIe) interface. Data is transmitted between the two interconnected chiplets in the form of a bitstream (i.e., 0s and 1s), which can also be called a data block. Reducing the bit error rate during transmission and ensuring the accuracy of the data blocks are urgent problems to be solved.

[0004] Currently, within a transmission cycle, data blocks are transmitted one clock cycle at a time, meaning one data block is transmitted per clock cycle. When transmitting a data block, the transmitting chiplet determines the corresponding scrambling code and uses this scrambling code to scramble the data block, obtaining a scrambled code block. The data block can be valid or invalid data. Any two data blocks within a transmission cycle have different scrambling codes, resulting in different scrambled code blocks for each clock cycle. This ensures that the scrambled code block for each clock cycle is different from the scrambled code block for the previous clock cycle. In other words, the scrambled code block for each clock cycle is flipped compared to the previous clock cycle, guaranteeing uniform flipping of each scrambled code block within a transmission cycle. This avoids bit errors introduced by the aging of the physical layer analog circuit supporting chiplet interconnects, as well as bit errors caused by the chiplet's power supply, thereby reducing the bit error rate.

[0005] However, the flipping of the scrambling code block corresponding to invalid data increases the power consumption overhead of the transmitting chiplet. Summary of the Invention

[0006] This application provides a data transmission method and a communication device for reducing the power consumption of a first communication device, which is a transmitting device.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] A first aspect provides a data transmission method applied to a first communication device, which communicates with a second communication device via an interface. The method includes: the first communication device transmitting a first target code block corresponding to a first data code block in a first clock cycle, the first target code block being obtained by scrambling the first data code block using a first scrambling code. The first scrambling code is the scrambling code corresponding to the first data code block, and the first clock cycle is located within a first transmission period. The first communication device transmitting a second target code block corresponding to a second data code block in a second clock cycle, the second data code block including invalid data, the second target code block being obtained by scrambling the second data code block using the first scrambling code. The second clock cycle is the clock cycle following the first clock cycle in the first transmission period, and the code pattern of the first data code block is the same as that of the second data code block.

[0009] In the above technical solution, the first communication device uses the first scrambling code corresponding to the first data code block to scramble the first data code block to obtain the first target code block, and transmits the first target code block in the first clock beat of the first transmission cycle. When the second data code block to be transmitted in the next clock beat of the first transmission cycle contains invalid data, the first communication device uses the first scrambling code as the scrambling code corresponding to the second data code block, and scrambles the second data code block according to the first scrambling code, and transmits the second target code block corresponding to the second data code block in the second clock beat. In this process, the first communication device does not need to re-determine the scrambling code for the second data code block, and directly uses the first scrambling code corresponding to the first data code block as the scrambling code corresponding to the second data code block, thereby reducing the power consumption of the first communication device. Since the code pattern of the second data code block is the same as that of the first data code block, the scrambling codes corresponding to the first data code block and the second data code block are both the first scrambling code, so that the first target code block obtained by scrambling is the same as the second target code block, that is, the second target code block is not flipped compared to the first target code block, that is, the second target code block is not updated compared to the first target code block, thereby reducing the power consumption of the first communication device. For example, if 50% of the data in a transmission cycle is invalid, the technical solution of this application can save 30% of power consumption.

[0010] In any possible implementation of the first aspect, when the first clock tick is the first clock tick in the first transmission cycle and the first data block includes invalid data, the method further includes: scrambling the first data block using a first scrambling code and a first idle code to obtain a first target code block. In the above possible implementations, when the first data block to be transmitted in the first clock tick of the first transmission cycle includes invalid data, the first data block is scrambled using the first idle code and the first scrambling code to obtain the first target code block. This makes the first target code block different from the target code block in the last clock tick of the previous transmission cycle, i.e., the first target code block is flipped compared to the target code block in the last clock tick of the previous transmission cycle. This avoids the target code block not being flipped for a long time, which could lead to aging of the physical layer analog circuit supporting chiplet interconnects, ensuring normal data transmission and improving the reliability of the physical layer analog circuit.

[0011] In any possible implementation of the first aspect, scrambling the first data code block using a first scrambling code and a first idle code to obtain a first target code block includes: determining a first idle code based on the first scrambling code; scrambling the first data code block using the first idle code to obtain a first data code block to be scrambled; and scrambling the first data code block to be scrambled using the first scrambling code to obtain the first target code block. In the above possible implementations, when the first data code block to be transmitted within the first clock cycle of the first transmission cycle includes invalid data, the first idle code is determined using the first data code block, and the first data code block is scrambled using the first idle code and the first scrambling code to obtain the first target code block. This ensures that the first target code block is different from the target code block in the last clock cycle of the previous transmission cycle, i.e., the first target code block is flipped compared to the target code block in the last clock cycle of the previous transmission cycle. This avoids the target code block not being flipped for a long time, which could lead to aging of the physical layer analog circuit supporting chiplet interconnects, ensuring normal data transmission and improving the reliability of the physical layer analog circuit.

[0012] In any possible implementation of the first aspect, the method further includes: scrambling the second data code block using a first scrambling code and a first idle code to obtain a second target code block. In the above possible implementations, the scrambling code and idle code of invalid data in a transmission cycle are not flipped, thereby ensuring that the target code blocks of invalid data in a transmission cycle are the same, i.e., the target code blocks of invalid data in a transmission cycle are not flipped, reducing the power consumption of the first communication device.

[0013] In any possible implementation of the first aspect, the second data code block is scrambled using a first idle code to obtain a second data code block to be scrambled; the second data code block to be scrambled is then scrambled using a first scrambling code to obtain a second target code block. In the above possible implementations, the scrambling code and idle code of invalid data in a transmission cycle are not flipped, thereby ensuring that the target code blocks of invalid data in a transmission cycle are the same, i.e., the target code blocks of invalid data in a transmission cycle are not flipped, reducing the power consumption of the first communication device.

[0014] In any possible implementation of the first aspect, the bit width of the first idle code is the same as the bit width of the first scrambling code. In the above possible implementations, scrambling the first data code block using the first scrambling code and the first idle code improves the efficiency of scrambling.

[0015] In any possible implementation of the first aspect, the method further includes: transmitting a third target code block corresponding to the third data code block in a third clock cycle, the third data code block including invalid data, the third target code block being obtained by scrambling the third data code block using a first scrambling code and a second idle code; the third clock cycle being the first clock cycle in a second transmission period, the second transmission period being the transmission period following the first transmission period; the second idle code being different from the first idle code. In the above possible implementations, the idle codes and target code blocks are different in different transmission periods, avoiding the aging of the physical layer analog circuit supporting chiplet interconnects due to the target code block not flipping for a long time, ensuring normal data transmission, and improving the reliability of the physical layer analog circuit.

[0016] In any possible implementation of the first aspect, transmitting the third target code block corresponding to the third data code block includes: determining a first scrambling code using a scrambling polynomial and an initial scrambling seed; determining a second idle code based on the first scrambling code; scrambling the third data code block using the second idle code to obtain a third data code block to be scrambled; and scrambling the third data code block to be scrambled using the first scrambling code to obtain and transmit the third target code block. In the above possible implementations, the idle code is different in different transmission cycles, and the target code block is different in different transmission cycles. This avoids the target code block not flipping for a long time, which could lead to aging of the physical layer analog circuit supporting chiplet interconnects, ensuring normal data transmission and improving the reliability of the physical layer analog circuit.

[0017] In any possible implementation of the first aspect, the sum of the number of 0s in the first idle code and the number of 0s in the second idle code is a first value; the sum of the number of 1s in the first idle code and the number of 1s in the second idle code is a second value; the first value and the second value are the same. In the above possible implementations, the number of 1s and the number of 0s in the target code block in the first and second transmission cycles are the same, that is, the number of 1s and the number of 0s in the target code block in the first and second transmission cycles are balanced, which avoids the aging problem of the physical layer analog circuit supporting chip interconnection and improves the reliability of the physical layer analog circuit.

[0018] In any possible implementation of the first aspect, an even number of transmission cycles are spaced between the first transmission cycle and the second transmission cycle. In the above possible implementations, the idle code in the odd-numbered cycles is different from the idle code in the even-numbered cycles, making the target code blocks of two adjacent transmission cycles different. This ensures that the target code blocks of two adjacent transmission cycles are flipped, preventing the physical layer analog circuit supporting chiplet interconnect from aging due to the target code blocks not being flipped for a long time, thus ensuring normal data transmission and improving the reliability of the physical layer analog circuit.

[0019] In any possible implementation of the first aspect, the bit width of the second idle code is the same as the bit width of the first scrambling code. The above possible implementations improve scrambling efficiency.

[0020] Secondly, a data transmission method is provided, applied to a second communication device, which communicates with a first communication device through an interface. The method includes: the second communication device receiving a first target code block in a first clock cycle, and decoding the first target code block using a first scrambling code to obtain a first data code block. The first scrambling code is the scrambling code corresponding to the first data code block. The second communication device receiving a second target code block in a second clock cycle, the second clock cycle being the next clock cycle in a first reception period. When the second target code block includes invalid data, the second communication device decoding the second target code block using the first scrambling code to obtain the second data code block.

[0021] In the above technical solution, a first target code block is received in the first clock cycle, and the first target code block is decoded using a first scrambling code to obtain a first data code block. The first scrambling code is the scrambling code corresponding to the first data code block. When the second target code block received in the next clock cycle of the first receiving period contains invalid data, the second target code block is directly decoded using the first scrambling code corresponding to the first data code block to obtain the second data code block. During this process, it is not necessary to re-determine the scrambling code for the second target code block, thus reducing the power consumption of the second communication device.

[0022] In any possible implementation of the second aspect, when the first clock beat is the first clock beat of the first reception period and the first target code block includes invalid data, the first target code block is decoded using the first scrambling code to obtain the first data code block, including: decoding the first target code block using the first scrambling code and the first idle code to obtain the first data code block.

[0023] In any possible implementation of the second aspect, decoding the first target code block using the first scrambling code and the first idle code to obtain the first data code block includes: determining the first idle code based on the first scrambling code; decoding the first target code block using the first scrambling code to obtain the first data code block to be scrambled; and decoding the first data code block to be scrambled using the first idle code to obtain the first data code block.

[0024] In any possible implementation of the second aspect, decoding the second target code block using the first scrambling code to obtain the second data code block includes: decoding the second target code block using the first scrambling code and the first idle code to obtain the second target code block.

[0025] In any possible implementation of the second aspect, decoding the second target code block using the first scrambling code and the first idle code to obtain the second target code block includes: decoding the second target code block using the first scrambling code to obtain the second data code block to be scrambled; and decoding the second data code block to be scrambled using the first idle code to obtain the second data code block.

[0026] In any possible implementation of the second aspect, the bit width of the first idle code is the same as the bit width of the first scrambling code. In the above possible implementations, using the first scrambling code and the first idle code to decode the first target code block improves decoding efficiency.

[0027] In any possible implementation of the second aspect, the method further includes: receiving a third target code block in a third clock cycle; the third clock cycle is the first clock cycle in a second reception period, and the second reception period is a reception period following the first reception period; when the third target code block includes invalid data, decoding the third target code block using a first scrambling code and a second idle code to obtain a third data code block; the second idle code is different from the first idle code.

[0028] In any possible implementation of the second aspect, decoding the third target code block using the first scrambling code and the second idle code to obtain the third data code block includes: determining the first scrambling code based on the scrambling polynomial and the initial scrambling seed; determining the second idle code based on the first scrambling code; decoding the third target code block using the first scrambling code to obtain the third data code block to be scrambled; and decoding the third data code block to be scrambled using the second idle code to obtain the third data code block.

[0029] In any possible implementation of the second aspect, the sum of the number of 0s in the first free code and the number of 0s in the second free code is a first value; the sum of the number of 1s in the first free code and the number of 1s in the second free code is a second value; the first value and the second value are the same.

[0030] In any possible implementation of the second aspect, the interval between the first reception period and the second reception period is an even number of reception periods.

[0031] In any possible implementation of the second aspect, the bit width of the second idle code is the same as the bit width of the first scrambling code. In the above possible implementations, using the first scrambling code and the second idle code to decode the first target code block improves decoding efficiency.

[0032] Thirdly, a communication device is provided, comprising a module that performs the operation steps of the data transmission method provided by the first aspect or any possible implementation thereof, or a module that performs the operation steps of the data transmission method provided by the second aspect or any possible implementation thereof.

[0033] Fourthly, a communication device is provided, comprising a processor and a memory, wherein the memory stores instructions that, when executed on the processor, cause the processor to perform a data transmission method provided by the first aspect or any possible implementation thereof, or a data transmission method provided by the second aspect or any possible implementation thereof.

[0034] Fifthly, a computer-readable storage medium is provided, wherein a computer program or instructions are stored therein, which, when executed, implement the data transmission method provided by the first aspect or any possible implementation thereof.

[0035] In a sixth aspect, a computer-readable storage medium is provided, wherein a computer program or instructions are stored therein, which, when executed, implement the data transmission method provided by the second aspect or any possible implementation thereof.

[0036] In a seventh aspect, a computer program product is provided, comprising: a computer program, also known as code or instructions, which, when executed, causes a computer to perform a data transmission method provided by the first aspect or any possible implementation thereof.

[0037] Eighthly, a computer program product is provided, comprising: a computer program, also known as code or instructions, which, when run, causes a computer to perform a data transmission method provided by the second aspect or any possible implementation thereof.

[0038] Understandably, the beneficial effects that can be achieved by the third to eighth aspects mentioned above can be referred to in the beneficial effects of the data transmission method provided by the first aspect or any possible implementation of the first aspect, and will not be repeated here. Attached Figure Description

[0039] Figure 1 is a schematic diagram of a scrambling method provided in an embodiment of this application;

[0040] Figure 2 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0041] Figure 3 is a flowchart of a data transmission method provided in an embodiment of this application;

[0042] Figure 4 is a schematic diagram of a data transmission method provided in an embodiment of this application;

[0043] Figure 5 is a schematic diagram of the structure of a first communication device provided in an embodiment of this application;

[0044] Figure 6 is a schematic diagram of the structure of a second communication device provided in an embodiment of this application;

[0045] Figure 7 is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0046] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this application and technology, and do not limit the scope of this application.

[0047] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0048] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, a, b, and c; where a, b, and c can be single or multiple.

[0049] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or roles. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order.

[0050] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] Before introducing the embodiments of this application, we will first introduce and explain the relevant knowledge of chiplets.

[0052] A chiplet is a pre-manufactured, functionally specific die that can be assembled and integrated. Chiplets can also be called small chips or bare dies. Chiplet interconnection refers to the connection of two chiplets through an interface, such as the Universal Chiplet Interconnect Express (UCIe) interface. The two interconnected chiplets transmit data in the form of a bitstream (i.e., 0s and 1s). This data transmitted in bitstream form can also be called data blocks or data bitstreams. How to reduce the bit error rate during transmission and ensure the accuracy of data blocks has become a pressing problem to be solved.

[0053] In one possible embodiment, data blocks are transmitted one clock cycle at a time, i.e., one data block is transmitted per clock cycle. When transmitting a data block, the transmitting chiplet determines the scrambling code corresponding to the data block and uses this scrambling code to scramble the data block to obtain a scrambled code block, which the chiplet then transmits. The data block can be valid or invalid data. Within a transmission cycle, if a data block includes invalid data, the code pattern of that data block is the same as the code pattern of the last valid data block preceding it. Any two data blocks within a transmission cycle have different scrambling codes, ensuring that any two scrambled code blocks obtained after scrambling are different, thus making the scrambled code block of each clock cycle different from the scrambled code block of the previous clock cycle. In other words, the scrambled code block of each clock cycle within a transmission cycle is flipped compared to the scrambled code block of the previous clock cycle, thereby ensuring that each scrambled code block within a transmission cycle flips uniformly to avoid bit errors introduced by the aging of the physical layer analog circuit supporting chiplet interconnects, as well as bit errors caused by the chiplet's power supply. For example, the physical layer analog circuit supporting chiplet interconnects may age due to long-term high and low level imbalance. Sudden changes in the flip rate of the scrambling code block may cause drastic fluctuations in the power supply current, leading to bit errors. Therefore, it is necessary to reduce the bit error rate.

[0054] In this data block, valid data indicates that the data block contains the valid data that the transmitting chiplet actually needs to send. Invalid data indicates that the data block does not contain the valid data that the transmitting chiplet actually needs to send; that is, the data in the data block is padding data added by the transmitting chiplet to meet the transmission bit width requirement. Padding data can also be called invalid data. The transmission bit width of the transmitting chiplet is fixed. Any two data blocks have the same bit width, and the bit width of the scrambling code is also the same as the bit width of the data blocks.

[0055] However, when a data block contains invalid data, the flipping of the corresponding scrambling block increases the power consumption of the transmitting chiplet. For example, when there is no valid data to be transmitted in the transmitting chiplet (i.e., no traffic) or when there is little valid data to be transmitted in the transmitting chiplet (i.e., light traffic), most of the data blocks to be transmitted in the transmitting chiplet contain invalid data.

[0056] For example, Figure 1 is a schematic diagram of a scrambling method provided in an embodiment of this application. Assume that the transmitting chiplet does not include any valid data to be transmitted during transmission periods T0 to T2, i.e., all data blocks to be transmitted by the transmitting chiplet during transmission periods T0 to T2 are invalid data, and the invalid data block can be represented as P. Each transmission period includes n clock cycles, and one data block P is transmitted per clock cycle, so n data blocks P can be transmitted in one transmission period. When transmitting each data block P, the transmitting chiplet determines the scrambling code corresponding to each data block P. For example, the transmitting chiplet determines the scrambling code corresponding to each data block P based on the scrambling polynomial and the initial scrambling seed. Any two data blocks P within a transmission period have different scrambling codes, and the scrambling codes are the same for each transmission period. For example, the scrambling codes corresponding to the n data blocks P in each transmission period from T0 to T2 are S0 to Sn, and any two scrambling codes from S0 to Sn are different. The transmitting chiplet uses the scrambling code corresponding to each data code block P to scramble each data code block P to obtain a scrambled code block. For example, the scrambled code blocks corresponding to the n data code blocks P in each transmission period from transmission period T0 to transmission period T2 are R0 to Rn respectively. n is a positive integer greater than 1.

[0057] As shown in Figure 1, each scrambling code block is flipped compared to the previous scrambling code block, which means that each scrambling code block is updated compared to the previous scrambling code block. Since the data code block P is invalid data, the power consumption of the transmitting chiplet is increased.

[0058] Based on this, embodiments of this application provide a data transmission method. In this method, a first communication device scrambles a first data code block using a first scrambling code corresponding to the first data code block to obtain a first target code block, and transmits the first target code block in a first clock cycle. The first data code block is a data code block to be transmitted within the first clock cycle of the first transmission period. When a second data code block to be transmitted in the next clock cycle of the first transmission period includes invalid data, the first communication device uses the first scrambling code as the scrambling code corresponding to the second data code block, scrambles the second data code block according to the first scrambling code, and transmits the second target code block corresponding to the second data code block in the second clock cycle. In this process, there is no need to re-determine the scrambling code for the second data code block; the first scrambling code corresponding to the first data code block is directly used as the scrambling code for the second data code block, reducing the power consumption of the first communication device. Since the code pattern of the second data code block is the same as that of the first data code block, the scrambling codes corresponding to both the first and second data code blocks are the first scrambling codes, making the first target code block obtained by scrambling the same as the second target code block. That is, the second target code block is not flipped compared to the first target code block, and the second target code block is not updated compared to the first target code block, thereby reducing the power consumption of the first communication device. For example, when there is 50% invalid data in a transmission cycle, the technical solution of this application can save 30% of power consumption.

[0059] The technical solution provided in this application can be applied to communication devices that include multiple communication devices, which can be devices or chips used in devices, etc., and different communication devices are interconnected. In this application, the multiple communication devices can transmit signals through an interface.

[0060] Optionally, when the communication device is a chip, the chip can also be connected to an interface, allowing different chips to transmit signals through the interface. This application can be used in chip-to-chip communication scenarios. For example, the chip can be a system-on-chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU), and the aforementioned interface can be an interface for connecting or communicating with the SoC, CPU, or GPU. Optionally, the chip can also be a small chip such as a die, and the interface can be a transmitting circuit and / or receiving circuit coupled to the die. This interface can also be called an interface module.

[0061] The following example illustrates the structure of a communication device, which includes two communication units.

[0062] Figure 2 is a schematic diagram of a communication device provided in an embodiment of this application. The communication device includes a first communication device 201 and a second communication device 202 connected via interfaces. Exemplarily, the first communication device 201 includes interface A, and the second communication device 202 includes interface B. The first communication device 201 and the second communication device 202 are connected by a cable. In one possible embodiment, the first communication device 201 can be a transmitting device, and the second communication device 202 can be a receiving device; the first communication device 201 can output signals to the second communication device 202 through interface A, and the second communication device 202 can receive signals from the first communication device 201 through interface B. In another possible embodiment, the first communication device 201 can be a receiving device, and the second communication device 202 can be a transmitting device; the first communication device 201 can receive signals from the second communication device 202 through interface A, and the second communication device 202 can output signals to the first communication device 201 through interface B.

[0063] Optionally, the first communication device 201 and / or the second communication device 202 may be processors. Exemplary examples include a central processing unit (CPU), a neural-network processing unit (NPU), a graphics processing unit (GPU), an application processor, an application-specific integrated circuit (ASIC), a complex programmable logic device (CPLD), and a field-programmable gate array (FPGA), etc. In one possible embodiment, the first communication device 201 and / or the second communication device 202 may also be chiplets capable of implementing processor functions.

[0064] The first communication device 201 and / or the second communication device 202 may be a memory. For example, the memory may include random access memory (RAM), read-only memory (ROM), flash memory, and hard disk, etc. In one possible embodiment, the first communication device 201 and / or the second communication device 202 may also be a chiplet implementing memory functionality.

[0065] In this application, the first communication device 201 and the second communication device 202 can be either homogeneous or heterogeneous. Homogeneous devices refer to devices where the structures of the first communication device 201 and the second communication device 202 are identical. For example, the first communication device 201 and the second communication device 202 can be GPUs, or the first communication device 201 and the second communication device 202 can be two homogeneous chiplets capable of implementing CPU functions. Heterogeneous devices refer to devices where the structures of the first communication device 201 and the second communication device 202 are different. For example, the first communication device 201 can be a CPU, and the second communication device 202 can be an NPU, or the first communication device can be a chiplet capable of implementing CPU functions, and the second communication device 202 can be a chiplet capable of implementing GPU functions.

[0066] Optionally, the aforementioned interfaces A and B may include, but are not limited to: Universal Chiplet Interconnect Express (UCIe) interface, Peripheral Component Interconnect Express (PCIe) interface, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS) interface, Universal Serial Bus (USB) interface, Mobile Industry Processor Interface (MIPI), High Definition Multimedia Interface (HDMI), mini HDMI, micro HDMI, DisplayPort (DP), Unified Multimedia Interconnection (UMMI) interface, Unified Media Interconnection (UMI) interface, Type-A interface, Type-B interface, Type-C interface, or proprietary interfaces, etc. The different types of interfaces indicate different protocols used by the interfaces. For example, a UCIe interface indicates that interface A uses the UCIe protocol, and DP indicates that interfaces A and B use the DP protocol, etc. In this application, when the first communication device 201 and the second communication device 202 are chiplets, interface A and interface B are UCIe interfaces.

[0067] Furthermore, the communication equipment provided in this application can be used in electronic devices, including but not limited to: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smartwatches, smart bracelets, pedometers, etc.), audio equipment, audio and video players, set-top boxes, game consoles, in-vehicle equipment (such as equipment on vehicles like cars, bicycles, electric vehicles, airplanes, ships, trains, and high-speed trains), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying equipment (such as intelligent robots, drones, airplanes), etc.

[0068] The data transmission method provided in this application embodiment will be described below with reference to Figure 2. In this application embodiment, a first communication device 201 is used as the transmitting side device, and a second communication device 202 is used as the receiving side device. Figure 3 is a flowchart of a data transmission method provided in this application embodiment. This data transmission method includes the following steps.

[0069] S301, the first communication device 201 transmits a first target code block corresponding to a first data code block in the first clock pulse. The first target code block is obtained by scrambling the first data code block using a first scrambling code. The first scrambling code is the scrambling code corresponding to the first data code block. The first clock pulse is located in the first transmission period.

[0070] The first transmission cycle is any one of the multiple transmission cycles included in the first communication device 201, excluding the last transmission cycle. For example, the first communication device 201 includes m transmission cycles, and the first transmission cycle can be any one of the m transmission cycles except for the m-th transmission cycle. For instance, the first transmission cycle can be the first, second, or fifth transmission cycle among the m transmission cycles. The first transmission cycle refers to the cycle in which the first communication device 201 first sends a data code block to the second communication device 202 after the communication devices including the first communication device 201 and the second communication device 202 are powered on. Optionally, each of the multiple transmission cycles can include j clock cycles. m and j are positive integers greater than 1.

[0071] In addition, the first clock beat can be any clock beat other than the j-th clock beat in the j-th clock beats included in the first transmission period. For example, if the first transmission period includes ten clock beats, the first clock beat can be the first clock beat, or it can be the fourth clock beat, etc.

[0072] In practical applications, the first communication device 201 encapsulates the data to be transmitted within each clock cycle to obtain corresponding data code blocks. Each data code block carries corresponding indication information, which is used to indicate whether the data code block is valid data. For example, the first communication device 201 encapsulates the data to be transmitted within the first clock cycle to obtain a first data code block, and the first data code block carries first indication information to indicate whether the first data code block is valid data.

[0073] Since the transmission bit width and transmission period of the first communication device 201 are fixed, the data to be transmitted by the first communication device 201 in each clock cycle includes the valid data and / or padding data that the first communication device 201 actually needs to transmit in that clock cycle. The following uses the data to be transmitted in the first clock cycle as an example to illustrate several possible cases of the first data block.

[0074] In a first possible embodiment, when the bit width of the valid data to be transmitted within the first clock cycle is the same as the transmission bit width of the first communication device 201, there is no padding data (i.e., invalid data) in the data to be transmitted within the first clock cycle; that is, all the data to be transmitted within the first clock cycle is valid data. The first communication device 201 encapsulates the data to be transmitted within the first clock cycle to obtain a first data code block P0-a, and the first indication information ga carried in the first data code block P0-a is used to indicate that the first data code block P0-a includes valid data.

[0075] In a second possible embodiment, when the bit width of the valid data to be transmitted within the first clock cycle is greater than zero and less than the transmission bit width of the first communication device 201, the data to be transmitted within the first clock cycle includes valid data and padding data (i.e., invalid data). The first communication device 201 encapsulates the data to be transmitted within the first clock cycle to obtain a first data code block P0-b, and the first indication information gb carried in the first data code block P0-b is used to indicate that the first data code block P0-b includes valid data.

[0076] In a third possible embodiment, when the bit width of the valid data that actually needs to be transmitted within the first clock cycle is equal to zero, that is, there is no valid data that actually needs to be transmitted within the first clock cycle, and all the data to be transmitted within the first clock cycle is padding data (i.e., invalid data). The first communication device 201 encapsulates the data to be transmitted within the first clock cycle to obtain a first data code block P0-c, and the first indication information gc carried in the first data code block P0-c is used to indicate that the first data code block P0-c includes invalid data.

[0077] In the following embodiments, valid data and invalid data are described from the perspective of data code blocks. That is, valid data in the following embodiments means that the data code block includes valid data, and invalid data means that the data code block includes invalid data.

[0078] Furthermore, the transmission bit width of the first communication device 201 is fixed; that is, the bit width of the data to be transmitted within any clock cycle is fixed, and thus the bit width of any data block is fixed. For example, the bit width of a data block can be 5 bits, 50 bits, or 100 bits. Each data block can include multiple data units, and the multiple data units have the same bit width. For example, a 100-bit data block can include 10 data units, each with a bit width of 10 bits. A data unit is the smallest unit that makes up a data block. For ease of understanding and description, the following embodiments use a first data block with a bit width of 5 bits as an example.

[0079] In practical applications, the first communication device 201 determines the first scrambling code corresponding to the first data code block, and uses the first scrambling code to scramble the first data code block to obtain the first target code block. Since the first data code block is the data code block to be transmitted within the first clock cycle, the process of determining the first scrambling code corresponding to the first data code block is different when the first clock is a different clock cycle within the first transmission period. The two possible cases are explained below.

[0080] In the first scenario, the first clock tick is the first clock tick of the first transmission cycle.

[0081] The first communication device 201 determines the first scrambling code corresponding to the first data code block based on the scrambling polynomial and the initial scrambling seed. For example, the first scrambling code can be 00111. The initial scrambling seed can be configured according to actual needs or the experience of relevant personnel.

[0082] In the second case, when j is greater than or equal to 3, the first data block includes the data block to be transmitted in any clock clock cycle except for the first and last clock clock cycles.

[0083] Case a: When the first data code block includes valid data, that is, when the first indication information carried by the first data code block indicates that the first data code block includes valid data, the process of determining the first scrambling code is similar to the process of determining the first scrambling code in the first case above, and will not be repeated here.

[0084] Case b: When the first data block includes invalid data, that is, when the first indication information carried by the first data block indicates that the first data block includes invalid data, the first communication device 201 uses the scrambling code corresponding to the data block to be transmitted in the clock beat before the first clock beat in the first transmission cycle and adjacent to the first clock beat as the scrambling code of the first data block. That is, the first communication device 201 uses the scrambling code corresponding to the data block to be transmitted in the clock beat before the first clock beat in the first transmission cycle as the scrambling code of the first data block.

[0085] The bit width of the first scrambling code is the same as the bit width of the first data code block. For example, if the bit width of the first data code block is 5 bits, the bit width of the first scrambling code is also 5 bits.

[0086] For ease of understanding, the following embodiments will use the first clock of the first transmission cycle as an example.

[0087] Since the first data block can be valid or invalid data, the process of determining the code pattern of the first data block will be explained below, depending on the case. The code pattern of the first data block refers to the specific value of the first data block.

[0088] In a first possible embodiment, the first data block includes valid data. The code pattern of the first data block is determined based on the data to be transmitted at the first clock tick. For example, the first communication device 201 encapsulates the data to be transmitted at the first clock tick to determine the code pattern of the first data block as 11100.

[0089] In a second possible embodiment, the first data block includes invalid data.

[0090] Example a: When the first transmission cycle is the first transmission cycle among the m transmission cycles included in the first communication device 201, the first communication device 201 uses a preset code pattern as the code pattern of the first data code block. For example, the preset code pattern can be 00000. Specifically, the first communication device 201 encapsulates the data to be transmitted in the first clock tick and uses the preset code pattern 00000 as the code pattern of the first data code block. When the first communication device 201 transmits valid data, the preset code pattern is updated in real time to the code pattern of the valid data.

[0091] Example b: When the first transmission period is any one of the m transmission periods included in the first communication device 201, excluding the first transmission period and the m-th transmission period, the first communication device 201 uses the code pattern of the data code block in the clock period preceding and adjacent to the first clock period as the code pattern of the first data code block. That is, the first communication device 201 uses the code pattern of the data code block in the clock period preceding the first clock period as the code pattern of the first data code block.

[0092] For ease of understanding, the following embodiments will use the first transmission period as the first transmission period out of m transmission periods as an example.

[0093] In one possible embodiment, when the first data code block includes a data code block to be transmitted within the first clock tick of the first transmission period, and the first data code block includes invalid data, the method provided in this application embodiment further includes: the first communication device 201 scrambling the first data code block using a first scrambling code and a first idle code to obtain a first target code block. For example, the first communication device 201 determines the first idle code based on the first scrambling code; and scrambles the first data code block using the first idle code to obtain a first data code block to be scrambled; the first communication device 201 scrambles the first data code block to be scrambled using the first scrambling code to obtain the first target code block and transmits it.

[0094] Since the first free code is determined based on the first scrambling code, in one possible embodiment, the bit width of the first free code is the same as the bit width of the first scrambling code. For example, if the bit width of the first scrambling code is 5 bits, the bit width of the first free code is also 5 bits.

[0095] In this embodiment of the application, a target code block (including a first target code block) is obtained by scrambling a data code block (including a first data code block). The indication information carried by the target code block indicates whether the target code block is valid data.

[0096] S302, the second communication device 202 receives the first target code block at the first clock cycle and decodes the first target code block using the first scrambling code to obtain the first data code block.

[0097] Wherein, the first clock beat is any clock beat in the first receiving cycle except for the last clock beat. For example, the second communication device 202 includes m receiving cycles, and the first receiving cycle can be any receiving cycle other than the m-th receiving cycle. For instance, the first receiving cycle can be the first, second, or fifth receiving cycle among the m receiving cycles. The first receiving cycle refers to the cycle in which the second communication device 202 first receives the target code block from the first communication device 201 after the communication devices including the first communication device 201 and the second communication device 202 are powered on. Optionally, each receiving cycle in the multiple receiving cycles may include j clock beats. m and j are positive integers greater than 1. The following example uses the first receiving cycle as the first receiving cycle.

[0098] Furthermore, the first clock beat is any clock beat in the first receiving cycle except for the last clock beat. The process by which the second communication device 202 determines the first scrambling code will be explained below, depending on the specific case.

[0099] In the first case, the first clock beat is the first clock beat in the first receiving cycle, and the second communication device 202 determines the first scrambling code based on the scrambling polynomial and the initial scrambling seed.

[0100] In the second case, the first clock beat is any clock beat in the first receiving cycle other than the first and last clock beats.

[0101] Case a: When the first target code block is valid data, that is, when the indication information carried by the first target code block indicates that the first target code block includes valid data, the process of the second communication device 202 determining the first scrambling code is similar to the process of determining the first scrambling code in the first case above, and will not be described again here.

[0102] Case b: When the first target code block includes invalid data, that is, when the indication information carried by the first target code block indicates that the first target code block includes invalid data, the second communication device 202 uses the scrambling code determined in the clock beat before the first clock beat in the first transmission cycle and adjacent to the first clock beat as the first scrambling code of the first clock beat. That is, the second communication device 202 uses the scrambling code determined in the clock beat before the first clock beat in the first transmission cycle as the first scrambling code of the first clock beat.

[0103] In one possible embodiment, when the first clock beat is the first clock beat of the first reception period, and the first target code block includes invalid data, the first target code block is decoded using a first scrambling code to obtain a first data code block, including: the second communication device 202 decodes the first target code block using the first scrambling code and a first idle code to determine the first data code block. For example, the second communication device 202 determines the first idle code based on the first scrambling code, decodes the first target code block using the first scrambling code to obtain a first scrambling code block to be scrambled, and decodes the first scrambling code block to be scrambled using the first idle code to obtain the first data code block.

[0104] S303, the first communication device 201 transmits the second target code block corresponding to the second data code block in the second clock cycle. The second data code block includes invalid data. The second target code block is obtained by scrambling the second data code block using the first scrambling code. The code pattern of the first data block is the same as that of the second data block. The second clock cycle is the next clock cycle after the first clock cycle in the first transmission period.

[0105] The second clock beat is the clock beat following the first clock beat in the first transmission cycle, that is, the second clock beat is the clock beat adjacent to the first clock beat after the first clock beat in the first transmission cycle.

[0106] In practical applications, since the second data block includes invalid data, the first communication device 201 encapsulates the data to be transmitted within the second clock cycle and uses the code pattern of the first data block as the code pattern of the second data block. For example, when the code pattern of the first data block is 11100, the code pattern of the second data block is also 11100; when the code pattern of the first data block is 00000, the code pattern of the second data block is also 00000. The second indication information carried by the second data block is used to indicate that the second data block includes invalid data.

[0107] In one possible embodiment, when the first data code block includes invalid data, the method provided in this application further includes: the first communication device 201 scrambling the second data code block using a first scrambling code and a first idle code to obtain a second target code block. For example, the first communication device 201 uses the first idle code as the idle code corresponding to the second data code block, and uses the first idle code to scramble the second data code block to obtain a second data code block to be scrambled; and uses the first scrambling code to scramble the second data code block to obtain the second target code block.

[0108] In this embodiment, the first scrambling code corresponding to the first data code block is used as the scrambling code for the second data code, and the first idle code corresponding to the first data code block is used as the idle code for the second data code. This means that the scrambling code and idle code corresponding to invalid data are not flipped. The second data code block is scrambled using the first scrambling code and the first idle code to obtain the second target code block. Since both the first and second data code blocks are invalid data, and the code patterns of the first and second data code blocks are the same, the scrambled first target code block and the second target code block are identical. That is, the second target code block is not flipped compared to the first target code block, meaning the first target code block is not updated compared to the second target code block. This ensures that the target code block obtained after scrambling does not flip or flips as little as possible, reducing the additional power consumption caused by the flipping of invalid data, thereby reducing the power consumption of the first communication device 201. For example, taking 50% valid data as an example, the technical solution of this application can save 30% of power consumption.

[0109] S304, the second communication device 202 receives the second target code block in the second clock beat, where the second clock beat is the next clock beat in the first receiving cycle.

[0110] The second clock beat is the clock beat that follows the first clock beat and is adjacent to the first clock beat in the first receiving cycle.

[0111] S305. When the second target code block includes invalid data, the second communication device 202 uses the first scrambling code to decode the second target code block to obtain the second data code block.

[0112] For example, when the second target code block includes invalid data, that is, when the indication information carried by the second target code block indicates that the second target code block includes invalid data, the second communication device 202 uses the first scrambling code determined in the first clock beat as the scrambling code of the second clock beat, and uses the first scrambling code determined in the first clock beat to decode the second target code block to obtain the second data code block.

[0113] In one possible embodiment, decoding the second target code block using a first scrambling code to obtain a second data code block includes: the second communication device 202 decoding the first target code block using the first scrambling code and a first idle code to obtain the first data code block. For example, the second communication device 202 uses the first idle code and the first scrambling code determined in the first clock cycle as the idle code and scrambling code for the second clock cycle, and decodes the second target code block using the first scrambling code to obtain a second scrambling code block, and decodes the second scrambling code block using the first idle code to obtain the second data code block.

[0114] Similarly, for the fourth data block to be transmitted within the clock tick following the second clock tick in the first transmission cycle, when the fourth data block contains invalid data, the process by which the first communication device 201 processes the fourth data block is similar to the process by which the first communication device 201 processes the second data block. When the fourth data block contains valid data, the process by which the first communication device 201 processes the fourth data block is similar to step S301 described above, and will not be repeated here.

[0115] Similarly, for the fourth target code block received within a clock cycle after the second clock cycle in the first receiving period, when the fourth target code block contains invalid data, the process by which the second communication device 202 processes the fourth target code block is similar to the process by which the second communication device 202 processes the second target code block. When the fourth target code block contains valid data, the process by which the second communication device 202 processes the fourth target code block is similar to step S302 described above, and will not be repeated here.

[0116] In one possible embodiment, the method provided in this application further includes: a first communication device 201 transmitting a third target code block corresponding to a third data code block in a third clock cycle, the third data code block including invalid data. The third target code block is obtained by scrambling the third data code block using a first scrambling code and a second idle code; the third clock cycle is the first clock cycle in a second transmission period, the second transmission period being the transmission period following the first transmission period; the second idle code is different from the first idle code.

[0117] In one possible embodiment, the first communication device 201 determines a first scrambling code based on the scrambling polynomial and the initial scrambling seed, and determines a second idle code based on the first scrambling code; the first communication device 201 uses the second idle code to scramble a third data code block to obtain a third data code block to be scrambled, and uses the first scrambling code to scramble the third data code block to be scrambled to obtain a third target code block and sends it.

[0118] The second transmission period is one of the multiple transmission periods included in the first communication device 201, located after the first transmission period and spaced an even number of transmission periods apart from the first transmission period. For example, when the first transmission period is the first transmission period, the second transmission period can be the second, fourth, or sixth transmission period. Optionally, when the first transmission period is represented as T0, the first transmission period is an even number of periods, and the second transmission period is an odd number of periods. When the first transmission period is represented as T1, the first transmission period is an odd number of periods, and the second transmission period is an even number of periods.

[0119] In addition, the bit width of the second idle code is the same as that of the first scrambling code.

[0120] Furthermore, the first and second free codes are different; that is, the code patterns of the first and second free codes are different. The sum of the number of 0s in the first and second free codes is the first value; the sum of the number of 1s in the first and second free codes is the second value; the first and second values ​​are the same. In one possible instance, the number of 1s and 0s in the first and second free codes are the same, and the number of 1s and 0s in the second free code are also the same, in which case the first value and the second value are the same. In another possible example, the number of 1s and 0s in the first and second free codes are different, and the number of 1s and 0s in the second free code are also different, in which case the first value and the second value are the same.

[0121] For example, suppose the first free code is 10101 and the second free code is 01010. The first free code contains 3 1s and 2 0s; the second free code contains 2 1s and 3 0s. The sum of the number of 1s in the first and second free codes is a first value, which equals 5; the sum of the number of 0s in the first and second free codes is a second value, which also equals 5. The first and second values ​​are the same.

[0122] In this embodiment, when both the data block to be transmitted in the first transmission cycle and the data block to be transmitted in the second transmission cycle are invalid data (i.e., no data flow), the data block to be transmitted in the first transmission cycle is scrambled using a first idle code, and the data block in the second transmission cycle is scrambled using a second idle code. This makes the third target code block in the second transmission cycle different from the target code block transmitted in the last clock cycle of the first transmission cycle. This means that the third target code block in the second transmission cycle has been flipped compared to the target code block transmitted in the last clock cycle of the first transmission cycle, ensuring that the target code block does not flip in the first or second transmission cycle. This ensures that the target code block flips as few times as possible between adjacent transmission cycles, reducing the power consumption overhead caused by the flipping of the target code block corresponding to invalid data. At the same time, it avoids the bit error problem caused by the aging of the physical layer analog circuit supporting chip interconnection due to the long-term non-flipping of the target code block, as well as the bit error problem caused by the sudden change in the flip rate of the chip power supply, thus reducing the bit error rate.

[0123] In one possible embodiment, the method provided in this application further includes: a second communication device 202 receiving a third target code block in a third clock cycle; the third clock cycle is the first clock cycle in a second reception period, and the second reception period is the reception period following the first reception period; when the third target code block includes invalid data, that is, when the indication information carried by the third target code block indicates that the third target code block includes invalid data, the second communication device 202 decodes the third target code block using a first scrambling code and a second idle code to obtain a third data code block; the second idle code is different from the first idle code.

[0124] In one possible embodiment, the second communication device 202 determines a first scrambling code using a scrambling polynomial and an initial scrambling seed; determines a second idle code based on the first scrambling code; decodes a third target code block using the first scrambling code to obtain a third data code block to be scrambled; and decodes the third data code block to be scrambled using the second idle code to obtain a third data code block.

[0125] The second receiving period is one of the multiple receiving periods included in the second communication device 202, located after the first receiving period and spaced an even number of receiving periods apart from the first receiving period. For example, when the first receiving period is the first receiving period, the second receiving period is the second, fourth, or sixth receiving period. Optionally, when the first receiving period is represented as T0, the first receiving period is an even number of periods, and the second receiving period is an odd number of periods. When the first receiving period is represented as T1, the first receiving period is an odd number of periods, and the second receiving period is an even number of periods.

[0126] Furthermore, the first idle code, the second idle code, and the initial scrambling seed can all be configured through registers. In practical applications, the first idle code, the second idle code, and the initial scrambling seed can be configured through registers to ensure that the number of 1s and 0s in the first target code block, the second target code block, and the third target code block are the same, that is, the number of 1s and 0s in the first target code block, the second target code block, and the third target code block are balanced.

[0127] Similarly, for the data block to be transmitted within any clock cycle after the first clock cycle in the second transmission period, when the data block contains invalid data, the process by which the first communication device 201 processes the data block is similar to the process by which the first communication device 201 processes the second data block. When the data block contains valid data, the process by which the first communication device 201 processes the data block is similar to step S301 described above, and will not be repeated here.

[0128] Similarly, for the data block to be transmitted within any clock cycle after the first clock cycle in the second transmission period, when the data block contains invalid data, the process by which the first communication device 201 processes the data block is similar to the process by which the first communication device 201 processes the second data block. When the data block contains valid data, the process by which the first communication device 201 processes the data block is similar to step S301 described above, and will not be repeated here.

[0129] Similarly, for the target code block received within any clock clock after the first clock clock in the second receiving cycle, when the target code block contains invalid data, the process by which the second communication device 202 processes the target code block is similar to the process by which the second communication device 202 processes the second target code block. When the target code block contains valid data, the process by which the second communication device 202 processes the target code block is similar to step S302 described above, and will not be repeated here.

[0130] For ease of understanding, the data transmission method provided in this application embodiment will be described below using Figure 4 as an example.

[0131] For example, Figure 4 is a schematic diagram of a data transmission method provided in an embodiment of this application. It is assumed that the first communication device 201 includes m transmission cycles, which can be sequentially represented as T0 to Tm-1. Each transmission cycle includes j clock beats, which can be sequentially represented as C0 to Cj-1. In the first transmission cycle T0, the first data block P0 to the third data block P2 to be transmitted within the first clock beat C0 to the third clock beat C2 are valid data. The remaining clock beats of the first transmission cycle and the remaining clock beats of the other transmission cycles are all invalid data P. The code pattern of the invalid data P is the same as the code pattern of the third data block P2. Since the first data code blocks P0 to P2 to be transmitted within the first clock cycle C0 to the third clock cycle C2 of the first transmission period T0 are valid data, the first communication device 201 determines the first scrambling code S0 to the third scrambling code S2 corresponding to the first data code blocks P0 to P2 in sequence according to the scrambling polynomial and the initial scrambling code seed, and scrambles the first data code blocks P0 to P2 in sequence according to the first scrambling code S0 to the third scrambling code S2 to obtain the first target code block R0 to the third target code block R2. There is no corresponding idle code in the first transmission period T0. For the fourth data code block P to be transmitted within the fourth clock cycle C3 of the first transmission period, the first communication device 201 uses the third scrambling code S2 corresponding to the third data code block P2 as the scrambling code for the fourth data code block P, and scrambles the fourth data code block P according to the third scrambling code S2 to obtain the fourth target code block R2. For any data block P to be transmitted in any one of the fifth clock beats C4 to the j-th clock beat Cj-1 of the first transmission cycle, the processing procedure of the first communication device 201 for the data block P is similar to the processing procedure for the fourth data block P to be transmitted in the fourth clock beat C3.

[0132] For a data block P to be transmitted within the first clock beat C0 of any transmission period from the second transmission period T1 to the m-th transmission period Tm-1, the first communication device 201 determines the first scrambling code S0 corresponding to the data block P to be transmitted within the first clock beat C0 according to the scrambling polynomial and the initial scrambling seed. For a data block P to be transmitted within the first clock beat C0 of an even-numbered period from the second transmission period T1 to the m-th transmission period Tm-1, the first communication device 201 determines the first idle code I1 according to the first scrambling code S0, and determines the data block K1 to be scrambled according to the first idle code I1 and the data block P. The first scrambling code S0 is used to scramble the data block K1 to be scrambled to obtain the target code block R3 within the first clock beat C0. For a data block P to be transmitted within the second clock beat C1 of an even-numbered period, the first communication device 201 uses a first scrambling code as the scrambling code for the data block P to be transmitted within the second clock beat C1, and uses a first idle code I1 as the idle code for the data block P to be transmitted within the second clock beat C1. Based on the first idle code I1 and the data block P, the data block K1 to be scrambled is determined, and the first scrambling code S0 is used to scramble the data block K1 to be scrambled to obtain the target code block R3 within the second clock beat C1. For a data block P to be transmitted within any clock beat from the third clock beat C2 to the j-th clock beat Cj-1 of an even-numbered period, the processing procedure of the first communication device 201 for the data block P is similar to the processing procedure for the data block P in the second clock beat C1 of an even-numbered period.

[0133] For the data block P to be transmitted within the first clock cycle C0 of the odd-numbered periods from the second transmission period T1 to the m-th transmission period Tm-1, the first communication device 201 determines the second idle code I2 according to the first scrambling code S0, and determines the data block K2 to be scrambled according to the second idle code I2 and the data block P. The first scrambling code S0 is used to scramble the data block K2 to be scrambled to obtain the target block R4 within the first clock cycle C0. For the data block P to be transmitted within the second clock cycle C1 of the odd-numbered periods, the first communication device 201 uses the first scrambling code as the scrambling code for the data block P to be transmitted within the second clock cycle C1, and uses the second idle code I2 as the idle code for the data block P to be transmitted within the second clock cycle C1. The second idle code I2 and the data block P are used to determine the data block K2 to be scrambled, and the first scrambling code S0 is used to scramble the data block K2 to be scrambled to obtain the target block R4 within the second clock cycle C1. For any data block P to be transmitted in any clock beat from the third clock beat C2 to the j-th clock beat Cj-1 in an odd-numbered period, the processing procedure of the first communication device 201 for the data block P is similar to the processing procedure for the data block P in the second clock beat C1 of the odd-numbered period.

[0134] Therefore, in any transmission period from the second transmission period T1 to the m-th transmission period Tm-1, the scrambling code corresponding to the data block P to be transmitted within any clock ...

[0135] As shown in Figure 4, for any transmission cycle from the first transmission cycle T0 to the m-th transmission cycle Tm-1, regardless of whether the data block to be transmitted within the first clock tick of that transmission cycle is valid data, the first communication device 201 updates the code pattern corresponding to the data block to be transmitted within the first clock tick of that transmission cycle to the first scrambling code S0. When the first data code P0 to be transmitted within the first clock tick of the first transmission cycle T0 is valid data, there is no corresponding idle code pattern for the data block to be transmitted in the first transmission cycle T0. For any transmission cycle from the second transmission cycle T1 to the m-th transmission cycle Tm-1, the invalid data, the invalid data code pattern, the scrambling code corresponding to the invalid data, and the idle code remain unchanged. The idle codes of two adjacent transmission cycles are different. The target code block within this transmission cycle is not flipped; the target code block within two adjacent transmission cycles is only flipped at the first clock tick of the next transmission cycle, that is, the target code block at the boundary of two adjacent transmission cycles is flipped, reducing the power consumption of the first communication device 201.

[0136] In practical applications, the duration of the target code pattern can be adjusted by configuring a periodic window, based on the duration requirements of the physical layer analog circuit supporting the interconnection of the first communication device 201 and the second communication device 202. In one possible embodiment, when the physical layer analog circuit supporting the interconnection of the first communication device 201 and the second communication device 202 has no special requirements on the duration of the target code pattern, the second code pattern and the first code pattern can be the same. Figure 4 illustrates this using the example of a low-traffic first transmission period T0 and no-traffic transmission periods for the remaining periods.

[0137] This application provides a data transmission method in which a first communication device determines a first scrambling code corresponding to a first data code block, and scrambles the first data code block according to the first scrambling code to obtain a first target code block, and transmits the first target code block in the first clock cycle of a first transmission period. When a second data code block in the next clock cycle of the first transmission period contains invalid data, the first communication device uses the first scrambling code as the scrambling code corresponding to the second data code block, and scrambles the second data code block according to the first scrambling code to obtain the second target code block and transmits it. In this process, there is no need to re-determine the scrambling code for the second data code block. The first scrambling code corresponding to the first data code block is directly used as the scrambling code corresponding to the second data code block, which reduces the power consumption of the first communication device. The second data code block includes invalid data, and the code pattern of the second data code block is the same as that of the first data code block, that is, the code pattern of the invalid data is controlled not to be flipped. The scrambling codes corresponding to the first data code block and the second data code block are both the first scrambling code, that is, the scrambling code of the invalid data is controlled not to be flipped. This makes the first target code block obtained by scrambling the same as the second target code block, that is, the second target code block has not been flipped compared to the first target code block, that is, the second target code block has not been updated compared to the first target code block, which reduces the flip rate of the target code block corresponding to the invalid data in the first transmission period, thereby reducing the power consumption overhead caused by the flip of the target code block corresponding to the invalid data. In addition, in scenarios with light or no traffic, such as when there is no valid data in the first and second transmission cycles, different idle codes are used to scramble the data code blocks, so that the target code blocks of two adjacent transmission cycles are flipped at the critical point of the transmission cycle, and the target code blocks within a single transmission cycle are not flipped, thus ensuring that the target code blocks are flipped as little as possible between two adjacent transmission cycles.

[0138] It is understood that, in order to achieve the above-mentioned functions, the first and second communication devices include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] This application embodiment can divide the first communication device and the second communication device into functional modules according to the above method example. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the division of each functional module according to each function as an example.

[0140] In the case of using integrated units, FIG5, for example, shows a schematic diagram of the structure of the first communication device involved in the above embodiments. The first communication device includes a determining unit 501, a scrambling unit 502, and a transmitting unit 503. The determining unit 501 is used to support the first communication device in determining a scrambling code, a first idle code, and a second idle code. The scrambling unit 502 is used to support the first communication device in scrambling data code blocks (including a first data code block, a second data code block, and a third data code block) using the scrambling code and / or the idle code (including the first idle code and the second idle code). The transmitting unit 503 is used to support the first communication device in executing one or more steps S301 and S303 in the above method embodiments.

[0141] All relevant content of each step involved in the above method embodiments can be referenced to the functional description of the corresponding functional module in the first communication device, and will not be repeated here in the embodiments of this application.

[0142] For example, Figure 6 shows a schematic diagram of the structure of the second communication device involved in the above embodiments. The second communication device includes a determining unit 601, a decoding unit 602, and a receiving unit 603. The receiving unit 603 is used to support the second communication device in performing one or more steps S302 and S304 in the above method embodiments. The decoding unit 602 is used to support the second communication device in performing one or more steps S302 and S305 in the above method embodiments. The determining unit 601 is used to support the second communication device in determining the scrambling code, the first idle code, and the second idle code.

[0143] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module of the second communication device, and will not be repeated here in the embodiments of this application.

[0144] In another embodiment of this application, a communication device is provided, which includes a first communication device and a second communication device. The first communication device is connected to the second communication device through an interface. The communication device may be or include the communication device shown in FIG2 above. The first communication device is used to perform the steps of the first communication device in the method embodiment provided above, and the second communication device is used to perform the steps of the second communication device in the method embodiment provided above.

[0145] It is understood that all relevant content of each step involved in the above method embodiments can be referenced in the embodiments of the communication device, and the embodiments of this application will not be repeated here.

[0146] In another embodiment of this application, a communication device is provided. A schematic diagram of the communication device is shown in Figure 7. The communication device includes a processor 701, a memory 702, and an interface 703, which can also be called a communication interface. The processor 701, memory 702, and interface 703 communicate with each other via a bus. The memory stores instructions, which, when executed on the processor, cause the processor to perform the steps of the first communication device in the above method embodiment.

[0147] It is understood that all relevant content of each step involved in the above method embodiments can be referenced in the embodiments of communication devices, and the embodiments of this application will not be repeated here.

[0148] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed.

[0149] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0150] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. This readable storage medium may include various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory, random access memory, magnetic disk, or optical disk. Based on this understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0151] In another embodiment of this application, a readable storage medium is also provided, which stores a computer program or instructions that, when executed by a chip or processor, perform the steps of the first communication device in the above method embodiment.

[0152] In another embodiment of this application, a readable storage medium is also provided, which stores a computer program or instructions that, when executed by a chip or processor, perform the steps of the second communication device in the above method embodiment.

[0153] In another embodiment of this application, a computer program product is also provided, which includes a computer program or instructions stored in a readable storage medium; at least one processor of the device can read the computer program or instructions from the readable storage medium, and when the at least one processor executes the computer program or instructions, it performs the steps of the first communication device in the above method embodiment.

[0154] In another embodiment of this application, a computer program product is also provided, which includes a computer program or instructions stored in a readable storage medium; at least one processor of the device can read the computer program or instructions from the readable storage medium, and when the at least one processor executes the computer program or instructions, it performs the steps of the second communication device in the above method embodiment.

[0155] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data transmission method, characterized by, The method includes: In the first clock cycle, a first target code block corresponding to a first data code block is transmitted. The first target code block is obtained by scrambling the first data code block using a first scrambling code. The first clock cycle is located in the first transmission period. In the second clock cycle, the second target code block corresponding to the second data code block is transmitted. The second data code block includes invalid data. The second target code block is obtained by scrambling the second data code block using the first scrambling code. The second clock cycle is the next clock cycle after the first clock cycle in the first transmission period. The code pattern of the first data code block is the same as that of the second data code block.

2. The method of claim 1, wherein, When the first data code block includes invalid data, the method further includes: The first data code block is scrambled using the first scrambling code and the first idle code to obtain the first target code block.

3. The method of claim 2, wherein, The method further includes: The second data code block is scrambled using the first scrambling code and the first idle code to obtain the second target code block.

4. The method according to claim 2 or 3, characterized in that, The method further includes: In the third clock cycle, the third target code block corresponding to the third data code block is sent. The third data code block includes invalid data. The third target code block is obtained by scrambling the third data code block using the first scrambling code and the second idle code. Wherein, the third clock beat is the first clock beat in the second transmission cycle, and the second transmission cycle is the transmission cycle following the first transmission cycle; the second idle code is different from the first idle code.

5. The method of claim 4, wherein, The method further includes: The first scrambling code is determined using the scrambling polynomial and the initial scrambling seed; The second idle code is determined based on the first scrambling code; The third data code block is scrambled using the second free code to obtain the third data code block to be scrambled. The third target code block is obtained by scrambling the third data code block to be scrambled using the first scrambling code.

6. The method according to claim 4 or 5, characterized in that, The sum of the number of 0s in the first free code and the number of 0s in the second free code is a first value; the sum of the number of 1s in the first free code and the number of 1s in the second free code is a second value; the first value and the second value are the same.

7. The method according to any one of claims 4-6, characterized in that, The interval between the first transmission period and the second transmission period is an even number of transmission periods.

8. A data transmission method, characterized by, The method includes: In the first clock cycle, a first target code block is received, and the first target code block is decoded using a first scrambling code to obtain a first data code block; the first scrambling code is the scrambling code corresponding to the first data code block. The second target code block is received in the second clock cycle, which is the next clock cycle after the first clock cycle in the first reception period. When the second target code block contains invalid data, the second target code block is decoded using the first scrambling code to obtain the second data code block.

9. The method of claim 8, wherein, When the first target code block contains invalid data, the step of decoding the first target code block using a first scrambling code to obtain a first data code block includes: The first target code block is decoded using the first scrambling code and the first idle code to obtain the first data code block.

10. The method of claim 9, wherein, Decoding the second target code block using the first scrambling code to obtain the second data code block includes: The second target code block is decoded using the first scrambling code and the first idle code to obtain the second data code block.

11. The method according to claim 9 or 10, characterized in that, The method further includes: The third target code block is received in the third clock cycle; the third clock cycle is the first clock cycle in the second reception period, and the second reception period is the reception period after the first reception period. When the third target code block includes invalid data, the third target code block is decoded using the first scrambling code and the second idle code to obtain the third data code block; the second idle code is different from the first idle code.

12. The method of claim 11, wherein, The step of decoding the third target code block using the first scrambling code and the second idle code to obtain the third data code block includes: The first scrambling code is determined based on the scrambling polynomial and the initial scrambling seed; The second idle code is determined based on the first scrambling code; The third target code block is decoded using the first scrambling code to obtain the third data code block to be scrambled; The third data code block to be scrambled is decoded using the second idle code to obtain the third data code block.

13. The method according to claim 11 or 12, characterized in that, The sum of the number of 0s in the first free code and the number of 0s in the second free code is a first value; the sum of the number of 1s in the first free code and the number of 1s in the second free code is a second value; the first value and the second value are the same.

14. The method according to any one of claims 11-13, characterized in that, An even number of reception cycles are spaced between the first reception cycle and the second reception cycle.

15. A communication device, characterized in that, The communication device includes a module that performs the operational steps of the method as described in any one of claims 1-14.

16. A communication device, characterized by The communication device includes a processor and a memory, the memory storing instructions that, when executed on the processor, cause the processor to perform the data transmission method as described in any one of claims 1-7, or the data transmission method as described in any one of claims 8-14.

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