Control method, control apparatus, compute-in-memory system, and electronic device

Abstract

A control method, a control apparatus, a compute-in-memory system, and an electronic device, which relate to the technical field of electronics. The control method is used for controlling the refreshing of a memory circuit, wherein the memory circuit comprises a plurality of memory partitions. The control method comprises: when a refresh condition is met, determining a first memory partition and a second memory partition of a memory circuit, wherein the first memory partition is a memory partition to be refreshed from among a plurality of memory partitions, and the second memory partition is a memory partition, the current storage state of which is empty or invalid, from among the plurality of memory partitions; writing into the second memory partition data stored in the first memory partition; and controlling the storage state of the first memory partition to be empty or invalid. In the control method, refreshing is performed per memory partition, such that service or operation suspension caused by full-circuit refreshing can be reduced, thereby improving the overall responsiveness of the compute-in-memory system to services.

Description

Control methods, control devices, computing systems, and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411923892.2, filed on December 24, 2024, entitled "Control Method, Control Device, In-Memory System and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and more specifically, to control methods, control devices, storage circuits, memory computing systems, and electronic devices. Background Technology

[0003] In-memory computing (IMC) is an innovative technology proposed to address the problem of the separation of computation and storage in the traditional von Neumann computer architecture. IMC reduces transmission latency and memory access power consumption by physically integrating data storage and computation, or bringing them closer together. IMC can significantly improve data processing efficiency, but it still faces challenges, such as the need to improve its reliability. Summary of the Invention

[0004] This application provides a control method, control device, memory computing system, and electronic device to improve the reliability of memory computing.

[0005] In a first aspect, a control method is provided for controlling the refresh of a storage circuit, the storage circuit including multiple storage partitions. The control method includes: when refresh conditions are met, determining a first storage partition and a second storage partition of the storage circuit, the first storage partition being the storage partition to be refreshed among the multiple storage partitions, and the second storage partition being the storage partition whose current storage state is empty or invalid among the multiple storage partitions; writing the data stored in the first storage partition to the second storage partition; and controlling the storage state of the first storage partition to be empty or invalid.

[0006] In some implementations of the first aspect, the refresh condition includes a first precision index exceeding a preset precision index range, the first precision index including the precision index of the storage circuit or the precision index of the first storage partition.

[0007] In some implementations of the first aspect, the control method further includes: obtaining a first precision index; and determining that the refresh condition is met when the first precision index exceeds a preset precision index range.

[0008] Optionally, based on the data storage status of multiple storage partitions, a first storage partition and a second storage partition of the storage circuit are determined, wherein the first storage partition may be a partition that currently stores data, and the second storage partition may be a partition that is currently empty (i.e., a backup storage partition).

[0009] In some implementations of the first aspect, the control method further includes: determining a first accuracy index based on one or more of the following factors: the usage status of the storage circuit or the first storage partition; a first sampled value of a storage cell or a second sampled value of a group of storage cells in the storage circuit or the first storage partition, wherein the first sampled value indicates the equivalent data stored in the storage cell, and the second sampled value indicates the calculation result of the group of storage cells; and the bit error rate of the original codeword, wherein the original codeword is used to generate data written to the storage circuit or the first storage partition. Optionally, the usage status of the storage circuit may include the continuous operating time of the storage circuit or the continuous operating time of the first storage partition.

[0010] Optionally, the first sampled value may also correspond to the calculation result of the first storage partition.

[0011] Optionally, the aforementioned bit error rate is used to indicate the deviation between the original codeword of the error correction code written to the storage circuit or the first storage partition and the read codeword of the error correction code read from the storage circuit or the first storage partition.

[0012] In some implementations of the first aspect, the multiple storage partitions also include a third storage partition, and the above control method further includes: writing the data stored in the third storage partition to the first storage partition; controlling the storage state of the third storage partition to be empty or invalid.

[0013] Optionally, after the data stored in the third storage partition is written to the first storage partition, the third storage partition can be marked as invalid. After a certain period of time, an erase operation can be performed on the storage partition marked as invalid, i.e., the third storage partition, so that the storage state of the third storage partition is changed to an empty state, thereby making the third storage partition usable as a storage partition for storing new data.

[0014] Optionally, after writing the data stored in the third storage partition to the first storage partition, the third storage partition can be directly erased, so that the storage state of the third storage partition is changed to an empty state, thereby making the third storage partition usable as a storage partition for storing new data.

[0015] Optionally, during subsequent data transfer, if the third storage partition is marked as invalid and not empty when writing data to it, the third storage partition can be erased first, and then data can be written to it.

[0016] In some implementations of the first aspect, the multiple storage partitions also include a fourth storage partition, and the control method further includes: writing the data stored in the second storage partition to the fourth storage partition; and controlling the storage state of the second storage partition to be empty or invalid.

[0017] At this point, the fourth storage partition can be used as a new backup storage partition.

[0018] Optionally, after the data stored in the fourth storage partition is written to the second storage partition, the fourth storage partition can be marked as invalid. After a certain period of time, an erase operation can be performed on the storage partition marked as invalid, i.e., the fourth storage partition, so that the storage state of the fourth storage partition is changed to an empty state, thereby making the fourth storage partition usable as a storage partition for storing new data.

[0019] Optionally, after writing the data stored in the fourth storage partition to the second storage partition, the fourth storage partition can be directly erased, so that the storage state of the fourth storage partition is changed to an empty state, thereby making the fourth storage partition usable as a storage partition for storing new data.

[0020] Optionally, during subsequent data transfer, if the fourth storage partition is marked as invalid and not empty when writing data to it, the fourth storage partition can be erased first, and then data can be written to it.

[0021] Optionally, before writing the data stored in the fourth storage partition to the second storage partition, it can be determined whether the fourth storage partition meets the refresh conditions. If the refresh conditions are met, the operation of writing the data stored in the fourth storage partition to the second storage partition can be performed. The refresh conditions include whether the precision index of the fourth storage partition exceeds the preset precision index range.

[0022] Optionally, data written to the second storage partition does not need to be written back to the fourth storage partition, and the related computational tasks for this data can be migrated to the second storage partition for execution.

[0023] In some implementations of the first aspect, the control method further includes: rewriting the data stored in the second storage partition back to the first storage partition.

[0024] In some implementations of the first aspect, refresh control of multiple storage partitions is performed in rotation.

[0025] In some implementations of the first aspect, the refresh control of multiple storage partitions is performed periodically, and the refresh control start times of the multiple storage partitions are different.

[0026] After the first storage partition has been running for a first period of time, refresh control as described in the aforementioned embodiments can be applied to the first storage partition. Similarly, after the second storage partition has been running for a second period of time, refresh control as described in the aforementioned embodiments can be applied to the second storage partition. The same principle applies to other storage partitions. The first period of time can be referred to as the refresh cycle of the first storage partition, and the second period of time can be referred to as the refresh cycle of the second storage partition. The first period of time and the second period of time can be the same or different.

[0027] Optionally, when the storage circuit includes N storage partitions, the storage circuit corresponds to N-1 refresh cycles, each corresponding to one of the N-1 refresh partitions.

[0028] Optionally, the refresh cycle of the storage partition can be dynamically adjusted in conjunction with the precision detection operation. Taking the first storage partition as an example, if the refresh cycle previously set for the first storage partition has elapsed, but the first precision index has not yet exceeded the preset precision index range, the next refresh control time for the first storage partition can be postponed, or the refresh cycle for the first storage partition can be increased after the current refresh control operation. Specifically, the next refresh control time (or refresh cycle) for the storage partition can be determined through precision monitoring, or the next refresh control time (or refresh cycle) for the storage partition can be determined based on the first precision using a preset model.

[0029] In some implementations of the first aspect, multiple storage partitions have the same capacity.

[0030] In some implementations of the first aspect, a second precision index is obtained, which includes a precision index of the storage circuit or a precision index of the first storage partition; based on the second precision index, the computational load of the storage circuit or the first storage partition is controlled.

[0031] Optionally, the aforementioned computational load may include at least one of the following parameters: the parallelism (or computational parallelism) of the storage circuit or the first storage partition, the computational speed of the storage circuit or the first storage partition, the power consumption of the storage circuit or the first storage partition, and the operating voltage of the storage circuit or the first storage partition.

[0032] Optionally, when the first precision index includes the precision index of the first storage partition, the parallelism of the first storage partition can be determined based on the precision index of the first storage partition.

[0033] Optionally, when the first accuracy index includes the accuracy index of the storage circuit, the parallelism of the storage circuit can be determined based on the accuracy index of the storage circuit.

[0034] Optionally, the accuracy index of the above-mentioned storage circuit can be determined based on the accuracy index of the entire storage circuit, wherein the accuracy index of the entire storage circuit can be a weighted average of the accuracy indices of multiple storage partitions, and the weight can be 1.

[0035] Optionally, the accuracy of the aforementioned storage circuit can be determined based on the lowest accuracy among the multiple storage partitions included in the storage circuit.

[0036] Optionally, the aforementioned second precision index is related to the lifecycle of the storage circuit or the lifecycle of the first storage partition. Therefore, the parallelism of the storage circuit or the first storage partition can be determined based on the stage of the lifecycle of the storage circuit or the first storage partition, or the duration of continuous operation, the number of calculations, etc.

[0037] Optionally, the parallelism of each storage partition in the above storage circuit can be the same or different.

[0038] Optionally, the aforementioned parallelism can be related to a threshold for the vector sum of the data input to the storage circuit or storage partition. The vector sum can represent the accumulated value of non-zero values ​​in the data. For data represented by digital signals, the vector sum can further represent the number of 1s in the data. Therefore, the threshold for the vector sum limits the upper limit of the accumulated value of non-zero values ​​in the input data. The larger the accumulated value of non-zero values ​​in the input data, the lower the accuracy of the storage circuit's multiplication and accumulation operation based on that input data and the corresponding weight data; that is, the lower the computational accuracy.

[0039] The computational accuracy of a storage circuit is related to the accuracy (or storage accuracy) of the data stored in the storage circuit. The worse the storage accuracy, the worse the accuracy of the result obtained by the storage circuit based on that storage accuracy, that is, the worse the computational accuracy of the storage circuit. In addition, the computational accuracy of a storage circuit is also related to the parallelism of the storage circuit. Therefore, the accuracy (or storage accuracy) of the data stored in the storage circuit and the parallelism of the storage circuit jointly affect the computational accuracy of the storage circuit.

[0040] Secondly, a control device is provided for controlling the refresh of a storage circuit, the storage circuit including multiple storage partitions. The control device includes: a determining unit, an operating unit, and a controlling unit. The determining unit is used to determine a first storage partition and a second storage partition of the storage circuit when refresh conditions are met. The first storage partition is the storage partition to be refreshed among the multiple storage partitions, and the second storage partition is the storage partition whose current storage state is empty or invalid among the multiple storage partitions. The operating unit is used to write the data stored in the first storage partition to the second storage partition. The controlling unit is used to control the storage state of the first storage partition to be empty or invalid.

[0041] In some implementations of the second aspect, the refresh condition includes a first precision index exceeding a preset precision index range, wherein the first precision index includes the precision index of the storage circuit or the precision index of the first storage partition.

[0042] In some implementations of the second aspect, the control device further includes: an acquisition unit for acquiring a first precision index; the determination unit is further configured to: determine that the refresh condition is met when the first precision index exceeds a preset precision index range.

[0043] In some implementations of the second aspect, the aforementioned acquisition unit is further configured to: determine a first precision index based on one or more of the following factors: the usage status of the storage circuit or the first storage partition; a first sampled value of a storage cell or a second sampled value of a group of storage cells in the storage circuit or the first storage partition, wherein the first sampled value is used to indicate the equivalent data stored in the storage cell, or the first sampled value corresponds to the calculation result of the first storage partition, and the second sampled value is used to indicate the calculation result of the group of storage cells; and the bit error rate of the original codeword, wherein the original codeword is used to generate data written to the storage circuit or the first storage partition.

[0044] In some implementations of the second aspect, the plurality of storage partitions further include a third storage partition, and the operation unit is further configured to: write the data stored in the third storage partition to the first storage partition; the control unit is further configured to: control the storage state of the third storage partition to be empty or invalid.

[0045] In some implementations of the second aspect, the plurality of storage partitions further include a fourth storage partition, and the operation unit is further configured to: write the data stored in the second storage partition to the fourth storage partition; the control unit is further configured to: control the storage state of the second storage partition to be empty or invalid.

[0046] In some implementations of the second aspect, after the control unit controls the storage state of the first storage partition to be empty, it is also used to: rewrite the data stored in the second storage partition back into the first storage partition.

[0047] In some implementations of the second aspect, the refresh control of the aforementioned multiple storage partitions is performed in rotation.

[0048] In some implementations of the second aspect, the refresh control of the aforementioned multiple storage partitions is performed periodically, and the refresh control start time of the multiple storage partitions is different.

[0049] In some implementations of the second aspect, the aforementioned multiple storage partitions have the same capacity.

[0050] In some implementations of the second aspect, the aforementioned acquisition unit is further configured to: acquire a second precision index, the second precision index including a precision index of the storage circuit or a precision index of the first storage partition; the aforementioned control unit is further configured to: control the computational load of the storage circuit or the first storage partition based on the second precision index.

[0051] For a description of the beneficial effects of the second aspect, please refer to the description of the beneficial effects of the first aspect, which will not be repeated here.

[0052] Thirdly, a control device is provided, comprising at least one processing circuit and an interface circuit, the interface circuit being signal-connected to a storage circuit, the at least one processing circuit being used to execute any of the control methods of the first aspect.

[0053] Fourthly, a storage computing system is provided, comprising: a storage circuit including multiple storage partitions; and a control device for performing a method as described in any possible implementation of the method design in the first aspect above, to perform refresh control on the multiple storage partitions.

[0054] Fifthly, an electronic device is provided, which includes any of the storage and computing systems of the fourth aspect.

[0055] In a sixth aspect, a computer program product is provided, the computer program product including instructions that, when executed by a processor, cause any of the control methods of the first aspect above to be executed.

[0056] In a seventh aspect, a computer-readable medium is provided that stores instructions which, when executed by a processor, cause any of the control methods of the first aspect above to be performed.

[0057] Based on the above technical solution, the internal storage circuit can be refreshed in the form of storage partitions, thereby reducing the interruption of business or work caused by refreshing the entire circuit, and thus improving the overall responsiveness of the in-memory computing system to business needs. Moreover, refreshing can be achieved without using external storage resources, improving refresh efficiency. Attached Figure Description

[0058] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application;

[0059] Figure 2 shows a schematic diagram of yet another in-memory computing system according to an exemplary embodiment of this application;

[0060] Figure 3 is a flowchart illustrating a control method according to an exemplary embodiment of this application;

[0061] Figure 4 is a flowchart illustrating another control method according to an exemplary embodiment of this application;

[0062] Figure 5 is a flowchart illustrating another control method according to an exemplary embodiment of this application;

[0063] Figure 6 is a flowchart illustrating another control method according to an exemplary embodiment of this application;

[0064] Figure 7 is a schematic diagram of a rotating refresh control method according to an exemplary embodiment of this application;

[0065] Figure 8 is a schematic diagram of the precision of multiple storage partitions according to an exemplary embodiment of this application;

[0066] Figure 9 is a flowchart illustrating another control method according to an exemplary embodiment of this application;

[0067] Figure 10 is a schematic diagram of a control device according to an exemplary embodiment of the present application;

[0068] Figure 11 is a schematic diagram of a control device according to an exemplary embodiment of the present application;

[0069] Figure 12 is a schematic diagram of an electronic device according to an exemplary embodiment of the present application. Detailed Implementation

[0070] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0071] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0072] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0073] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0074] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0075] In in-memory computing technology, in-memory computing systems can use memory as a carrier to perform in-memory computation (or operations). This memory can include: non-volatile memory (NVM) or volatile memory (VM). Volatile memory can include, but is not limited to, static random access memory (SRAM); non-volatile memory can include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), or phase change memory (PCM), etc.

[0076] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0077] As shown in Figure 1, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0078] Storage cells can utilize the conduction capability of semiconductor devices, such as electrical conductance or transconductance, to store weight data. For example, a storage cell may include a resistive storage device or a transistor storage device. For instance, weight data can be stored by controlling the electrical conductance of a resistive storage device, or by controlling the transconductance of a transistor storage device.

[0079] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group can achieve an equivalent multiplication operation. The storage cell array includes one-dimensional arrays, two-dimensional arrays, or three-dimensional arrays, etc., and the storage cell group includes multiple storage cells located in the same row or column, or multiple storage cells located in multiple rows or columns, etc. These multiple storage cells can output their output signals collinearly.

[0080] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0081] As an example, Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0082] As shown in Figure 2, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data w ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0083] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0084] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For example, if the input signal includes a voltage signal and the output signal includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242. The second conversion can be implemented, for example, through a sampling circuit, and the signal converted by the first conversion circuit 241 can be further provided to the second conversion circuit 242 for the second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert the current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal and provide it to the subsequent circuit. Additionally, in the example of FIG. 2, the control circuit 220 can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0085] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly by columns, and the output terminals can be connected collinearly by rows. Furthermore, the input terminal of a memory cell can include the gate of a transistor memory device, or it can include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell can include a floating gate transistor (FGT), a memristor, a magnetic tunnel junction (MTJ), or a phase-change structure. Furthermore, a memory cell can include multiple transistors; for example, a memory cell can include a first transistor and a second transistor, where the gate of one transistor is connected to the source or drain of the other transistor, and the charge stored at the gate can be used to characterize weight data. Optionally, the gate can also be connected to a capacitor to increase the stability and duration of the stored charge.

[0086] During use, storage circuits may experience precision loss, which can lead to decreased accuracy of calculation results and thus affect the reliability of the in-memory computing system. Therefore, embodiments of this application propose a control method, control device, in-memory computing system, and electronic device. While utilizing refresh to improve storage precision, this method can reduce the impact of storage circuit refresh on services, thereby improving the overall responsiveness of the in-memory computing system to services.

[0087] Figure 3 is a flowchart illustrating a control method according to an exemplary embodiment of this application.

[0088] In some possible embodiments, the above control method can be used to control the refresh of a storage circuit, which may include multiple storage partitions. Referring to FIG3, the control method 300 may include the following steps:

[0089] S310: When the refresh conditions are met, determine the first storage partition and the second storage partition of the storage circuit; wherein, the first storage partition is the storage partition to be refreshed among the above multiple storage partitions, and the second storage partition is the storage partition whose current storage state is empty or invalid among the above multiple storage partitions.

[0090] S320: Write the data stored in the first storage partition to the second storage partition.

[0091] S330: Controls the storage status of the first storage partition to be empty or invalid.

[0092] In some possible embodiments, the above storage state may include: non-empty, empty, invalid, or valid, etc.

[0093] In some possible embodiments, after executing S320, the first storage partition can be marked, for example, as invalid. For the storage partition marked as invalid, an erasure operation can be flexibly performed. For example, the erasure operation can be performed directly after the data is transferred, or the erasure operation can be performed when the set erasure time or erasure trigger condition is met, so that the storage state of the first storage partition is changed to an empty state, thereby making the first storage partition usable as a storage partition for storing new data.

[0094] In some possible embodiments, after executing S320, the first storage partition can be directly erased, so that the storage state of the first storage partition is changed to an empty state, thereby making the first storage partition usable as a storage partition for storing new data.

[0095] In some possible embodiments, during subsequent data storage, if the first storage partition is marked as invalid when rewriting data to the first storage partition, the first storage partition can be erased first, and then data can be written to the first storage partition.

[0096] Based on the above technical solution, the internal storage circuit can be refreshed in the form of storage partitions, thereby reducing the interruption of business or work caused by refreshing the entire circuit, and thus improving the overall responsiveness of the storage and computing system to business.

[0097] The fact that the current storage state of the second storage partition is empty or invalid allows it to be reserved for the first storage partition to be refreshed. This enables data in the first storage partition to be transferred within the storage circuitry, achieving refresh without the need for external storage resources, thus improving refresh efficiency. Furthermore, refreshing by storage partition ensures that while the first storage partition is being refreshed, other storage partitions remain in a responsive state. This allows for area refresh without interrupting business processing, improving the responsiveness of the in-memory computing system.

[0098] After weight data is written to the storage cells of the storage circuit, its storage accuracy may decrease with increased usage time or frequency; for example, storage accuracy may decrease due to charge leakage or external interference. The accumulation of this accuracy loss may lead to a decrease in the accuracy of the in-memory computation results, or even errors in the results, thus affecting the reliability of the in-memory computing system. In the above control method, a refresh condition is used to trigger a refresh of the storage circuit, improving the storage accuracy during use and thus enhancing the reliability of the in-memory computing system. Furthermore, by setting reserved partitions, the impact of storage circuit refresh on business operations can be reduced while improving storage accuracy, thereby improving the overall responsiveness of the in-memory computing system to business operations.

[0099] There is a deviation between the data actually stored in the storage unit and the target data to be stored. This deviation may include the initial deviation caused by the difficulty in achieving an ideal state of control during the initial write; it may also include the dynamic usage deviation caused by external interference or leakage during use.

[0100] The data stored in a storage partition refers to the target data stored in that storage partition, not the equivalent data (referred to as equivalent data). The equivalent data deviates from the target data. For example, the target data stored in the first storage partition is 10. In the initial storage state, the equivalent data might be 10.1. As usage time increases, the equivalent data might change to 9.8. Writing the data stored in the first storage partition to the second storage partition means writing the target data to the second storage partition. The equivalent data after writing might be 9.95, etc. The numerical examples in the above or subsequent embodiments are merely for ease of understanding and do not constitute any limitation on this application. The data used in actual use is also unrestricted and varies depending on the business requirements. Furthermore, the precision of the same target data during initial storage in different storage partitions may be the same or different; that is, the equivalent data may be the same or different.

[0101] The above refresh refers to the process of rewriting the data (e.g., weight data) stored in the storage circuit. This rewriting can be done to the same or different storage partitions. For example, data originally stored in the first storage partition may lose precision as usage time or frequency increases. Rewriting this data to the second storage partition restores its initial storage precision, which is higher than the precision after use in the first storage partition, effectively improving the reliability of the storage system. For instance, suppose the target weight data is 3. When initially written to the first storage partition, it has the initial storage precision, for example, the equivalent stored weight data is 3.05. As usage time or frequency increases, the storage precision decreases, for example, the equivalent stored weight data changes to 3.2. Rewriting the target weight data to the second storage partition restores its initial storage precision, for example, the equivalent stored weight data is 3.02. This improves the storage precision of the storage circuit.

[0102] In some possible embodiments, the current storage state of the second storage partition is empty, and determining the second storage partition may include a storage partition in the storage circuit where the currently stored data is empty (i.e., the storage state is empty).

[0103] In some possible embodiments, the current storage state of the second storage partition is invalid. Determining the second storage partition may include a storage partition in the storage circuit whose currently stored data is invalid (i.e., its storage state is invalid). When writing data stored in the first storage partition to the second storage partition, the invalid data stored therein can be erased.

[0104] In some possible embodiments, data written to the second storage partition does not need to be written back to the first storage partition, and the related computational tasks for this data can be migrated to the second storage partition for execution. This reduces the impact of the first storage partition on business operations, further increases the responsiveness of the in-memory computing system, and allows for the timely migration of computational tasks from the first storage partition to the second storage partition.

[0105] In some possible embodiments, data written to the second storage partition can be written back to the first storage partition. For example, data stored in the first storage partition can be written to the second storage partition, the data stored in the first storage partition can be erased, and then the data can be written back to the first storage partition. In this scenario, the second storage partition may include a pre-defined storage partition for refreshing, which can be called a backup storage partition. It is only used for data transfer and backup and will not participate in the related computational operations on the transferred data.

[0106] In some possible embodiments, the second storage partition can be a preset backup storage partition. Alternatively, in some possible embodiments, the second storage partition can be dynamically changing. For example, multiple storage partitions can be controlled to rotate and refresh, and during the rotation process, there is a dynamically changing second storage partition, that is, storage partitions with empty or invalid storage states are rotated accordingly. This rotational refresh method can improve refresh efficiency and has a greater advantage in terms of the overall business responsiveness of the storage computing system.

[0107] In some possible embodiments, by setting refresh conditions, the refresh of the storage circuit can be initiated in a timely manner, thereby improving the timeliness of the refresh of the storage circuit and improving the overall data storage accuracy of the storage circuit, thus improving the reliability of the storage system.

[0108] In some possible embodiments, the refresh conditions described above may be related to the precision of the storage circuit. For example, the refresh conditions may include: a first precision index exceeding a preset precision index range, wherein the first precision index includes the precision index of the storage circuit or the precision index of the first storage partition. When the first precision index includes the precision index of the storage circuit, the refresh can be initiated based on the precision of the storage circuit, and the refresh can be performed in a polling manner, eliminating the need to judge the refresh conditions for each storage partition, thus simplifying implementation. When the first precision index includes the precision index of the storage partition, the refresh of the corresponding storage partition can be initiated based on the precision of the storage partition, resulting in finer refresh control granularity. This allows for timely initiation of a refresh for a storage partition when its precision decreases, reducing precision degradation caused by premature or late refreshes.

[0109] Figure 4 is a flowchart illustrating another control method according to an exemplary embodiment of this application. In some possible embodiments, the control method 400 may further include, relative to the embodiment shown in Figure 3:

[0110] S410: Obtain the first precision index.

[0111] S420: When the first accuracy index exceeds the preset accuracy index range, it is determined that the refresh condition is met.

[0112] In some possible embodiments, the aforementioned first accuracy metric may be acquired in real time.

[0113] In some possible embodiments, the first precision index may be acquired periodically. For example, the first precision index is acquired periodically, and when the first precision index exceeds a preset precision index range, a refresh of the first storage partition of the storage circuit is initiated. The first storage partition may include any storage partition in the storage circuit, or may include the storage partition in the storage circuit with the longest interval since the last refresh, or may include the storage partition in the storage circuit with the lowest precision.

[0114] In some possible embodiments, the first precision indicator may be event-triggered, for example, triggered after the storage circuit or the first storage partition has continuously performed computational operations. Alternatively, it may be triggered based on the runtime of the storage circuit or the first storage partition, such as when the runtime of the storage circuit or the first storage partition reaches or exceeds a time threshold.

[0115] For accuracy testing, the overall accuracy of the storage circuit can be tested, or the accuracy can be tested according to the storage partition. Regardless of the testing method, the above partition refresh mechanism can be used for refreshing. This ensures that during the refresh of one storage partition, the data in other storage partitions is not affected, and other storage partitions can continue to support the operation of computing services. This allows the storage circuit to maintain its working or service state while being refreshed.

[0116] Furthermore, the precision-triggered refresh mechanism enables dynamic refreshing of the storage circuitry. This means that when the precision of the storage circuitry falls below a certain level, it can be refreshed promptly to raise the precision back up. This improves the flexibility and timeliness of the refresh, ensuring that the storage precision remains at a high level, further enhancing computational accuracy and thus improving the reliability of the in-memory computing system. Additionally, the precision detection mechanism based on storage partitions allows for dynamic refresh matching specific storage partitions, providing finer-grained control over the refresh of the storage circuitry.

[0117] The aforementioned first precision indicator refers to an indicator that reflects the computational or storage precision of the storage circuit or storage partition. This application does not limit the type of this indicator. For example, it may include usage time, number of uses, sampled values ​​of the computation results, or bit error rate, etc. Depending on the type of indicator, exceeding the preset precision indicator range may include being greater than or equal to the preset precision indicator threshold, or it may include being less than or equal to the preset precision indicator threshold.

[0118] In some possible embodiments, the first accuracy index described above can be obtained or determined by at least one of the following methods. Optionally, the factors used in the following methods can be used in combination:

[0119] Method 1: Determine the first precision index of the storage circuit based on its usage; or determine the first precision index of the first storage partition based on its usage.

[0120] In some possible embodiments, the usage of the storage circuitry may include the runtime (or duration) of the storage circuitry; or, the usage of the first storage partition may include the runtime (or duration) of the first storage partition.

[0121] The above runtime refers to the runtime accumulated by the storage circuit or storage partition before the refresh. In some possible embodiments, the storage circuit or storage partition can count the runtime after the refresh, and restart the storage circuit or storage partition corresponding to the runtime count after the data is rewritten.

[0122] In some possible embodiments, the usage of the above-mentioned storage circuit may include the number of times the storage circuit is used; or, the usage of the above-mentioned first storage partition may include the number of times the first storage partition is used.

[0123] For example, the above usage counts may include the usage of data stored in the storage circuit or the first storage partition, such as one or more of the following: data read counts or calculation counts.

[0124] The above usage count refers to the cumulative usage count of the storage circuit or storage partition before the refresh. In some possible embodiments, the storage circuit or storage partition can count the usage count after the refresh, and restart the storage circuit or storage partition corresponding to the usage count after the data is rewritten.

[0125] The above usage information, such as usage time or number of uses, can be used as the primary accuracy indicator. Alternatively, a correlation can be established between usage information such as usage time or number of uses and the accuracy value to obtain the corresponding accuracy value as the primary accuracy indicator.

[0126] For example, a relationship table can be established between the usage of a storage circuit or storage partition (e.g., the runtime or number of times the storage circuit or storage partition has been used) and the precision value of the storage circuit or storage partition. Based on the current usage of the storage circuit or storage partition, the corresponding precision value is determined by looking up this relationship table, serving as a primary precision indicator. For example, the relationship table can be determined through one or more methods such as experience, theoretical derivation, experimentation, or simulation.

[0127] For example, the relationship between the usage of storage circuits or storage partitions and accuracy values ​​can be modeled. By statistically analyzing the usage data of storage circuits or storage partitions and inputting the usage data into the model, the corresponding accuracy value can be obtained as the first accuracy indicator.

[0128] When using usage information such as usage time or number of uses as the primary accuracy indicator, a refresh condition can be determined if the usage time or number of uses is greater than or equal to a usage time threshold or a usage number threshold. When determining the accuracy value based on usage information such as usage time or number of uses, a refresh condition can be determined if the accuracy value is less than or equal to an accuracy threshold.

[0129] Method 2: Determine the first precision index of the storage circuit based on the first sampled value of the storage cell of the storage circuit; or determine the first precision index of the first storage partition based on the first sampled value of the storage cell of the first storage partition, wherein the first sampled value can be used to indicate the equivalent data stored in the storage cell.

[0130] In some possible embodiments, a reading method (e.g., sampling reading) can be used to obtain the representation value of the equivalent data stored in the current tested storage unit, and a first accuracy index can be determined based on the difference between the representation value and the target value of the target data.

[0131] Optionally, this difference can be used as a first precision indicator, and when the difference is greater than or equal to the difference threshold, it can be determined that the refresh condition is met.

[0132] Optionally, a first precision index can be determined based on this difference. For example, a relationship table can be established between this difference and the precision values ​​of the memory circuit or memory partition. The corresponding precision value is determined based on the current difference, serving as the first precision index. For instance, the relationship table can be determined through one or more methods such as experience, theoretical derivation, experimentation, or simulation. For example, by modeling the relationship between this difference and the precision value, statistically analyzing the difference data, and inputting the difference data into the model, the corresponding precision value can be obtained as the first precision index.

[0133] The above differences may be differences obtained by reading a storage cell of the storage circuit or the first storage partition; or, the average of differences obtained by reading all or part of the storage cells of the storage circuit or the first storage partition.

[0134] The above sampling and reading can be achieved using an ADC, for example.

[0135] Method 3: Determine the first precision index of the storage circuit based on the second sampled value of the storage cell group of the storage circuit; or determine the first precision index of the first storage partition based on the second sampled value of the storage cell group of the first storage partition, wherein the second sampled value can be used to indicate the calculation result of the storage cell group.

[0136] In some possible embodiments, when using a sampling circuit to obtain the calculation results of the memory cell group, the sampling precision of the sampling circuit can be set to be higher than that used in actual operation. For example, the ADC can be configured with additional redundant precision bits during the sampling process. The value of this redundant precision bit can reflect the magnitude of the calculation precision; for example, a larger value indicates a greater deviation in the calculation result and lower precision. A first precision index can be determined based on this redundant precision bit.

[0137] Optionally, the value corresponding to the redundant precision bit can be used as the first precision index. When the value is less than or equal to the threshold, it can be determined that the refresh condition is met.

[0138] Optionally, a first precision index can be determined based on the value corresponding to the redundant precision bit. For example, a relationship table can be established between this value and the precision value of the storage circuit or storage partition. The corresponding precision value is determined based on the currently sampled value, serving as the first precision index. For instance, the relationship table can be determined through one or more methods such as experience, theoretical derivation, experimentation, or simulation. For example, the relationship between this value and the precision value can be modeled, and the corresponding precision value can be obtained by statistically analyzing the values ​​corresponding to the redundant precision bits and inputting these values ​​into the model, serving as the first precision index.

[0139] Method 4: Determine the first precision index of the storage circuit or the first storage partition based on the bit error rate of the original codeword. The original codeword is used to generate data to be written to the storage circuit or the first storage partition.

[0140] In some possible embodiments, data stored in the storage circuit or the first storage partition can be read, or calculation results can be sensed. The read or sensed data can be verified, for example, through error correction codes. The lower the precision of the storage circuit or the first storage partition, the higher the bit error rate; therefore, the bit error rate can be used to determine a first precision index.

[0141] This application does not limit the type of error correction code. For example, error correction codes may include error correction codes (ECC), low-density parity-check codes (LDPC), and other error correction codes.

[0142] Optionally, the bit error rate can be used as the first precision indicator. When the bit error rate is greater than or equal to the bit error rate threshold, it can be determined that the refresh condition is met.

[0143] Optionally, a first precision metric can be determined based on the bit error rate (BER). For example, a relationship table can be established between the BER and the precision value of the memory circuit or memory partition. The corresponding precision value is determined based on the currently obtained BER, serving as the first precision metric. For instance, the relationship table can be determined through one or more methods such as experience, theoretical derivation, experimentation, or simulation. Alternatively, the relationship between the BER and precision value can be modeled, and the corresponding precision value can be obtained by statistically analyzing the BER and inputting it into the model, serving as the first precision metric.

[0144] Based on the above technical solutions, one or more methods can be used to determine whether the refresh conditions are met. Combining multiple methods can help improve the accuracy of the evaluation results.

[0145] In some possible embodiments, when the first accuracy index includes the accuracy index of the storage circuit, for example, any storage partition among multiple storage partitions can be determined as the first storage partition, or the storage partition with the lowest accuracy among multiple storage partitions can be determined as the first storage partition, or the storage partition with the longest time since the last refresh among multiple storage partitions can be determined as the first storage partition, or the storage partition located at a certain physical location among multiple storage partitions can be determined as the first storage partition.

[0146] In some possible embodiments, the state of the first storage partition after refresh control can be adjusted to empty or invalid. The first storage partition with an empty or invalid state can serve as a new backup storage partition, thereby increasing the refresh efficiency of the entire storage circuit. For example, FIG5 is a flowchart illustrating another control method according to an exemplary embodiment of this application. The aforementioned plurality of storage partitions may further include a third storage partition. As shown in FIG5, relative to the embodiment shown in FIG3, the control method 500 may further include the following steps:

[0147] S510: Write the data from the third storage partition to the first storage partition.

[0148] S520: Controls the storage status of the third storage partition to be empty or invalid.

[0149] At this point, the third storage partition can be used as a new backup storage partition.

[0150] In some possible embodiments, the third storage partition can be erased in a similar manner to the first storage partition, as described in the above embodiments, and will not be repeated here.

[0151] In some possible embodiments, before executing S510, it can be determined whether the third storage partition meets the refresh conditions. These refresh conditions include whether the precision index of the storage circuit or the precision index of the third storage partition exceeds a preset precision index range. The method for determining whether the third storage partition meets the refresh conditions can be referred to the relevant description in the above embodiments. When it is determined that the third storage partition meets the refresh conditions, step S510 is executed.

[0152] In some possible embodiments, when the accuracy index of the storage circuit or the accuracy index of the first storage partition exceeds a preset accuracy index range, refresh control of the entire storage circuit can be triggered, and multiple storage partitions begin to perform round-robin refresh based on a first order. This first order may include a preset order, or it may be determined based on the accuracy of multiple storage partitions, or it may be determined based on the time interval since the last refresh. For example, the lower the accuracy, the earlier the refresh order; similarly, the longer the time interval since the last refresh, the earlier the refresh order. Multiple methods can be combined to determine the refresh order. In this case, it is no longer necessary to determine whether the third storage partition meets the refresh conditions.

[0153] In some possible embodiments, data written to the first storage partition does not need to be written back to the third storage partition, and the related computational operations of this data can be migrated to the first storage partition for execution.

[0154] In some possible embodiments, the second storage partition can continue to participate in the round-robin refresh. For example, Figure 6 is a flowchart illustrating another control method according to an exemplary embodiment of this application. The aforementioned plurality of storage partitions may also include a fourth storage partition. As shown in Figure 6, relative to the embodiment shown in Figure 3, the control method 600 may further include the following steps:

[0155] S610: Write the data stored in the second storage partition to the fourth storage partition.

[0156] S620: Controls the storage status of the second storage partition to be empty or invalid.

[0157] In some possible embodiments, the second storage partition can be erased in a similar manner to the first storage partition, as described in the above embodiments, and will not be repeated here.

[0158] In some possible embodiments, before executing S610, it can be determined whether the second storage partition meets the refresh conditions. These refresh conditions include whether the precision index of the storage circuit or the precision index of the second storage partition exceeds a preset precision index range. If it is determined that the second storage partition meets the refresh conditions, the above S610 is executed.

[0159] In some possible embodiments, when the accuracy index of the storage circuit or the accuracy index of the first storage partition exceeds a preset accuracy index range, refresh control of the entire storage circuit can be triggered, and multiple storage partitions begin to perform round-robin refresh based on a first order. This first order may include a preset order, or it may be determined based on the accuracy of multiple storage partitions, or it may be determined based on the time interval since the last refresh. For example, the lower the accuracy, the earlier the refresh order; similarly, the longer the time interval since the last refresh, the earlier the refresh order. A combination of these methods can be used to determine the refresh order. In this case, it is no longer necessary to determine whether the second storage partition meets the refresh conditions.

[0160] The process of writing data stored in a storage partition (e.g., the first storage partition) to other storage partitions can be understood as refreshing control of that storage partition (e.g., the first storage partition). In some possible embodiments, the state of the refresh-controlled storage partition can be adjusted to be empty or invalid. For example, the state of the storage partition can be controlled to be empty by erasing the data stored in the storage partition. Alternatively, the state of the storage partition can be adjusted to be invalid by using its identifier (or identifier field). Data stored in a storage partition with an invalid identifier (or identifier field) is unavailable or invalid, and this invalid data can be erased at any time before the data is written.

[0161] This application does not limit the number of storage partitions. When there are other storage partitions among the multiple storage partitions, any of the refresh mechanisms described in the above embodiments can be used to control the refresh of the remaining storage partitions.

[0162] In some possible embodiments, refresh control of multiple storage partitions of the storage circuit is performed in a round-robin fashion. This simplifies refresh control, improves refresh fairness, prevents some storage partitions from missing refresh resources, and makes the refreshed storage partitions predictable, facilitating the control of computing operations.

[0163] In some possible embodiments, the number of storage partitions in the rotation can be flexibly adjusted according to business needs, increasing the flexibility of refresh control and adaptability to business scenarios. For two adjacent storage partitions in the refresh order of multiple storage partitions, the interval between their rotation refreshes can be called the rotation interval. From the time data is written from one storage partition to another until the rotation interval expires, refresh control for the next storage partition can be triggered, i.e., the operation of writing data from the next storage partition to other storage partitions is initiated. Based on this rotation mechanism, the accuracy indicators of the storage partitions can be relatively evenly distributed within a preset accuracy indicator range. In some possible embodiments, the refresh condition is met after the rotation interval of a storage partition expires. That is, the refresh condition is related to the rotation interval, and the storage partition to be refreshed can be determined based on the rotation order and the rotation interval. Taking the first storage partition as an example, when the rotation order reaches the first storage partition and the rotation interval expires, the refresh condition is met, and refresh control for the first storage partition is initiated.

[0164] In some possible implementations, the rotation interval between two adjacent storage partitions can be the same or different. A similar rotation interval is more conducive to simplifying and ensuring fairness in refresh control. Optionally, the rotation interval can be related to the precision of the storage partition.

[0165] In some possible embodiments, the refresh control of multiple storage partitions of the storage circuit is performed periodically, and the refresh control start times of the multiple storage partitions are different. For example, after a refresh cycle has elapsed since the last refresh control of the first storage partition, the first storage partition is refreshed again, and the same applies to other storage partitions. The refresh cycles of the multiple storage partitions can be the same or different. In addition, there is a rotation interval between the refresh control of different storage partitions, so that the refresh control start times of the multiple storage partitions are different.

[0166] In some possible embodiments, the refresh condition is met when the refresh cycle has elapsed since the last refresh control of the first storage partition.

[0167] In some possible embodiments, the rotation interval or refresh cycle can be determined or dynamically adjusted in conjunction with the accuracy. The time for initiating refresh control of the storage partition can be determined by a preset model based on a first accuracy index.

[0168] In some possible embodiments, the refresh cycle of the storage partition has not expired since the last refresh control, but the precision index of the storage partition has exceeded the preset precision index range. At this time, the next refresh control of the storage partition can be started to reduce the refresh cycle of the storage partition.

[0169] In some possible embodiments, the rotation interval after the refresh control of the storage partition has not expired, but the accuracy index of the storage partition has exceeded the preset accuracy index range. At this time, the refresh control of the storage partition can be started to reduce the rotation interval.

[0170] In some possible embodiments, the lifecycle can correspond to the time from the start of data writing until the accuracy index exceeds a preset accuracy index. For example, the preset accuracy index can correspond to the accuracy index of data becoming erroneous data, the data storage noise reaching the maximum tolerable noise, or the minimum accuracy requirement of the design. This application embodiment does not limit this. The lifecycle of data stored in a storage circuit or storage partition can be described as the lifecycle of the storage circuit or storage partition.

[0171] In some possible embodiments, the aforementioned rotation interval and refresh cycle can be determined based on the number of storage partitions and their expected lifespan. For example, by setting the rotation interval and / or refresh cycle, the accuracy indicators of the storage partitions being rotated and refreshed can be evenly distributed within a preset accuracy indicator range.

[0172] In some possible embodiments, the preset accuracy range of the storage circuit and the preset accuracy range of the storage partition may be the same or different.

[0173] The following describes the rotation refresh method with reference to the attached diagram:

[0174] Figure 7 is a schematic diagram of a rotating refresh control method according to an exemplary embodiment of this application.

[0175] Referring to Figure 7, the rotation refresh of 5 storage partitions is described as an example. The process is similar for more or fewer storage partitions. These 5 storage partitions are labeled Storage Partition 1, Storage Partition 2, Storage Partition 3, Storage Partition 4, and Storage Partition 5. Assume the refresh order is from Storage Partition 1 to Storage Partition 5. Initially, storage partitions 1 to 4 are used to store data, and storage partition 5 is either empty or invalid. When the rotation interval or refresh cycle of storage partition 1 expires, refresh control of storage partition 1 is triggered, writing the data stored in storage partition 1 to storage partition 5, and controlling the storage state of storage partition 1 to be empty or invalid. Similarly, when the rotation interval or refresh cycle of storage partition 2 expires, it triggers refresh control for storage partition 2, writing the data stored in storage partition 2 to storage partition 1, and controlling the storage status of storage partition 2 to be empty or invalid. And so on, when the rotation interval or refresh cycle of storage partition 5 expires, it triggers refresh control for storage partition 5, writing the data stored in storage partition 5 to storage partition 4, and controlling the storage status of storage partition 5 to be empty or invalid. This process repeats, achieving rotational refresh of storage partitions 1 through 5.

[0176] Figure 8 is a schematic diagram of the precision of multiple storage partitions according to an exemplary embodiment of this application.

[0177] Referring to Figure 8, the accuracy of the storage circuit can be characterized by the noise of the storage circuit. The greater the noise, the lower the accuracy of the storage circuit, and the smaller the noise, the higher the accuracy of the storage circuit.

[0178] In some possible embodiments, the accuracy of the storage circuit can also be characterized by the signal-to-noise ratio (SNR) of the storage circuit's output data, where SNR = P(signal) / P(noise), and signal indicates the actual output data under unbiased conditions, noise indicates the difference between the actual output and the ideal output, and P indicates the power of the signal output. A larger SNR indicates higher calculation accuracy, and a smaller SNR indicates lower calculation accuracy.

[0179] Figure 8 shows examples of noise corresponding to each storage partition in Figure 7 when storage partition 1 is undergoing refresh control. As can be seen from Figure 8, multiple storage partitions exhibit different noise levels.

[0180] Referring to Figures 7 and 8, when refreshing storage partition 1, the data stored in storage partition 1 has the longest usage time and the highest noise level. When the data stored in storage partition 1 is written to storage partition 5, storage partition 5 begins operation, and its noise level is the lowest among all storage partitions. Before erasing the data in storage partition 1, its storage state is invalid; after erasing the data, its storage state is empty.

[0181] As time continues, the noise in storage partitions 2 through 5 will gradually increase with data usage until the rotation interval of storage partition 1 expires, at which point the data stored in storage partition 1 is written to storage partition 5, at which point the noise in storage partition 5 is minimal. Before erasing the data in storage partition 5, the state of storage partition 5 is invalid; after erasing the data in storage partition 5, the state of storage partition 5 is empty.

[0182] Based on the above technical solution, a round-robin refresh mechanism for multiple storage partitions in the storage circuit can be implemented, minimizing the noise of data written to storage partitions that are currently empty or invalid. This ensures that the overall accuracy of the storage circuit meets the preset accuracy target and remains stable. Furthermore, by using a round-robin refresh mechanism for multiple storage partitions, data is written to other idle (empty or invalid) storage partitions in the storage circuit during the refresh process, preventing the corresponding computational operations from being affected or interrupted, thereby improving the utilization rate of the storage circuit.

[0183] In some possible embodiments, the capacity of a storage partition is used to characterize its storage capability. For example, it can be replaced by parameters such as storage space, storage size, storage limit, storage scale, storage range, or storage quota. The storage partitions can have the same capacity, which can reduce the possibility of insufficient capacity or redundant waste of storage capacity in the partitions where data is to be written during refresh control. In other possible embodiments, the capacities of the storage partitions can also be different.

[0184] Figure 9 is a flowchart illustrating another control method according to an exemplary embodiment of this application.

[0185] Referring to Figure 9, the control method 900 is described using the overall storage circuit or the first storage partition as an example. The method 900 may include the following steps:

[0186] S910: Obtain a second precision index, which includes a precision index of the storage circuit or a precision index of the first storage partition.

[0187] S920: Based on the second precision index, control the computational load of the storage circuit or the first storage partition.

[0188] In some possible embodiments, the second precision index may reuse the first precision index.

[0189] In some possible embodiments, the second precision index may also be acquired separately, for example, at a different time than the first precision index.

[0190] In some possible embodiments, the computational load may include at least one of the following: the degree of parallelism (or computational parallelism) of a single computation of the storage circuit or the first storage partition, and the operating parameters (e.g., operating voltage) of the storage circuit or the first storage partition. In this way, when the storage circuit or storage partition has high precision, higher precision can be better utilized; for example, computation speed can be increased by increasing parallelism, or computational power consumption can be reduced by decreasing the operating voltage. Conversely, when the precision of the storage circuit or storage partition is low, the computational load can be adjusted to improve computational accuracy.

[0191] In some possible embodiments, when the second precision index includes the precision index of the first storage partition, the computational load of the first storage partition, such as parallelism or operating parameters, can be determined based on the precision index of the first storage partition. When the second precision index includes the precision index of the storage circuit, the computational load of the storage circuit, such as parallelism or operating parameters, can be determined based on the precision index of the storage circuit.

[0192] In some possible embodiments, the precision index of the above-described storage circuit can be determined based on the precision index of the entire storage circuit, wherein the precision index of the entire storage circuit can be the average of the precision indices of multiple storage partitions, such as an arithmetic mean or a weighted average. Alternatively, the precision index of the above-described storage circuit can be determined based on the lowest precision index among the multiple storage partitions included in the storage circuit.

[0193] In some possible embodiments, the computational load, such as parallelism and operating parameters, of different storage partitions in the above-described storage circuit can be the same or different.

[0194] In some possible embodiments, taking a storage circuit as an example, when the second precision index is far from the upper or lower limit of the preset precision index range, the parallelism of the storage circuit can be adaptively increased, thereby improving the calculation speed of the storage circuit. When the second precision index is close to the upper or lower limit of the preset precision index range, the parallelism of the storage circuit can be adaptively reduced, thereby meeting the requirements for calculation precision.

[0195] In some possible embodiments, a relationship table can be established between the second precision index and the computational load of the storage circuitry or the first storage partition, such as parallelism or operating parameters. The corresponding computational load is determined based on the currently obtained second precision index. For example, the relationship table can be determined through one or more methods such as experience, theoretical derivation, experimentation, or simulation.

[0196] In some possible embodiments, the parallelism can be obtained by modeling the relationship between the second precision index and the computational load of the storage circuit or the first storage partition, such as parallelism or operating voltage, by inputting the second precision index into the model.

[0197] This application also provides an apparatus for implementing any of the above methods. For example, a control device is provided, which includes a unit (or means) for implementing any of the above control methods.

[0198] Figure 10 is a schematic diagram of a control device according to an exemplary embodiment of the present application.

[0199] The control device 1000 can be used to control the refresh of a storage circuit, which includes multiple storage partitions. Referring to Figure 10, the control device 1000 includes: a determining unit 1010, an operating unit 1020, and a control unit 1030. The determining unit 1010 is used to determine a first storage partition and a second storage partition of the storage circuit when refresh conditions are met. The first storage partition is the storage partition to be refreshed among the multiple storage partitions, and the second storage partition is the storage partition whose current storage state is empty or invalid among the multiple storage partitions. The operating unit 1020 is used to write the data stored in the first storage partition to the second storage partition. The control unit 1030 is used to control the storage state of the first storage partition to be empty or invalid.

[0200] The description of refresh conditions and refresh control can be found in the above embodiments, and will not be repeated here.

[0201] In some possible embodiments, the control device 1000 further includes: an acquisition unit 1040 for acquiring a first accuracy index; the determination unit 1010 is further configured to: determine that the refresh condition is met when the first accuracy index exceeds a preset accuracy index range.

[0202] In some possible embodiments, the plurality of storage partitions may further include a third storage partition, and the operation unit 1020 is further configured to: write the data stored in the third storage partition to the first storage partition; the control unit 1030 is further configured to: control the storage state of the third storage partition to be empty or invalid.

[0203] In some possible embodiments, the plurality of storage partitions may further include a fourth storage partition, and the operation unit 1020 is further configured to: write the data stored in the second storage partition to the fourth storage partition; the control unit 1030 is further configured to: control the storage state of the second storage partition to be empty or invalid.

[0204] In some possible embodiments, after the control unit 1030 controls the storage state of the first storage partition to be empty, the operation unit 1020 is further configured to: rewrite the data stored in the second storage partition into the first storage partition.

[0205] In some possible embodiments, the acquisition unit 1040 is further configured to: acquire a second precision index, the second precision index including the precision index of the in-memory computing circuit or the precision index of the first storage partition; the control unit 1030 is further configured to: control the computing load of the in-memory computing circuit or the first storage partition based on the second precision index.

[0206] It should be understood that the above division of units is only a logical functional division. In actual implementation, all or part of them can be integrated into a single physical entity, or they can be physically separated. Furthermore, the above units can be implemented in the form of a processor calling software; for example, a control device may include a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above control methods. The memory can be internal to the control device or external to it. Alternatively, the above units can be implemented in the form of hardware circuits. The functions of some or all units can be achieved through the design of the hardware circuits, which can be understood as one or more processing circuits. For example, in some embodiments, the hardware circuit may include an application-specific integrated circuit (ASIC), which implements the functions of some or all of the above units through the design of the logical relationships between the devices within the circuit. Furthermore, in some embodiments, the hardware circuit can be implemented using a programmable logic device (PLD) circuit, which may include a large number of logic devices. The logical relationships between the logic devices are configured through a configuration file, thereby achieving the functions of some or all of the above units. The above control devices can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0207] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, including, for example, a central processing unit (CPU), a microcontroller unit (MCU), a graphics processing unit (GPU), or a digital signal processor (DSP). Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), or a deep learning processing unit (DPU).

[0208] In some possible embodiments, the units in the above control device may be integrated in whole or in part, or may be implemented independently. In some embodiments, these units are integrated together and implemented in the form of a system on chip (SOC).

[0209] This application also provides a control device, which may be located within or include the above-described control circuit. The control device may be located within the control circuit 120 / 220 shown in FIG. 1 or FIG. 2, or may be independent of the control circuit 120 / 220. This control device can be used to execute any of the above-described control methods.

[0210] This application also provides a control device, as shown in FIG11. FIG11 is a schematic diagram of a control device according to an exemplary embodiment of this application. As shown in FIG11, the control device 1100 includes: at least one processing circuit 1110 and an interface circuit 1120, the interface circuit 1120 being used for signal connection with a storage circuit, and the at least one processing circuit 1110 being used for executing any of the control methods provided in the above embodiments.

[0211] This application also provides a memory computing system, which includes: a memory computing circuit including multiple memory partitions; and a control device for executing any of the control methods proposed in this application to refresh the multiple memory partitions.

[0212] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0213] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0214] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0215] This application also provides an electronic device, as shown in FIG12. FIG12 is a schematic diagram of an electronic device according to an exemplary embodiment of this application. As shown in FIG12, the electronic device 1200 may include any of the above-mentioned in-memory computing systems 1210 for processing data of the electronic device. The electronic device may also include an input / output device 1220 for receiving user input or outputting processing results. This application does not limit the input type and output type. For example, the input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may also include a processor 1230, which may process the data provided to the in-memory computing system 1210 or process the output data of the in-memory computing system 1210. The output of the input / output device 1220 may be based on the output of the processor 1230 or the output of the in-memory computing system 1210.

[0216] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0217] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A control method, characterized in that, The control method is used to control the refresh of a storage circuit, the storage circuit including multiple storage partitions, and the control method includes: When the refresh conditions are met, the first storage partition and the second storage partition of the storage circuit are determined. The first storage partition is the storage partition to be refreshed among the plurality of storage partitions, and the second storage partition is the storage partition whose current storage state is empty or invalid among the plurality of storage partitions. Write the data stored in the first storage partition to the second storage partition; Control the storage status of the first storage partition to be empty or invalid.

2. The control method according to claim 1, characterized in that, The refresh condition includes a first precision index exceeding a preset precision index range, wherein the first precision index includes the precision index of the storage circuit or the precision index of the first storage partition.

3. The control method according to claim 2, characterized in that, The control method further includes: Obtain the first accuracy index; When the first accuracy index exceeds the preset accuracy index range, it is determined that the refresh condition is met.

4. The control method according to claim 3, characterized in that, Obtaining the first accuracy index includes: determining the first accuracy index based on one or more of the following factors: The usage status of the storage circuit or the first storage partition; For the storage circuit or the storage cell of the first storage partition, a first sampled value or a second sampled value of the storage cell group, the first sampled value is used to indicate the equivalent data stored in the storage cell, and the second sampled value is used to indicate the calculation result of the storage cell group; The bit error rate of the original codeword, which is used to generate data written to the storage circuit or the first storage partition.

5. The control method according to any one of claims 1 to 4, characterized in that, The plurality of storage partitions further includes a third storage partition, and the control method further includes: Write the data stored in the third storage partition to the first storage partition; Control the storage status of the third storage partition to be empty or invalid.

6. The control method according to any one of claims 1 to 5, characterized in that, The plurality of storage partitions further includes a fourth storage partition, and the control method further includes: Write the data stored in the second storage partition to the fourth storage partition; Control the storage status of the second storage partition to be empty or invalid.

7. The control method according to any one of claims 1 to 4, characterized in that, The control method further includes: The data stored in the second storage partition is rewritten to the first storage partition.

8. The control method according to any one of claims 1 to 7, characterized in that, The refresh control of the multiple storage partitions is performed in rotation.

9. The control method according to any one of claims 1 to 8, characterized in that, The refresh control of the multiple storage partitions is performed periodically, and the refresh control start time of the multiple storage partitions is different.

10. The control method according to any one of claims 1 to 9, characterized in that, The multiple storage partitions have the same capacity.

11. The control method according to any one of claims 1 to 10, characterized in that, The control method further includes: Obtain a second precision index, which includes the precision index of the storage circuit or the precision index of the first storage partition; Based on the second accuracy index, the computational load of the storage circuit or the first storage partition is controlled.

12. A control device, characterized in that, include: Interface circuitry used for communication with storage circuitry; At least one processing circuit is used to perform the control method as described in any one of claims 1 to 11.

13. An in-memory computing system, characterized in that, include: The storage circuit includes multiple storage partitions; A control device is configured to perform the control method as described in any one of claims 1 to 11 to refresh the plurality of storage partitions.

14. An electronic device, characterized in that, Including the in-memory computing system as described in claim 13.

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