LED display device

Abstract

The present application discloses an LED display device. The LED display device comprises a light-emitting epitaxial layer, a first insulating layer, a plurality of pixel electrodes, a common electrode, and a plurality of first via holes. The light-emitting epitaxial layer comprises a first semiconductor layer, an active layer, and a second semiconductor layer which are stacked; the pixel electrodes are disposed on one side of the first semiconductor layer and electrically connected to the first semiconductor layer; and the first insulating layer covers the pixel electrodes and the first semiconductor layer. The first via holes pass through the first insulating layer, the first semiconductor layer, and the active layer, and expose the second semiconductor layer; the common electrode comprises a plurality of lead-out portions and an interconnection portion; the lead-out portions are provided in the first via holes and are in electrical contact with the second semiconductor layer; the lead-out portions are electrically isolated from the first semiconductor layer and the active layer; and the interconnection portion is located on one side of the first insulating layer and conductively connects the plurality of lead-out portions. In this way, the present application can reduce the wiring difficulty of an LED display device, and reduce the fabrication difficulty of the LED display device, so as to improve the yield rate.

Description

LED display devices

[0001] This application claims priority to Chinese Patent Application No. 2024119200395, entitled "LED Display Device", filed on December 24, 2024, the entire contents of which are incorporated herein by reference.

[0002] [Technical Field]

[0003] This application relates to the field of semiconductor light-emitting diode technology, and in particular to LED display devices.

[0004] [Background Technology]

[0005] LED, short for Light Emitting Diode, is a semiconductor device that converts electrical energy into visible light. It is a widely used lighting source in modern applications such as indicator lighting, displays, decoration, backlighting, general lighting, and urban nightscapes. The main light-emitting structure in an LED display device is the LED chip, which contains a matrix-like, high-density integrated array of LED display pixels.

[0006] Currently, the manufacturing process of LED display devices typically requires metal wiring to connect the LED display pixels in order to achieve power control. However, since LED light-emitting chips are usually small in size, it is difficult to perform metal wiring on the LED display pixels. Moreover, a large number of etching and embedding wires are required during the wiring process, making LED display devices very susceptible to damage. This results in high manufacturing difficulty and low yield of LED display devices.

[0007] [Summary of the Invention]

[0008] The embodiments of this application provide LED display devices that can reduce the difficulty of wiring processes and reduce etching damage to LED display devices, thereby reducing the manufacturing difficulty of LED display devices and improving the yield of LED display devices.

[0009] To address the aforementioned technical problems, this application provides an LED display device comprising a display substrate. The display substrate includes a light-emitting epitaxial layer, a first insulating layer, multiple pixel electrodes, and a common electrode. The light-emitting epitaxial layer comprises a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked along a predetermined stacking direction. The multiple pixel electrodes are arranged in an array on the side of the first semiconductor layer away from the active layer and are electrically connected to the first semiconductor layer. The first insulating layer covers the multiple pixel electrodes and the first semiconductor layer from the side away from the first semiconductor layer. The display substrate has multiple first vias spaced apart, each first via penetrating the first insulating layer, the first semiconductor layer, and the active layer and exposing the second semiconductor layer. The common electrode includes multiple leads, each lead disposed in a corresponding first via and electrically contacting the second semiconductor layer. Each lead is further electrically isolated from the first semiconductor layer and the active layer within the first via. The common electrode also includes interconnects located on the side of the first insulating layer away from the first semiconductor layer and electrically connected to the multiple leads.

[0010] The beneficial effects of this application are as follows: This application etches the light-emitting epitaxial layer to form multiple first vias to expose the second semiconductor layer. The lead-out portion of the common electrode is located in the first via and electrically contacts the second semiconductor layer. The interconnect portion is disposed on the side of the first insulating layer away from the first semiconductor layer to electrically connect the lead-out portion, thereby transmitting current to the second semiconductor layer through the lead-out portion. This arrangement allows the interconnect portion to be etched into the light-emitting epitaxial layer without needing to be etched into it. Only the light-emitting epitaxial layer needs to be etched to form multiple first vias, so that the lead-out portion of the common electrode is electrically contacted in the corresponding first via, and the interconnect portion is then electrically connected to all the lead-out portions. This achieves electrical connection between the common electrode and the second semiconductor layer while reducing etching damage to the light-emitting epitaxial layer. Moreover, placing the interconnect portion on the side of the first insulating layer away from the first semiconductor layer facilitates the wiring arrangement of the interconnect portion and reduces the possibility of short circuits caused by electrical contact between the interconnect portion and the pixel electrode and the first semiconductor layer during the fabrication process. This improves the safety of the LED display device and reduces the difficulty of the LED display device fabrication process, thereby increasing the yield of the LED display device.

[0011] [Attached Image Description]

[0012] Figure 1 is a structural schematic diagram of an embodiment of an LED display device;

[0013] Figure 2 is a structural schematic diagram of the LED display device embodiment shown in Figure 1 from another perspective;

[0014] Figure 3 is a structural schematic diagram of another embodiment of the LED display device shown in Figure 1 from another perspective.

[0015]

Detailed Implementation Methods

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0017] The following embodiments of the LED display device in this application provide an exemplary description of the LED display device.

[0018] LED display device 1 refers to a device that can form multiple LED display pixels 101 inside to generate light, and the generated light can be emitted from one side of the LED display device 1 to illuminate or display various information such as text and images. For example, LED display device 1 can be an AR glasses chip, a projection display chip, an LED display chip, an LED digital vehicle light chip, or a digital light strip chip. In some embodiments, LED display device 1 can also be a Micro-LED display device with a high-density array integration at the micrometer level.

[0019] In some embodiments, as shown in FIG1, the LED display device 1 may include a display substrate 100. The display substrate 100 is a component in the LED display device 1 that can convert current into light energy. The display substrate 100 can define and provide a plurality of display pixels 101, which can realize the display and light emission function under the action of driving current.

[0020] In some embodiments, as shown in FIG1, the LED display device 1 may further include a driving substrate 200, the display substrate 100 is connected to the driving substrate 200, and the driving substrate 200 is used to provide driving current to the display substrate 100 so that the display substrate 100 can realize display light emission.

[0021] In some embodiments, as shown in FIG1, the display substrate 100 may include a light-emitting epitaxial layer 110, a first insulating layer 120, a plurality of pixel electrodes 130, and a common electrode 140. The light-emitting epitaxial layer 110 is used to emit light through electron-hole recombination and defines a plurality of display pixels 101. The plurality of pixel electrodes 130 and the common electrode 140 may serve as the P-electrode and N-electrode of the light-emitting epitaxial layer 110, respectively, thereby transmitting driving current to the plurality of display pixels 101 in the light-emitting epitaxial layer 110.

[0022] As shown in Figure 1, the light-emitting epitaxial layer 110 may include a first semiconductor layer 111, an active layer 112, and a second semiconductor layer 113 sequentially stacked along a predetermined stacking direction. For example, the stacking direction may be as shown by arrow A in Figure 1.

[0023] Specifically, the first semiconductor layer 111 and the second semiconductor layer 113 can be respectively a P-type semiconductor layer and an N-type semiconductor layer. The active layer 112 can be a multilayer quantum well light-emitting layer. The first semiconductor layer 111 and the second semiconductor layer 113 are located on both sides of the active layer 112 and are in contact with the active layer 112. The active layer 112 can form a NiP structure together with the first semiconductor layer 111 and the second semiconductor layer 113 on both sides, thereby enabling electron and hole recombination to emit light and form one or more display pixels 101.

[0024] As an example, the first semiconductor layer 111 and the second semiconductor layer 113 may be formed by doping with semiconductor materials such as AlN, AlGaN, GaN, InGaN, AlInGaN, GaAs, GaP, GaInN, GaAsP, AlGaAs, and AlGaInP.

[0025] As shown in Figure 1, a plurality of pixel electrodes 130 can be arranged in an array on the side of the first semiconductor layer 111 opposite to the active layer 112 and are electrically connected to the first semiconductor layer 111 respectively. The plurality of pixel electrodes 130 can serve as P electrodes to provide driving current to the first semiconductor layer 111. The array arrangement of the plurality of pixel electrodes 130 can be set according to the array arrangement of the display pixels 101 required by the LED display device 1, so that when the plurality of pixel electrodes 130 transmit driving current to the light-emitting epitaxial layer 110, the light-emitting epitaxial layer 110 defines a plurality of display pixels 101 arranged in an array.

[0026] As an example, the pixel electrode 130 may be formed of a conductive material such as Al, Ag, Cr, Ti, Ni, Au or ITO metal.

[0027] The first insulating layer 120 covers the multiple pixel electrodes 130 and the first semiconductor layer 111 from the side of the multiple pixel electrodes 130 away from the first semiconductor layer 111. The first insulating layer 120 can electrically isolate the multiple pixel electrodes 130 and the first semiconductor layer 111 from the side of the multiple pixel electrodes 130 away from the first semiconductor layer 111, thereby making it less likely for leakage or short circuits to occur inside the display substrate 100.

[0028] As shown in Figure 1, the display substrate 100 may have a plurality of first vias 102 spaced apart. Each first via 102 penetrates the first insulating layer 120, the first semiconductor layer 111, and the active layer 112, and exposes the second semiconductor layer 113. The common electrode 140 may include a plurality of leads 141, each lead 141 being disposed in a corresponding first via 102 and electrically contacting the second semiconductor layer 113. Each lead 141 is further electrically isolated from the first semiconductor layer 111 and the active layer 112 within the first via 102. The common electrode 140 may also include interconnects 142, which are located on the side of the first insulating layer 120 opposite to the first semiconductor layer 111 and electrically connect the plurality of leads 141. As an example, the common electrode 140 may also be formed of conductive materials such as Al, Ag, Cr, Ti, Ni, Au, or ITO metal.

[0029] In this design, the interconnect portion 142 of the common electrode 140 connects to multiple leads 141 on the side of the first insulating layer 120 away from the first semiconductor layer 111, and the interconnect portion 142 of the common electrode 140 transmits driving current to the multiple leads 141. The leads 141 of the common electrode 140 are electrically in contact with the second semiconductor layer 113 in the corresponding first via 102, providing driving current to the second semiconductor layer 113. The driving current can diffuse laterally in the second semiconductor layer 113 to reach the position corresponding to the display pixel 101, thereby enabling the common electrode 140 to act as the N-electrode of the light-emitting epitaxial layer 110 to power the display pixel 101. Moreover, each lead 141 is electrically isolated from the first semiconductor layer 111 and the active layer 112 in the first via 102, thereby reducing the occurrence of short circuit leakage in the display substrate 100.

[0030] This configuration allows the interconnect portion 142 to enter the light-emitting epitaxial layer 110 without etching. Instead, it only requires etching the light-emitting epitaxial layer 110 to form the first via 102. This allows the lead-out portion 141 of the common electrode 140 to electrically contact the second semiconductor layer 113 in the corresponding first via 102. The interconnect portion 142 then electrically connects all the leads 141 to transmit driving current to the second semiconductor layer 113 through the leads 141. This reduces etching damage to the light-emitting epitaxial layer 110 while achieving electrical connection between the common electrode 140 and the second semiconductor layer 113. Furthermore, by placing the interconnect portion 142 on the side of the first insulating layer 120 away from the first semiconductor layer 111, it is convenient to configure the interconnect portion 142 for wiring. It also reduces the possibility of short circuits caused by electrical connection between the interconnect portion 142 and the pixel electrode 130 and the first semiconductor layer 111 during the manufacturing process. This can improve the safety of the LED display device 1 and reduce the difficulty of the manufacturing process of the LED display device 1, thereby improving the yield of the LED display device 1.

[0031] In some embodiments, the arrangement density of two adjacent leads 141 is less than the arrangement density of the pixel electrodes 130.

[0032] The arrangement density is a measure of the number of targets within a specific unit area. The arrangement density of the lead-out portion 141 can be obtained by dividing the total number of lead-out portions 141 by the total area of ​​the light-emitting epitaxial layer 110, and the arrangement density of the pixel electrode 130 can be obtained by dividing the total number of pixel electrodes 130 by the total area of ​​the light-emitting epitaxial layer 110. The total area of ​​the light-emitting epitaxial layer 110 is the projected area of ​​the light-emitting epitaxial layer 110 when viewed along the stacking direction A.

[0033] Specifically, if the arrangement density of two adjacent leads 141 is less than the arrangement density of the pixel electrode 130, it means that the arrangement density of the adjacent pixel electrode 130 is greater than the arrangement density of the two adjacent leads 141. This means that within the area of ​​the two adjacent leads 141, there are more pixel electrodes 130 and fewer leads 141, resulting in a higher arrangement density of pixel electrodes 130 and a lower arrangement density of leads 141 than that of pixel electrodes 130.

[0034] If the arrangement density of two adjacent leads 141 is set to be greater than or equal to the arrangement density of the pixel electrode 130, it means that the arrangement density of the first via 102 of the lead 141 is also greater than or equal to the arrangement density of the pixel electrode 130. This further indicates that the number of first vias 102 is too large, which will increase the etching damage of the light-emitting epitaxial layer 110 and increase the difficulty of wiring the interconnect 142 to connect each lead 141, thereby increasing the wiring difficulty of the common electrode 140.

[0035] Therefore, by setting the arrangement density of two adjacent leads 141 to be less than the arrangement density of the pixel electrode 130, the number of first vias 102 can be reduced, thereby reducing the etching damage of the light-emitting epitaxial layer 110. It can also reduce the difficulty of wiring the interconnect 142 to connect each lead 141, thereby reducing the wiring difficulty of the common electrode 140 and reducing the fabrication difficulty of the LED display device 1.

[0036] In some embodiments, as shown in Figures 1 and 2, the display substrate 100 may have a reference cross section parallel to the stacking direction A. When projected orthogonally onto the reference cross section, at least two pixel electrodes 130 may be disposed in the spacer region between two adjacent leads 141. For example, the number of pixel electrodes 130 in the spacer region between two adjacent leads 141 may be two, three, four, or five, etc.

[0037] For example, in some embodiments, the number of pixel electrodes 130 in the spacer region between two adjacent leads 141 is two. A reference cross-section of the display substrate 100 can be shown as plane BB in FIG2. FIG1 shows the projection structure of the leads 141 and pixel electrodes 130 projected onto the reference cross-section BB. As shown in FIG1 and FIG2, the two pixel electrodes 130 in the spacer region between two adjacent leads 141 define two display pixels 101 in the light-emitting epitaxial layer 110. The two adjacent leads 141 transmit driving current to the second semiconductor layer 113, and the driving current diffuses in the second semiconductor layer 113 and is transmitted to the positions corresponding to the two display pixels 101.

[0038] In other embodiments, the lead-out portion 141 and the interconnect portion 142 can be arranged as shown in FIG3. A reference cross-section of the display substrate 100 can be shown as surface BB in FIG3. The cross-sectional structure of the display substrate 100 obtained after crossing the reference interface BB can be shown as shown in FIG1. ​​When the lead-out portion 141 and the pixel electrode 130 are projected onto the reference cross-section BB, it can be observed that two pixel electrodes 130 can be disposed in the interval area between two adjacent lead-out portions 141. Of course, in other embodiments, the lead-out portion 141 and the interconnect portion 142 can also be arranged in other ways, which will not be specifically listed here.

[0039] This configuration reduces the number of lead-out portions 141 to fewer than the number of pixel electrodes 130, thereby reducing the number of first vias 102, which in turn reduces the etching damage to the light-emitting epitaxial layer 110. It also reduces the wiring difficulty of the common electrode 140, thus reducing the fabrication difficulty of the LED display device 1.

[0040] In some embodiments, as shown in FIG1, the first via 102 may include a first via segment 1021 and a second via segment 1022. The first via segment 1021 may penetrate the first insulating layer 120, the first semiconductor layer 111 and the active layer 112, and expose the second semiconductor layer 113. The second via segment 1022 communicates with the bottom of the first via 102 and is located in the second semiconductor layer 113.

[0041] The diameter of the second hole segment 1022 can be smaller than the diameter of the first hole segment 1021, and varies in a stepped manner. The lead-out portion 141 includes a first lead-out segment 1411 and a second lead-out segment 1412 respectively disposed within the first hole segment 1021 and the second hole segment 1022. Therefore, the diameter of the second lead-out segment 1412 in the second hole segment 1022 is also smaller than the diameter of the first lead-out segment 1411 in the first hole segment 1021. As an example, the diameter of the first hole segment 1021 can be as shown by width L1 in Figure 1, and the diameter of the second hole segment 1022 can be as shown by width L2 in Figure 1, where L2 is smaller than L1.

[0042] This configuration allows the lead-out portion 141 to form a damascus structure in the light-emitting epitaxial layer 110, and also facilitates the formation of a smaller second via 1022 within the first via 1021, thereby reducing the difficulty of forming the first via 102 and thus reducing the fabrication difficulty of the LED display device 1. Furthermore, the first via 1021 can expose the second semiconductor layer 113, and the second via 1022, connected to the bottom of the first via 102 and located within the second semiconductor layer 113, increases the exposed area of ​​the second semiconductor layer 113 within the first via 102. This facilitates electrical connection between the lead-out portion 141 and the second semiconductor layer 113, reduces the occurrence of poor contact and open circuits between the lead-out portion 141 and the second semiconductor layer 113, and improves the transmission efficiency of the driving current from the lead-out portion 141 to the second semiconductor layer 113.

[0043] In some embodiments, as shown in FIG1, the end face connecting the first lead-out segment 1411 and the second lead-out segment 1412 may contact the second semiconductor layer 113, and the sidewall surface of the second lead-out segment 1412 may contact the second semiconductor layer 113.

[0044] Specifically, the first insulating layer 120, the first semiconductor layer 111, and the active layer 112 can be exposed on the sidewall of the first lead-out section 1411, and the first insulating layer 120, the first semiconductor layer 111, and the active layer 112 are electrically isolated from the first lead-out section 1411. The bottom of the first lead-out section 1411 is in electrical contact with the second lead-out section 1412 and the second semiconductor layer 113, and the second lead-out section 1412 is formed in the second semiconductor layer 113 and is in electrical contact with the second semiconductor layer 113. This arrangement can increase the contact area between the second semiconductor layer 113 and the lead-out section 141, thereby reducing the phenomenon of poor contact and open circuit between the lead-out section 141 and the second semiconductor layer 113, and also improving the transmission effect of the driving current from the lead-out section 141 to the second semiconductor layer 113.

[0045] In some embodiments, as shown in FIG1, the display substrate 100 may have an insulating spacer layer 150 disposed on the sidewall of each first hole segment 1021. The insulating spacer layer 150 may be disposed between the first lead segment 1411 and the first semiconductor layer 111 and the active layer 112, so that the first lead segment 1411 is electrically isolated from the first semiconductor layer 111 and the active layer 112, thereby making the display substrate 100 less prone to leakage short circuits. The insulating spacer layer 150 may be made of silicon dioxide, silicon nitride, PI, BCB or other insulating materials.

[0046] Of course, in other embodiments, other methods can be used to maintain electrical isolation between the first lead-out segment 1411 and the first semiconductor layer 111 and the active layer 112. For example, the portions of the first semiconductor layer 111 and the active layer 112 exposed to the first via segment 1021 can be ion-sputtered, thereby achieving electrical insulation between the portions of the first semiconductor layer 111 and the active layer 112 exposed to the first via segment 1021. Therefore, the first lead-out segment 1411 can be electrically isolated from the first semiconductor layer 111 and the active layer 112.

[0047] In some embodiments, as shown in Figures 1 and 2, the interconnect portion 142 may include a plurality of cover portions 1421 and a plurality of linear portions 1422. Each cover portion 1421 covers one end of the corresponding lead-out portion 141 away from the second semiconductor layer 113 and forms a conductive connection. The plurality of linear portions 1422 may be arranged in a grid pattern and conductively connect to the plurality of cover portions 1421. The linear portions 1422 may be connected to other external circuits to transmit current to the cover portions 1421, and further to the lead-out portion 141 and the second semiconductor layer 113 through the cover portions 1421.

[0048] When viewed along the stacking direction A, the line width of the linear portion 1422 is less than or equal to the maximum size of the covering portion 1421. As an example, the line width of the linear portion 1422 can be as shown by width L3 in FIG2, and the maximum size of the covering portion 1421 can be as shown by width L4 in FIG2, wherein L4 is greater than L3.

[0049] This configuration facilitates the injection of current from the linear portion 1422 into the covering portion 1421, thereby enhancing the transmission effect of the driving current in the common electrode 140.

[0050] In some embodiments, as shown in FIG1, when viewed along the stacking direction A, the size of the cover portion 1421 can be larger than the size of the lead portion 141, so as to achieve electrical contact between the cover portion 1421 and the lead portion 141 during the manufacturing process, thereby reducing the occurrence of poor contact between the cover portion 1421 and the lead portion 141.

[0051] Of course, in some embodiments, the cover portion 1421 may also contact a portion of the lead portion 141, or the size of the cover portion 1421 may be smaller than the size of the lead portion 141, thereby facilitating the injection of drive current from the cover portion 1421 into the lead portion 141.

[0052] In some embodiments, as shown in Figures 2 and 3, the display substrate 100 may include a display area 160 and a peripheral area 170 located around the display area 160. A plurality of pixel electrodes 130 may be located within the display area 160, and the linear portion 1422 may extend into the peripheral area 170. As an example, the projections of the display area 160 and the peripheral area 170 in the stacking direction A may be as shown in Figure 2 or Figure 3.

[0053] By extending the linear portion 1422 into the peripheral region 170, the linear portion 1422 can electrically lead each covering portion 1421 and lead-out portion 141 into the peripheral region 170, so that an external circuit can be electrically connected to the linear portion 1422 in the peripheral region 170 to provide driving current to the covering portion 1421 and lead-out portion 141 through the linear portion 1422, thereby facilitating the provision of driving current to the first semiconductor layer 111.

[0054] In some embodiments, the first insulating layer 120 is a first dielectric reflective layer. As shown in FIG1, the display substrate 100 further includes a second dielectric reflective layer 180, which covers the side of the second semiconductor layer 113 opposite to the active layer 112. Both the first insulating layer 120 and the second dielectric reflective layer 180 may have reflective functions.

[0055] The reflectivity of the second dielectric reflective layer 180 can be less than that of the first dielectric reflective layer. This configuration allows the display substrate 100 to form a resonant cavity at the position corresponding to the display pixel 101, and the light from the display pixel 101 can be emitted from the side of the second dielectric reflective layer 180 away from the second semiconductor layer 113 under the influence of the first dielectric reflective layer, which has a higher reflectivity. Furthermore, using the first insulating layer 120 as the first dielectric reflective layer not only reduces light leakage and improves the light extraction efficiency and collimation of the LED display device 1, but also saves resources and costs, eliminating the need for an additional reflective layer.

[0056] As an example, the first insulating layer 120 can be made of a material that is both insulating and highly reflective, such as a DBR mirror. The second dielectric reflective layer 180 can also be made of a highly reflective material, such as a DBR mirror.

[0057] Of course, in other embodiments, the first insulating layer 120 may not serve as the first dielectric reflective layer. The display substrate 100 may have the first dielectric reflective layer disposed on the side of the first insulating layer 120 away from the pixel electrode 130 and the first semiconductor layer 111. The first insulating layer 120 may be a transparent insulating layer, for example, it may be made of a transparent insulating material such as SiO2, SiN, or Al2O3. Therefore, light passing through the first insulating layer 120 can be reflected by the first dielectric reflective layer. The first dielectric reflective layer may be made of a highly reflective material such as a DBR mirror.

[0058] In some embodiments, as shown in FIG1, the display substrate 100 may include a first dielectric bonding layer 190 and a plurality of lead-out electrodes 1000. The first dielectric bonding layer 190 covers the interconnect portion 142 and the first insulating layer 120 from the side of the interconnect portion 142 away from the first insulating layer 120. The display substrate 100 is provided with a plurality of second vias 103, which penetrate the first dielectric bonding layer 190 and the first insulating layer 120 and expose the corresponding pixel electrode 130. Each lead-out electrode 1000 is disposed in the corresponding second via 103 and is electrically connected to the corresponding pixel electrode 130. Each lead-out electrode 1000 electrically leads the corresponding pixel electrode 130 out of the side of the first dielectric bonding layer 190 away from the interconnect portion 142 and the first insulating layer 120.

[0059] As shown in Figure 1, the driving substrate 200 may include a substrate body 210, a second dielectric bonding layer 220, and a plurality of power supply electrodes 230. The second dielectric bonding layer 220 is disposed on the side of the substrate body 210 facing the first semiconductor layer 111, and has a plurality of third vias 201, with each power supply electrode 230 disposed within a corresponding third via 201. The first dielectric bonding layer 190 and the second dielectric bonding layer 220 are bonded together, and the plurality of lead-out electrodes 1000 are bonded together with the plurality of power supply electrodes 230.

[0060] Specifically, the positions of the plurality of third vias 201 correspond to the positions of the plurality of second vias 103, and the power supply electrode 230 located in the third via 201 corresponds to the lead-out electrode 1000 located in the second via 103. The first dielectric bonding layer 190 and the second dielectric bonding layer 220 can be insulating dielectric layers, and they can be fused together. The power supply electrode 230 and the lead-out electrode 1000 can also be fused together, thereby achieving a hybrid bonding between the display substrate 100 and the driving substrate 200. Using a hybrid bonding method can also improve the bonding strength between the display substrate 100 and the driving substrate 200. Furthermore, the driving substrate 200 can sequentially provide driving current to the first semiconductor layer 111 through the power supply electrode 230, the lead-out electrode 1000, and the pixel electrode 130.

[0061] As an example, the substrate body 210 can be a CMOS (Complementary Metal Oxide Semiconductor) substrate. The substrate body 210 can contain related circuits, multiple electrodes, and multiple switching devices to control multiple power supply electrodes 230 to provide drive current to multiple lead-out electrodes 1000. The lead-out electrodes 1000 and the power supply electrodes 230 can be made of Al, Ag, Cr, Ti, Ni, Au, ITO metals, or other conductive materials.

[0062] The first dielectric bonding layer 190 and the second dielectric bonding layer 220 can be dielectric layers made of silicon nitride, silicon dioxide, PI, BCB, or other insulating materials. The bonding between the display substrate 100 and the driving substrate 200 can be a mixed bonding between Cu / SiO2 and Cu / SiO2, a mixed bonding between Cu / SiN and Cu / SiN, a mixed bonding between Cu / SiO2 and Cu / SiN, a mixed bonding between Cu / BCB and Cu / BCB, or a mixed bonding between Cu / PI and Cu / PI.

[0063] In some embodiments, as shown in Figures 2 and 3, the interconnect portion 142 is arranged in a mesh pattern, and multiple lead electrodes 1000 are respectively disposed within the mesh area of ​​the interconnect portion 142. Lead portions 141 can be located within the projection of the mesh-shaped interconnect portion 142, so that the mesh-shaped interconnect portion 142 can electrically contact the lead portions 141. By distributing multiple lead electrodes 1000 within the mesh area of ​​the interconnect portion 142, the second vias 103 corresponding to the lead electrodes 1000 will not expose the interconnect portion 142 after formation, thereby reducing the occurrence of electrical contact between the lead electrodes 1000 and the interconnect portion 142, thus reducing the possibility of short circuits in the LED display device 1 and improving the safety of the LED display device 1.

[0064] In summary, this application etches the light-emitting epitaxial layer 110 to form multiple first vias 102 to expose the second semiconductor layer 113. The lead-out portion 141 of the common electrode 140 is located in the first via 102 and electrically contacts the second semiconductor layer 113. The interconnect portion 142 is disposed on the side of the first insulating layer 120 away from the first semiconductor layer 111 to electrically connect the lead-out portion 141, thereby transmitting current to the second semiconductor layer 113 through the lead-out portion 141. This arrangement allows the interconnect portion 142 to be formed without etching into the light-emitting epitaxial layer 110. Only multiple first vias 102 need to be etched into the light-emitting epitaxial layer 110, so that the lead-out portion 141 of the common electrode 140 is electrically in contact with the second semiconductor layer 113 in the corresponding first via 102. The interconnect portion 142 then electrically connects all the lead-out portions 141, thereby reducing etching damage to the light-emitting epitaxial layer 110 while achieving electrical connection between the common electrode 140 and the second semiconductor layer 113. Furthermore, by placing the interconnect portion 142 on the side of the first insulating layer 120 away from the first semiconductor layer 111, it is convenient to configure the interconnect portion 142 for wiring. It also reduces the possibility of short circuits caused by electrical contact between the interconnect portion 142 and the pixel electrode 130 and the first semiconductor layer 111 during the manufacturing process. This improves the safety of the LED display device 1 and reduces the difficulty of the manufacturing process of the LED display device 1, thereby increasing the yield of the LED display device 1.

[0065] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An LED display device, characterized in that, The LED display device includes a display substrate; The display substrate includes a light-emitting epitaxial layer, a first insulating layer, a plurality of pixel electrodes, and a common electrode. The light-emitting epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially along a predetermined stacking direction. The plurality of pixel electrodes are arranged in an array on the side of the first semiconductor layer away from the active layer and are electrically connected to the first semiconductor layer respectively. The first insulating layer covers the plurality of pixel electrodes and the first semiconductor layer from the side of the plurality of pixel electrodes away from the first semiconductor layer. The display substrate is provided with a plurality of first vias spaced apart. Each first via penetrates the first insulating layer, the first semiconductor layer and the active layer and exposes the second semiconductor layer. The common electrode includes a plurality of leads. Each lead is disposed in a corresponding first via and electrically contacts the second semiconductor layer. Each lead is further electrically isolated from the first semiconductor layer and the active layer in the first via. The common electrode also includes an interconnection portion. The interconnection portion is located on the side of the first insulating layer away from the first semiconductor layer and is electrically connected to the plurality of leads.

2. The LED display device according to claim 1, characterized in that, The arrangement density of two adjacent leads is less than the arrangement density of the pixel electrodes.

3. The LED display device according to claim 2, characterized in that, The display substrate has a reference cross section parallel to the stacking direction, and when projected orthogonally onto the reference cross section, at least two pixel electrodes are disposed in the spacer region between two adjacent leads.

4. The LED display device according to claim 1, characterized in that, The first via includes a first segment and a second segment. The first segment penetrates the first insulating layer, the first semiconductor layer, and the active layer, and exposes the second semiconductor layer. The second segment connects to the bottom of the first via and is located in the second semiconductor layer. The diameter of the second segment is smaller than that of the first segment and changes in a stepped manner. The lead-out portion includes a first lead-out segment and a second lead-out segment respectively disposed in the first segment and the second segment.

5. The LED display device according to claim 4, characterized in that, The end face connecting the first lead segment and the second lead segment is in contact with the second semiconductor layer, and the side wall surface of the second lead segment is in contact with the second semiconductor layer.

6. The LED display device according to claim 1, characterized in that, The interconnect portion includes multiple cover portions and multiple linear portions. Each cover portion covers one end of the corresponding lead portion away from the second semiconductor layer and forms a conductive connection. The multiple linear portions are arranged in a grid pattern and are conductively connected to the multiple cover portions. When viewed along the stacking direction, the linewidth of the linear portion is less than or equal to the maximum size of the cover portion.

7. The LED display device according to claim 6, characterized in that, The display substrate includes a display area and a peripheral area located around the display area, the plurality of pixel electrodes are located within the display area, and the linear portion extends into the peripheral area.

8. The LED display device according to claim 1, characterized in that, The first insulating layer is a first dielectric reflective layer, and the display substrate further includes a second dielectric reflective layer. The second dielectric reflective layer covers the side of the second semiconductor layer away from the active layer, and the reflectivity of the second dielectric reflective layer is less than that of the first dielectric reflective layer.

9. The LED display device according to claim 1, characterized in that, The display substrate includes a first dielectric bonding layer and a plurality of lead-out electrodes. The first dielectric bonding layer covers the interconnect portion and the first insulating layer from the side of the interconnect portion away from the first insulating layer. The display substrate is provided with a plurality of second vias. The second vias penetrate the first dielectric bonding layer and the first insulating layer and expose the corresponding pixel electrode. Each lead-out electrode is disposed in the corresponding second via and is electrically connected to the corresponding pixel electrode. The LED display device further includes a driving substrate, which includes a substrate body, a second dielectric bonding layer, and a plurality of power supply electrodes. The second dielectric bonding layer is disposed on the side of the substrate body facing the first semiconductor layer and has a plurality of third vias. Each power supply electrode is disposed in a corresponding third via. The first dielectric bonding layer and the second dielectric bonding layer are bonded to each other, and the plurality of lead-out electrodes are bonded to the plurality of power supply electrodes.

10. The LED display device according to claim 9, characterized in that, The interconnection portion is arranged in a grid pattern, and the plurality of lead-out electrodes are respectively disposed in the mesh area of ​​the interconnection portion.

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