Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor according to the present disclosure has a ceramic element body in which a plurality of dielectric layers and a plurality of internal electrode layers are laminated, wherein the dielectric layers include a ceramic material having a perovskite structure represented by formula (1), the perovskite structure includes an orthorhombic crystal structure and a cubic crystal structure, and, in the ceramic material, the ratio of the orthorhombic crystal structure to the cubic crystal structure (orthorhombic crystal structure / cubic crystal structure) is 1.3 or more.　Formula (1): ABO3 [In formula (1), A is one or more selected from the group consisting of Sr, Ba, and Ca; B is one or more selected from the group consisting of Hf, Zr, and Ti; and 0.9≤A / B≤1.1]

Description

Multilayer ceramic capacitor

[0001] This disclosure relates to multilayer ceramic capacitors.

[0002] In recent years, with the miniaturization of electronic devices, there has been a demand for further miniaturization of the multilayer ceramic capacitors used in them. As a means of miniaturizing multilayer ceramic capacitors while maintaining their capacitance, a structure has been disclosed in which the dielectric layer is thinned and the number of layers is increased (for example, Patent Document 1).

[0003] Japanese Patent Publication No. 2024-077398

[0004] This disclosure provides the following means:

[0005] [1] A multilayer ceramic capacitor having a ceramic body in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked, wherein the dielectric layers include a ceramic material having a perovskite structure represented by the following formula (1), the perovskite structure includes an orthorhombic crystal structure and a cubic crystal structure, and the ratio of the orthorhombic crystal structure to the cubic crystal structure in the ceramic material (orthorhombic crystal structure / cubic crystal structure) is 1.3 or more. ABO ３ ...Equation (1) [In Equation (1), A is one or more selected from the group consisting of Sr, Ba, and Ca, B is one or more selected from the group consisting of Hf, Zr, and Ti, 0.9 ≤ A / B ≤ 1.1]

[0006] This is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present disclosure. This is a perspective view showing the main body of the multilayer ceramic capacitor in Figure 1. This is a cross-sectional view taken along the line III-III in Figure 1. This is a graph showing the results of analyzing the residual stress on the material surface using X-ray diffraction (XRD) (XRD stress). This is a graph showing the relationship between the ratio of the thickness of the internal electrode layer to the thickness of the ceramic body and the residual stress on the material surface.

[0007] In multilayer ceramic capacitors, a problem has been that cracks are more likely to occur in structures where the dielectric layer is thinned and the number of layers is increased. According to this disclosure, it is possible to reduce the occurrence of cracks in multilayer ceramic capacitors.

[0008] The present disclosure will be described in detail below with reference to one embodiment.

[0009] In this disclosure, the notation "XX to YY" means "XX or more and YY or less." Furthermore, in this disclosure, the lower and upper limits of numerical ranges (for example, ranges of content, etc.) described in stages can be combined independently. In addition, in numerical ranges described in this disclosure, the upper or lower limit of that numerical range may be replaced with the values ​​shown in the examples.

[0010] Embodiments of the multilayer ceramic capacitor of this disclosure will be described below with reference to the drawings. The drawings referenced below are schematic, and the dimensional ratios shown in the drawings are not necessarily accurately represented. In this disclosure, a Cartesian coordinate system XYZ is defined for convenience in some of the drawings. The X-axis direction is also referred to as the first direction or length direction. The Y-axis direction is also referred to as the second direction or width direction. The Z-axis direction is also referred to as the third direction, height direction, or stacking direction.

[0011] [1. Multilayer Ceramic Capacitor] The multilayer ceramic capacitor 1 of this embodiment includes a ceramic element 2, as shown in Figure 1. The ceramic element 2 may have a substantially rectangular parallelepiped shape, as shown in Figure 2. The ceramic element 2 may have a first surface 7a and a second surface 7b facing each other in the third direction, a first end surface 8a and a second end surface 8b facing each other in the first direction, and a first side surface 9a and a second side surface 9b facing each other in the second direction. Hereinafter, the first surface 7a and the second surface 7b may be collectively referred to as main surfaces 7a and 7b, the first end surface 8a and the second end surface 8b may be collectively referred to as end surfaces 8a and 8b, and the first side surface 9a and the second side surface 9b may be collectively referred to as side surfaces 9a and 9b. The main surfaces 7a and 7b may be perpendicular to the third direction, the end surfaces 8a and 8b may be perpendicular to the first direction, and the side surfaces 9a and 9b may be perpendicular to the second direction.

[0012] As shown in Figure 3, the magnetic element 2 may be constructed by alternately stacking dielectric layers 5 and internal electrode layers 6. The dielectric layers 5 and internal electrode layers 6 may be stacked in a third direction. The internal electrode layers 6 may be exposed on the first side surface 9a and the second side surface 9b. The ends of the internal electrode layers 6 exposed on the first side surface 9a and the ends exposed on the second side surface 9b may be covered by the side margin portion 3, as shown in Figure 2, and may not be exposed to the outside. In addition, the internal electrode layers 6 may be exposed on the first end surface 8a or the second end surface 8b depending on the polarity. The ends of the internal electrode layers 6 exposed on the first end surface 8a and the ends exposed on the second end surface 8b may be covered by the first external electrode 4a and the second external electrode 4b, respectively, as shown in Figure 3, and may be electrically connected to the first external electrode 4a and the second external electrode 4b.

[0013] In one embodiment, a multilayer ceramic capacitor includes a ceramic material having a perovskite structure represented by the following formula (1) in its dielectric layer. The perovskite structure includes an orthorhombic crystal structure and a cubic crystal structure. The ratio of the orthorhombic crystal structure to the cubic crystal structure in the ceramic material (orthorhombic crystal structure / cubic crystal structure) is 1.3 or greater. As a method for calculating the ratio, for example, the XRD peak intensity ratio Orth / Cubic may be used, where Orth represents the XRD peak intensity attributed to the orthorhombic crystal structure and Cubic represents the XRD peak intensity attributed to the cubic crystal structure. The method for calculating the ratio is not limited to the above example. For example, it may be calculated by Rietveld analysis. ABO ３ ...Equation (1) [In Equation (1), A is one or more selected from the group consisting of Sr, Ba, and Ca, B is one or more selected from the group consisting of Hf, Zr, and Ti, and 0.9 ≤ A / B ≤ 1.1] Note that the value of A / B in Equation (1) may be determined by ICP spectroscopy analysis of the ceramic element 2 of the multilayer ceramic capacitor.

[0014] The magnetic element may be formed by alternately stacking a plurality of dielectric layers and a plurality of internal electrode layers. The external electrodes may be provided on both end faces of the capacitor body, on the surfaces where the plurality of internal electrode layers are exposed.

[0015] The shape of the capacitor body is not particularly limited and may be rectangular. The dimensions of the capacitor body are also not particularly limited and may be appropriate for the application.

[0016] The shape and size of the multilayer ceramic capacitor are not particularly limited and may be, for example, rectangular. For example, the dimensions of the "stack direction × width direction × length direction" may be 1 mm × 0.5 mm × 0.5 mm, 1.6 mm × 0.8 mm × 0.8 mm, 2 mm × 1.25 mm × 1.25 mm, or 3.2 mm × 1.6 mm × 1.6 mm.

[0017] [1.1. Dielectric Layer] The dielectric layer mainly consists of a ceramic material having a perovskite structure represented by formula (1). The compositions of A and B and the A / B ratio may be appropriately changed within the range that satisfies formula (1). For example, formula (1) may be the following formula (2). Sr ｘ Ba ｙ Ca １－ｘ－ｙ Zr １－ｚ Ti ｚ O3...Equation (2) [In Equation (2), x = 0.3 to 0.8, y = 0 to 0.1, z = 0.05 to 0.1] Note that the values ​​of x, y, and z in Equation (2) may be determined by ICP spectroscopy analysis of the ceramic element 2 of the multilayer ceramic capacitor.

[0018] The ceramic material having a perovskite structure represented by formula (1) includes an orthorhombic crystal structure, which is a crystal system in which three crystal axes of different lengths intersect at right angles, and a cubic crystal structure, which is a crystal system in which three crystal axes of equal length intersect at right angles. The crystal grains constituting the ceramic material have multiple orientation states (i.e., twinning structures) within a single crystal grain, and the Orth / Cubic ratio is 1.3 or higher. In this disclosure, twinning structure means, for example, a structure having domain walls.

[0019] The Orth / Cubic value is mainly determined by the x, y, and z composition in the composite component system of equation (2).

[0020] When the residual stress on the material surface is analyzed using X-ray diffraction (XRD), as shown in Figure 4, it can be confirmed that in ceramic materials having a perovskite structure represented by equation (1) and an Orth / Cubic ratio of 1.3 or higher, the residual stress on the material surface ("XRD stress" in Figure 4) is small. This is presumed to be because, in compositions where Orth / Cubic is 1.3 or higher and there is a large amount of orthorhombic crystal structure, the crystal grains spontaneously orient themselves to lower their elastic energy. Therefore, it is presumed that in the multilayer ceramic capacitor of this disclosure, even when the proportion of the internal electrode layer is relatively increased and the residual stress due to the difference in thermal expansion coefficients between the dielectric layer and the internal electrode layer increases, causing large thermal stress in the dielectric layer, the arrangement of the crystal structure makes it possible to minimize the elastic energy, i.e., stress relaxation is possible, and the occurrence of cracks is reduced.

[0021] Orth / Cubic may be 8.4 or less, 6.5 or less, or 5.7 or less. For example, if Orth / Cubic is 8.4 or less, a multilayer ceramic capacitor with good temperature characteristics can be obtained.

[0022] Orth / Cubic may also be determined by measuring the powder XRD of the main component dielectric powder and taking the ratio of the XRD peak intensity of orthorhombic (Orth) located around 36-37.5° to the XRD peak intensity of cubic (Cubic) located around 37.5-38.5°. Alternatively, Orth / Cubic may also be determined by measuring the powder XRD of the dielectric layer 5 contained in the ceramic element 2 of the multilayer ceramic capacitor after firing and taking the ratio of the XRD peak intensity of orthorhombic (Orth) located around 36-37.5° to the XRD peak intensity of cubic (Cubic) located around 37.5-38.5°.

[0023] Whether or not the crystalline grains constituting a ceramic material have a twinning structure can be determined by embedding the sample in resin, creating a cross-section, and then visually observing the crystalline grains using a scanning electron microscope (SEM). Multiple fields of view may be observed at magnifications ranging from 10,000 to 150,000 times. In particles with twinning, differences in contrast can be observed due to the difference in crystal orientation across the twinning boundary, and due to the difference in composition between orthorhombic and cubic crystal structures. The presence of a twinning structure can also be confirmed by observing the crystal orientation using a transmission electron microscope (TEM).

[0024] The proportion of particles having a twinned structure among the crystalline particles constituting the ceramic material may be 0.9% or more. The proportion of particles having a twinned structure among the crystalline particles constituting the ceramic material is determined by the proportion of conductive material derived from the internal electrode layer in the chip after the external electrode is formed, and the mass ratio of the orthorhombic crystal structure to the cubic crystal structure. In compositions where Orth / Cubic is 1.3 or more, the proportion of particles having a twinned structure among the crystalline particles constituting the ceramic material is 0.9% or more. Therefore, in a multilayer ceramic capacitor in one embodiment, the proportion of particles having a twinned structure among the crystalline particles constituting the ceramic material contained in the dielectric layer may be 0.9% or more.

[0025] The proportion of particles with a twinning structure can be calculated, for example, by examining multiple fields of view at magnifications of 10,000 to 50,000 times using a scanning electron microscope (SEM) and identifying 300 randomly selected crystal particles.

[0026] In addition to the ceramic material which is the main component described above, the dielectric layer may contain a predetermined additive compound according to the purpose. The additive compound is, for example, oxides of Mo (molybdenum), Nb (niobium), Ta (tantalum), W (tungsten), Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), Zr (zirconium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)), and at least one selected from the group consisting of oxides and glasses of Co (cobalt), Ni (nickel), Li (lithium), B (boron), Na (sodium), K (potassium), Al (aluminum) and Si (silicon) may be used.

[0027] When the ceramic material which is the main component is 100 mol%, the addition amount of the additive compound may be 1 to 5 mol% or 1 to 10 mol% in terms of oxide conversion. When the addition amount of the additive compound is 1 mol% or more, insufficient sintering during firing can be avoided. When the addition amount of the additive compound is 10 mol% or less, a decrease in the capacitance of the multilayer ceramic capacitor can be avoided.

[0028] [1.2. Internal Electrode Layer] The conductive material contained in the internal electrode layer may mainly contain base metals such as Ni (nickel), Cu (copper), Sn (tin), etc., and noble metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold) or alloys containing these may also be used. In Ni, Ni-based alloys, Cu or Cu-based alloys, various trace components such as P and / or S may be contained at about 0.1 mass% or less.

[0029] The ratio of the thickness of the internal electrode layer to the thickness of the ceramic body may be 30% or more, may be 40% or more, or may be 50% or more. The ratio of the thickness of the internal electrode layer to the thickness of the ceramic body may be at most 80%. In the present disclosure, "thickness" means the thickness in the Z-axis direction. In the present disclosure, "the thickness of the ceramic body" means the thickness in the stacking direction of the ceramic body in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked. In the present disclosure, "the thickness of the internal electrode layer" means, for example, the average value of the thicknesses in the Z-axis direction of any 15 layers among the plurality of dielectric layers constituting the ceramic body.

[0030] As shown in FIG. 5, in the prior art, when the ratio of the thickness of the internal electrode layer to the thickness of the ceramic body is 30% or more, the residual stress caused by the difference in the thermal expansion coefficients between the dielectric layer and the internal electrode layer becomes significantly large. The dielectric layer of the prior art multilayer ceramic capacitor in FIG. 5 has the composition of Sample 21 in Table 1 below, and Orth / Cubic is 0.6586. On the other hand, when the dielectric layer is the dielectric layer of the present disclosure, that is, a dielectric layer containing a ceramic material having a perovskite structure represented by the above formula (1) and having an Orth / Cubic of 1.3 or more, even when the ratio of the thickness of the internal electrode layer is 30% or more, a significant increase in residual stress as in the prior art is not observed. As described above, it is presumed that the crystal grains of the ceramic material constituting the dielectric layer of the present disclosure can have a plurality of types of orientation states (i.e., twin structure) within one crystal grain, and the crystal grains can spontaneously orient so as to reduce the elastic energy, resulting in stress relaxation.

[0031] The internal electrode layer may be formed using a commercially available electrode paste. The thickness of the internal electrode layer may be appropriately determined according to the application and the like.

[0032] [1.3. External Electrode] The conductive material contained in the external electrode is not particularly limited. For example, known conductive materials such as Ni, Cu, Sn, Ag, Pd, Pt, Au, alloys thereof, and conductive resins may be used. The thickness of the external electrode may be appropriately determined according to the application and the like.

[0033] [2. Method for manufacturing a multilayer ceramic capacitor] The method for manufacturing a multilayer ceramic capacitor in one embodiment may be manufactured as follows.

[0034] (Preparation of dielectric main component powder) The raw material powder of the main component is weighed so as to have a predetermined composition, and wet pulverized and mixed with a bead mill to obtain a mixed powder. The raw material powder of the main component uses CaCO ３ , SrCO ３ , BaCO ３ , TiO ２ , ZrO ２ powders. The purity of the raw material powder is 99% or more, but it may contain inevitable impurities such as HfO ２ . At this time, the molar ratio (number of moles of A-site element / number of moles of B-site element) of the A-site element (Sr, Ba, Ca) and B-site element (Zr, Ti) of the main component, which is a perovskite-type compound of ABO ３ , may be 0.9 or more and 1.1 or less. The raw material powder of the main component may be a carbonate, an oxide, a hydroxide, or a chloride. After drying the mixed powder, it is calcined at a temperature of 900 °C or higher and 1300 °C or lower, and wet pulverized and mixed again with a bead mill to obtain a dielectric main component powder. From the viewpoint of thinning the dielectric layer, the average particle size of the dielectric main component powder is preferably 50 to 300 nm. For example, for the dielectric main component powder obtained as described above, the particle size may be adjusted by performing a pulverization treatment as necessary, or the particle size may be adjusted by combining with a classification treatment.

[0035] (Preparation of ceramic slurry) The obtained dielectric main component powder, sub-components (for example, SiO ２ , MnCO ３ ), a polyvinyl butyral-based binder, a plasticizer, and an organic solvent are added and wet pulverized and mixed with a bead mill to prepare a ceramic slurry. Other additives common in multilayer ceramic capacitors, for example, Al ２ O ３ , MgO, Li ２ O, B ２ O ３ may be added. In the process of preparing the ceramic slurry, CaCO ３ , SrCO３ BaCO ３ , TiO ２ , ZrO ２ The molar ratio may be adjusted by adding more powder.

[0036] (Preparation of Metal Conductive Paste) The paste for the internal electrode layer is obtained by kneading the conductive material described above, a binder, and a solvent. Known binders and solvents may be used. The paste for the internal electrode layer may contain additives such as co-materials and plasticizers as needed. The paste for the external electrode can be prepared in the same manner as the paste for the internal electrode layer.

[0037] (Forming to Printing) A ceramic green sheet is formed on a carrier film using a die coater. The ceramic green sheet may be formed using a doctor blade coater or a gravure coater. The thickness of the ceramic green sheet may be, for example, about 0.7 to 4 μm. The thinner the ceramic green sheet, the higher the capacitance of the multilayer ceramic capacitor can be. Next, an internal electrode paste is printed on the ceramic green sheet formed as described above using a screen printing method in a predetermined pattern. The internal electrode paste may be printed using a gravure printing method or the like. The conductive material of the internal electrode paste may be, for example, Ni.

[0038] (Lamination and Pressing) A predetermined number of ceramic green sheets are laminated on top of a predetermined number of ceramic green sheets, on which an internal electrode layer is printed, and then a predetermined number of ceramic green sheets are laminated again. The ceramic green sheets with the printed internal electrode layer are laminated in a predetermined number of layers while shifting the pattern of the internal electrode layer. Next, the laminate, which consists of multiple laminated ceramic green sheets, is pressed in the lamination direction to obtain a master laminate. The laminate can be pressed using, for example, a hydrostatic press. Inside the master laminate, the internal electrode layer is embedded in layers with the ceramic green sheets in between. By cutting the master laminate lengthwise and widthwise, laminated chips cut to a predetermined size are obtained.

[0039] (Degreasing ~ Calcination ~ Reoxidation) The obtained laminated chips are heated to a temperature of 200-300°C under air to burn off organic components such as binders. After that, under a reducing atmosphere (oxygen partial pressure 10°C) －８ ~10 －１４ The ceramic sintered body is fired at a temperature of 1240°C or lower for 5 to 120 minutes. Next, a re-oxidation treatment is performed. The conditions for the re-oxidation treatment may be a nitrogen atmosphere with a maximum temperature of 850°C and a holding time of 5 hours.

[0040] (Plating process) Next, the ceramic sintered body is barrel polished to expose the internal electrodes from the end face, and an external electrode paste is applied thereto. After drying the external electrode paste, it is baked at 700 to 850°C to form the external electrodes. The external electrode paste may, for example, contain Cu powder and glass. Then, using an electrolytic barrel machine, Ni plating and Sn plating are sequentially formed on the surface of the external electrodes to obtain a multilayer ceramic capacitor.

[0041] The present disclosure will now be specifically illustrated by examples, but the present disclosure is not limited to these examples.

[0042] <Fabrication of Multilayer Ceramic Capacitors> Multilayer ceramic capacitors (samples No. 1 to 26 in Table 1) were fabricated using the manufacturing method described above. The main component of the dielectric layer is the ceramic material raw material powder CaCO3 ３ SrCO ３ BaCO ３ , TiO ２ , ZrO ２ The powder was weighed so that the initial composition matched that shown in Table 1. The Ca, Sr, Ba, Ti, and Zr composition ratios listed in Table 1 can also be determined by ICP spectroscopy analysis of the ceramic element 2 of the multilayer ceramic capacitor. For the internal electrode layer paste, a mixture containing 100 parts by mass of Ni powder as a metal powder, 7 parts by mass of ethyl cellulose as an organic vehicle, and terpineol as a solvent was used. During the firing of the multilayer chip, the binder was burned by heating to 250°C in air, followed by heating at a rate of 30°C / min, a maximum temperature of 1200°C, and an oxygen partial pressure of 10°C. －１１The ceramic sintered body was obtained by firing atm. ICP analysis of the obtained sintered body confirmed that it was almost identical to the composition shown in Table 1. The internal electrodes were exposed from the end face by barrel firing of the sintered body, and an external electrode paste containing Cu powder and glass was applied thereto. After drying the external electrode paste, it was fired at a maximum temperature of 800°C to form the external electrodes. Then, Ni plating and Sn plating were sequentially formed on the surface of these external electrodes using an electrolytic barrel machine to obtain a multilayer ceramic capacitor. The obtained multilayer ceramic capacitor had dimensions of 1 mm × 0.5 mm × 0.5 mm, with a dielectric layer thickness of 1.1 to 4 μm and an internal electrode layer thickness of 0.6 to 0.9 μm.

[0043] The multilayer ceramic capacitors obtained in this manner (samples No. 1 to 26 in Table 1) were subjected to the following measurements or evaluations. The measurement or evaluation results are shown in Table 1. Samples marked with "*" in Table 1 (No. 17, 20-21, 23-26) do not satisfy the requirement that "Orth / Cubic is 1.3 or higher".

[0044] <Orth / Cubic> Using the main component powder of the dielectric layer weighed to have the composition shown in Table 1, XRD measurements were taken, and the Orth / Cubic ratio was determined from the ratio of the XRD peak intensity Orth, which belongs to the orthorhombic crystal structure of 36–37.5°, and the XRD peak intensity Cubic, which belongs to the cubic crystal structure of 37.5–38.5°.

[0045] <Percentage of particles containing twinned structures> After embedding the sample in resin and preparing a cross-section, the crystal grains were visually observed using a scanning electron microscope (SEM) to determine whether or not they contained twinned structures. The observation magnification was 10,000x. A result of "○" was given when the percentage of particles containing twinned structures was 0.9% or more, and a result of "×" was given when the percentage of particles containing twinned structures was less than 0.9%.

[0046] <Presence or Absence of Cracks> Samples No. 1 to 26 in Table 1 were subjected to a heat cycle load. The heat cycle load consisted of one cycle of room temperature → -55°C for 5 min → room temperature → 150°C for 5 min → room temperature. After being exposed to the environment for 1000 cycles, the products were evaluated for the occurrence of cracks using a microscope at 40 to 800x magnification. A result of "○" indicated that no cracks occurred, and a result of "×" indicated that one or more cracks occurred in the product.

[0047]

[0048] In the multilayer ceramic capacitors of this disclosure (samples No. 1-16, 18-19, and 22 in Table 1), it was confirmed that the occurrence of cracks was suppressed.

[0049] The multilayer ceramic capacitors disclosed herein are suitable for applications where thinning or high-density stacking of dielectric layers is required for miniaturization and high capacitance.

[0050] 1 Multilayer ceramic capacitor 2 Porcelain element 21 Cover layer 3 Side margin 3a Outer surface 4a First external electrode 4b Second external electrode 41 First layer (underlayment) 42 Second layer (outer layer) 5 Dielectric layer 6 Internal electrode layer 7a First surface 7b Second surface 8a First end surface 8b Second end surface 9a First side surface 9b Second side surface

Claims

1. A multilayer ceramic capacitor having a ceramic body in which multiple dielectric layers and multiple internal electrode layers are stacked, wherein the dielectric layers include a ceramic material having a perovskite structure represented by the following formula (1), the perovskite structure includes an orthorhombic crystal structure and a cubic crystal structure, and the ratio of the orthorhombic crystal structure to the cubic crystal structure in the ceramic material (orthorhombic crystal structure / cubic crystal structure) is 1.3 or more. ３ ...Equation (1) [In Equation (1), A is one or more selected from the group consisting of Sr, Ba, and Ca, B is one or more selected from the group consisting of Hf, Zr, and Ti, 0.9 ≤ A / B ≤ 1.1] 2. The multilayer ceramic capacitor according to claim 1, wherein the ratio of the thickness of the internal electrode layer to the thickness of the ceramic body is 30% or more.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the average grain size of the crystals constituting the ceramic material is 100 nm or more.

4. A multilayer ceramic capacitor according to any one of claims 1 to 3, wherein formula (1) is the following formula (2). Sr ｘ Ba ｙ Ca １－ｘ－ｙ Zr １－ｚ Ti ｚ O3...Equation (2) [In Equation (2), x = 0.3 to 0.8, y = 0 to 0.1, z = 0.05 to 0.1] 5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the internal electrode layer includes at least one selected from the group consisting of Ni, Cu, and Sn.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the ratio of the orthorhombic crystal structure to the cubic crystal structure (orthorhombic crystal structure / cubic crystal structure) is 8.4 or less.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the proportion of particles having a twinned structure among the crystalline particles constituting the ceramic material is 0.9% or more.

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