Display panel, display device, and data voltage driving method

Abstract

The present disclosure provides a display panel, a display device, and a data voltage driving method. The display panel comprises: a plurality of pixel units, wherein each pixel unit comprises a pixel circuit, and each pixel circuit comprises a data writing transistor; and a plurality of data lines, wherein a first electrode of each data writing transistor in the corresponding pixel circuit is coupled to at least two data lines, so that when some data lines are broken, a data voltage can be provided to the pixel circuits by means of other unbroken data lines, so that it is ensured that the data voltage can be written to the pixel circuits normally, thereby avoiding a display anomaly of the display panel.

Description

Display panel and display device, data voltage driving method Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to display panels and display devices, and data voltage driving methods. Background Technology

[0002] Typically, display panels control the writing of data voltage to pixels through crisscrossing data lines and scan lines. Data voltage is provided to a column of pixels through a data line. When the data line is broken, the data line after the break point is left floating, and the data voltage cannot be written to the pixel normally, resulting in display abnormalities. Summary of the Invention

[0003] This disclosure provides a display panel, including:

[0004] Multiple pixel units, each pixel unit including a pixel circuit, the pixel circuit including a data writing transistor;

[0005] Multiple data lines, wherein the first electrode of the data writing transistor in the pixel circuit is coupled to at least two of the data lines.

[0006] In some possible implementations, the display panel further includes:

[0007] A plurality of diodes are provided, wherein the first terminal of the data writing transistor is connected to the data line through at least one of the diodes, wherein the positive terminal of the diode is connected to the data line and the negative terminal of the diode is connected to the first terminal of the data writing transistor.

[0008] In some possible implementations, the plurality of pixel units include a plurality of column groups, the column group comprising two pixel units that are adjacent along the row direction;

[0009] The data lines coupled to the first pole of the data write transistor in each pixel unit of the column group are the same.

[0010] In some possible implementations, the data line is located between two adjacent pixel units in the column group.

[0011] In some possible implementations, the data lines coupled to the pixel circuits in the same column of pixel units are the same.

[0012] In some possible implementations, the display panel further includes:

[0013] The first scan line and the second scan line are provided, wherein the control terminal of the data writing transistor of one pixel unit in the column group is connected to the first scan line, and the control terminal of the data writing transistor of the other pixel unit is connected to the second scan line.

[0014] In some possible implementations, in the same row of pixel units, the control terminals of the data write transistors in odd-numbered column pixel units are connected to the first scan line, and the control terminals of the data write transistors in even-numbered column pixel units are connected to the second scan line.

[0015] In some possible implementations, the display panel further includes;

[0016] Substrate;

[0017] A semiconductor material layer is located on one side of the substrate, the semiconductor material layer includes a plurality of diode regions, and the diode regions include the diodes;

[0018] A conductive layer is located on the side of the semiconductor material layer opposite to the substrate. The conductive layer includes the data line, which is connected to the positive terminal of the diode in the diode region through a connection hole.

[0019] In some possible implementations, the semiconductor material layer further includes an active layer of the data writing transistor, and the negative terminal of the diode is connected to the active layer of the data writing transistor.

[0020] This disclosure also provides a data voltage driving method, including:

[0021] Acquire image data to be displayed, wherein the image data to be displayed includes the initial data voltage corresponding to each pixel unit;

[0022] When a portion of the data lines of at least two data lines coupled to the first pole of the data writing transistor are disconnected, the pixel unit where the data writing transistor is located, connected to the disconnected data line, is taken as the target pixel unit. The initial data voltage corresponding to the target pixel unit is increased and then output to at least the unconnected data line connected to the target pixel unit.

[0023] This disclosure also provides a data voltage driving method, including:

[0024] Acquire image data to be displayed, wherein the image data to be displayed includes the initial data voltage corresponding to each pixel unit;

[0025] When a portion of the data lines of at least two data lines coupled to the first pole of the data writing transistor are disconnected, the pixel unit where the data writing transistor is located is the target pixel unit, and the initial data voltage corresponding to the target pixel unit is output to each of the data lines connected to the target pixel unit.

[0026] This disclosure also provides a display device, including the display panel described above.

[0027] In some possible implementations, the display device further includes a timing controller and a source drive circuit, the timing controller and the source drive circuit being connected, and the source drive circuit being connected to the plurality of data lines;

[0028] The timing controller is configured to: acquire image data to be displayed, and control the source drive circuit to, when a portion of the data lines of at least two data lines coupled to the first pole of the data write transistor are disconnected, increase the initial data voltage corresponding to the target pixel unit and output it to at least the unconnected data lines connected to the target pixel unit, or output the initial data voltage corresponding to the target pixel unit to each of the data lines connected to the target pixel unit; wherein, the pixel unit where the data write transistor is located on the disconnected data line is the target pixel unit. Attached Figure Description

[0029] Figure 1 is a schematic diagram of the pixel circuit provided in an embodiment of this disclosure;

[0030] Figure 2 is a schematic diagram of the distribution of pixel circuits and data lines in a display panel in related technologies;

[0031] Figure 3 is a schematic diagram of some structures of the display panel provided in the embodiments of this disclosure;

[0032] Figure 4 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0033] Figure 5 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0034] Figure 6 is a schematic diagram of some structures of the display device provided in the embodiments of this disclosure;

[0035] Figure 7 is a schematic diagram of some structures of the pixel circuit provided in the embodiments of this disclosure;

[0036] Figure 8 is a schematic diagram of some structures of pixel unit column groups provided in the embodiments of this disclosure;

[0037] Figure 9 is a timing diagram of some signals of the pixel unit column group provided in the embodiments of this disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0040] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0041] Typically, a display panel may include multiple pixel units, each pixel unit including pixel circuitry and a light-emitting element connected to the pixel circuitry. For example, the pixel circuitry may include transistors and capacitors, and the interaction between the transistors and capacitors drives the connected light-emitting element to emit light.

[0042] For example, the light-emitting element may include: organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED), micro light-emitting diode (Micro LED), and mini light-emitting diode (Mini LED).

[0043] For example, as shown in Figure 1, the pixel circuit may include a 7T1C circuit, specifically including: two reset transistors M1 and M7, a scan transistor M2, a drive transistor M3, a data write transistor M4, two light-emitting control transistors M5 and M6, and a storage capacitor Cs. Specifically, the first terminal of the reset transistor M1 is coupled to the initial signal terminal Initial, the second terminal is coupled to the first node N1, and the control terminal is coupled to the reset signal terminal RESET. The first terminal of the scan transistor M2 is coupled to the first node N1, the second terminal is coupled to the second node N2, and the control terminal is coupled to the scan signal terminal Gate. The first terminal of the drive transistor M3 is coupled to the third node N3, the second terminal is coupled to the second node N2, and the control terminal is coupled to the first node N1. The first terminal of the data write transistor M4 is coupled to the data line Data, the second terminal is coupled to the third node N3, and the control terminal is coupled to the scan signal terminal Gate. The first terminal of the light-emitting control transistor M5 is coupled to the second power supply terminal Vdd, the second terminal is coupled to the third node N3, and the control terminal is coupled to the light-emitting control signal terminal EM. The first terminal of the light-emitting control transistor M6 is coupled to the second node N2, and the second terminal is coupled to the anode of the light-emitting element. Its control terminal is coupled to the light-emitting control signal terminal EM. The first terminal of the reset transistor M7 is coupled to the initial signal terminal Initial, and the second terminal is coupled to the anode of the light-emitting element. Its control terminal is coupled to the reset signal terminal RESET. The first plate of the storage capacitor Cs is coupled to the second power supply terminal Vdd, and the second plate is coupled to the first node N1.

[0044] For example, the reset transistor M1 is turned on when the RESET signal is active and turned off when the RESET signal is inactive. Optionally, as shown in Figure 1, the reset transistor M1 can be an N-type transistor, in which case the active level of the RESET signal is high and the inactive level is low. Of course, the reset transistor M1 can also be a P-type transistor, in which case the active level of the RESET signal is low and the inactive level is high.

[0045] For example, the scanning transistor M2 is turned on when the signal at the scanning signal terminal Gate is active, and turned off when the signal at the scanning signal terminal Gate is inactive. Optionally, as shown in Figure 1, the scanning transistor M2 can be configured as an N-type transistor, in which case the active signal level at the scanning signal terminal Gate is high, and the inactive signal level is low. Of course, the scanning transistor M2 can also be configured as a P-type transistor, in which case the active signal level at the scanning signal terminal Gate is low, and the inactive signal level is high.

[0046] For example, the driving transistor M3 is turned on under the control of the effective level of the signal at the first node N1, and turned off under the control of the ineffective level of the signal at the first node N1. Optionally, as shown in FIG1, the driving transistor M3 can be set as an N-type transistor, in which case the effective level of the signal at the first node N1 is a high level and the ineffective level is a low level. Of course, the driving transistor M3 can also be set as a P-type transistor, in which case the effective level of the signal at the first node N1 is a low level and the ineffective level is a high level.

[0047] For example, the data writing transistor M4 is turned on when the signal at the scan signal terminal Gate is active, and turned off when the signal at the scan signal terminal Gate is inactive. Optionally, as shown in Figure 1, the data writing transistor M4 can be configured as an N-type transistor, in which case the active signal level at the scan signal terminal Gate is high, and the inactive signal level is low. Of course, the data writing transistor M4 can also be configured as a P-type transistor, in which case the active signal level at the scan signal terminal Gate is low, and the inactive signal level is high.

[0048] For example, the light-emitting control transistor M5 is turned on under the control of the effective level of the light-emitting control signal terminal EM, and turned off under the control of the ineffective level of the light-emitting control signal terminal EM. Optionally, as shown in FIG1, the light-emitting control transistor M5 can be set as an N-type transistor, in which case the effective level of the light-emitting control signal terminal EM is a high level and the ineffective level is a low level. Of course, the light-emitting control transistor M5 can also be set as a P-type transistor, in which case the effective level of the light-emitting control signal terminal EM is a low level and the ineffective level is a high level.

[0049] For example, the light-emitting control transistor M6 is turned on under the control of the effective level of the light-emitting control signal terminal EM, and turned off under the control of the ineffective level of the light-emitting control signal terminal EM. Optionally, as shown in FIG1, the light-emitting control transistor M6 can be set as an N-type transistor, in which case the effective level of the light-emitting control signal terminal EM is high and the ineffective level is low. Of course, the light-emitting control transistor M6 can also be set as a P-type transistor, in which case the effective level of the light-emitting control signal terminal EM is low and the ineffective level is high.

[0050] For example, the reset transistor M7 is turned on when the reset signal at the RESET terminal is active and turned off when the reset signal at the RESET terminal is inactive. Optionally, as shown in Figure 1, the reset transistor M7 can be configured as an N-type transistor, in which case the active level of the RESET signal at the RESET terminal is high and the inactive level is low. Of course, the reset transistor M7 can also be configured as a P-type transistor, in which case the active level of the RESET signal at the RESET terminal is low and the inactive level is high.

[0051] In some embodiments of this disclosure, the first power supply terminal Vss can be configured to apply a constant first power supply voltage, which is generally ground voltage or a negative value. Similarly, the second power supply terminal Vdd can apply a constant second power supply voltage, which is generally a positive value. In practical applications, the specific values ​​of the first and second power supply voltages can be designed and determined according to the actual application environment, and are not limited herein.

[0052] In some embodiments of this disclosure, the first terminal of the transistor can be used as its source and the second terminal as its drain, depending on the type of the transistor and the signal at its control terminal; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. This can be designed and determined according to the actual application environment, and no specific distinction is made here.

[0053] The above are merely examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this disclosure and are not specifically limited here.

[0054] As shown in Figure 2, in the display panel, the pixel circuits in a column of pixel units are connected to a data line. When this data line is broken, the data writing transistor M4 in each pixel circuit connected after the break point will have no data voltage input, making it impossible for these pixel circuits to control the corresponding light-emitting elements to emit light, thus causing display abnormalities. However, during the manufacturing process, such as during exposure and development, foreign objects can easily cause data line breakage problems. Foreign object problems are difficult to avoid during the manufacturing process, and therefore, breakage problems are also difficult to avoid.

[0055] To address the aforementioned issues, the display panel provided in this embodiment connects each pixel circuit to at least two data lines. This ensures that when some data lines are disconnected, data voltage can be supplied to the pixel circuit through other unconnected data lines, thereby preventing display abnormalities from occurring on the display panel.

[0056] In this embodiment of the disclosure, as shown in FIG3, the display panel may include:

[0057] Multiple pixel units 1, each pixel unit 1 includes a pixel circuit 11, and the pixel circuit includes a data writing transistor T1;

[0058] Multiple data lines 2, the first electrode of the data writing transistor T1 in the pixel circuit 11 is coupled to at least two data lines 2.

[0059] The display panel provided in this embodiment of the present disclosure is coupled to at least two data lines through the first terminal of the data writing transistor in the pixel circuit. In this way, when some data lines are broken, data voltage can be provided to the pixel circuit through other unbroken data lines, ensuring that the data voltage can be written to the pixel circuit normally and avoiding display abnormalities of the display panel.

[0060] For example, when the data writing transistor T1 of the pixel circuit in the display panel is connected to the data line 2 in the manner shown in Figure 3, the image displayed on the display panel can be acquired by a CCD camera (charge coupled device, a digital camera with a charge coupled device image sensor) during the programming process. The acquired image is then subjected to brightness analysis. Based on the brightness analysis results, the presence or absence of open-circuit data lines and the location information of the open-circuit data lines are determined. Then, based on the location information of the open-circuit data lines, the open-circuit data lines are left floating, and the data voltage on the non-open-circuit data lines corresponding to the open-circuit data lines is compensated to avoid the problem of reduced data voltage caused by excessive resistance of the open-circuit data lines, thus ensuring that the pixel circuit can work normally.

[0061] The display panel provided in this embodiment, as shown in FIG4, may further include:

[0062] Multiple diodes 3 are connected to the data line 2 through at least one diode 3, wherein the positive terminal of the diode 3 is connected to the data line 2, and the negative terminal of the diode 3 is connected to the first terminal of the data writing transistor T1.

[0063] For example, as shown in FIG4, the first terminal of the data writing transistor T1 of each pixel circuit 11 can be connected to the data lines 21 and 22 respectively through a diode 3. That is, the first terminal of the data writing transistor T1 is connected to two diodes 31 and 32, and the data writing transistor T1 is connected to the negative terminals of the two diodes. The positive terminal of one of the two diodes 31 is connected to the data line 21, and the positive terminal of the other diode 32 is connected to the data line 22.

[0064] A diode is a PN junction formed by P-type and N-type semiconductors. The electrode leading from the P-region is the anode, and the electrode leading from the N-region is the cathode. When the data line is not open, the data voltage can be applied to the anode of the diode, the diode conducts, and the data voltage can be supplied to the first terminal of the data writing transistor. When the data line is open, the data voltage cannot be applied to the anode of the diode, the diode is cut off, and the data voltage cannot be supplied to the first terminal of the data writing transistor.

[0065] The display panel provided in this embodiment connects the first electrode of the data writing transistor to the data line via a diode. This enables the diode to conduct when the data line is not broken, providing the data voltage on the data line to the data writing transistor. When the data line is broken, the diode is cut off. This not only ensures that the data voltage can be written to the pixel circuit normally, but also prevents the data voltage on the unbroken data line from being lost due to the increased resistance of the broken data line, thus avoiding display abnormalities.

[0066] In some embodiments of this disclosure, as shown in FIG4, the plurality of pixel units 1 include a plurality of column groups 101, and the column group 101 includes two pixel units 1A and 1B that are adjacent along the row direction;

[0067] In column group 101, the first electrode of the data writing transistor T1 in each pixel unit 1 is coupled to the same data line 2. For example, as shown in FIG4, the first electrode of the data writing transistors in two pixel units 1A and 1B in column group 101 is coupled to data lines 21 and 22 respectively.

[0068] In some embodiments of this disclosure, data lines 2 are located between two adjacent pixel units in column group 101. For example, as shown in FIG4, data lines 21 and 22 are located between two adjacent pixel units 1A and 1B in column group 101.

[0069] In some embodiments of this disclosure, the pixel circuits in the same column of pixel units are coupled to the same data lines. For example, as shown in FIG4, the pixel circuits in the same column of pixel units are all coupled to data lines 21 and 22.

[0070] For example, multiple data lines in the display panel extend along the column direction and are arranged along the row direction. There are m data lines between every two columns of pixel units. For example, there are m data lines between the (2n-1)th column of pixel units and the 2nth column of pixel units in the display panel, where m is an integer not less than 2 and n is an integer not less than 1. The first pole of the data writing transistor of each pixel circuit in these two columns of pixel units is coupled to these m data lines.

[0071] For example, the display panel is provided with multiple first scan lines and multiple second scan lines; the multiple first scan lines extend along the row direction and are arranged along the column direction; the multiple second scan lines extend along the row direction and are arranged along the column direction; each row of pixel units corresponds to one first scan line and one second scan line, wherein the control terminal of each data writing transistor in the pixel units located in the odd-numbered columns of the row is connected to the first scan line, and the control terminal of each data writing transistor in the pixel units located in the even-numbered columns is connected to the second scan line.

[0072] In some embodiments of this disclosure, as shown in FIG4, the display panel may further include: a first scan line 4 and a second scan line 5.

[0073] As shown in Figure 4, the control terminal of the data writing transistor T1 of one pixel unit 1A in column group 101 is connected to the first scan line 4, and the control terminal of the data writing transistor of another pixel unit 1B is connected to the second scan line 5.

[0074] For example, the scanning signals provided by the first scan line 4 and the second scan line 5 are different. For instance, the scanning signal provided by the second scan line 5 is delayed by a set phase difference compared to the scanning signal provided by the first scan line 4. The set phase difference is the scanning time required for the pixel circuit connected to the first scan line 4 to input the data voltage. In this way, the two pixel circuits in the column group can stagger the time of writing the data voltage under the control of the first scan line and the second scan line, respectively, so as to achieve different display effects on the display panel.

[0075] In some embodiments of this disclosure, as shown in FIG4, in the same row of pixel units, the control terminals of the data writing transistors in the odd-numbered column pixel units are connected to the first scan line 4, and the control terminals of the data writing transistors in the even-numbered column pixel units are connected to the second scan line 5. This enables the data writing transistors in the odd-numbered column pixel units to simultaneously write data voltage under the control of the first scan line 4, and the data writing transistors in the even-numbered column pixel units to simultaneously write data voltage under the control of the second scan line 5. Furthermore, the odd and even columns can stagger the data voltage writing time.

[0076] In some embodiments of this disclosure, as shown in FIG5, the display panel may further include:

[0077] Substrate 100;

[0078] A semiconductor material layer 200 is located on one side of the substrate 100. The semiconductor material layer 200 includes a plurality of diode regions 201, and each diode region 201 includes a diode 3.

[0079] The conductive layer 300 is located on the side of the semiconductor material layer 200 away from the substrate 100. The conductive layer 300 includes a data line 2, which is connected to the positive electrode of the diode 3 in the diode region 201 through a connection hole 001.

[0080] In some embodiments of this disclosure, as shown in FIG5, the semiconductor material layer 200 may further include an active layer 202 of the data writing transistor T1, and the negative electrode of the diode 3 is connected to the active layer 202 of the data writing transistor T1.

[0081] For example, as shown in FIG5, the display panel may further include a first gate layer 400 and a second gate layer 500. The first gate layer 400 is located between the semiconductor material layer 200 and the conductive layer 300, and includes the gate 401 of the data writing transistor T1. The second gate layer 500 is located between the first gate layer 400 and the conductive layer 300, and includes a first scan line 4 and a second scan line 5. The first scan line 4 and the second scan line 5 are respectively connected to the gate 401 of the data writing transistor T1 through connection holes 002 and 003.

[0082] For example, as shown in FIG6, the display panel may include an initial signal line Initial, a reset control signal line RESET, a first scan line Gate1, a second scan line Gate2, an emissive control signal line EM, a second power supply voltage signal line Vdd, a data line Vdata, and a pixel circuit as shown in FIG1. ​​The first terminals of reset transistors M1 and M7 are coupled to the initial signal line Initial, which provides an initial signal. The gates of reset transistors M1 and M7 are respectively coupled to the reset control signal line RESET, which provides a reset control signal. The gates of scan transistor M2 and data write transistor M4 in the left pixel circuit are respectively coupled to the first scan line Gate1, and the gates of scan transistor M2 and data write transistor M4 in the right pixel circuit are respectively coupled to the second scan line Gate2. The first scan line Gate1 and the second scan line Gate2 provide scan signals. The gates of emissive control transistors M5 and M6 are respectively coupled to the emissive control signal line EM, which provides an emissive control signal. The first terminal of the LED control transistor M5 and the first plate of the storage capacitor are coupled to the second power supply voltage signal line Vdd, which provides the second power supply voltage. The positive terminal of the diode is coupled to the data line Vdata, which provides the data voltage.

[0083] This disclosure also provides a display device, as shown in FIG7, including the above-described display panel DP.

[0084] In some embodiments of this disclosure, as shown in FIG7, the display device may further include a timing controller 6 and a source drive circuit 7. The timing controller 6 and the source drive circuit 7 are connected, and the source drive circuit 7 is connected to multiple data lines 2;

[0085] The timing controller 6 is configured to: acquire image data to be displayed, and control the source drive circuit 7 to increase the initial data voltage corresponding to the target pixel unit and output it to at least the unbroken data line connected to the target pixel unit when some of the data lines of at least two data lines coupled to the first pole of the data writing transistor are disconnected; or, output the initial data voltage corresponding to the target pixel unit to each data line connected to the target pixel unit; wherein the pixel unit where the data writing transistor is located connected to the disconnected data line is the target pixel unit.

[0086] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0087] The following describes the working process of the column group provided in the embodiments of this disclosure, taking column group 101 shown in Figure 8 as an example and referring to the signal timing diagram shown in Figure 9.

[0088] As shown in Figure 8, column group 101 includes two pixel units, and each pixel unit may include a 7T1C pixel circuit as shown in Figure 1. The first terminal of the data writing transistor M4 in each pixel circuit is coupled to the negative terminal of diodes 31 and 32, and the positive terminals of diodes 31 and 32 are coupled to data lines 21 and 22, respectively.

[0089] Specifically, stages T1, T2, T3, and T4 are selected from the signal timing diagram shown in Figure 9. It should be noted that the signal timing diagram shown in Figure 9 only represents the operation of a single column group within one frame. The operation of this column group in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0090] In the first stage T1, the reset signal at the reset terminal is high, the gate1 signal at the first scan terminal is low, the gate2 signal at the second scan terminal is low, and the em signal at the light emission control terminal is low.

[0091] Under the control of the reset signal at the reset signal terminal, the reset transistors M1 and M7 in the pixel circuits distributed on the left and right sides of the data lines 21 and 22 are turned on, providing the Initial signal at the Initial signal terminal to the first node N1 and the anode of the light-emitting element, thereby charging and resetting the storage capacitor Cs and the light-emitting element.

[0092] In the second stage T2, the reset signal at the reset terminal is low, the gate1 signal at the first scan terminal is high, the gate2 signal at the second scan terminal is low, and the em signal at the light emission control terminal is low.

[0093] Under the control of signal gate1 at the scanning signal terminal, the scanning transistor M2 and data writing transistor M4 in the pixel circuit distributed on the left side of data lines 21 and 22 are turned on. At the same time, under the storage effect of storage capacitor Cs, the first node can maintain the high level of the previous stage, control the driving transistor M3 to turn on, and the turned scanning transistor M2, driving transistor M3, and data writing transistor M4 provide the data voltage on the two data lines Data to the storage capacitor Cs.

[0094] In the third stage T3, the reset signal at the reset terminal is low, the gate1 signal at the first scan terminal is low, the gate2 signal at the second scan terminal is high, and the em signal at the light emission control terminal is low.

[0095] Under the control of signal gate2 at the scanning signal terminal, the scanning transistor M2 and data writing transistor M4 in the pixel circuit distributed on the right side of data lines 21 and 22 are turned on. At the same time, under the storage effect of storage capacitor Cs, the first node can maintain the high level of the previous stage, control the driving transistor M3 to turn on, and the turned-on scanning transistor M2, driving transistor M3, and data writing transistor M4 provide the data voltage on the two data lines Data to the storage capacitor Cs.

[0096] In the fourth stage T4, the reset signal at the reset terminal is low, the gate1 signal at the first scan terminal is low, the gate2 signal at the second scan terminal is low, and the em signal at the light emission control terminal is high.

[0097] Under the control of the signal em at the light emission control signal terminal, the light emission control transistors M5 and M6 in the pixel circuits distributed on the left and right sides of the data lines 21 and 22 are turned on. At the same time, due to the storage effect of the storage capacitor Cs, the first node N1 is kept at a high level, controlling the driving transistor M3 to turn on. The turned-on light emission control transistor M5, driving transistor M3, and light emission control transistor M7 provide the signal of the second power supply terminal Vdd to the anode of the light emission element, controlling the light emission element to emit light.

[0098] For the display panel shown in Figure 3, when some of the data lines in the data lines electrically connected to the pixel circuit are broken, the increased resistance of the broken data lines will cause the data voltage on the other unbroken data lines to decrease, resulting in insufficient data voltage written to the pixel circuit. This causes the pixel circuit to malfunction and the display panel to exhibit display abnormalities.

[0099] To address the aforementioned problems, this disclosure provides a data voltage driving method, which may include the following steps:

[0100] Acquire the image data to be displayed, which includes the initial data voltage corresponding to each pixel unit;

[0101] When a portion of the data lines of at least two data lines coupled to the first electrode of the data writing transistor are disconnected, the pixel unit where the data writing transistor is located, connected to the disconnected data line, is taken as the target pixel unit. The initial data voltage corresponding to the target pixel unit is increased and then output to at least the unconnected data line connected to the target pixel unit.

[0102] For example, the initial data voltage can be increased by a preset value and then output to the unbroken data line connected to the target pixel unit, while no data voltage is output to the broken data line connected to the target pixel unit; alternatively, the initial data voltage can be increased by a preset value and then output to all data lines connected to the target pixel unit. The preset value can be designed and determined according to the actual application environment, and no limitation is made here.

[0103] The data voltage driving method provided in this embodiment can boost the data voltage output to the unbroken data line to avoid the problem of reduced data voltage caused by the loss of some voltage due to the increased resistance of the broken data line. This ensures that the pixel circuit can work normally and avoids display abnormalities on the display panel.

[0104] For the display panel shown in Figure 4, when some data lines in the data lines electrically connected to the pixel circuit are open-circuited, the positive terminal of the diode connected to these data lines is not loaded with data voltage, the diode is cut off, and the data voltage of the unopened data lines will not suffer voltage loss, and can continue to be provided to the unopened data lines with the original initial data voltage. In this regard, another data voltage driving method provided by the embodiments of this disclosure, applied to the display panel shown in Figure 4, may include the following steps:

[0105] Acquire the image data to be displayed, which includes the initial data voltage corresponding to each pixel unit;

[0106] When a portion of the data lines of at least two data lines coupled to the first electrode of the data writing transistor are disconnected, the pixel unit where the data writing transistor is located is the target pixel unit, and the initial data voltage corresponding to the target pixel unit is output to each data line connected to the target pixel unit.

[0107] The display panel and display device, and the data voltage driving method provided in this disclosure embodiment are coupled to at least two data lines through the first terminal of the data writing transistor in the pixel circuit. So that when some data lines are broken, data voltage can be provided to the pixel circuit through other unbroken data lines, ensuring that the data voltage can be written to the pixel circuit normally and avoiding display abnormalities of the display panel.

[0108] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0109] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, include: Multiple pixel units, each pixel unit including a pixel circuit, the pixel circuit including a data writing transistor; Multiple data lines, wherein the first electrode of the data writing transistor in the pixel circuit is coupled to at least two of the data lines.

2. The display panel as claimed in claim 1, wherein, Also includes: A plurality of diodes are provided, wherein the first terminal of the data writing transistor is connected to the data line through at least one of the diodes, wherein the positive terminal of the diode is connected to the data line and the negative terminal of the diode is connected to the first terminal of the data writing transistor.

3. The display panel as described in claim 2, wherein, The plurality of pixel units include a plurality of column groups, and the column group includes two pixel units that are adjacent along the row direction; The data lines coupled to the first pole of the data write transistor in each pixel unit of the column group are the same.

4. The display panel as claimed in claim 3, wherein, The data line is located between two adjacent pixel units in the column group.

5. The display panel as claimed in claim 4, wherein, The data lines coupled to the pixel circuits in the same column of pixel units are the same.

6. The display panel as described in any one of claims 3-5, wherein, Also includes: The first scan line and the second scan line are provided, wherein the control terminal of the data writing transistor of one pixel unit in the column group is connected to the first scan line, and the control terminal of the data writing transistor of the other pixel unit is connected to the second scan line.

7. The display panel as claimed in claim 6, wherein, In the same row of pixel units, the control terminal of the data writing transistor in the odd-numbered column pixel units is connected to the first scan line, and the control terminal of the data writing transistor in the even-numbered column pixel units is connected to the second scan line.

8. The display panel according to any one of claims 2-7, wherein, Also includes; Substrate; A semiconductor material layer is located on one side of the substrate, the semiconductor material layer includes a plurality of diode regions, and the diode regions include the diodes; A conductive layer is located on the side of the semiconductor material layer opposite to the substrate. The conductive layer includes the data line, which is connected to the positive terminal of the diode in the diode region through a connection hole.

9. The display panel as claimed in claim 8, wherein, The semiconductor material layer further includes the active layer of the data writing transistor, and the negative electrode of the diode is connected to the active layer of the data writing transistor.

10. A data voltage driving method for a display panel as described in any one of claims 1-9, wherein, include: Acquire image data to be displayed, wherein the image data to be displayed includes the initial data voltage corresponding to each pixel unit; When a portion of the data lines of at least two data lines coupled to the first pole of the data writing transistor are disconnected, the pixel unit where the data writing transistor is located, connected to the disconnected data line, is taken as the target pixel unit. The initial data voltage corresponding to the target pixel unit is increased and then output to at least the unconnected data line connected to the target pixel unit.

11. A data voltage driving method for a display panel as described in any one of claims 2-9, wherein, include: Acquire image data to be displayed, wherein the image data to be displayed includes the initial data voltage corresponding to each pixel unit; When a portion of the data lines of at least two data lines coupled to the first pole of the data writing transistor are disconnected, the pixel unit where the data writing transistor is located is the target pixel unit, and the initial data voltage corresponding to the target pixel unit is output to each of the data lines connected to the target pixel unit.

12. A display device, wherein, Includes the display panel as described in any one of claims 1-9.

13. The display device as claimed in claim 12, wherein, It also includes a timing controller and a source drive circuit, wherein the timing controller and the source drive circuit are connected, and the source drive circuit is connected to the multiple data lines; The timing controller is configured to: acquire image data to be displayed, and control the source drive circuit to, when a portion of the data lines of at least two data lines coupled to the first pole of the data write transistor are disconnected, increase the initial data voltage corresponding to the target pixel unit and output it to at least the unconnected data lines connected to the target pixel unit, or output the initial data voltage corresponding to the target pixel unit to each of the data lines connected to the target pixel unit; wherein, the pixel unit where the data write transistor is located on the disconnected data line is the target pixel unit.

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