Information transmission method and apparatus

Abstract

The present application provides an information transmission method and apparatus, which are capable of reducing decoding latency of information at a receiving end. The method comprises: a first communication apparatus obtaining a parity-check matrix according to a first LDPC matrix, a first expansion factor, and a shift value corresponding to the first LDPC matrix, wherein any first shift value in a first shift value set corresponding to a first element and any second shift value in a second shift value set corresponding to a second element satisfy at least one of a first condition or a second condition, the first element and the second element are two non-zero elements located in adjacent rows and the same column in the first LDPC matrix, and the first LDPC matrix is a base matrix or a matrix obtained by lifting the base matrix; the first communication apparatus sending, to a second communication apparatus, information encoded by using the parity-check matrix, and the second communication apparatus decoding, on the basis of the parity-check matrix, received information to be decoded, so as to obtain a decoded bit sequence.

Description

Methods and apparatus for information transmission

[0001] This application claims priority to Chinese Patent Application No. 202411996400.2, filed with the State Intellectual Property Office of the People's Republic of China on December 31, 2024, entitled "Method and Apparatus for Information Transmission", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more specifically, to a method and apparatus for information transmission. Background Technology

[0003] Low-density parity check (LDPC) is a channel coding scheme that closely resembles the Shannon line. It features high performance and low complexity and has been selected by the 3rd Generation Partnership Project (3GPP) as the coding and decoding scheme for data channels in 5th generation (5G) communication.

[0004] The current LDPC encoding scheme has a relatively large decoding delay, and how to reduce the LDPC decoding delay is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a method and apparatus for information transmission, which can reduce the decoding delay of information at the receiving end.

[0006] In a first aspect, a method for transmitting information is provided. This method can be applied to a first communication device, for example, executed by the first communication device. The first communication device can be a network device or a module (e.g., a circuit, chip, chip system, or processor) in a network device, or a logical node, logical module, or software capable of implementing all or part of the functions of the network device. Alternatively, the first communication device can be a terminal device or a module (e.g., a circuit, chip, chip system, or processor) in a terminal device, or a logical node, logical module, or software capable of implementing all or part of the functions of the terminal device.

[0007] The method includes: obtaining a parity check matrix based on a first low-density parity check (LDPC) matrix, a first expansion factor, and shift values ​​corresponding to the first LDPC matrix; wherein any first shift value in the set of first shift values ​​corresponding to the first element and any second shift value in the set of second shift values ​​corresponding to the second element satisfy at least one of a first condition or a second condition; the first element and the second element are two elements in the first LDPC matrix that are row-adjacent, column-adjacent, and both non-zero; the first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix; the first condition is associated with the first shift value, the second shift value, the first expansion factor, and a first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and a second parameter, wherein the second parameter is an integer greater than or equal to 3; and sending information encoded using the parity check matrix.

[0008] Based on the above technical solution, after receiving the information to be decoded (information encoded using a parity check matrix), the second communication device decodes the information using the parity check matrix to obtain the decoded bit sequence. Since any first shift value in the set of first shift values ​​corresponding to the first element and any second shift value in the set of second shift values ​​corresponding to the second element satisfy at least one of the first or second conditions, the orthogonality of the parity check matrix is ​​improved. Therefore, the decoding delay of the second communication device for the information to be decoded can be reduced, thereby improving the decoding throughput.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the second condition is associated with the first shift value, the second shift value, the second parameter, and a third parameter, wherein the third parameter is an integer.

[0010] In conjunction with the first aspect, in certain implementations of the first aspect, any one of the first shift values ​​in the first shift value set corresponding to the first element includes: the first shift value corresponding to the first element; any one of the second shift values ​​in the second shift value set corresponding to the second element includes: the second shift value corresponding to the second element. In this implementation, the first shift value set includes only one first shift value, and the second shift value set includes only one second shift value.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, obtaining the parity check matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix includes: obtaining a second LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix, wherein the first LDPC matrix is ​​the base matrix; and obtaining the parity check matrix based on the second LDPC matrix, the second expansion factor, and the shift value corresponding to the second LDPC matrix. Optionally, the first communication device can perform a single boost on the base matrix to obtain the parity check matrix, or the first communication device can perform two boosts on the base matrix to obtain the parity check matrix; in this implementation, the parity check matrix is ​​obtained by performing two boosts on the base matrix.

[0012] In conjunction with the first aspect, some implementations of the first aspect further include: promoting the elements with a value of 1 in the base matrix to an a-row, b-column matrix of all 1s, and promoting the elements with a value of 0 in the base matrix to an a-row, b-column matrix of 0s, thereby obtaining the first LDPC matrix. In this implementation, the parity check matrix is ​​obtained by performing two promotions on the base matrix.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, Zc is the first expansion factor or the maximum value in the set of expansion factors corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the first condition includes: SV2-SV1+1-2t0≠0mod(Zc), or SV2-SV1+1-2t0≥1mod(Zc), or SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, and t0 is the first parameter.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, t0 is 1, 2, or 3, or t0 is an integer related to Zc.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, or, Where n is an integer greater than or equal to 2.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the second condition includes: SV1 = (SV2 + x) mod (y); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, y is the second parameter, and x is a third parameter, wherein the third parameter is an integer. For example, if x = 0, the second condition includes: SV1 = SV2 mod (y).

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the first element and the second element are two elements in the first column set of the first LDPC matrix that are adjacent in row, have the same column, and are both non-zero. Exemplarily, the first column set includes a subset of the columns of the first LDPC matrix; exemplarily, the first column set includes all columns of the first LDPC matrix. When the first column set includes a subset of the columns of the first LDPC matrix, some columns of the parity check matrix can satisfy the orthogonality condition, which can reduce decoding latency and improve decoding throughput. When the first column set includes all columns of the first LDPC matrix, all columns of the parity check matrix can satisfy the orthogonality condition, resulting in the lowest decoding latency and the highest decoding throughput.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the first column set includes the information column corresponding to the first LDPC matrix, or the core column corresponding to the first LDPC matrix, or all columns corresponding to the first LDPC matrix except for the punched column. Based on this implementation, decoding latency can be reduced without sacrificing decoding performance.

[0020] Secondly, a method for transmitting information is provided. This method can be applied to a second communication device, such as being executed by the second communication device. The second communication device can be a terminal device or a module (e.g., a circuit, chip, chip system, or processor) in the terminal device, or a logical node, logical module, or software capable of implementing all or part of the functions of the terminal device. Alternatively, the second communication device can be a network device or a module (e.g., a circuit, chip, chip system, or processor) in the network device, or a logical node, logical module, or software capable of implementing all or part of the functions of the network device.

[0021] The method includes: receiving information to be decoded; decoding the information to be decoded based on a parity check matrix to obtain a decoded bit sequence, wherein the parity check matrix is ​​obtained based on a first LDPC matrix, a first expansion factor, and shift values ​​corresponding to the first LDPC matrix; any first shift value in the set of first shift values ​​corresponding to a first element and any second shift value in the set of second shift values ​​corresponding to a second element satisfy at least one of a first condition or a second condition; the first element and the second element are two elements in the first LDPC matrix that are adjacent in rows, have the same column, and are both non-zero; the first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix; the first condition is associated with the first shift value, the second shift value, the first expansion factor, and a first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and a second parameter, wherein the second parameter is an integer greater than or equal to 3.

[0022] The method provided in the second aspect is the method on the second access network device side corresponding to the first aspect, and its beneficial effects can be referred to the first aspect.

[0023] In conjunction with the second aspect, in some implementations of the second aspect, the second condition is associated with the first shift value, the second shift value, the second parameter, and a third parameter, wherein the third parameter is an integer.

[0024] In conjunction with the second aspect, in some implementations of the second aspect, any first shift value in the first shift value set corresponding to the first element includes: the first shift value corresponding to the first element; any second shift value in the second shift value set corresponding to the second element includes: the second shift value corresponding to the second element.

[0025] In conjunction with the second aspect, in some implementations of the second aspect, -t1+1-SV1≠t2-SV2mod(Zc); where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0026] In conjunction with the second aspect, in some implementations of the second aspect, SV2-SV1+1-2t0≠0mod(Zc), or SV2-SV1+1-2t0≥1mod(Zc), or SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, and t0 is the first parameter.

[0027] In conjunction with the second aspect, in some implementations of the second aspect, t0 is 1, 2, or 3, or t0 is an integer related to Zc.

[0028] In conjunction with the second aspect, in some implementations of the second aspect, or, Where n is an integer greater than or equal to 2.

[0029] In conjunction with the second aspect, in some implementations of the second aspect, SV1 = (SV2 + x) mod (y); where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0030] In conjunction with the second aspect, in some implementations of the second aspect, the first element and the second element are two elements in the first column set of the first LDPC matrix that are adjacent in row, have the same column, and are both non-zero.

[0031] In conjunction with the second aspect, in some implementations of the second aspect, the first column set includes the information column corresponding to the first LDPC matrix, or the core column corresponding to the first LDPC matrix, or all columns corresponding to the first LDPC matrix except for the punched column.

[0032] Thirdly, a method for transmitting information is provided. This method can be applied to a first communication device, for example, executed by the first communication device. The first communication device can be a network device or a module (e.g., a circuit, chip, chip system, or processor) in a network device, or a logical node, logical module, or software capable of implementing all or part of the functions of the network device; or, the first communication device can be a terminal device or a module (e.g., a circuit, chip, chip system, or processor) in a terminal device, or a logical node, logical module, or software capable of implementing all or part of the functions of the terminal device.

[0033] The method includes: obtaining a second LDPC matrix based on a first LDPC matrix, a first expansion factor, and a shift value corresponding to the first LDPC matrix, wherein each zero element in the first LDPC matrix corresponds to a zero matrix in the second LDPC matrix, and each non-zero element in the first LDPC matrix corresponds to a non-zero matrix in the second LDPC matrix; shifting the elements of the non-zero matrices in the second LDPC matrix to obtain a check matrix, wherein the check matrix includes multiple block matrices, each block matrix corresponding one-to-one with the non-zero matrices, and each block matrix is ​​composed of multiple sub-matrices, wherein the sub-matrices are zero matrices or have row and column weights. Both are cyclic shift matrices with values ​​of 1. The shift values ​​corresponding to the first and second cyclic shift matrices satisfy at least one of a first condition or a second condition. The first and second cyclic shift matrices are two cyclic shift matrices that are row-adjacent and have the same columns in the block matrix. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and a first parameter, where the first parameter is an integer greater than or equal to 1. The second condition is associated with the first shift value, the second shift value, and a second parameter, where the second parameter is an integer greater than or equal to 3. The information encoded using the check matrix is ​​then sent.

[0034] Based on the above technical solution, after receiving the information to be decoded (information encoded using a parity-check matrix), the second communication device decodes the information using the parity-check matrix to obtain the decoded bit sequence. Because the orthogonality of the parity-check matrix is ​​improved, the decoding delay of the second communication device on the information to be decoded can be reduced, thereby increasing the decoding throughput.

[0035] In conjunction with the third aspect, in some implementations of the third aspect, the second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer.

[0036] In conjunction with the third aspect, in some implementations of the third aspect, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0037] In conjunction with the third aspect, in some implementations of the third aspect, the first condition includes: SV4-SV3+1-2t0≠0mod(Zc'), or SV4-SV3+1-2t0≥1mod(Zc'), or SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, and t0 is the first parameter.

[0038] In conjunction with the third aspect, in some implementations of the third aspect, t0 is 1, 2, or 3, or t0 is an integer related to Zc'.

[0039] In conjunction with the third aspect, in some implementations of the third aspect, or, Where n is an integer greater than or equal to 2.

[0040] In conjunction with the third aspect, in some implementations of the third aspect, the second condition includes: SV3 = (SV4 + x) mod (y); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0041] Fourthly, a method for transmitting information is provided. This method can be applied to a second communication device, such as being executed by the second communication device. The second communication device can be a terminal device or a module (e.g., a circuit, chip, chip system, or processor) in the terminal device, or a logical node, logical module, or software capable of implementing all or part of the functions of the terminal device; or, the second communication device can be a network device or a module (e.g., a circuit, chip, chip system, or processor) in the network device, or a logical node, logical module, or software capable of implementing all or part of the functions of the network device.

[0042] The method includes: receiving information to be decoded; decoding the information to be decoded based on a parity check matrix to obtain a decoded bit sequence, wherein the parity check matrix includes multiple block matrices, each block matrix having a one-to-one correspondence with a non-zero matrix, each block matrix being composed of multiple sub-matrices, each sub-matrice being a zero matrix or a cyclic shift matrix with both row and column weights of 1, wherein the shift value corresponding to a first cyclic shift matrix and the shift value corresponding to a second cyclic shift matrix satisfy at least one of a first condition or a second condition, wherein the first cyclic shift matrix and the second cyclic shift matrix are two cyclic shift matrices that are row-adjacent and have the same columns in the block matrix; the first condition is associated with the first shift value, the second shift value, the first expansion factor, and a first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and a second parameter, wherein the second parameter is an integer greater than or equal to 3.

[0043] The method provided in the fourth aspect is the same as the method on the second access network device side corresponding to the third aspect, and its beneficial effects can be referred to the third aspect.

[0044] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer.

[0045] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0046] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first condition includes: SV4-SV3+1-2t0≠0mod(Zc'), or SV4-SV3+1-2t0≥1mod(Zc'), or SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, and t0 is the first parameter.

[0047] In conjunction with the fourth aspect, in some implementations of the fourth aspect, t0 is 1, 2, or 3, or t0 is an integer related to Zc'.

[0048] In conjunction with the fourth aspect, in some implementations of the fourth aspect, or, Where n is an integer greater than or equal to 2.

[0049] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the second condition includes: SV3 = (SV4 + x) mod (y); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0050] Fifthly, a communication device is provided, which can be the first communication device described in the first aspect. The communication device includes: a processing module, configured to obtain a parity check matrix based on a first low-density parity check (LDPC) matrix, a first expansion factor, and shift values ​​corresponding to the first LDPC matrix, wherein any first shift value in the set of first shift values ​​corresponding to a first element and any second shift value in the set of second shift values ​​corresponding to a second element satisfy at least one of a first condition or a second condition; the first element and the second element are two elements in the first LDPC matrix that are row-adjacent, column-adjacent, and both non-zero; the first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix; the first condition is associated with the first shift value, the second shift value, the first expansion factor, and a first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and a second parameter, wherein the second parameter is an integer greater than or equal to 3; and a transceiver module, configured to transmit information encoded using the parity check matrix.

[0051] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer.

[0052] In conjunction with the fifth aspect, in some implementations of the fifth aspect, any first shift value in the first shift value set corresponding to the first element includes: the first shift value corresponding to the first element; any second shift value in the second shift value set corresponding to the second element includes: the second shift value corresponding to the second element.

[0053] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the processing module is specifically used to: obtain a second LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix, wherein the first LDPC matrix is ​​the base matrix; and obtain the parity check matrix based on the second LDPC matrix, the second expansion factor, and the shift value corresponding to the second LDPC matrix.

[0054] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the processing module is further configured to promote the elements with a value of 1 in the base matrix to a matrix of all 1s in rows a and b columns, and promote the elements with a value of 0 in the base matrix to a matrix of 0s in rows a and b columns, thereby obtaining the first LDPC matrix.

[0055] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, Zc is the first expansion factor or the maximum value in the set of expansion factors corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0056] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the first condition includes: SV2-SV1+1-2t0≠0mod(Zc), or SV2-SV1+1-2t0≥1mod(Zc), or SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, and t0 is the first parameter.

[0057] In conjunction with the fifth aspect, in some implementations of the fifth aspect, t0 is 1, 2, or 3, or t0 is an integer related to Zc.

[0058] In conjunction with the fifth aspect, in some implementations of the fifth aspect, or, Where n is an integer greater than or equal to 2.

[0059] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the second condition includes: SV1 = (SV2 + x) mod (y); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0060] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the first element and the second element are two elements in the first column set of the first LDPC matrix that are adjacent in row, have the same column, and are both non-zero.

[0061] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the first column set includes the information column corresponding to the first LDPC matrix, or the core column corresponding to the first LDPC matrix, or all columns corresponding to the first LDPC matrix except for the punched column.

[0062] In a sixth aspect, a communication device is provided, which can be the second communication device described in the second aspect. The communication device includes: a transceiver module for receiving information to be decoded; and a processing module for decoding the information to be decoded based on a parity check matrix to obtain a decoded bit sequence. The parity check matrix is ​​obtained based on a first LDPC matrix, a first expansion factor, and shift values ​​corresponding to the first LDPC matrix. Any first shift value in the set of first shift values ​​corresponding to a first element and any second shift value in the set of second shift values ​​corresponding to a second element satisfy at least one of a first condition or a second condition. The first element and the second element are two elements in the first LDPC matrix that are row-adjacent, column-adjacent, and both non-zero. The first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and a first parameter, where the first parameter is an integer greater than or equal to 1. The second condition is associated with the first shift value, the second shift value, and a second parameter, where the second parameter is an integer greater than or equal to 3.

[0063] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer.

[0064] In conjunction with the sixth aspect, in some implementations of the sixth aspect, any first shift value in the first shift value set corresponding to the first element includes: the first shift value corresponding to the first element; any second shift value in the second shift value set corresponding to the second element includes: the second shift value corresponding to the second element.

[0065] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, Zc is the first expansion factor or the maximum value in the set of expansion factors corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0066] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the first condition includes: SV2-SV1+1-2t0≠0mod(Zc), or SV2-SV1+1-2t0≥1mod(Zc), or SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, Zc is the first expansion factor or the maximum value in the set of expansion factors corresponding to the first expansion factor, and t0 is the first parameter.

[0067] In conjunction with the sixth aspect, in some implementations of the sixth aspect, t0 is 1, 2, or 3, or t0 is an integer related to Zc.

[0068] In conjunction with the sixth aspect, in some implementations of the sixth aspect, or, Where n is an integer greater than or equal to 2.

[0069] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the second condition includes: SV1 = (SV2 + x) mod (y); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0070] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the first element and the second element are two elements in the first column set of the first LDPC matrix that are adjacent in row, have the same column, and are both non-zero.

[0071] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the first column set includes the information column corresponding to the first LDPC matrix, or the core column corresponding to the first LDPC matrix, or all columns corresponding to the first LDPC matrix except for the punched column.

[0072] In a seventh aspect, a communication device is provided, which can be the first communication device described in the third aspect. The communication device includes: a processing module, configured to obtain a second LDPC matrix based on a first LDPC matrix, a first expansion factor, and a shift value corresponding to the first LDPC matrix, wherein each zero element in the first LDPC matrix corresponds to a zero matrix in the second LDPC matrix, and each non-zero element in the first LDPC matrix corresponds to a non-zero matrix in the second LDPC matrix.

[0073] The processing module is further configured to shift the elements of the non-zero matrix in the second LDPC matrix to obtain a parity check matrix. The parity check matrix includes multiple block matrices, each block matrix corresponding one-to-one with the non-zero matrix. Each block matrix is ​​composed of multiple sub-matrices, which are either zero matrices or cyclic shift matrices with row and column weights of 1. The shift value corresponding to the first cyclic shift matrix and the shift value corresponding to the second cyclic shift matrix satisfy at least one of a first condition or a second condition. The first cyclic shift matrix and the second cyclic shift matrix are two cyclic shift matrices in the block matrix that are row-adjacent and have the same columns. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and a first parameter, where the first parameter is an integer greater than or equal to 1. The second condition is associated with the first shift value, the second shift value, and a second parameter, where the second parameter is an integer greater than or equal to 3. The transceiver module is configured to send information encoded using the parity check matrix.

[0074] In conjunction with the seventh aspect, in some implementations of the seventh aspect, the second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer.

[0075] In conjunction with the seventh aspect, in some implementations of the seventh aspect, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0076] In conjunction with the seventh aspect, in some implementations of the seventh aspect, the first condition includes: SV4-SV3+1-2t0≠0mod(Zc'), or SV4-SV3+1-2t0≥1mod(Zc'), or SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, and t0 is the first parameter.

[0077] In conjunction with the seventh aspect, in some implementations of the seventh aspect, t0 is 1, 2, or 3, or t0 is an integer related to Zc'.

[0078] In conjunction with the seventh aspect, in some implementations of the seventh aspect, or, Where n is an integer greater than or equal to 2.

[0079] In conjunction with the seventh aspect, in some implementations of the seventh aspect, the second condition includes: SV3 = (SV4 + x) mod (y); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0080] Eighthly, a communication device is provided, which can be the second communication device described in the fourth aspect. The communication device includes: a transceiver module for receiving information to be decoded; and a processing module for decoding the information to be decoded based on a parity check matrix to obtain a decoded bit sequence. The parity check matrix includes multiple block matrices, each block matrix corresponding one-to-one with a non-zero matrix. Each block matrix is ​​composed of multiple sub-matrices, each sub-matrice being a zero matrix or a cyclic shift matrix with a row weight and a column weight of 1. The shift value corresponding to a first cyclic shift matrix and the shift value corresponding to a second cyclic shift matrix satisfy at least one of a first condition or a second condition. The first cyclic shift matrix and the second cyclic shift matrix are two cyclic shift matrices that are row-adjacent and have the same columns in the block matrix. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and a first parameter, wherein the first parameter is an integer greater than or equal to 1. The second condition is associated with the first shift value, the second shift value, and a second parameter, wherein the second parameter is an integer greater than or equal to 3.

[0081] In conjunction with the eighth aspect, in some implementations of the eighth aspect, the second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer.

[0082] In conjunction with the eighth aspect, in some implementations of the eighth aspect, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0083] In conjunction with the eighth aspect, in some implementations of the eighth aspect, the first condition includes: SV4-SV3+1-2t0≠0mod(Zc'), or SV4-SV3+1-2t0≥1mod(Zc'), or SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, and t0 is the first parameter.

[0084] In conjunction with the eighth aspect, in some implementations of the eighth aspect, t0 is 1, 2, or 3, or t0 is an integer related to Zc'.

[0085] In conjunction with the eighth aspect, in some implementations of the eighth aspect, or, Where n is an integer greater than or equal to 2.

[0086] In conjunction with the eighth aspect, in some implementations of the eighth aspect, the second condition includes: SV3 = (SV4 + x) mod (y); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0087] A ninth aspect provides a communication device comprising: a processor configured to implement the methods of the first to fourth aspects or any possible implementation thereof. Optionally, the communication device further comprises an interface circuit configured to receive signals from other communication devices and transmit them to the processor, or to send signals from the processor to other communication devices.

[0088] In a tenth aspect, a communication system is provided, comprising a first communication device for performing the method as described in the first aspect, and a second communication device for performing the method as described in the second aspect; or, comprising a first communication device for performing the method as described in the third aspect, and a second communication device for performing the method as described in the fourth aspect.

[0089] Eleventhly, a computer-readable storage medium is provided, the computer-readable medium storing a computer program; when the computer program is executed by a processor, the methods in the first to fourth aspects or any possible implementation of the first to fourth aspects are performed.

[0090] In a twelfth aspect, a computer program product is provided, the computer program product comprising a computer program that, when executed, causes the methods of the first to fourth aspects or any possible implementation thereof to be performed.

[0091] The solutions provided in aspects five through twelfth above are used to implement or cooperate with the methods provided in aspects one, two, three or four above, and therefore can achieve the same or corresponding beneficial effects as aspects one, two, three or four, which will not be elaborated here. Attached Figure Description

[0092] Figure 1 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application;

[0093] Figure 2 is an example diagram of an open radio access network (open RAN, O-RAN, or ORAN) system;

[0094] Figure 3 is a schematic diagram of the information transmission process applicable to an embodiment of this application;

[0095] Figure 4 is a schematic diagram of the matrix structure of the basis matrix of 5G LDPC code;

[0096] Figure 5 is a schematic diagram of the matrix regions corresponding to different code rates;

[0097] Figure 6 is a schematic flowchart of an information transmission method provided in an embodiment of this application;

[0098] Figure 7 is a comparison example of the first shift value and the second shift value satisfying the first condition and not satisfying the first condition;

[0099] Figure 8 is a schematic diagram of expanding element 2 in the first LDPC matrix into multiple cyclic shift matrices and then adding them together;

[0100] Figure 9 is an example diagram of a two-stage boosting of the first LDPC matrix according to an embodiment of this application;

[0101] Figure 10 is an example diagram of a two-stage lifting of the basis matrix according to an embodiment of this application;

[0102] Figure 11 is a schematic diagram comparing the relationship between the number of chip cycles required by the second communication device in 5G and the embodiment of this application to decode the information to be decoded and the code rate of the information to be decoded.

[0103] Figure 12 is a schematic flowchart of another information transmission method provided in an embodiment of this application;

[0104] Figure 13 is an example diagram of a non-zero matrix in the second LDPC matrix and a block matrix in the parity check matrix corresponding to an element in the first LDPC matrix of this application embodiment.

[0105] Figure 14 is a schematic block diagram of a communication device provided in an embodiment of this application;

[0106] Figures 15 to 18 are schematic block diagrams of another communication device provided in the embodiments of this application. Detailed Implementation

[0107] The technical solution provided in this application will now be described with reference to the accompanying drawings.

[0108] The embodiments of this application can be applied to various communication systems, such as wireless local area network (WLAN), narrowband internet of things (NB-IoT), global system for mobile communications (GSM), enhanced data rate for GSM evolution (EDGE), wideband code division multiple access (WCDMA), code division multiple access 2000 (CDMA2000), time division-synchronization code division multiple access (TD-SCDMA), long term evolution (LTE), universal mobile telecommunication system (UMTS), worldwide interoperability for microwave access (WiMAX), satellite communication systems, 5G communication systems, and future communication network systems.

[0109] The communication system applicable to embodiments of this application may include one or more transmitters and one or more receivers. Optionally, one of the transmitter and receiver may be a terminal device, and the other may be a network device. Optionally, both the transmitter and receiver may be terminal devices. Optionally, both the transmitter and receiver may be network devices.

[0110] Figure 1 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application. The communication system includes RAN 100 and core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal device (120a-120j in Figure 1, collectively referred to as 120). RAN may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal device 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network device in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and wireless access network logical functions.

[0111] RAN 100 can be a 3GPP-related cellular system, such as a 4G or 5G mobile communication system, a non-terrestrial network (NTN) system, or a future communication network system. RAN 100 can also be an O-RAN, a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system, or a communication system that integrates two or more of the above systems.

[0112] The terminal device 120 involved in the embodiments of this application can also be referred to as a terminal, user equipment (UE), mobile station, mobile terminal, etc. Terminal devices can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality (AR), industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. The terminal typically contains a communication module, circuit, or chip that performs the corresponding communication function. The terminal can also be configured with program instructions for performing the corresponding communication function.

[0113] The RAN node 110 involved in this application embodiment can also be called an access network device, RAN entity, or access node, etc., and constitutes part of the communication system to help terminal devices achieve wireless access. Multiple RAN nodes 110 in the communication system 1000 can be nodes of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal device 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminal devices 120j that access RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal device 120 are sometimes referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions. In the embodiments of this application, the access network device can also be called a network device.

[0114] In one possible scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), or a base station in a future communication network system. A RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU).

[0115] In another possible scenario, multiple RAN nodes collaborate to assist terminal devices in achieving wireless access, with different RAN nodes implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CUs (control plane, CP), CUs (user plane, UP), or radio units (RUs). CUs and DUs can be set up separately or included in the same network element, such as the baseband unit (BBU). CU and DU nodes separate the gNB's protocol layers; some protocol layer functions are centrally controlled by the CU, while the remaining partial or complete protocol layer functions are distributed in the DU, which is centrally controlled by the CU. As one implementation, the CU deploys the RRC layer, Packet Data Convergence Protocol (PDCP) layer, and Service Data Adaptation Protocol (SDAP) layer from the protocol stack; the DU deploys the radio link control (RLC) layer, media access control (MAC) layer, and physical layer (PHY) from the protocol stack. Therefore, the CU has RRC, PDCP, and SDAP processing capabilities. The DU has RLC, MAC, and PHY processing capabilities. It is understood that the above functional division is merely an example and does not constitute a limitation on the CU and DU. The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0116] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an O-RAN system, CU can also be called O-CU (Open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0117] Figure 2 is an example diagram of an O-RAN system. An O-RAN system may include components other than those shown in Figure 2. As shown in Figure 2, access network devices (e.g., eNB, gNB, or next-generation access network devices) communicate with the core network (CN) via a backhaul link and with terminal devices via an air interface.

[0118] Specifically, the BBU in the access network equipment communicates with the core network via a backhaul link, and the radio unit (RU) in the access network equipment communicates with at least one terminal device via an air interface. The BBU communicates with at least one RU via a fronthaul link. The BBU and RU may or may not be co-located.

[0119] The BBU includes at least one CU and at least one DU, which can communicate via at least one midhaul link.

[0120] There is an interface between the DU and RU. Depending on the functions of the DU and RU, and / or the switching method, the interface between the DU and RU can be CPRI or enhanced common public radio interface (eCPRI).

[0121] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a SoC or modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0122] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0123] Figure 3 is a schematic diagram of the information transmission process according to an embodiment of this application. As shown in Figure 3, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery, and other processing, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 3 (including source coding, channel coding, and modulation) is performed on the coding side, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed on the decoding side.

[0124] The embodiments of this application can be implemented in hardware, such as through a dedicated chip or a programmable chip, or by a processor executing software instructions, and mainly involve channel coding and channel decoding as shown in Figure 3. It should be noted that the embodiments of this application can be used for the channel decoding part, and the decoding method of the embodiments of this application is a general decoding means, effective for any coding scheme.

[0125] Furthermore, the embodiments of this application can be applied to one or more specific application scenarios, or they can be general methods applicable to various application scenarios. Application scenarios may include peak rate scenarios, high throughput scenarios, high reliability scenarios, low latency scenarios, high reliability low latency scenarios, or low power consumption scenarios, etc. High-throughput scenarios include enhanced mobile broadband (eMBB), eMBB+, extended-reality (XR), cloud gaming (CG), and augmented reality scenarios. High-reliability and low-latency scenarios include ultra-reliable low-latency communication (URLLC) or hyper-reliable low-latency communication (HRLLC). Low-power scenarios include M2M, MTC, massive MTC (mMTC), IoT, narrowband Internet of Things (NB-IoT), advanced Internet of Things (A-IoT), and low-power wide-area (LPWA) scenarios.

[0126] To facilitate understanding of the embodiments of this application, the terms and related technical solutions involved in the embodiments of this application will be briefly introduced below.

[0127] 1. LDPC

[0128] LDPC codes are error-correcting codes with low-density parity-check matrices. The basic idea is to represent a linear code using a set of sparse parity-check matrices and to use these parity-check matrices to perform error correction at the receiving end.

[0129] LDPC codes are a channel coding scheme very close to the Shannon limit, characterized by high performance, low complexity, and flexible structure. LDPC codes have become a research hotspot in the field of channel coding in recent years and have been widely applied in deep space communication, fiber optic communication, satellite digital video and audio broadcasting, and other fields; they have now been selected by 3GPP as the 5G data channel coding scheme. The main decoding algorithms for LDPC codes are the min-sum (MS) algorithm and the belief propagation (BP) decoding algorithm. In terms of decoding performance, the BP decoding algorithm has better performance, but it requires a large amount of information storage and has a complex calculation method, making it unsuitable for hardware implementation. Therefore, the offset-MS decoding algorithm and the normalized-MS decoding algorithm are currently used in practical communication systems.

[0130] Mainstream LDPC codes have a quasi-cyclic (QC) structure, also known as quasi-cyclic LDPC (QC-LDPC) codes. QC-LDPC codes are a special type of LDPC code with a quasi-periodic structure. Unlike traditional LDPC codes, the parity-check matrix (PCM) of a QC-LDPC code is not completely random, but rather a large matrix constructed by repeating a smaller base matrix. The base matrix can be viewed as a small matrix that constructs the entire LDPC code. The base matrix is ​​typically a small sparse matrix containing elements that define the code structure, such as the position and number of non-zero elements. In QC-LDPC codes, a large-scale PCM can be formed by cyclically shifting or periodically copying the base matrix. This matrix has a low-density structure similar to traditional LDPC codes, but exhibits periodic or quasi-periodic characteristics. For example, if the elements in the base matrix are 0 or 1, expanding the 1s in the base matrix into a cyclic shift matrix and expanding the 0s into a 0 matrix of the corresponding size yields the PCM.

[0131] The basis matrix of a practical QC-LDPC code can be represented graphically, called the base graph (BG). The BG model can be BG = (X, Y, F), where X corresponds to variables, Y corresponds to the checksum equation, and F corresponds to the edge relationships. After QC expansion with a lifting size, the BG yields a Tanner graph, modeled as G = (V, C, E), where V represents variable nodes, C represents checksum nodes, and E represents edge relationships. The number of columns in the checksum matrix corresponding to BG is N = |V| = Zc|X|, the number of rows is M = |C| = Zc|Y|, and the number of non-zero elements in the checksum matrix is ​​|E| = Zc|F|, where Zc is the lifting size.

[0132] 2. The basis matrix of LDPC codes

[0133] As an example, the basis matrices of the 5G LDPC code include BG1 and BG2. BG1 is a 46x68 matrix, and BG2 is a 42x52 matrix. Both BG1 and BG2 have the matrix structure shown in Figure 4, containing, for example, multiple regions as shown in Figure 4. Region A corresponds to the high-rate information column (or the region with the highest code rate), region B corresponds to the core checksum of the high code rate, region C is a zero matrix, region D is the incremental redundancy part of the basis matrix and corresponds to the low code rate, and region E is the incremental redundancy region and is an identity matrix. The values ​​of the basis matrix are 0 or 1; a value of 0 represents an empty element, and a value of 1 represents an edge in the basis graph, or the association between the checksum and the variable.

[0134] In Figure 4, the dashed boxes represent punched columns. The first two columns of BG1 and BG2 are punched columns. In terms of matrix characteristics, their column weight is very large, where the column weight is the total number of 1s contained in a column. In terms of transmission characteristics, the bits corresponding to the punched bits are not transmitted; the receiver has no received information about this part, setting its log-likelihood ratio to 0, and recovering it through decoding. BG1 and BG2 are designed for the lowest bit rate. When different bit rates need to be supported, the upper left portion of BG1 or BG2 can be used. Figure 5 shows the matrix regions corresponding to different bit rates. The rows and columns of each dashed box region form a base matrix. As the size of the dashed box region increases, the bit rate of the corresponding base matrix gradually decreases. When the rows and columns of the high bit rate region shown in Figure 5 are selected from BG1 or BG2 to form the base matrix, the bit rate of this base matrix is ​​the highest; therefore, this base matrix is ​​also called the highest bit rate matrix. When a base matrix is ​​constructed by selecting more rows and columns from BG1 or BG2 than from the high-bitrate region, the bitrate of that base matrix will be lower than the highest bitrate. Furthermore, as the number of rows and columns increases, the bitrate of the corresponding matrix region gradually decreases.

[0135] Similarly, the base matrix structure applicable to the scheme of this application may also include: region A, region B, region C, region D, and region E. Region A corresponds to the high bitrate information column (or the region of the highest bitrate information column), region B corresponds to the core check for high bitrate, region C is a zero matrix, region D is the incremental redundancy part of the base matrix and corresponds to the low bitrate, and region E is the incremental redundancy region and is an identity matrix. The base matrix takes values ​​of 0 or 1, where a value of 0 represents an empty element, and a value of 1 represents an edge in the base graph, or represents the association between the check and the variable.

[0136] Alternatively, the columns of the base matrix applicable to the scheme of this application consist of information columns and verification columns, and the rows of the base matrix applicable to the scheme of this application consist of the rows corresponding to the core verification, as described below.

[0137] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to area A.

[0138] Check columns: Corresponding to check bits (or check digits, etc.), these are the columns corresponding to regions B and C, and can include core check columns and extended check columns. The core check columns are those corresponding to region B, while the extended check columns are those corresponding to parts of region C. Extended check columns can also be called raptor-like columns. Alternatively, the core check columns are the check columns in region B where the column weight is greater than 1 (region B has 1 element both above and below its diagonal), and the extended check columns are the remaining check columns excluding the core check columns.

[0139] Core rows: The core rows of the base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or regions A, B, or C.

[0140] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate regions, or the columns corresponding to regions A and B.

[0141] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the base matrix. In other words, the kernel matrix is ​​the high-bitrate region of the base matrix, or a portion composed of regions A and B.

[0142] The base matrix (BG) used in this application can be designed with the lowest possible bitrate. When different bitrates need to be supported, the upper left portion of the BG can be used. When rows and columns from a high-bitrate region are selected from the BG to form the base matrix, the bitrate of this base matrix is ​​the highest; therefore, this base matrix is ​​also called the highest bitrate matrix. When more rows and columns than high-bitrate regions are selected from the BG to form the base matrix, the bitrate of this base matrix is ​​lower than the highest bitrate. Furthermore, as the number of rows and columns increases, the bitrate of the corresponding matrix region gradually decreases.

[0143] 3. Construct the parity check matrix

[0144] The basis matrix can be represented as H BG Based on the basis matrix H BG And the expansion factor, which can transform the basis matrix H BG Expanding it into a parity-check matrix for encoding or decoding; this process involves transforming the basis matrix H... BG Each element in the matrix is ​​promoted to a Zc×Zc square matrix. Specifically, 0 is promoted to a Zc×Zc zero matrix, and 1 is promoted to a Zc×Zc identity matrix, then cyclically shifted by P (left or right). i，j Secondary or cyclic shift P i，j A matrix of degree (mod)Zc, where P i，j Represents the basis matrix H BG The shifting value (SV) corresponding to the i-th row and j-th column. The expansion factor can also be called the lifting factor, expansion value, expansion coefficient, lifting value, lifting size, etc. "mod" means modulo.

[0145] With a 4x4 unit array For example, the result of shifting it to the right cyclically once is: The result of shifting it to the right twice is: The result of shifting it to the right 3 times is: The result of shifting it 0 times to the right is

[0146] When constructing the parity check matrix, first determine the size of Zc, then determine a set of shift values ​​corresponding to Zc, and then construct the parity check matrix based on Zc and the shift values.

[0147] As an example, Table 1 shows various values ​​for the expansion factor (Zc).

[0148] Table 1

[0149] As shown in Table 1, Zc takes the value of j represents the j-th row in Table 1, where j = 0, 1, 2, 3, 4, 5, 6, 7; a0, a1, a2, a3, a4, a5, a6, a7 are respectively 2, 3, 5, 7, 9, 11, 13, 15. k j The value of traverses from 0 to max(k) j The values ​​of max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, 4, respectively. For example, if j = 0, then a0 = 2, and k0 iterates through 0 to 7. Therefore, the value of Zc can be 2*2. 0 2*2 1 2*2 2 2*2 3 2*2 4 2*2 5 2*2 6 ,2*2 7 That is, 2, 4, 8, 16, 32, 64, 128, 256. The cases where j takes values ​​from 1 to 7 are similar and will not be elaborated further. It should be noted that each row in Table 1 represents a set of expansion factors.

[0150] Each row of Zc in Table 1 corresponds to a set of SVs (also called SV sets). Table 2 below shows a partial example of a set of SVs defined in the 3GPP 212 protocol. Table 2 shows the basis matrix H. BG The shift value SV corresponding to each element in row 0 that has a value of 1 ij It should be noted that Table 2 only shows the shift values ​​corresponding to each element in row 0. In reality, it also includes the shift values ​​corresponding to each element in other rows (such as row 1, row 2, etc.).

[0151] Table 2

[0152] Table 2 shows the basis matrix H. BG The shift value SV corresponding to each element in row 0 that has a value of 1 ij The set index i in Table 2 LS That is, the set index i in Table 1 LS Furthermore, the basis matrix H BG The cyclic shift values ​​corresponding to the elements with a value of 1 in row 0 can be obtained by taking the modulo of Zc using the shift value of that element. Table 2 only shows the translation values ​​corresponding to the elements in row 0; in practice, it also includes the translation values ​​corresponding to the elements in other rows (such as row 1, row 2, etc.).

[0153] Referring to Table 2, when Zc takes the values ​​2, 4, 8, 16, 32, 64, 128, or 256, then i LS =0, basis matrix H BG The SV values ​​of the elements with a value of 1 in row 0 are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming Zc = 4, then the basis matrix H... BG The cyclic shift counts corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. This means that the 4x4 identity matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times to obtain the basis matrix H. BG The elements in row 0 that have a value of 1 correspond to a 4x4 matrix. For the basis matrix H... BG If any element in the 0th row has a value of 0, then replace it with a zero matrix of size 4*4.

[0154] For other values ​​of Zc, there are corresponding shift values ​​and cyclic shift counts, as detailed in Table 2. For the basis matrix H... BG The rows other than row 0 are also determined using a similar method to form the corresponding Zc×Zc matrix.

[0155] The parity-check matrix can be obtained by performing a single lifting operation on the basis matrix, as described above; alternatively, it can be obtained by performing two lifting operations. For example, first, each element of the basis matrix can be lifted into a Zc1×Zc1 square matrix to obtain a new LDPC matrix; then, each element of this new LDPC matrix can be lifted into a Zc2×Zc2 square matrix to obtain the parity-check matrix. When constructing the parity-check matrix, the sizes of Zc1 and Zc2 are first determined, and then a set of shift values ​​corresponding to Zc1 and Zc2 are determined respectively. The parity-check matrix is ​​then constructed based on Zc1, Zc2, and the shift values. The method for determining Zc1, Zc2, and the shift values ​​is similar to the method described above and will not be repeated here.

[0156] For example, first, each element in the basis matrix is ​​promoted to an a×b matrix of all 1s, resulting in a new LDPC matrix; then, each element in this new LDPC matrix is ​​promoted to a Zc×Zc square matrix, resulting in the parity check matrix. When constructing the parity check matrix, the sizes of a, b, and Zc are first determined, then a set of shift values ​​corresponding to Zc is determined, and finally, the parity check matrix is ​​constructed based on a, b, Zc, and the shift values.

[0157] NR-LDPC encoding imposes significant limitations on the decoding architecture. The high-rate part (core part) can only support parallel QC blocks and cannot support parallel decoding of the entire line. Although the low-rate part supports parallel decoding of two lines, the computational units for high and low rate cannot be equalized, resulting in a large waste of area. Furthermore, the peak throughput cannot reach 100Gbps, leading to large decoding latency.

[0158] To address this, embodiments of this application provide an information transmission method that improves the orthogonality of the parity-check matrix by designing shift values, thereby reducing decoding latency and increasing decoding throughput. The first communication device in this application can be a network device or a module within a network device (e.g., a circuit, chip, chip system, or processor), or a logical node, logical module, or software capable of implementing all or part of the network device's functions; alternatively, the first communication device in this application can be a terminal device or a module within a terminal device (e.g., a circuit, chip, chip system, or processor), or a logical node, logical module, or software capable of implementing all or part of the terminal device's functions. The second communication device in this application can be a terminal device or a module within a terminal device (e.g., a circuit, chip, chip system, or processor), or a logical node, logical module, or software capable of implementing all or part of the terminal device's functions; alternatively, the second communication device in this application can be a network device or a module within a network device (e.g., a circuit, chip, chip system, or processor), or a logical node, logical module, or software capable of implementing all or part of the network device's functions.

[0159] The chip can be a modem chip, also known as a baseband chip; or a system-on-a-chip (SoC) chip containing a modem core; or a system-in-package (SIP) chip. The network device in this embodiment can be a base station. Furthermore, the processing performed by a single execution entity can be divided into multiple execution entities, which can be logically and / or physically separated. For example, the processing performed by the network device can be divided into at least one execution entity among CU, DU, RU, etc. The first communication device can be understood as a transmitting end, and the second communication device can be understood as a receiving end.

[0160] Figure 6 is a schematic flowchart of an information transmission method 600 provided in an embodiment of this application.

[0161] S610, the first communication device obtains a check matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. Any first shift value in the set of first shift values ​​corresponding to the first element and any second shift value in the set of second shift values ​​corresponding to the second element satisfy at least one of the first conditions or the second conditions. The first element and the second element are two elements in the first LDPC matrix that are adjacent in rows, have the same column, and are both non-zero. The first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, where the first parameter is an integer greater than or equal to 1. The second condition is associated with the first shift value, the second shift value, and the second parameter, where the second parameter is an integer greater than or equal to 3.

[0162] The first communication device obtains the parity check matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. This can be understood as the first communication device performing lift and cyclic shift on the first LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix to obtain the parity check matrix.

[0163] For example, any first shift value in the first shift value set corresponding to the first element and any second shift value in the second shift value set corresponding to the second element satisfy the first condition.

[0164] For example, any first shift value in the first shift value set corresponding to the first element and any second shift value in the second shift value set corresponding to the second element satisfy the second condition.

[0165] For example, any first shift value in the first shift value set corresponding to the first element and any second shift value in the second shift value set corresponding to the second element satisfy the first condition and the second condition.

[0166] In this application, all shift values ​​in the first shift value set are referred to as first shift values, and all shift values ​​in the second shift value set are referred to as second shift values. The first shift value set may contain one or more first shift values, and the second shift value set may also contain one or more second shift values. For example, if the first element is greater than 1, then the first shift value set corresponding to the first element includes multiple first shift values; if the first element is equal to 1, then the first shift value set corresponding to the first element includes one first shift value.

[0167] For example, any one of the first shift values ​​in the first shift value set corresponding to the first element includes: the first shift value corresponding to the first element; any one of the second shift values ​​in the second shift value set corresponding to the second element includes: the second shift value corresponding to the second element. In this example, the first shift value set includes only one first shift value, and the second shift value set includes only one second shift value.

[0168] It should be noted that for two elements in the first LDPC matrix that are adjacent in row, have the same column, and are both 0 or one of them is 0, the shift values ​​corresponding to them do not need to satisfy the first condition and the second condition, or, by default, the two elements satisfy at least one of the first condition or the second condition.

[0169] Optionally, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc); where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is an integer greater than or equal to 1, and t1 and t2 are integers. t0 is the aforementioned first parameter. For example, if Zc = 2, then the expansion factor set corresponding to Zc is {2, 4, 8, 16, 32, 64, 128, 256}, and the maximum value in the expansion factor set corresponding to Zc is 256; as another example, if Zc = 3, then the expansion factor set corresponding to Zc is {3, 6, 12, 24, 48, 96, 192, 384}, and the maximum value in the expansion factor set corresponding to Zc is 384.

[0170] It should be noted that -t1+1-SV1 ≠ t2-SV2 mod (Zc), which can be understood as the remainder of -t1+1-SV1 divided by Zc not being equal to the remainder of t2-SV2 divided by Zc.

[0171] Optionally, the first condition includes: SV2-SV1+1-2t0≠0mod(Zc), or SV2-SV1+1-2t0≥1mod(Zc), or SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, and t0 is an integer greater than or equal to 1.

[0172] It should be noted that SV2-SV1+1-2t0≠0mod(Zc) can be understood as the remainder of SV2-SV1+1-2t0 divided by Zc is not equal to 0; SV2-SV1+1-2t0≥1mod(Zc) can be understood as the remainder of SV2-SV1+1-2t0 divided by Zc is greater than or equal to 1; SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc) can be understood as the remainder of SV2-SV1+1-2t0 divided by Zc belongs to the set {1,2,…,Zc-1,}. The expressions SV2-SV1+1-2t0≠0mod(Zc), SV2-SV1+1-2t0≥1mod(Zc), and SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc) are equivalent.

[0173] Optionally, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc), and SV2-SV1+1-2t0≠0mod(Zc); or, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc), and SV2-SV1+1-2t0≥1mod(Zc); or, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc), and SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc).

[0174] Optionally, the first condition includes: the remainder when any element in the first set is divided by Zc is not equal to the remainder when any element in the second set is divided by Zc; the first set is {Zc-t+1-SV1|1≤t≤t0}, and the second set is {t-SV2|1≤t≤t0}; where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, t0 is an integer greater than or equal to 1, and t is an integer.

[0175] Optionally, t0 is 1, 2, or 3, or t0 is an integer related to Zc.

[0176] For example, or, Where n is an integer greater than or equal to 2.

[0177] Figure 7 shows a comparison of the first and second shift values ​​satisfying and not satisfying the first condition. The first shift value is the shift value corresponding to the first element, and the second shift value is the shift value corresponding to the second element. The first and second elements are two adjacent elements in the first LDPC matrix that are in the same column and are both non-zero. The left side of Figure 7 shows the two submatrices in the parity check matrix corresponding to the first and second elements when the first and second shift values ​​satisfy the first condition; these two submatrices are orthogonal. The right side of Figure 7 shows the two submatrices in the parity check matrix corresponding to the first and second elements when the first and second shift values ​​do not satisfy the first condition; these two submatrices are non-orthogonal. It should be noted that the blank spaces in Figure 7 represent elements that are 0.

[0178] Optionally, the second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, where the third parameter is an integer.

[0179] Optionally, the second condition includes: SV1 = (SV2 + x) mod (y); where SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, y is an integer greater than or equal to 3, and x is an integer. y is the second parameter mentioned above, and x is the third parameter mentioned above.

[0180] For example, x = 0, and the second condition includes: SV1 = SV2 mod (y). In this example, the second condition can be considered to be associated with the first shift value, the second shift value, and the second parameter.

[0181] Optionally, the first communication device can perform a single boosting operation on the base matrix to obtain the parity check matrix, or the first communication device can perform two boosting operations on the base matrix to obtain the parity check matrix.

[0182] In the implementation of the first communication device performing a boost on the base matrix to obtain the parity check matrix, the first LDPC matrix is ​​the base matrix, and the elements in the first LDPC matrix are 0 or 1, or the elements in the first LDPC matrix are 0, 1, or integers greater than 1. When the elements in the first LDPC matrix are 0, 1, or integers greater than 1, the first LDPC matrix can be called a multi-edge LDPC matrix.

[0183] When the elements in the first LDPC matrix are 0 or 1, each element 1 in the first LDPC matrix corresponds to a shift value; according to the first expansion factor Zc and the first LDPC matrix (basis matrix) H BGThe process of obtaining the parity check matrix by the corresponding shift values ​​includes: expanding the elements 1 in the first LDPC matrix into a Zc×Zc cyclic shift matrix, and expanding the elements 0 in the first LDPC matrix into a Zc×Zc zero matrix. After expansion, the parity check matrix is ​​obtained. Specifically, the first LDPC matrix H... BG The element t in the i-th row and j-th column i,j (where t) i,j =1) Replace with a Zc×Zc cyclic displacement matrix I(P) i,j ), where I(P i,j ) is a Zc×Zc identity matrix I cyclically shifted (to the left) by P i,j A matrix of order P i,j For element t i,j The corresponding shift value; the first LDPC matrix H BG Replace the 0s in the matrix with a Zc×Zc matrix of all zeros.

[0184] When the elements in the first LDPC matrix are 0, 1, or integers greater than 1, each element 1 in the first LDPC matrix corresponds to one shift value, and each element greater than 1 in the first LDPC matrix corresponds to multiple shift values. The elements 1 in the first LDPC matrix are expanded into a cyclic shift matrix, and the elements greater than 1 in the first LDPC matrix are expanded into multiple cyclic shift matrices. These multiple cyclic shifts are then added together to obtain the parity check matrix. Figure 8 is a schematic diagram of expanding element 2 in the first LDPC matrix into multiple cyclic shift matrices and then adding them together. In this example, the expansion factor Zc = 4, and the shift values ​​corresponding to element 2 are 0 and 1.

[0185] The first communication device can obtain the parity-check matrix by performing two lifting operations on the base matrix, including but not limited to the following two methods.

[0186] In the first implementation, the first LDPC matrix is ​​the base matrix. The first communication device obtains the second LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. The first communication device then obtains the parity check matrix based on the second LDPC matrix, the second expansion factor, and the shift value corresponding to the second LDPC matrix. In this implementation, the parity check matrix is ​​obtained by performing two lifting operations on the base matrix.

[0187] Specifically, the first communication device performs a boosting and cyclic shift on the first LDPC matrix (base matrix), a first expansion factor, and the shift value corresponding to the first LDPC matrix to obtain a second LDPC matrix; the first communication device then performs a boosting and cyclic shift on the second LDPC matrix, a second expansion factor, and the shift value corresponding to the second LDPC matrix to obtain a parity check matrix. Figure 9 is an example diagram of a two-stage boosting of the first LDPC matrix according to an embodiment of this application; in this example, a first-stage boosting is performed first, using a first expansion factor of 2, replacing each non-zero element in the first LDPC matrix with a 2×2 cyclic shift matrix to obtain the second LDPC matrix; then a second-stage boosting is performed, using a second expansion factor of 3, replacing each zero element in the second LDPC matrix with a 3×3 all-zero matrix, and replacing each non-zero element in the second LDPC matrix with a 3×3 cyclic shift matrix to obtain the parity check matrix.

[0188] For example, in the first condition, t0 = 1, and in the second condition, x = 0 and y = 3; any first shift value in the first shift value set corresponding to the first element in the first LDPC matrix and any second shift value in the second shift value set corresponding to the second element satisfy at least one of the first or second conditions. Based on the decoding matrix obtained according to the first LDPC matrix and the shift value corresponding to the first LDPC matrix, the information to be decoded is decoded. This can reduce the decoding latency at the receiving end not only in the case of row-parallel decoding, but also in the case of block-parallel decoding, thereby reducing the decoding latency at the receiving end and improving the decoding throughput.

[0189] In the second implementation, the first LDPC matrix is ​​obtained by improving the base matrix. Before the first communication device obtains the parity check matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix, the first communication device improves the base matrix to obtain the first LDPC matrix. In other words, the first communication device improves the base matrix to obtain the first LDPC matrix; the first communication device obtains the parity check matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. In this implementation, the parity check matrix is ​​obtained by improving the base matrix twice.

[0190] For example, the first communication device promotes the elements with a value of 1 in the base matrix to a matrix of all 1s in rows and columns b, and promotes the elements with a value of 0 in the base matrix to a matrix of 0s in rows and columns b, thus obtaining a first LDPC matrix. The first communication device obtains a parity check matrix based on the first LDPC matrix, a first expansion factor, and the shift value corresponding to the first LDPC matrix. Figure 10 is an example diagram of a two-stage promotion of the base matrix according to an embodiment of this application. In this example, the first stage promotes the elements with a value of 1 in the base matrix to a matrix of all 1s in rows and columns 1. The second stage uses a first expansion factor of 3 to replace each non-zero element in the first LDPC matrix with a 3×3 cyclic shift matrix, thus obtaining a parity check matrix.

[0191] The first element and the second element can be two elements that are adjacent in all columns of the first LDPC matrix, have the same column, and are both non-zero. Alternatively, the first element and the second element can be two elements that are adjacent in some columns of the first LDPC matrix, have the same column, and are both non-zero.

[0192] Optionally, the first element and the second element are two adjacent elements in the first column set of the first LDPC matrix, with the same column and both non-zero values; the first column set includes a portion of the columns of the first LDPC matrix. Based on this implementation, some columns of the parity check matrix can satisfy the orthogonality condition, which can reduce decoding latency and improve decoding throughput.

[0193] For example, the first column set includes the information columns corresponding to the first LDPC matrix. The information columns corresponding to the first LDPC matrix are the columns corresponding to region A of the first LDPC matrix, including all information columns. When the first column set is an information column, decoding latency can be reduced without sacrificing decoding performance.

[0194] For example, the first column set includes the core columns corresponding to the first LDPC matrix. The core columns corresponding to the first LDPC matrix are the columns corresponding to regions A and B of the first LDPC matrix, including all information columns and all core check columns. When the first column set consists of core columns, decoding latency can be reduced with virtually no loss in decoding performance.

[0195] For example, the first column set includes all columns corresponding to the first LDPC matrix except for the punched columns. Specifically, the first column set includes all columns except for the large re-punched columns; for example, the first column set includes all columns except for the first and second columns (the first two columns). This allows for reduced decoding latency while maintaining superior decoding performance.

[0196] It should be noted that, in order to reduce the decoding latency at the receiving end, there are certain requirements regarding the number of columns included in the first column set. For example, the number of columns in the first column set must be greater than or equal to a certain threshold to achieve a reduction in the decoding latency at the receiving end. The decoding latency at the receiving end is related to the number of columns included in the first column set; the more columns included in the first column set, the lower the decoding latency at the receiving end.

[0197] For example, the first column set includes columns 1 to m0 of the first LDPC matrix, and the first column set is the leftmost part of the columns of the first LDPC matrix; where m0 is a positive integer less than end, and end is the total number of columns of the first LDPC matrix.

[0198] For example, the first column set includes columns m1 to end of the first LDPC matrix. The first column set is the rightmost part of the first LDPC matrix, which may be the rightmost information column or the rightmost core column; where m1 is a positive integer less than end.

[0199] Optionally, the first column set can also include all columns of the first LDPC matrix. Based on this implementation, all columns of the parity check matrix can satisfy the orthogonality condition, resulting in the lowest decoding latency and the highest decoding throughput.

[0200] S620, the first communication device sends information encoded using a check matrix to the second communication device; correspondingly, the second communication device receives information to be decoded from the first communication device, which is information encoded by the first communication device using a check matrix.

[0201] Optionally, before the first communication device sends the information encoded using the parity check matrix to the second communication device, the first communication device encodes the information to be sent using the parity check matrix to obtain the encoded information.

[0202] S630, the second communication device decodes the information to be decoded based on the parity check matrix to obtain the decoded bit sequence.

[0203] Specifically, the second communication device obtains a parity check matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix, and decodes the information to be decoded based on the parity check matrix to obtain the decoded bit sequence.

[0204] In the technical solution provided in this application embodiment, the first communication device obtains a parity check matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. The shift value corresponding to the first element (any shift value in the first shift value set) and the shift value corresponding to the second element (any shift value in the second shift value set) satisfy at least one of the first condition or the second condition. The first element and the second element are two elements in the first LDPC matrix that are adjacent in row, have the same column, and are both non-zero. The first communication device sends information encoded using the parity check matrix to the second communication device. The second communication device uses the parity check matrix to decode the information to be decoded received from the first communication device to obtain the decoded bit sequence. Since the orthogonality of the parity check matrix is ​​improved, the decoding delay of the second communication device for the information to be decoded can be reduced, thereby improving the decoding throughput.

[0205] Figure 11 is a comparative diagram showing the relationship between the number of chip steps required for decoding the information to be decoded by the second communication device in 5G and the embodiment of this application, and the code rate of the information to be decoded. As can be seen from Figure 11, when the code rate of the information to be decoded is the same, the number of chip steps required for decoding the information to be decoded by the receiver in 5G is greater than the number required by the receiver in the embodiment of this application. Therefore, the technical solution provided in this embodiment can reduce the decoding complexity of the receiver, thereby reducing decoding latency.

[0206] Figure 12 is a schematic flowchart of another information transmission method 1200 provided in an embodiment of this application.

[0207] S1210, the first communication device obtains a second LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. Each zero element in the first LDPC matrix corresponds to a zero matrix in the second LDPC matrix, and each non-zero element in the first LDPC matrix corresponds to a non-zero matrix in the second LDPC matrix. For example, the first LDPC matrix is ​​a base matrix, and the elements in the first LDPC matrix are 0, 1, or integers greater than 1.

[0208] The first communication device obtains the second LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. This can be understood as the first communication device performing a lift and cyclic shift on the first LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix to obtain the second LDPC matrix.

[0209] S1220, the first communication device shifts the elements of the non-zero matrices in the second LDPC matrix to obtain a parity check matrix. The parity check matrix includes multiple block matrices, each corresponding one-to-one with a non-zero matrix. Each block matrix is ​​composed of multiple sub-matrices, which are either zero matrices or cyclic shift matrices with row and column weights of 1. The shift value corresponding to the first cyclic shift matrix and the shift value corresponding to the second cyclic shift matrix satisfy at least one of the first or second conditions. The first and second cyclic shift matrices are two cyclic shift matrices in the block matrix that are row-adjacent and have the same columns. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, where the first parameter is an integer greater than or equal to 1. The second condition is associated with the first shift value, the second shift value, and the second parameter, where the second parameter is an integer greater than or equal to 3.

[0210] In this matrix, the columns of the first and second cyclic shift matrices are the same. This can be understood as the columns of the first and second cyclic shift matrices in the block matrix being the same; for example, if the first cyclic shift matrix is ​​in columns 1 and 2 of the block matrix, the second cyclic shift matrix is ​​also in columns 1 and 2 of the block matrix. The rows of the first and second cyclic shift matrices are adjacent. This can be understood as the rows of the first and second cyclic shift matrices in the block matrix being different but adjacent; for example, if the first cyclic shift matrix is ​​in rows 1 and 2 of the block matrix, the second cyclic shift matrix is ​​in rows 3 and 4 of the block matrix.

[0211] Figure 13 is an example diagram showing an element in the first LDPC matrix of this application, corresponding to a non-zero matrix in the second LDPC matrix and a corresponding block matrix in the parity check matrix. In this example, the element is 2, the first expansion factor is 12, and the shift values ​​of the two adjacent cyclic shift matrices with the same columns in the block matrix are 1 and 2, respectively. It should be noted that the blank spaces in Figure 13 represent elements that are 0.

[0212] For example, the shift value corresponding to the first cyclic shift matrix and the shift value corresponding to the second cyclic shift matrix satisfy a first condition. For example, the shift value corresponding to the first cyclic shift matrix and the shift value corresponding to the second cyclic shift matrix satisfy a second condition. For example, the shift value corresponding to the first cyclic shift matrix and the shift value corresponding to the second cyclic shift matrix satisfy both the first and second conditions.

[0213] Optionally, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of submatrices included in the block matrix, 1≤t1≤t0, 1≤t2≤t0, t0 is an integer greater than or equal to 1, and t1 and t2 are integers. t0 is the first parameter mentioned above.

[0214] It should be noted that -t1+1-SV3≠t2-SV4mod(Zc'), which can be understood as the remainder of -t1+1-SV3 divided by Zc' not being equal to the remainder of t2-SV4 divided by Zc'.

[0215] Optionally, the first condition includes: SV4-SV3+1-2t0≠0mod(Zc'), or SV4-SV3+1-2t0≥1mod(Zc'), or SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of submatrices included in the block matrix, and t0 is an integer greater than or equal to 1.

[0216] It should be noted that SV4-SV3+1-2t0≠0mod(Zc') can be understood as the remainder of SV4-SV3+1-2t0 divided by Zc' is not equal to 0; SV4-SV3+1-2t0≥1mod(Zc') can be understood as the remainder of SV4-SV3+1-2t0 divided by Zc' is greater than or equal to 1; SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc') can be understood as the remainder of SV4-SV3+1-2t0 divided by Zc' belongs to the set {1,2,…,Zc'-1,}. The expressions SV4-SV3+1-2t0≠0mod(Zc'), SV4-SV3+1-2t0≥1mod(Zc'), and SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc') are equivalent.

[0217] Optionally, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'), and SV4-SV3+1-2t0≠0mod(Zc'); or, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'), and SV4-SV3+1-2t0≥1mod(Zc'); or, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'), and SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc').

[0218] Optionally, the first condition includes: the remainder when any element in the first set is divided by Zc' is not equal to the remainder when any element in the second set is divided by Zc', the first set is {Zc'-t+1-SV3|1≤t≤t0}, and the second set is {t-SV4|1≤t≤t0}; where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of submatrices included in the block matrix, t0 is an integer greater than or equal to 1, and t is an integer.

[0219] Optionally, t0 is 1, 2 or 3, or t0 is an integer related to Zc'.

[0220] For example, or, Where n is an integer greater than or equal to 2.

[0221] Optionally, the second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, where the third parameter is an integer.

[0222] Optionally, the second condition includes SV3 = (SV4 + x) mod (y); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, y is an integer greater than or equal to 3, and x is an integer. y is the second parameter mentioned above, and x is the third parameter mentioned above.

[0223] For example, x = 0, and the second condition includes: SV1 = SV2 mod (y). In this example, the second condition can be considered to be associated with the first shift value, the second shift value, and the second parameter.

[0224] S1230, the first communication device sends information encoded using a parity check matrix to the second communication device. Correspondingly, the second communication device receives information to be decoded from the first communication device, which is the information encoded by the first communication device using a parity check matrix.

[0225] Optionally, before the first communication device sends the information encoded using the parity check matrix to the second communication device, the first communication device encodes the information to be sent using the parity check matrix to obtain the encoded information.

[0226] S1240, the second communication device decodes the information to be decoded based on the parity check matrix to obtain the decoded bit sequence.

[0227] Specifically, the second communication device obtains the second LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix; the second communication device shifts the elements of the non-zero matrices in the second LDPC matrix to obtain a parity check matrix; the second communication device decodes the information to be decoded based on the parity check matrix to obtain the decoded bit sequence.

[0228] In the technical solution provided in this application embodiment, the first communication device obtains a second LDPC matrix based on a first LDPC matrix, a first expansion factor, and the shift value corresponding to the first LDPC matrix; and shifts the elements of the non-zero matrices in the second LDPC matrix to obtain a parity check matrix. This parity check matrix includes multiple block matrices. The shift value corresponding to the first cyclic shift matrix and the shift value corresponding to the second cyclic shift matrix in the block matrix satisfy at least one of a first condition or a second condition. The first cyclic shift matrix and the second cyclic shift matrix are two cyclic shift matrices that are row-adjacent and have the same columns in the block matrix. The first communication device sends information encoded using the parity check matrix to a second communication device. The second communication device uses the parity check matrix to decode the information to be decoded received from the first communication device to obtain a decoded bit sequence. Because the orthogonality of the parity check matrix is ​​improved, the decoding latency of the second communication device for the information to be decoded can be reduced, thereby improving the decoding throughput.

[0229] The above describes the information transmission method provided by the embodiments of this application. The following will describe the execution subject used to perform the above information transmission method.

[0230] Figure 14 is a schematic block diagram of a communication device 1400 provided in an embodiment of this application. The communication device 1400 can be the first communication device in the method embodiment of Figure 6. The communication device 1400 includes:

[0231] Processing module 1410 is used to obtain a parity check matrix based on a first low-density parity check (LDPC) matrix, a first expansion factor, and shift values ​​corresponding to the first LDPC matrix. The first shift value in the set of first shift values ​​corresponding to the first element and any second shift value in the set of second shift values ​​corresponding to the second element satisfy at least one of a first condition or a second condition. The first element and the second element are two elements in the first LDPC matrix that are row-adjacent, column-adjacent, and both non-zero. The first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix.

[0232] The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and the second parameter, wherein the second parameter is an integer greater than or equal to 3.

[0233] The transceiver module 1420 is used to send information encoded using the verification matrix.

[0234] Optionally, the second condition is associated with the first shift value, the second shift value, the second parameter, and a third parameter, wherein the third parameter is an integer.

[0235] Optionally, any one of the first shift values ​​in the first shift value set corresponding to the first element includes: the first shift value corresponding to the first element; any one of the second shift values ​​in the second shift value set corresponding to the second element includes: the second shift value corresponding to the second element.

[0236] Optionally, the processing module 1410 is specifically used to: obtain a second LDPC matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix, wherein the first LDPC matrix is ​​the base matrix; and obtain the check matrix based on the second LDPC matrix, the second expansion factor, and the shift value corresponding to the second LDPC matrix.

[0237] Optionally, the processing module 1410 is further configured to promote the elements with a value of 1 in the base matrix to a matrix of all 1s in rows a and b columns, and promote the elements with a value of 0 in the base matrix to a matrix of 0s in rows a and b columns, thereby obtaining the first LDPC matrix.

[0238] Optionally, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, Zc is the first expansion factor or the maximum value in the set of expansion factors corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0239] Optionally, the first condition includes: SV2-SV1+1-2t0≠0mod(Zc), or SV2-SV1+1-2t0≥1mod(Zc), or SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, Zc is the first expansion factor or the maximum value in the set of expansion factors corresponding to the first expansion factor, and t0 is the first parameter.

[0240] Optionally, t0 is 1, 2, or 3, or t0 is an integer related to Zc.

[0241] Optionally, or, Where n is an integer greater than or equal to 2.

[0242] Optionally, the second condition includes: SV1 = (SV2 + x) mod (y); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0243] Optionally, the first element and the second element are two adjacent elements in the first column set of the first LDPC matrix, have the same column, and are both non-zero.

[0244] Optionally, the first column set includes the information column corresponding to the first LDPC matrix, or the core column corresponding to the first LDPC matrix, or all columns corresponding to the first LDPC matrix except for the punched column.

[0245] Figure 15 is a schematic block diagram of another communication device 1500 provided in an embodiment of this application. This communication device 1500 can be the second communication device in the method embodiment of Figure 6. The communication device 1500 includes:

[0246] The transceiver module 1510 is used to receive information to be decoded;

[0247] Processing module 1520 is used to decode the information to be decoded based on a parity check matrix to obtain a decoded bit sequence. The parity check matrix is ​​obtained based on a first LDPC matrix, a first expansion factor, and shift values ​​corresponding to the first LDPC matrix. Any first shift value in the set of first shift values ​​corresponding to the first element and any second shift value in the set of second shift values ​​corresponding to the second element satisfy at least one of a first condition or a second condition. The first element and the second element are two elements in the first LDPC matrix that are adjacent in rows, have the same column, and are both non-zero. The first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix.

[0248] The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and the second parameter, wherein the second parameter is an integer greater than or equal to 3.

[0249] Optionally, the second condition is associated with the first shift value, the second shift value, the second parameter, and a third parameter, wherein the third parameter is an integer.

[0250] Optionally, any one of the first shift values ​​in the first shift value set corresponding to the first element includes: the first shift value corresponding to the first element; any one of the second shift values ​​in the second shift value set corresponding to the second element includes: the second shift value corresponding to the second element.

[0251] Optionally, the first condition includes: -t1+1-SV1≠t2-SV2mod(Zc); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, Zc is the first expansion factor or the maximum value in the set of expansion factors corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0252] Optionally, the first condition includes: SV2-SV1+1-2t0≠0mod(Zc), or SV2-SV1+1-2t0≥1mod(Zc), or SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, Zc is the first expansion factor or the maximum value in the set of expansion factors corresponding to the first expansion factor, and t0 is the first parameter.

[0253] Optionally, t0 is 1, 2, or 3, or t0 is an integer related to Zc.

[0254] Optionally, or, Where n is an integer greater than or equal to 2.

[0255] Optionally, the second condition includes: SV1 = (SV2 + x) mod (y); where SV1 is any first shift value in the first set of shift values, SV2 is any second shift value in the second set of shift values, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0256] Optionally, the first element and the second element are two adjacent elements in the first column set of the first LDPC matrix, have the same column, and are both non-zero.

[0257] Optionally, the first column set includes the information column corresponding to the first LDPC matrix, or the core column corresponding to the first LDPC matrix, or all columns corresponding to the first LDPC matrix except for the punched column.

[0258] Figure 16 is a schematic block diagram of another communication device 1600 provided in an embodiment of this application. This communication device 1600 can be the first communication device in the method embodiment of Figure 12. The communication device 1600 includes:

[0259] Processing module 1610 is used to obtain a second LDPC matrix based on a first LDPC matrix, a first expansion factor, and a shift value corresponding to the first LDPC matrix, wherein each zero element in the first LDPC matrix corresponds to a zero matrix in the second LDPC matrix, and each non-zero element in the first LDPC matrix corresponds to a non-zero matrix in the second LDPC matrix.

[0260] The processing module 1610 is further configured to shift the elements of the non-zero matrix in the second LDPC matrix to obtain a check matrix. The check matrix includes multiple block matrices, each block matrix being in one-to-one correspondence with the non-zero matrix. Each block matrix is ​​composed of multiple sub-matrices, each sub-matrice being a zero matrix or a cyclic shift matrix with both row and column weights of 1. The shift value corresponding to the first cyclic shift matrix and the shift value corresponding to the second cyclic shift matrix satisfy at least one of a first condition or a second condition. The first cyclic shift matrix and the second cyclic shift matrix are two cyclic shift matrices in the block matrix that are adjacent in rows and have the same columns.

[0261] The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and the second parameter, wherein the second parameter is an integer greater than or equal to 3.

[0262] The transceiver module 1620 is used to send information encoded using the verification matrix.

[0263] Optionally, the second condition is associated with the first shift value, the second shift value, the second parameter, and a third parameter, wherein the third parameter is an integer.

[0264] Optionally, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0265] Optionally, the first condition includes: SV4-SV3+1-2t0≠0mod(Zc'), or SV4-SV3+1-2t0≥1mod(Zc'), or SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, and t0 is the first parameter.

[0266] Optionally, t0 is 1, 2 or 3, or t0 is an integer related to Zc'.

[0267] Optionally, or, Where n is an integer greater than or equal to 2.

[0268] Optionally, the second condition includes: SV3 = (SV4 + x) mod (y); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0269] Figure 17 is a schematic block diagram of another communication device 1700 provided in an embodiment of this application. This communication device 1700 can be the second communication device in the method embodiment of Figure 12. The communication device 1700 includes:

[0270] The transceiver module 1710 is used to receive information to be decoded;

[0271] Processing module 1720 is used to decode the information to be decoded based on a parity check matrix to obtain a decoded bit sequence. The parity check matrix includes multiple block matrices, each block matrix being in one-to-one correspondence with a non-zero matrix. Each block matrix is ​​composed of multiple sub-matrices, which are either zero matrices or cyclic shift matrices with row and column weights of 1. The shift values ​​corresponding to the first cyclic shift matrix and the shift values ​​corresponding to the second cyclic shift matrix satisfy at least one of a first condition or a second condition. The first cyclic shift matrix and the second cyclic shift matrix are two cyclic shift matrices that are adjacent in rows and have the same columns in the block matrix.

[0272] The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and the second parameter, wherein the second parameter is an integer greater than or equal to 3.

[0273] Optionally, the second condition is associated with the first shift value, the second shift value, the second parameter, and a third parameter, wherein the third parameter is an integer.

[0274] Optionally, the first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers.

[0275] Optionally, the first condition includes: SV4-SV3+1-2t0≠0mod(Zc'), or SV4-SV3+1-2t0≥1mod(Zc'), or SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc'); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, and t0 is the first parameter.

[0276] Optionally, t0 is 1, 2 or 3, or t0 is an integer related to Zc'.

[0277] Optionally, or, Where n is an integer greater than or equal to 2.

[0278] Optionally, the second condition includes: SV3 = (SV4 + x) mod (y); where SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer.

[0279] Figure 18 is a schematic block diagram of another communication device 1800 provided in an embodiment of this application. The communication device 1800 can be either the first or second communication device described above. The communication device 1800 includes a processor 1810, which implements the information transmission method provided in the embodiment of this application through logic circuits or by executing code instructions.

[0280] Optionally, the communication device 1800 may also include interface circuitry 1820. Processor 1810 and interface circuitry 1820 are coupled to each other. It is understood that interface circuitry 1820 may be a transceiver or an input / output interface.

[0281] Optionally, the communication device 1800 may also include a memory 1830 for storing instructions executed by the processor 1810, or storing input data required by the processor 1810 to execute instructions, or storing data generated after the processor 1810 executes instructions.

[0282] The aforementioned processor 1810 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by software instructions. The aforementioned processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0283] This application also provides a communication system, including a first communication device in the information transmission method provided in this application, and other communication devices communicating with the first communication device, a second communication device, and other communication devices communicating with the second communication device.

[0284] This application also provides a computer-readable storage medium storing a computer program for implementing the methods in the above-described method embodiments. When the computer program is run on a computer, the computer can implement the methods in the above-described method embodiments.

[0285] This application also provides a computer program product, which includes a computer program that, when run on a computer, causes the methods in the above method embodiments to be executed.

[0286] This application also provides a chip, including a processor connected to a memory for storing computer programs, and the processor for executing the computer programs stored in the memory, so that the chip performs the methods described in the above method embodiments.

[0287] In the embodiments of this application, for a technical feature, the technical features in the technical feature are distinguished by "first", "second" and "third", and there is no order of precedence or size among the technical features described by "first", "second" and "third".

[0288] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The term "at least one" in this application can represent "one" and "two or more." For example, A, B, and C can represent: A existing alone, B existing alone, C existing alone, A and B existing simultaneously, A and C existing simultaneously, C and B existing simultaneously, and A, B, and C existing simultaneously.

[0289] In this embodiment of the application, expressions such as "A includes B" are used to indicate that A may or may not include other items besides B. When other items are not included, it can be understood as "A is B", in which case "A" can be replaced with "B".

[0290] In the embodiments of this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to XX" can be understood as the destination of the information being XX, which may include direct transmission via the air interface or indirect transmission via the air interface by other units or modules. "Receive information from YY" can be understood as the source of the information being YY, which may include direct reception from YY via the air interface or indirect reception from YY via the air interface by other units or modules. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface.

[0291] In other words, sending and receiving can occur between devices, such as between network devices and terminal devices, or within a device, such as between components, modules, chips, software modules, or hardware modules within the device via buses, wiring, or interfaces.

[0292] It is understandable that information may undergo necessary processing, such as encoding and modulation, between the source and destination, but the destination can understand the valid information from the source. Similar statements in this application can be interpreted in a similar way and will not be elaborated further.

[0293] In the embodiments of this application, "instruction" can include direct and indirect instructions, as well as explicit and implicit instructions. The information indicated by a certain piece of information (hereinafter referred to as instruction information) is called the information to be instructed. In specific implementation, there are many ways to indicate the information to be instructed, such as, but not limited to, directly indicating the information to be instructed, such as the information to be instructed itself or its index. It can also indirectly indicate the information to be instructed by indicating other information, where there is an association between the other information and the information to be instructed; or it can indicate only a part of the information to be instructed, while the other parts are known or pre-agreed upon. For example, the instruction can be implemented by using a pre-agreed (e.g., protocol predefined) arrangement of various information, thereby reducing the instruction overhead to a certain extent. This application does not limit the specific method of instruction. It is understood that for the sender of the instruction information, the instruction information can be used to indicate the information to be instructed; for the receiver of the instruction information, the instruction information can be used to determine the information to be instructed.

[0294] In this application, unless otherwise specified, the same or similar parts between the various embodiments can be referred to each other. In the various embodiments of this application, and in the various implementation methods / methods / implementations within each embodiment, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments and between the various implementation methods / methods / implementations within each embodiment are consistent and can be mutually referenced. The technical features in different embodiments and the various implementation methods / methods / implementations within each embodiment can be combined according to their inherent logical relationships to form new embodiments, implementation methods, methods, or implementation approaches. The embodiments described below do not constitute a limitation on the scope of protection of this application.

[0295] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0296] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0297] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0298] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0299] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0300] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

A method for information transmission, characterized in that, include: The parity check matrix is ​​obtained based on the first low-density parity check (LDPC) code matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix, wherein... Any first shift value in the first shift value set corresponding to the first element and any second shift value in the second shift value set corresponding to the second element satisfy at least one of the first conditions or the second conditions. The first element and the second element are two elements in the first LDPC matrix that are adjacent in rows, have the same columns, and are both non-zero. The first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and the second parameter, wherein the second parameter is an integer greater than or equal to 3. Send the information encoded using the aforementioned check matrix. The method according to claim 1, characterized in that, The second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer. The method according to claim 1 or 2, characterized in that, Any first shift value in the set of first shift values ​​corresponding to the first element includes: the first shift value corresponding to the first element; Any second shift value in the set of second shift values ​​corresponding to the second element includes: the second shift value corresponding to the second element. The method according to any one of claims 1 to 3 is characterized in that, The step of obtaining the check matrix based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix includes: The second LDPC matrix is ​​obtained based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix, wherein the first LDPC matrix is ​​the base matrix; The parity check matrix is ​​obtained based on the second LDPC matrix, the second expansion factor, and the shift value corresponding to the second LDPC matrix. The method according to any one of claims 1 to 3 is characterized in that, Also includes: The elements with a value of 1 in the base matrix are promoted to an a-row, b-column matrix of all 1s, and the elements with a value of 0 in the base matrix are promoted to an a-row, b-column matrix of 0s, thus obtaining the first LDPC matrix. The method according to any one of claims 1 to 5, characterized in that, The first condition includes: -t1+1-SV1≠t2-SV2mod(Zc); Wherein, SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers. The method according to any one of claims 1 to 6, characterized in that, The first condition includes: SV2-SV1+1-2t0≠0mod(Zc), or, SV2-SV1+1-2t0≥1mod(Zc), or, SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); Wherein, SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, and t0 is the first parameter. The method according to claim 6 or 7, characterized in that, t0 is 1, 2, or 3, or t0 is an integer related to Zc. The method according to claim 8, characterized in that, or, Where n is an integer greater than or equal to 2. The method according to any one of claims 1 to 9, characterized in that, The second condition includes: SV1 = (SV2 + x) mod (y); Wherein, SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer. The method according to any one of claims 1 to 10, characterized in that, The first element and the second element are two adjacent elements in the first column set of the first LDPC matrix, have the same column, and are both non-zero. The method according to claim 11, characterized in that, The first set of columns includes the information columns corresponding to the first LDPC matrix, or the core columns corresponding to the first LDPC matrix, or all columns corresponding to the first LDPC matrix except for the punched columns. A method for information transmission, characterized in that, include: Receive the information to be decoded; The information to be decoded is decoded based on the parity check matrix to obtain the decoded bit sequence. The parity check matrix is ​​obtained based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. Any first shift value in the set of first shift values ​​corresponding to the first element and any second shift value in the set of second shift values ​​corresponding to the second element satisfy at least one of the first conditions or the second conditions. The first element and the second element are two elements in the first LDPC matrix that are adjacent in rows, have the same column, and are both non-zero. The first LDPC matrix is ​​a base matrix or a matrix obtained by improving the base matrix. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and the second parameter, wherein the second parameter is an integer greater than or equal to 3. The method according to claim 13, characterized in that, The second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer. The method according to claim 13 or 14 is characterized in that, Any first shift value in the set of first shift values ​​corresponding to the first element includes: the first shift value corresponding to the first element; Any second shift value in the set of second shift values ​​corresponding to the second element includes: the second shift value corresponding to the second element. The method according to any one of claims 13 to 15, characterized in that, The first condition includes: -t1+1-SV1≠t2-SV2mod(Zc); Wherein, SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers. The method according to any one of claims 13 to 16, characterized in that, The first condition includes: SV2-SV1+1-2t0≠0mod(Zc), or, SV2-SV1+1-2t0≥1mod(Zc), or, SV2-SV1+1-2t0∈{1,2,…,Zc-1,}mod(Zc); Wherein, SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, Zc is the first expansion factor or the maximum value in the expansion factor set corresponding to the first expansion factor, and t0 is the first parameter. The method according to claim 16 or 17, characterized in that, t0 is 1, 2, or 3, or t0 is an integer related to Zc. The method according to claim 18, characterized in that, or, Where n is an integer greater than or equal to 2. The method according to any one of claims 13 to 19 is characterized in that, The second condition includes: SV1 = (SV2 + x) mod (y); Wherein, SV1 is any first shift value in the first shift value set, SV2 is any second shift value in the second shift value set, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer. The method according to any one of claims 13 to 20, characterized in that, The first element and the second element are two adjacent elements in the first column set of the first LDPC matrix, have the same column, and are both non-zero. The method according to claim 21, characterized in that, The first set of columns includes the information columns corresponding to the first LDPC matrix, or the core columns corresponding to the first LDPC matrix, or all columns corresponding to the first LDPC matrix except for the punched columns. A method for information transmission, characterized in that, include: The second LDPC matrix is ​​obtained based on the first LDPC matrix, the first expansion factor, and the shift value corresponding to the first LDPC matrix. Each zero element in the first LDPC matrix corresponds to a zero matrix in the second LDPC matrix, and each non-zero element in the first LDPC matrix corresponds to a non-zero matrix in the second LDPC matrix. The elements of the non-zero matrices in the second LDPC matrix are shifted to obtain a check matrix. The check matrix includes multiple block matrices, each corresponding one-to-one with the non-zero matrices. Each block matrix is ​​composed of multiple sub-matrices, which are either zero matrices or cyclic shift matrices with row and column weights of 1. The shift values ​​corresponding to the first cyclic shift matrix and the shift values ​​corresponding to the second cyclic shift matrix satisfy at least one of a first condition or a second condition. The first cyclic shift matrix and the second cyclic shift matrix are two cyclic shift matrices in the block matrix that are adjacent in rows and have the same columns. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and the second parameter, wherein the second parameter is an integer greater than or equal to 3. Send the information encoded using the aforementioned check matrix. A method for information transmission, characterized in that, include: Receive the information to be decoded; The information to be decoded is decoded based on the parity check matrix to obtain the decoded bit sequence. The parity check matrix includes multiple block matrices, and the block matrices are in one-to-one correspondence with the non-zero matrices. Each block matrix is ​​composed of multiple sub-matrices, which are either zero matrices or cyclic shift matrices with row and column weights of 1. The shift value corresponding to the first cyclic shift matrix and the shift value corresponding to the second cyclic shift matrix satisfy at least one of the first condition or the second condition. The first cyclic shift matrix and the second cyclic shift matrix are two cyclic shift matrices that are adjacent in rows and have the same columns in the block matrix. The first condition is associated with the first shift value, the second shift value, the first expansion factor, and the first parameter, wherein the first parameter is an integer greater than or equal to 1; the second condition is associated with the first shift value, the second shift value, and the second parameter, wherein the second parameter is an integer greater than or equal to 3. The method according to claim 23 or 24 is characterized in that, The second condition is associated with the first shift value, the second shift value, the second parameter, and the third parameter, wherein the third parameter is an integer. The method according to any one of claims 23 to 25, characterized in that, The first condition includes: -t1+1-SV3≠t2-SV4mod(Zc'); Wherein, SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, 1≤t1≤t0, 1≤t2≤t0, t0 is the first parameter, and t1 and t2 are integers. The method according to any one of claims 23 to 26, characterized in that, The first condition includes: SV4-SV3+1-2t0≠0mod(Zc'), or, SV4-SV3+1-2t0≥1mod(Zc'), or, SV4-SV3+1-2t0∈{1,2,…,Zc'-1,}mod(Zc'); Wherein, SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, and Zc' is... or The maximum value in the corresponding set of expansion factors, Zc is the first expansion factor, L is the number of sub-matrices included in the block matrix, and t0 is the first parameter. The method according to claim 26 or 27 is characterized in that, t0 is 1, 2, or 3, or t0 is an integer related to Zc'. The method according to claim 28, characterized in that, or, Where n is an integer greater than or equal to 2. The method according to any one of claims 23 to 29, characterized in that, The second condition includes: SV3 = (SV4 + x) mod (y); Wherein, SV3 is the shift value corresponding to the first cyclic shift matrix, SV4 is the shift value corresponding to the second cyclic shift matrix, y is the second parameter, and x is the third parameter, wherein the third parameter is an integer. A communication device, characterized in that, Includes a processor for implementing the method as described in any one of claims 1 to 30. A computer-readable storage medium, characterized in that, include: The computer-readable medium stores a computer program; When the computer program is run by the processor, the method of any one of claims 1 to 30 is performed. A computer program product, characterized in that, Includes a computer program, which, when executed, causes the method as described in any one of claims 1 to 30 to be performed.

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