Deadzone valley and peak switching control for power converter systems and methods

Abstract

Systems, circuits and methods provide dead zone control for multi-level converter circuitry including controlling switching circuitry to generate an output voltage at a target voltage level and entering a dead zone control mode when the output voltage is within a dead zone window associated with the target voltage level. The dead zone control mode includes, during each switching cycle, comparing a sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level; entering a valley current mode during the cycle when sensed current is higher than the target current; entering a peak current mode when sensed current is lower than the target current, and controlling the switching circuitry to decrease the sensed current in the valley current mode or increase the sensed current in the peak current mode until the target current is reached.

Description

Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTDEADZONE VALLEY AND PEAK SWITCHING CONTROL FOR POWER CONVERTER SYSTEMS AND METHODSGregory SzczeszynskiCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 742, 376 filed January 6, 2025 and entitled “DEADZONE VALLEY AND PEAK SWITCHING CONTROL FOR POWER CONVERTER SYSTEMS AND METHODS,” which is incorporated herein by reference in its entirety.

[0002] This application is related to International Patent Application No.PCT / US2025 / 010999 filed January 9, 2025 and entitled “INTEGRATED CURRENT RESISTOR SENSING FOR MULTI-LEVEL CONVERTER,” which claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 620,613 filed January 12, 2024 and entitled “INTEGRATED CURRENT RESISTOR SENSING FOR MULTI-LEVEL CONVERTER,” all of which are incorporated herein by reference in their entirety.

[0003] This application is also related to International Patent Application No.PCT / US2025 / 011001 filed January 9, 2025 and entitled “FULLY DIFFERENTIAL LEVEL SHIFT IN A NOISY ENVIRONMENT,” which claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 620,331 entitled “FULLY DIFFERENTIAL LEVEL SHIFT IN A NOISY ENVIRONMENT,” all of which are incorporated herein by reference in their entirety.

[0004] This application is also related to International Patent Application No.PCT / US2025 / 011002 filed January 9, 2025 and entitled “MULTI-LEVEL POWER CONVERTER WITH RECONFIGURABLE CHARGE PUMP AND FRACTIONAL CHARGE PUMP MODES,” which claims priority to and the benefit of U.S. Provisional Application No. 63 / 620,678 filed January 12, 2024 and entitled “MULTI-LEVEL POWER CONVERTER WITH RECONFIGURABLE CHARGE PUMP AND FRACTIONAL CHARGE PUMP MODES;” all of which are incorporated herein by reference in their entirety.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0005] This application is also related to International Patent Application No.PCT / US2025 / 011263 filed January 10, 2025 and entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 620,488 filed January 12, 2024 and entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS,” U.S. Provisional Patent Application No. 63 / 620,507 filed January 12, 2024 and entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS,” and U.S. Provisional Patent Application No. 63 / 620, 623 filed January 12, 2024 and entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS,” all of which are incorporated herein by reference in their entirety.

[0006] This application is also related to International Patent Application No.PCT / US2025 / 011261 filed January 10, 2025 and entitled “GENERAL STARTUP FOR MULTI-LEVEL POWER CONVERTER CIRCUITS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 620,465 filed January 12, 2024 and entitled “STARTUP INTERLOCK FOR POWER CONVERTER CIRCUITS,” U.S.Provisional Patent Application No. 63 / 620,607 filed January 12, 2024 and entitled “STARTUP VOLTAGE SELECTION FOR MULTI-LEVEL POWER CONVERTER CIRCUITS,” and U.S. Provisional Patent Application No. 63 / 620,638 filed January 12, 2024 and entitled “GENERAL STARTUP FOR MULTI-LEVEL POWER CONVERTER CIRCUITS,” all of which are incorporated herein by reference in their entirety.

[0007] This application is also related to International Patent Application No.PCT / US2025 / 011265 filed January 10, 2025 and entitled “CAPACITORY SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 620,450 filed January 12, 2024 and entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS,” and U.S. Provisional Patent Application No. 63 / 620,469 filed January 12, 2024 and entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS,” all of which are incorporated herein by reference in their entirety.

[0008] This application is also related to International Patent Application No.PCT / US2025 / 011224 filed January 10, 2025 and entitled “INPUT CURRENT SLEW FOR A MULTI-LEVEL CONVERTER,” which claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 620,417 filed January 12, 2024 and entitled “INPUT CURRENTDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTSLEW FOR A MULTI-LEVEL CONVERTER;” all of which are incorporated herein by reference in their entirety.

[0009] This application is also related to International Patent Application No.PCT / US2025 / 011240 filed January 10, 2025 and entitled “ADJUSTING OVER-VOLTAGE PROTECTION BASED ON MODE OF OPERATION,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,726 filed January 12, 2024 and entitled “ADJUSTING OVER-VOLTAGE PROTECTION BASED ON MODE OF OPERATION,” all of which are incorporated herein by reference in their entirety.

[0010] This application is also related to International Patent Application No.PCT / US2025 / 011248 filed January 10, 2025 and entitled “HYBRID PEAK AVERAGE CURRENT MODE CONTROL,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,737 filed January 12, 2024 and entitled “HYBRID PEAK AVERAGE CURRENT MODE CONTROL,” all of which are incorporated herein by reference in their entirety.

[0011] This application is also related to International Patent Application No.PCT / US2025 / 011181 filed January 10, 2025 and entitled “CURRENT LIMITED VOLTAGE MODE CONTROL OF MULTIPLE INPUTS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,741 filed January 12, 2024 entitled “CURRENT LIMITED VOLTAGE MODE CONTROL OF MULTIPLE INPUTS,” all of which are incorporated herein by reference in their entirety.

[0012] This application is also related to International Patent Application No.PCT / US2025 / 011191 filed January 10, 2025 and entitled “MULTI-FUNCTION COMP PIN SYSTEMS AND METHODS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,527 filed January 12, 2024 and entitled “MULTI-FUNCTION COMP PIN SYSTEMS AND METHODS,” all of which are incorporated herein by reference in their entirety.

[0013] This application is also related to International Patent Application No.PCT / US2025 / 011225 filed January 10, 2025 and entitled “MULTI-LEVEL REVERSE CURRENT BLOCKING SYSTEMS AND METHODS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,553 filed JanuaryDocket No. 61658.146WO01 Client Ref. No. PER-560-PCT12, 2024 and entitled “MULTI-LEVEL REVERSE CURRENT BLOCKING SYSTEMS AND METHODS,” all of which are incorporated herein by reference in their entirety.

[0014] This application is also related to International Patent Application No.PCT / US2025 / 011276 filed January 10, 2025 and entitled “PRECISION ANALOG TO DIGITAL CIRCUIT TUNED VOLTAGE AND CURRENT MODE DC-DC CONVERTER,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,733 filed January 12, 2024 and entitled “PRECISION ANALOG TO DIGITAL CIRCUIT TUNED VOLTAGE AND CURRENT MODE DC-DC CONVERTER,” and U.S. Provisional Patent Application No. 63 / 620,738 filed January 12, 2024 and entitled “PREDICTIVE CONTROL LOOP PRE-CHARGING DURING A MULTI-LEVEL ZONE CHANGE,” all of which are incorporated herein by reference in their entirety.

[0015] This application is also related to International Patent Application No.PCT / US2025 / 011241 filed January 10, 2025 and entitled “DETECTOR CIRCUIT FOR DETECTING ONE OF MULTI-INPUT CONTROLLING SIGNALS THAT CONTROLS A CONTROL LOOP CIRCUIT,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,764 filed January 12, 2024 and entitled “DETECTOR CIRCUIT FOR DETECTING ONE OF MULTI-INPUT CONTROLLING SIGNALS THAT CONTROLS A CONTROL LOOP CIRCUIT,” all of which are incorporated herein by reference in their entirety.

[0016] This application is also related to International Patent Application No.PCT / US2025 / 011232 filed January 10, 2025 and entitled “MULTI-LEVEL CAPACITOR FAULT DETECTION SYSTEMS AND METHODS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,575 filed January 12, 2024 and entitled “MULTI-LEVEL CAPACITOR FAULT DETECTION SYSTEMS AND METHODS,” all of which are incorporated herein by reference in their entirety.

[0017] This application is also related to International Patent Application No.PCT / US2025 / 011235 filed January 10, 2025 and entitled “PARALLEL OPERATION OF MULTI-LEVEL POWER CONVERTERS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,582 filed January 12, 2024 andDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTentitled “PARELLEL OPERATION OF MULTI-LEVEL POWER CONVERTERS,” all of which are incorporated herein by reference in their entirety.

[0018] This application is also related to International Patent Application No.PCT / US2025 / 011236 filed January 10, 2025 and entitled “AVERAGE AND PEAK CURRENT SENSE SYSTEMS AND METHODS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. Application No. 63 / 620,763 filed January 12, 2024 and entitled “AVERAGE AND PEAK CURRENT SENSE SYSTEMS AND METHODS,” all of which are incorporated herein by reference in their entirety.BACKGROUND

[0019] This disclosure relates to electronic circuits, and more particularly for example to multi-level power converters.

[0020] Many electronic products, including mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, LCD, LED displays, and the like) use multiple voltage levels for operation. For example, radio frequency (RF) transmitter power amplifiers may operate at relatively high voltages (e.g., 12V or more), whereas logic circuitry may operate at a relatively low voltage level (e.g., 1-3V) and other circuitry may operate at an intermediate voltage level (e.g., 5-10V).

[0021] Direct current power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, solar cells, and rectified AC sources. Power converters which generate a lower output voltage level from a higher input voltage power source are commonly known as buck converters, so-called because the output voltage VOUT is less than the input voltage VIN, and hence the converter is “bucking” the input voltage. Power converters which generate a higher output voltage level from a lower input voltage power source are commonly known as boost converters, because VOUT is greater than VIN. Some power converters may be either a buck converter or a boost converter depending on which terminals are used for input and output. Some power converters may provide an inverted output.

[0022] One type of direct current power converter known as a multi-level power converter includes charge transfer capacitors as energy storage elements coupled by controlled switches to transfer charge from VIN to VOUT. Such charge transfer capacitors are commonly known asDocket No. 61658.146WO01 Client Ref. No. PER-560-PCT“fly capacitors” or “pump capacitors”. When a fly capacitor is used ( / .< ., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it.

[0023] There is a continued need for improved circuits and methods for more effectively and efficiently operating and implementing various type of electrical circuits and devices, including for example multi-level converter circuits.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTSUMMARY

[0024] Embodiments of the present disclosure include systems, circuits, and methods for operating and implementing various electronics circuits, including multi-level converter circuits.

[0025] In some embodiments a method for dead zone control in a multi-level converter circuit include controlling switching circuitry of a multi-level power converter circuit to generate an output voltage at a target voltage level; and entering a dead zone control mode when the output voltage is within a dead zone window associated with the target voltage level, the dead zone control mode comprising, during each switching cycle: comparing a sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level; entering a valley current mode during the cycle when sensed current is higher than the target current, the valley current mode configured to control the switching circuitry to decrease the sensed current to the target current and settle at the target current; and entering a peak current mode when sensed current is lower than the target current, the peak current mode configured to control the switching circuitry to increase the sensed current to the target current and settle at the target current.

[0026] The method may further include entering a valley current mode and / or entering a peak current mode further comprise adjusting the target current based on an offset value; and / or sensing an instantaneous current of the multi-level power converter circuit, the instantaneous current based at least in part on a sensed current associated with a high-side switch of the multi-level power converter circuit and a low-side switch of the multi-level power converter circuit. Each level of the multi-level power converter circuit may include a corresponding dead zone window. Controlling the switching cycle of a multi-level power converter circuit to generate an output voltage at a target voltage level may further include operating the multi-level power converter circuit in a buck mode and / or boost mode.Comparing the sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level may further include receiving the sensed current at a first input of a pulse-width modulation circuit; receiving a target current as a second input of a pulse-width modulation circuit; and generating a pulse-width modulation signal based on a comparison of the sensed current and the target current.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0027] In various embodiments, a system includes control circuitry configured to control switching circuitry of a multi-level power converter circuit to generate an output voltage at a target voltage level, the control circuitry further configured to enter a dead zone control mode when the output voltage is within a dead zone window associated with the target voltage level, the dead zone control mode configured to, during each switching cycle: compare a sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level; enter a valley current mode during the cycle when sensed current is higher than the target current, the valley current mode configured to control the switching circuitry to decrease the sensed current to the target current and settle at the target current; and enter a peak current mode when sensed current is lower than the target current, the peak current mode configured to control the switching circuitry to increase the sensed current to the target current and settle at the target current.

[0028] The control circuitry may be further configured to adjust the target current based on an offset value and wherein the multi-level power converter circuit is driven towards the adjusted target current. The multi-level power converter circuit may include the switching circuitry; wherein the control circuitry is configured to operate the switching circuitry to charge and / or discharge one or more of a plurality of fly capacitors; and wherein the control circuitry is further configured to sense an instantaneous current of the multi-level power converter circuit, the instantaneous current based at least in part on a sensed current associated with a high-side switch of the switching circuitry and a low-side switch of the switching circuitry. In some embodiments, the system further includes the plurality of fly capacitors. Each level of the multi-level power converter circuit may include a corresponding dead zone window.

[0029] The control circuitry may be further configured to control the switching cycle of the multi-level power converter circuit by operating the multi-level power converter circuit in a buck mode and / or boost mode. The control circuitry may further include: a pulse-width modulation circuit configured to receive the sensed current at a first input and a target current at a second input, wherein the pulse-width modulation circuit is further configured to generate a pulse-width modulation signal based on a comparison of the sensed current and the target current; and an inverter circuit coupled to receive and invert the pulse-width modulation signal.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0030] In various embodiments, an integrated circuit includes: control circuitry couplable to a plurality of switches and a plurality of fly capacitors forming a network of interconnected switches and fly capacitors, wherein the control circuitry is configurable to control the plurality of switches to cycle the network between at least two switching configurations to generate an output voltage; wherein the control circuitry is further configured to enter a dead zone control mode when the output voltage is within a dead zone window associated with a target level, the dead zone control mode configured to, during each switching cycle: compare a sensed current of the network with a target current corresponding to the target level; and drive an output current of the network towards the target current.

[0031] The control circuitry may be further configured to drive the output current by: entering a valley current mode during the switching cycle when the sensed current is higher than the target current, the valley current mode configured to control the plurality of switches to decrease the sensed current to the target current and settle at the target current; and entering a peak current mode during the switching cycle when the sensed current is lower than the target current, the peak current mode configured to control the network to increase the sensed current to the target current and settle at the target current. The control circuitry may be further configured to drive the current of the network towards the target current by adjusting the target current based on an offset value and wherein output current is driven towards the adjusted target current.

[0032] The integrated circuit may further include the plurality of switches; wherein the control circuitry is configured to operate the network to charge and / or discharge one or more of the plurality of fly capacitors; and wherein the control circuitry is further configured to sense an instantaneous current of the network, the instantaneous current based at least in part on a sensed current associated with a high-side switch of the network and a low-side switch of the network. The control circuitry may be further configured to control the switching cycle of the network by operating the network in a buck mode and / or boost mode. The control circuitry may further include: a pulse- width modulation circuit configured to receive the sensed current at a first input and a target current at a second input, wherein the pulse-width modulation circuit is further configured to generate a pulse-width modulation signal based on a comparison of the sensed current and the target current. In some embodiments, the integrated circuit further includes an inverter circuit coupled to receive and invert the pulsewidth modulation signal.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0033] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present disclosure will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTDESCRIPTION OF THE DRAWINGS

[0034] FIG. 1 A is an example power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0035] FIG. IB is an example power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0036] FIG. 2A is an example dual integrated circuit (IC) power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0037] FIG. 2B is an example dual IC power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0038] FIG. 3A is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0039] FIG. 3B is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0040] FIG. 4 is a diagram illustrating an example charging function in step down regulation mode of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0041] FIG. 5 is a diagram illustrating an example charging function in step down divide by 3 charge pump mode, in accordance with one or more embodiments of the present disclosure.

[0042] FIG. 6 is a functional block diagram illustrating aspects of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0043] FIG. 7 is a block diagram illustrating an example system implementing a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0044] FIG. 8A is a circuit diagram illustrating an example 3-level converter circuit, in accordance with one or more embodiments of the present disclosure.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0045] FIG. 8B is a circuit diagram illustrating an example 4-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0046] FIG. 8C is a circuit diagram illustrating an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0047] FIG. 9 is an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0048] FIG. 10 is a block diagram of an example embodiment of control circuitry for an -level converter cell, in accordance with one or more embodiments of the present disclosure.

[0049] FIG. 11 is a chart illustrating dead zones in a 4-level power converter, in accordance with one or more embodiments of the present disclosure.

[0050] FIGs. 12A and 12B are charts illustrating a first example of dead zone control in a 4-level power converter, in accordance with one or more embodiments of the present disclosure.

[0051] FIGs. 13 A and 13B are charts illustrating a second example of dead zone control in a 4-level power converter, in accordance with one or more embodiments of the present disclosure.

[0052] FIG. 14 is a block diagram of an example embodiment of control circuitry for use in dead zone control of an M-level converter, in accordance with one or more embodiments of the present disclosure.

[0053] FIG. 15 illustrates an example dead zone control process 1500, in accordance with one or more embodiments of the present disclosure.

[0054] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It is noted that sizes of various components and distances between these components are not drawn to scale in the figures. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTDETAILED DESCRIPTION

[0055] The present disclosure encompasses novel circuits, architectures, systems, and methods that more effectively and efficiently address the configuration and operation of multilevel converter circuits. It will be appreciated that various improvements disclosed herein encompass innovative circuits, hardware components, architectures, and related logic that are applicable to applications beyond multi-level converter circuits.

[0056] FIGs. 1-6 illustrate various embodiments of a high efficiency 4-level step-down and step-up power converter for battery charging applications, such as single cell Li-ion and Li-polymer battery applications. In the illustrated embodiments, the power converter is configured to deliver up to 5 amperes (A) of charging current in regulation mode and in a divide-by-3 charge pump mode, though other configurations are within the scope of the present disclosure. The power converter can be configured, for example, into dual ICs operation for 9A charging current in regulation mode and in divide-by-3 charge pump mode. Although a 4-level power converter is illustrated, it will be appreciated that the embodiments described herein may be applicable to various M-level implementations, where M >= 3.

[0057] In some implementations, for example, the power converter may supply an input range of approximately 4.5 V to 18 V input to support both universal serial bus (USB) and wireless inputs, and in a reverse step-up mode, the output may be programmable from 4.8 V to 16 V in 100 mV step with a programmable output current limit up to 1.7 A. This input voltage range may be used, for example, to support fast charging of single Li-Ion cells from USB and wireless input. It will be appreciated that other voltage and current ranges and limits may be implemented depending on the application. It will also be appreciated that while compatibility with USB is described herein, other wired interfaces and protocols may be implemented with the power converter of the present disclosure.

[0058] In various embodiments, the power converter may be implemented as a single integrated circuit (IC) (see, e.g., Figs. 1 A-B), dual-integrated circuits (see, e.g., Figs. 2A-B), or in other configurations depending on the implementation. In various embodiments, the power converter may operate as a parallel charger along with a main charger, as shown in Fig. 3B, to provide the desired functionality noted herein and, for example, as illustrated in Figs. 4 and 5 for the desired charging functionality for various applications, as would be understood by one skilled in the art. Fig. 3B may represent a system level point of view of a mobile architectureDocket No. 61658.146WO01 Client Ref. No. PER-560-PCThaving a parallel charger and a main charger that accepts power from a wired port (e.g., a wired USB) or from a wireless interface. The parallel charger for one or more embodiments may represent an IC as illustrated in Figs. 1-3 A, for example, and may function to charge a battery for some portion of the charging profile (e.g., as shown in Figs. 4 and 5), while the main charger charges the battery for other portions of the charging profile. In various embodiments, the parallel charger may also be configured to function as the main charger as well, depending upon the desired application. The novel architecture disclosed herein may be implemented to enable (i) improved efficiency (e.g., at 9A charging current) in a low-profile solution; (ii) low electromagnetic interference (EMI) fixed-frequency operation under heavy load conditions; (iii) input and output current and voltage, IC temperature monitoring and telemetry via interintegrated circuit (EC) technology; and / or (iv) full protection including input and output under voltage lockout (UVLO), input and output over voltage protection (OVP), input and output over current protection (OCP), and IC over-temperature with fault and warning status. In some implementations, the power converter supports divide-by-3, step-down and step-up regulating modes, dual external disconnect switch control, and / or paralleled operation.

[0059] In the illustrated embodiments, the power converter is implemented as a multi-level charge pump incorporating power switches and control circuitry. The power converter’s internal bias may be provided by the system battery through a VOUT connection (e.g., pin). The charging input can be USB (or other wired input) or wireless input by an external FET register control. In some implementations, the power converter may be programmed to different operating modes, which may include a step-down regulation mode, a step-down divide-by-3 charge pump mode, and a reverse step-up mode.

[0060] In a step-down regulation mode, the power converter operates as a multi-level stepdown regulator to support USB power delivery (USB-PD) (or other wired protocol) or fixed input charging. During a constant-current (CC) phase, the maximum charging current may be limited for example, by configuring registers. When the input current does not reach a predetermined maximum input setting, the charge current is set to a predetermined maximum output setting. If the input current reaches the input maximum setting, then the charge current throttles and maintains input current at the input maximum setting. This allows maximum charging current while ensuring that the charge current does not go above a battery maximum current rating and the input current does not trip adapter over-current protection.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0061] During a constant-voltage (CV) phase, the CV regulation may be limited, for example, by configuring registers. In operation, a single-wire sense pin or other sensor is configured to sense the output voltage VOUT, which is compared to a predetermined value stored in a register, VOUT REG. The voltage differential between the battery’s positive terminal and negative terminal is sensed and compared to a predetermined value stored in a register, VBATT REG. In some implementations, a single-wire sense pin or other sensor senses VBATTP (battery voltage at positive terminal) and a single-wire sense pin or other sensor senses VBATTN (battery volage at negative terminal). The CV regulates to the lower of the two settings. If the VOUT sensed voltage reaches VOUT REG first, then CV is regulated to VOUT REG. If the VBATTP sensed voltage reaches VBATT REG first, then CV is regulated to VB ATT REG. This provides a fast battery top off while preventing voltage above safety limit.

[0062] In a step-down divide-by-3 charge pump mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a divide-by-3 step-down charge divider to support USB-Programmable Power Supply (USB-PPS) or other charging protocol or programmable input charging. In some embodiments, the power converter allows the USB-PPS adapter to control voltage and current and ignores conflicting settings (e.g., settings stored in registers for I0UT MAX, VOUT REG and VBATT REG). In this mode, the power converter monitors an IIN MAX setting, shuts down the power train (which includes switches to configure, enable and disable various modes of operation) and disconnects external FET when UN current exceeds IIN MAX setting. In the illustrated embodiment, the output current is up to 10A in dual IC operation and 5 A in single IC operation.

[0063] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register) the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired protocol or standard) or wireless input. The power converter draws power from the system battery and regulates VIN to the VOUT REG programmable setting of 4.8V to 16V. The VIN output current limit may be set, for example, by an IIN_MAX register.

[0064] In some embodiments, to enable the IC, both an EN pin and an IC EN bit are set to logic high (1). When either the EN pin or IC_EN bit is set to logic low (0), the IC is disabled. After the IC is enabled, the POR status bit sets to 1 to indicate the IC has a fresh power up.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0065] In some embodiments, the power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs may be controlled by registers (e.g., 1 -bit registers V EXTG, EXTG EN and EXTGX). The V EXTG bit sets the gate drive voltage and can be set to 9V or 5 V, in the illustrated embodiment. The EXTGX bits select which FET(s) to turn on. The EXTG EN bit enables the gate driver to turn on the selected FET(s). In various embodiments, the external FET can be turned on or off independently from other IC operations except when the IC is disabled. The EXT EN IND status bit set to 1 when external FET is enabled. When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respected FET would not turn on from the off mode.

[0066] In various embodiments, the power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path may be configured between the external FET on time and the power train on time to minimize in-rush current. Next, both PT EN pin and PT EN bit are set to logic high (1) to turn on the power train. When either PT EN pin or PT EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train may be configured to turn on first before the master IC. The COMP, SYNC and SYNCH pins from two ICs gate the power train and synchronize the operation. The SYNC SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down the power train operation when fault is detected.

[0067] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired port) or wireless input. The power converter draws power from the system battery and regulates VIN pin to a VOUT REG programmable setting of 4.8V to 16V. The VIN output current limit is set by IIN_MAX register.

[0068] To enable the IC, both the EN pin and IC EN bit are set to logic high (1). When either EN pin or IC EN bit is set to logic low (0), the IC is disabled. After the IC enables, the POR status bit sets to 1 to indicate the IC has a fresh power up. The power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs are controlled by register bits, such as V EXTG, EXTG EN and EXTGX. The V EXTG bit sets the gate drive voltage and can be set to 9V orDocket No. 61658.146WO01 Client Ref. No. PER-560-PCT5 V, for example. The EXTGX bits select which FET(s) to turn on. The EXTG EN bit enables the gate driver to turn on the selected FET(s). The external FET can be turned on or off independently from other IC operation except when the IC is disabled. The EXT EN IND status bit set to 1 when external FET is enabled.

[0069] When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respective FET would not turn on from off mode. The power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path should be given between external FET on time to power train on time to minimize in-rush current. Next, both PT EN pin and PT EN bit are set to logic high (1) to turn on the power train. When either PT EN pin or PT EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train is turned on before the master IC. The COMP, SYNC and SYNCH pins from the two ICs gate the power train and synchronize the operation. SYNC SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down power train operation when a fault is detected.

[0070] In accordance with various embodiments, an example power converter initialization, an example power up sequence, and an example fault handling will now be described for the three different operating modes. In an example step-down regulation mode, the initialization and power up sequence uses EXT1 as an example. The same sequence may apply to EXT2 with the only change in EXTGX bit and related EXT2 register settings. First, pull EN to logic high and then set IC EN bit= 1 at 100us(TBD) after EN is logic high to enable IC. IC startup from POR stage, POR bit reports 1 indicating fresh IC startup. Next, the POR bit is read to confirm the IC is enabled. The FREQUENCY register is then set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT REG register is set to the target regulation voltage on the VOUT sense pin in CV operation. The VBATT REG register is set to the target regulation voltage on the VBATTP sense pin in CV operation. The IOUT MAX register is set to the target maximum charger current in CC operation, and the IIN MAX register is set to a value below the adapter current limit. Next, the FAULT and WARNING registers was set to a desired setting. Each Fault and Warning enables at a different time based on IC status and operating mode. The WATCHDOG register is then set to a desired setting.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0071] The MODE register and other related registers are set for step-down regulation mode, including power train setup and enablement of an external FET, while checking for faults. In a dual IC operation, the external FETs are controlled by the master IC. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the external FET after the shutdown fault is initiated. Next, the power train is enabled. In a dual IC operation, the slave IC power train is turned on before the master IC. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation.

[0072] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0073] An example step-down divide-by-3 power converter mode initialization and power up sequence will now be described. The initialization and power up sequence uses EXT1 as an example, but it will be appreciated that the same sequence applies to EXT2 with a change in EXTGX bit and related EXT2 register settings. The EN is pulled to logic high and then IC EN bit=l at 100us(TBD) after EN is logic high to enable IC. The IC starts up from POR stage, POR bit reports 1 indicating fresh IC startup. The POR bit is read to confirm the IC is enabled. The FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The IIN MAX register is set to a value below the adapter current limit. VOUT REG, VBATT REG and I0UT MAX registers are not used in step-down divide-by-3 charge pump mode. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. The FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at different time based on IC status and operating mode.

[0074] The MODE register and other registers are set for step-down divide-by-three mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, aDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTbit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter.

[0075] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0076] An example reverse step-up mode initialization and power up sequence will now be described. This initialization and power up sequence uses EXT2 as an example, but the same sequence applies to EXT1 with the change in EXTGX bit and related EXT1 register setting. The value EN is pulled to logic high and then IC EN bit is set to 1 at lOOus(TBD) after EN is logic high to enable IC. The IC starts up from the POR stage, and the POR bit reports 1 indicating a fresh IC startup. The POR bit is read to confirm the IC is enabled. Next, the FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT REG register is set to the target regulation voltage at VIN. Next, the IIN MAX register is set to the target current limit. VBATT REG and I0UT MAX registers are not used in reverse step-up mode. FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at a different time based on IC status and operating mode.

[0077] The MODE register and other registers are set for reverse step-up mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. In dual IC operation, the slave IC power train is turned on before the master IC and is controlled by the master IC.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0078] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault. The EXT2 or VIN pins are not configured to detect OVP as it is set as the output in reverse step-up mode. But if EXT2 or VIN pin detects an OVP event, then IC STATUS1 and IC STATUS2 would report the fault event.

[0079] In an example system 700 illustrated in FIG. 7, a power converter 720 is implemented in a host 710 (e.g., a device or system) that includes a battery 730 and various system components 740. The host 710 may be any system or device that implements a power converter as described herein, including but not limited to a smart phone, tablet, portable electronics, a mobile device, low power electronics, and other electronic systems. The battery 730 may include one or more batteries that store electricity for use by the host 710, such as single cell Li-ion and Li-polymer batteries.

[0080] The power converter 720 may be configured to convert electricity stored in the battery 730 to a desired system voltage, VSYS, for powering various system components 740, which may include one or more logic devices 742, memories 744, communications components 746, input / output (I / O) components 748, circuitry 750, and other components 752. The power converter 720 may also supply power to one or more external devices 760, such as a component connected to the host 710 through a wired or wireless connection, such as a USB compatible device. The power converter 720 may also be configured to receive power from an external power source 712 and convert the received power to the battery 730 for storage, or to the system components 740 and / or external device 760, as applicable.

[0081] In various embodiments, the one or more logic devices 742 and memories 744 may be configured to perform operations of the host 710. A logic device 742 may be implemented as a general -purpose processor, a digital signal processor (DSP), an applicationspecific integrated circuit (ASIC), a microcontroller, a programmable logic device (PLD), a field-programmable gate array (FPGA), or other programmable logic device(s). The logic device 742 and other components may be configured through hardwiring, software execution, or a combination of both. In various embodiments, the host 710 includes one or more memory devices designed to retain data, such as software instructions for execution by the logic device. The memory may include volatile and non-volatile memories, such as random-Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTaccess memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile randomaccess memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), flash memory, hard disk drives, or other memory types. The logic device may be configured to execute software instructions residing in the memory, thereby accomplishing method steps and operations.

[0082] Referring to FIGs. 8A-8C, the converter circuit may be configured to switch between two or more switch states. One or more PWM duty cycle controllers may be provided to set the time in each switch state based on the voltage at VOUT. For example, FIG. 8A is a schematic diagram of a 3 -level DC-to-DC buck converter circuit 800 that may be used as the converter circuit 920 of FIG. 9. A set of four switches, S1-S4, is series-coupled between VIN and circuit ground. A fly capacitor Cl is coupled in series with switches S3 and S4, and in parallel with switches SI and S2. An inductor LI is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and the voltage across the output capacitor COUT is VOUT.

[0083] In the illustrated example, the presence of the single fly capacitor Cl in the converter circuit 800 enables four switch states that each generate one of three voltage levels at node Lx. In a first switch state, S2 and S4 are closed and SI and S3 are open, effectively bypassing Cl and connecting Lx to circuit ground (voltage level at Lx = GND). In a second switch state, S2 and S4 are open and SI and S3 are closed, effectively bypassing Cl and connecting Lx to VIN (voltage level at Lx = VIN). In a third switch state SI and S4 are open and S2 and S3 are closed, connecting Cl from VIN to LX, and thus charging Cl with inductor LI current flowing into a load. The voltage across Cl will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2. In a fourth switch state, SI and S4 are closed and S2 and S3 are open, connecting Cl from Lx to GND and thus discharging Cl with inductor LI current flowing to a load. The voltage across Cl will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2 (e.g., this may assume that Cl was previously charged in state three). Accordingly, the illustrated converter circuit 800 has two switch states that generate a voltage level of VIN / 2 at the Lx node.

[0084] If the converter circuit 800 is toggled between switch states three and four (avoiding switch state two that bypasses the fly capacitor Cl), the inductor LI sees small jumps in the voltage level at Lx, going from GND to only VIN / 2 and back to GND, which results in reducedDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTvoltage ripple across the inductor LI and less filtering to smooth VOUT than a converter circuit with only SI and S2 switches.

[0085] Adding additional series switches Sx and fly capacitors Cx to the 2-level converter circuit 800 increases the number of switch states and resulting voltage levels between VIN and circuit ground that can be applied to the Lx node, thus generating an even smaller voltage ripple across the inductor L. This reduces the filtering requirements to get a smooth output voltage. For example, a 4-level DC-to-DC buck converter circuit (see, e.g., FIG. 8B) includes 6 series-coupled switches S1-S6 and two fly capacitors Cx (X = 2). Consequently, a 4-level converter circuit can define 4 voltage levels (VIN, GND, ’AVIN, and %VIN) at node LX from 8 switch states (3 switch states result in the ’AVIN level at Lx, and 3 other switch states result in the %VIN level at Lx). For some applications, VOUT is set low enough that the voltage level at node Lx alternates between GND and the next higher voltage level available. For higher output voltages, the switching pattern may neveruse GND. For example, in a 4-level converter circuit, an output VOUT set to 0.5*VIN can be achieved by alternating the Lx node between % VIN and ’A V.

[0086] A different interpretation of a multi-level converter circuit is that the fly capacitors Cx create a charge-pump for the buck converter circuit. Unlike a standard charge-pump where the output is restricted to one output, a multi-level converter circuit allows the fly capacitors Cx to be coupled to create multiple intermediate voltages. For the 4-level example, the two fly capacitors each act as a ’A charge-pump with the additional benefit that any input voltage that is a sum of ’A ratios can be created, including VIN and GND.

[0087] A multi-level converter circuit couples the fly capacitors Cx in different combinations in order to bring the voltage level at the Lx node down or up. As noted above, when a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it, which creates a control problem in maintaining an average voltage.

[0088] Resolving the charge-balance problem so as to maintain an average voltage across the single capacitor in a 3 -level converter circuit will now be described. For example, in a 3-level converter circuit, one way to generate the Level- 1 (GND) and Level-3 (VIN) voltage levels at the Lx node is to not use the fly capacitors Cl for these Lx voltage levels. However, for the Level 2 (VIN / 2) voltage level at Lx, two separate switch states can be used: one switchDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTstate charges the capacitor (S3 and S2 closed, SI and S4 open) and the other switch state discharges the capacitor (S3 and S2 open, SI and S4 closed). The control of a 3-level converter circuit may operate such that each time the converter circuit switches states to Level-2, a controller can alternate between charging and discharging the single capacitor to maintain its voltage. A voltage comparator can be used to monitor the capacitor to help decide on a charging state or a discharging state. For instance, if the capacitor voltage is below VIN / 2, then a controller would select charge (the third switch state), and if the capacitor voltage is above VIN / 2, then the controller would select discharge (the fourth switch state).

[0089] Referring to FIGs. 8B, a 4-level converter circuit 830 (X = 2) illustrates the chargebalance difficulty when more capacitors are present. A Level- 1 voltage level (GND) and a Level-4 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level (’A VIN) and Level-3 voltage level (% VIN) at Lx each can be achieved by any of three different switch states. At higher orders of a multi-level converter circuit (X > 2), more switch states are possible for generating the intermediate levels between VIN and GND. The problem gets more complicated with a 5-level converter circuit (X= 3). A Level- 1 voltage level (GND) and a Level-5 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level (’AVIN) and Level-4 voltage level (% VIN) at Lx each can be achieved by any of four different switch states, the Level-3 voltage level (2 / 4 VIN) at Lx can be achieved by any of six different switch states.

[0090] As should be clear from these examples, determining a suitable charge-balance method can become exceedingly difficult as the complexity of a multi-level converter circuit increases. As previously noted, most conventional control methods rely on establishing a sequence of linked state-changes to try to achieve charge balance. Control systems based on long sequences of switch states generally assume that all system variables - such as input voltage and output current - are constant during the sequence. This is unrealistic for a real-world environment, where all system variables tend to be dynamic.

[0091] In a 2-Level example, the converter circuit switches between two switch states: SI closed and S2 open (voltage level at Lx = VIN), or SI open and S2 closed (voltage level at Lx = GND). APWM duty cycle controller sets the time in each switch state based on the voltage at VOUT, which determines the amplitude of the average voltage at Lx (noting that, the average Lx voltage in theory is equal to the VOUT average voltage, but that, due to parasitics, the Lx average voltage is higher and / or lower (for negative currents) than the VOUT average). As canDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTbe appreciated, the inductor L sees large jumps in the voltage level at Lx, from GND to VIN and back to GND. The resulting voltage ripple across the inductor L necessitates a significant amount of filtering to smooth VOUT.

[0092] An alternative way of reducing the voltage ripple across the inductor L is to add more series switches as well as charge transfer capacitors as energy storage elements to transfer charge from VIN to VOUT. AS noted above, such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors” and may be external components coupled to an integrated circuit embodiment of a converter circuit. The presence of X fly capacitors Cx defines a multi-level capacitive converter circuit capable of generating M=X+ 2 voltage levels at node Lx from 2C I’ switch states.

[0093] FIG. 8C is schematic diagram of a generalized AT-level multi-level converter cell 870 that may be used as the converter circuit 920 of FIG. 9. A set of switches, Sl-S[2*(Af- 1)], is series-coupled between VIN and circuit ground. The set of switches are organized in switch pairs: SI & S2, S3 & S4, ... S[2*(Af- 2)+l] & S[2*(Af- 1)]. A set ofM- 2 fly capacitor Cx is coupled in series with certain respective switches, and in parallel with switches in between those switches. In terms of switch pairs, there are M~ 1 pairs of switches, or one more than the number of fly capacitors. An optional inductor L is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and again the voltage across the output capacitor COUT is VOUT. The inductor L doubles as a virtual current source that facilitates movement of charge between the fly capacitors Cx. This creates a very efficient form of charge transfer, but introduces the problem of charge-balancing the fly capacitors Cx.

[0094] In various embodiments, each fly capacitor Cx has a first terminal coupled between an outer high-side switch S[2*x + 1] and an inner high-side switch S[2*x-1], where “high-side” refers to the VIN side of the converter circuit. Each fly capacitor Cx has a second terminal coupled between an outer low-side switch S[2*x + 2] and an inner low-side switch S[2*x], where “low-side” refers to the circuit ground (GND) side of the converter circuit. Thus, for an M= 3 multi-level converter cell, a first terminal of the single (X= 1) fly capacitor Cl would be coupled between outer high-side switch S3 and inner high-side switch SI, and a second terminal of the capacitor Cl would be coupled between inner low-side switch S2 and outer low-side switch S4. Accordingly, each fly capacitor Cx within the multi-level converter cell 870 has four switches that can affect current flow through that fly capacitor Cx.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0095] In some embodiments, a voltage detector, which may be a simple comparator-type circuit, is provided to sense the voltage across a corresponding fly capacitor Cx with respect to a reference voltage, VREF, which represents a desired target voltage for the fly capacitor Cx. Every fly capacitor Cx may have a target average voltage in order to maintain proper output level. For an Ff-level converter and capacitor Cx, where x = 1, 2, ... [M~ 2], its target voltage is:Vtarget

[0096] The voltage detector may be configured to output a HIGH / LOW status signal, CFX H / L, indicating with the voltage across the corresponding fly capacitor Cx is greater than VREF or less than VREF. The CFX H / L status signal is coupled to control circuitry for the switches associated with the fly capacitor Cx.

[0097] The control circuitry for the four switches that can affect current flow through a fly capacitor Cx set states for those switches in part as a function of the voltage across the fly capacitor Cx as measured by the associated voltage detector and conveyed by the CT.Vn i status signal. Accordingly, for ease of understanding, it can be said that each fly capacitor Cx “controls” its own pairs of high-side and low-side switches. If it is assumed that current flow in the inductor is charging the output VOUT, there are four possible states that can be defined for the pairs of high-side and low-side switches for each fly capacitor Cx.

[0098] In a switch state in which the outer high-side and inner low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a charging configuration (whether or not charging actually occurs may depend on the switch states for other fly capacitors Cx). In a switch state in which the inner high-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a discharging configuration (whether or not discharging actually occurs may depend on the switch states for other fly capacitors Cx). In a switching state in which the inner low-side and outer low-side switches associated with fly capacitor Cx are closed, and all other associated switches are open, fly capacitor Cx would be bypassed. In a switching state in which the outer high-side and inner high-side switches associated with fly capacitor Cx are closed, and all other associated switches are open, fly capacitor Cx would again be bypassed.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0099] While each fly capacitor Cx can control both of its own pairs of high-side and low-side switches, in general, methods of control disclosed herein may utilize either the outer switches or the inner switches controllable by each corresponding capacitor. For example, referring to FIG. 8B, in “outer- switch” methods, fly capacitor Cl will control its outer switches S3 and S4, fly capacitor C2 will control its outer switches S5 and S6, etc. Conversely, for example, in “inner-switch” methods, fly capacitor Cl will control its inner switches SI and S2, fly capacitor C2 will control its inner switches S3 and S4, etc. The switch states of either pair (inner or outer) of switches controlled by a fly capacitor Cx may be complementary - that is, no fly capacitor Cx closes or opens both of its high-side and low-side controlled switches at the same time. If each fly capacitor Cx controls its outer switches, then no fly capacitor controls the left-over innermost switches SI and S2. If instead each fly capacitor Cx controls its inner-switches, then no fly capacitor controls the left-over outermost switches S[2*(A / -1)] and S[2*(AT-2)+l ]. Switch states for the left-over switches are also complementary.

[0100] FIG. 9 is a high-level block diagram of an example circuit that includes a power converter 900, in accordance with one or more embodiments of the present disclosure. In the illustrated example, the power converter 900 includes a converter circuit 920 and a controller 910. The converter circuit 920 and controller 910 may be configured to implement, for example, any of the multi-level power converter circuits as previously described with reference to FIGs. 1 A-8C, and as described further herein. In the illustrated embodiment, the converter circuit 920 is configured to receive an input voltage VIN from a voltage source and transform the input voltage VIN into an output voltage VOUT. In some embodiments of the power converter 900, auxiliary circuitry (not shown), such as a bias voltage generator(s), a clock generator, a voltage control circuit, etc., may also be present and coupled to the converter circuit 920 and the controller 910.

[0101] The controller 910 receives a set of input signals and produces a set of output signals. Some of these input signals arrive along a signal path connected to the converter circuit 920. These input signals carry information that is indicative of the operational state of the converter circuit 920. The controller 910 may also receive a clock signal CLK (for synchronous converter circuits 920) and one or more external input / output signals VO that may be analog, digital (encoded or direct signal lines), or a combination of both. Based upon the received input signals, the controller 910 produces a set of control signals back to the converter circuit 920 that control the internal components of the converter circuit 920 (e.g., internal switches, suchDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTas low voltage FETs / MOSFETs) to cause the converter circuit 920 to boost or buck VIN to VOUT. In some embodiments, an auxiliary circuit (not shown) may provide various signals to the controller 910 (and optionally directly to the converter circuit 920), such as the clock signal CLK, the input / output signals VO, as well as various voltages, such as a general supply voltage VDD and a transistor bias voltage VBIAS.

[0102] FIG. 10 is a block diagram of one embodiment of advanced control circuitry 1000 for an A7-level converter cell such as the generalized version depicted in FIG. 8B. The A7-level converter cell 1020 is shown coupled to an output block 1001 comprising an inductor L and an output capacitor Cour (conceptually, the inductor L also may be considered as being included within the A7-level converter cell 1020). The advanced control circuitry 1000 functions as a control loop coupled to the output of the A7-level converter cell 1020 and to switch control inputs of the A7-level converter cell 1020. In general, the advanced control circuitry 1000 is configured to monitor the output (e.g., voltage and / or current) of the A7-level converter cell 1020 and dynamically generate a set of switch control inputs to the A7-level converter cell 1020 that attempt to stabilize the output voltage and / or current at specified values, taking into account variations of VIN and output load. In alternative embodiments, the advanced control circuitry 1000 may be configured to monitor the input of the A7-level converter cell 1020 (e.g., voltage and / or current) and / or an internal node of the A7-level converter cell 1020 (e.g., the voltage across one or more fly capacitors or the current through one or more power switches). Accordingly, most generally, the advanced control circuitry 1000 may be configured to monitor the voltage and / or current of a node (e.g., input terminal, internal node, or output terminal) of the A7-level converter cell 1020. The advanced control circuitry 1000 may be incorporated into, or separate from, the overall controller for a power converter 100 embodying the AT-level converter cell 1020.

[0103] A first block comprises a feedback controller 1002, which may be a traditional controller such as a fixed frequency voltage mode or current mode controller, a constant-ON-time controller, a hysteretic controller, or any other variant. The feedback controller 1002 is shown as being coupled to VOUT from the A7-level converter cell 1020. In alternative embodiments, the feedback controller 1002 may be configured to monitor the input of the M-level converter cell 1020 and / or an internal node of the A7-level converter cell 1020. The feedback controller 1002 produces a signal directly or indirectly indicative of the voltage at VOUT that determines in general terms what needs to be done in the multi-level converter cellDocket No. 61658.146WO01 Client Ref. No. PER-560-PCT1020 to maintain desired values for VOUT: charge, discharge, or tri-state (z.e., open, with no current flow).

[0104] In the illustrated example, the feedback controller 1002 includes a feedback circuit 1004, a compensation circuit 1006, and aPWM generator 1008. The feedback circuit 1004 may include, for example, a feedback-loop voltage detector which compares VOUT (or an attenuated version of VOUT) to a reference voltage which represents a desired VOUT target voltage (which may be dynamic) and outputs a control signal to indicate whether VOUT is above or below the target voltage. The feedback-loop voltage detector may be implemented with a comparison device, such as an operational amplifier (op-amp) or transconductance amplifier (gm amplifier).

[0105] The compensation circuit 1006 is configured to stabilize the closed-loop response of the feedback controller 1002 by avoiding the unintentional creation of positive feedback, which may cause oscillation, and by controlling overshoot and ringing in the step response of the feedback controller 1002. The compensation circuit 1006 may be implemented in known manner, and may include LC and / or RC circuits.

[0106] The PWM generator 1008 generates the actual PWM control signal which ultimately sets the duty cycle of the switches of the multi-level converter cell 1020. In addition, in some embodiments, the PWM generator 1008 may pass on additional optional control signals CTRL indicating, for example, the magnitude of the difference between VOUT and the reference voltage (thus indicating that some levels of the AT-level converter cell 1020 should be bypassed to get to higher or lower levels), and the direction of that difference (e.g., whether VOUT is greater than or less than the reference voltage). In other embodiments, the optional control signals CTRL can be derived from the output of the compensation circuit 1006, or from the output of the feedback circuit 1004, or from a separate comparator (not shown) coupled to, for example, VOUT. One purpose of the optional control signals CTRL is for advanced control algorithms, when it may be beneficial to know how far away VOUT is from a target output voltage, thus allowing faster charging of the inductor L if the VOUT is severely under regulated.

[0107] A second block comprises a multi-level controller 1010, the primary function of which is to select the switch states that generate a desired VOUT while maintaining a chargebalance state on the fly capacitors within the -level converter cell 1020 every time an output voltage level is selected, regardless of what switch state or states were used in the past.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0108] The multi-level controller 1010 includes a Voltage Level Selector 1012 which receives the PWM control signal and the additional control signals CTRL if available. In addition, the Voltage Level Selector 1012 may be coupled to VOUT and / or VIN, and, in some embodiments, to the HIGH / LOW status signals, CFX_H / L, from the voltage detectors coupled to corresponding fly capacitors Cx within the AT-level converter cell 1020. A function of the Voltage Level Selector 1012 is to translate the received signals to an output voltage Target Level (e.g., on a cycle-by-cycle basis). The Voltage Level Selector 1012 typically will consider at least VOUT and VIN to determine which Target Level should charge or discharge the output of the AT-level converter cell 1020 with a desired rate. For example, in a 6-level converter circuit, the available Target Levels are Level-1 (GND), Level-2 (1 / 5VIN), Level-3 (2 / 5VIN), Level-4 (3 / 5VIN), Level-5 (4 / 5VIN), and Level-6 (VIN), which may be represented as a count value from 1-6 (or 0-5).

[0109] As an example, in a 4-Level converter circuit, if VIN = 12V and VOUT nominally should be 3 V, then the Voltage Level Selector 1012 may indicate that a Target Level of “2” can be selected, which results in a 1 / 3 VIN voltage level at Lx (z.e. , 4V). The PWM control signal sets a duty cycle between that Target Level and another Target Level e.g., GND) so that the average voltage level at Lx will be about 3 V.

[0110] In general, for steady-state operations, the Target Level voltage closest to VOUT that either charges or discharges the inductor L may be selected for simplicity of the selection algorithm. In general, for transient response, a Target Level that is higher (for charging) or lower (for discharging) than the closest Target Level may be selected to quickly charge or discharge the inductor L. The Voltage Level Selector 1012 may be implemented, for example, as a look-up table (LUT) or as comparison circuitry and combinatorial logic or more generalized processor circuitry. In some embodiments, the Voltage Level Selector 1012 can implement advanced methods (described below) that try to speed up charging or discharging based on additional factors, such as inductor voltage drop, load transients, the magnitude of output deviations, and / or external input signals from external sources. The output of the Voltage Level Selector 1012 may include duty cycle information (e.g., derived from the input PWM control signal) as well as switch state.[oni] The output of the Voltage Level Selector 1012 is coupled to a Multi-Level Switch State Selector 1014, which generally would be coupled to the status signals, CFX_H / L, from the voltage detectors for the fly capacitors Cx. Taking into account the Target Level generated byDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTthe Voltage Level Selector 1012, the Multi-Level Switch State Selector 1014 determines a pattern of switch states for the desired output level that generally achieves charge-balancing the fly capacitors Cx. The Multi-Level Switch State Selector 1014 may be implemented, for example, as comparison circuitry and combinatorial logic, as a look-up table (LUT), or as more generalized processor circuitry. The output of the Multi-Level Switch State Selector 1014 is coupled to the switches of the multi-level converter cell 1020 (through appropriate level-shifter circuits and drivers circuits, as may be needed for a particular converter cell) and includes a pattern of switch state settings determined by the Multi-Level Switch State Selector 1014. The pattern of switch state settings selects the configuration of the switches within the multi-level converter cell 1020.

[0112] In general (but not always), for PWM-based control systems, the Voltage Level Selector 1012 and the AT-level Switch State Selector 1014 only change their states when the PWM signal changes. For example, when the PWM signal goes high, the Voltage Level Selector 1012 selects which level results in charging of the inductor L and the AT-level Switch State Selector 1014 sets which version to use of that level. Then when the PWM signal goes low, the Voltage Level Selector 1012 selects which level can discharge the inductor L and the AT-level Switch State Selector 1014 sets which version of that level to use. Thus, the Voltage Level Selector 1012 and the AT-level Switch State Selector 1014 generally only change states when the PWM signal changes (the PWM signal is in effect their clock signal). However, there may be situations or events where it is desirable for the CTRL signal to change the state of the Voltage Level Selector 1012. Further, there may be situations or events where it is desirable for the CFX H / L status signal(s) to cause the AT-level Switch State Selector 1014 to select a particular configuration of power switch settings, such as when a severe mid-cycle imbalance occurs. In some embodiments, it may be useful to include a timing function that forces the Al-level Switch State Selector 1014 to re-evaluate the optimal version of the state periodically, for example, in order to avoid being “stuck” at one level for a very long time, potentially causing charge imbalances.

[0113] One notable benefit of the control circuitry shown in FIG. 10 is that it enables generation of voltages in boundary zones between voltage levels, which represent unattainable output voltages for conventional multi-level DC-to-DC converter circuits.

[0114] In alternative unregulated charge-pumps embodiments, the feedback controller 1002 and the Voltage Level Selector 1012 may be omitted, and instead a clock signal CLKDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTmay be applied to the -level Switch State Selector 1014. The A^-level Switch State Selector 1014 would generate a pattern of switch state settings that periodically charge balances the fly capacitors Cx regardless of what switch state or states were used in the past (as opposed to cycling through a pre-defined sequency of states). This ensures that if VIN changes or anomalous evens occur, the system generally always seeks charge balance for the fly capacitors Cx.

[0115] In some embodiments, the AT-level Switch State Selector 1014 may take into account the current II flowing through the inductor L by way of an optional currentmeasurement input 1016, which may be implemented in conventional fashion.

[0116] In an AT-level multi-level converter circuit, the configuration of switches that achieves Level- 1 (e.g., GND) or Level -M (e.g., VIN) effectively bypasses the fly capacitors Cx. Conversely, for all intermediate voltage levels, at least one fly capacitor Cx is coupled to VOUT and there are always at least two configurations of switches that can achieve any intermediate voltage level. For any particular intermediate voltage level, at least one configuration of switches results in charging the associated fly capacitor and at least one other configuration of switches results in discharging the associated fly capacitor. One aspect of the present disclosure is the realization that any achievable output voltage VOUT requiring intermediate voltage levels can be attained by dynamically selecting patterns of switch configurations - that is, by selecting switch configurations without regard to or memory of the switch configurations of any previous switching cycle - to select appropriate Levels, and doing so in a way that purposefully selects either charging or discharging switch configurations that also balance charge across the fly capacitors Cx.

[0117] Embodiments of the disclosure use the following approach for positive inductor L current (charging VOUT):(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer high-side switch in outer-switch control methods, or the inner low-side switch for inner-switch control methods); and(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer low-side switch for outer-switch control methods, or the inner high-side switch for inner-switch control methods).Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0118] For negative inductor L current (discharging VOUT), the selection of switches inverts. Accordingly:(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer low-side switch in outer-switch control methods, or the inner high-side switch for inner-switch control methods); and(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer high-side switch for outer-switch control methods, or the inner low-side switch for inner-switch control methods).

[0119] Note again that whether or not charging actually occurs for a particular fly capacitor Cx generally depends on the switch states for all other fly capacitors. For a fly capacitor C(x) to actually charge or discharge, the next inward (if one exists) fly capacitor C(x 7) (for outerswitch control methods) or the previous outward (if one exists) fly capacitor C(x+7) (for inner-switch control methods) must be set to the opposite state (z.e., discharge or charge) so that a bypass situation does not occur.

[0120] For any multi-level converter circuit of order M that can create M voltage levels -z.e., Level-1 (e.g., GND) through Level -M (e.g., VIN) - then the following switch count rules apply for any Level -m:(1) - zzz low-side switches must be set to be closed (ON);(2) m - 1 high-side switches must be set to be closed (ON); and(3) switches that are not required to be ON must be set to be OFF (open).

[0121] With these switch count rules in mind, the following generalized capacitor control method applies for each state change of the Multi-Level Switch State Selector 1014:Step 1) Select a fly capacitor that has not previously been selected;Step 2) If the voltage of the selected fly capacitor is above its Vtarget and there are remaining (z.e., not been set by this method in this cycle) low-side or high-side switches that can be set to be closed to enable a discharge path for the selected fly capacitor, then set those switches that enable a discharge path for the selected fly capacitor to be closed, decrement one or more appropriate counters (e.g., for the number of low-side switches set to be closed and the number of high-side switches set to be closed), and flag the current fly capacitor as “done” (z.e., as having been selected); otherwise (since the voltage of the selected fly capacitor is below its Vtarget) set the switches that enable a charging path for the selected fly capacitor to be closed and flag the current fly capacitor as “done”;Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTStep 3) Loop to Step 1 until all fly capacitors have been selected;Step 4) For the remaining pair of left-over switches, set the high-side switch or the low-side switch to be closed based on the switch count rules and the counter values.

[0122] With the above generalized capacitor control method, more specific multi-level charge-balancing control methods can be created. Examples can be found, for example, in U.S. Patent Publication No. 20230148059, which is incorporated by reference herein in its entirety.Dead Zone Valley and Peak Switching Control Systems and Methods

[0123] As previously discussed, power converter control circuitry (e.g., advanced control circuitry 1000 for an -level converter cell as described with respect to FIG. 10) uses feedback to maintain a target voltage or current output. In some implementations, if the output voltage or inductor current is greater than a target voltage or current, the feedback may cause the converter to lower the output voltage or inductor current. In addition, if the output voltage or inductor current is less than the target voltage or current, the feedback may cause the converter to increase the output voltage or inductor current.

[0124] In some implementations, dead zone windows are defined around the boundary output values. For example, a 3 -level converter cell enables generation of three instantaneous voltage levels at node Lx during normal operation, depending on the ON-OFF state of power FETs: VIN, VIN / 2, or OV For example, if VIN = 5 V, then during normal operation Lx can have the values 5V, 2.5V, or 0V. Using these values as one example, the average voltage values at VOUT can be in one of two zones: in Zone 1, VOUT can theoretically range from 0V to 2.5V ( / .< ., VIN / 2) by alternating between 0V and 2.5V at node Lx, and in Zone 2, VOUT can theoretically range from 2.5V to 5.V ( / .< ., VIN) by alternating between 2.5V and 5V at node Lx. However, the inductor L needs a minimum voltage drop to quickly charge / discharge the inductor L in order not to impact loop response. If VOUT approaches a voltage close to or at the boundary between adjacent voltage levels (e.g., the boundary at VIN / 2) of the converter circuit, the converter cell 200 reaches a “dead zone” where there is not enough voltage drop across the inductor L to meet transient responses. Stated another way, the duty cycle of the power FETs cannot be at or close to 100% (when approaching an upper zone from a lower zone, such as transitioning from Zone 1 to Zone 2) or at or close to 0% (when approaching a lower zone from an upper zone, such as transitioning from Zone 2 to Zone 1).Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0125] Referring to FIGs. 11-15, dead zone control systems and methods will now be described, according to some embodiments. FIG. 11 is an example chart 1100 illustrating output voltage levels of a four-level converter, such as the four-level converter illustrated in FIG. 8B. It will be appreciated that while a four-level converter is use for discussion purposes, the dead zone control systems and methods described herein may be implemented in other converter circuit configurations, including M-level converters circuits as described herein with respect to FIGs. 1-10.

[0126] As illustrated in the chart 1100, a four-level converter may be configured to provide a voltage to the inductor at 0 volts, 4 volts, 8 volts, and 12 volts, though it will be appreciated that other voltage output levels may be used in other implementations. During operation, if the four-level converter is configured to provide 4 volts, for example, then the output voltage Vout will be charged up from 0 to 4 volts as illustrated by the voltage curve 1110. In practice, the voltage is unlikely to settle at exactly 4 volts due to capacitor ripple, inductor ripple, hysteresis loss, and / or other factors, and may be difficult to control within a dead zone 1120 around the target voltage. A dead zone may be defined and controlled around any target voltage level of an -level converter.

[0127] Referring to FIG. 12A, a chart 1200 illustrating a dead zone control system will now be described, according to some embodiments. In the dead zone region, the power converter circuitry may not charge the inductor sufficiently fast or discharge the inductor sufficiently fast to meet power converter operational requirements. In some embodiments, the power converter circuitry may be configured to ramp up the output voltage by increasing a duty cycle between the target voltage (e.g., 4V) and 0. However, in operation there may not be a guarantee that the output will ever reach the target voltage. As illustrated, a dead zone control approach may be configured to increase the voltage to a higher target voltage level, such as to 8 volts at 1210 to provide charging over 4V and then discharge to 0 to provide discharging at 1212, and then settle the voltage at the 4V target voltage level as shown at 1214.

[0128] Referring to FIG. 12B, a chart 1250 illustrates the inductor current in the dead zone control approach of FIG. 12A, according to some embodiments. As illustrated, the inductor current increases at 1252 higher than a target current, then decreases at 1254 toward the target current, and then drifts at 1256 near the target current (also referred to herein as a parking, when the system is no longer actively charging and / or discharging), where the current may drift higher or lower as illustrated by 1256. In some embodiments, the ripple during the chargingDocket No. 61658.146WO01 Client Ref. No. PER-560-PCT1252 and discharging 1254 is configured to be larger than the range of potential drift 1256, which provides sufficient control over the ripple. Although this approach provides many advantages for dead zone control, this approach switches three times during a cycle to charge up two levels, discharge down two levels, and then settle at the target voltage. This dead zone control mode, which uses a large ripple to overcome the drift while parking at the target voltage, may be less efficient than the approaches described below in FIGs. 13A-15, and if not tuned correctly (e.g., not enough ripple) can lose control of the inductor.

[0129] Referring to FIG. 13 A, an improved dead zone control approach will now be described, according to some embodiments. In the illustrated embodiment, the target current for the peak current and the valley current is the same. It will be understood that the illustrated features also pertain to embodiments in which the target for the peak current is different from the target for the valley current (e.g., where target offsets are implemented as described herein). Referring to the chart 1300, the power converter circuitry is configured for a desired output voltage level having a target inductor current (e.g., 4A). At the start of a switching cycle, the inductor current is sensed and the dead zone control circuitry is configured to determine whether the sensed current is above or below the target current. For example, if the sensed current 1310 is above the target current, the dead zone control circuitry is configured to switch to a valley current mode 1312, in which the inductor is discharged until the target current is reached 1314. The current is parked at the target current (e.g., not driven higher or lower), where it may drift higher or lower. If the current drifts higher 1316, then at the next cycle the sensed current 1318 will be higher than the target current and dead zone control circuitry is configured to switch to the valley current mode 1320 to lower the current to the target current 1322. If the current drifts lower 1324, then the sensed current 1326 at the next cycle will be below the target current, and the dead zone control circuitry is configured to switch to a peak current mode 1328, in which the inductor is charged until the target current is reached 1330. The dead zone control circuitry is configured to continue this approach through subsequent cycles to maintain the output at the target current level.

[0130] Referring to FIG. 13B, a corresponding waveform for a target voltage of 4V is illustrated, according to some embodiments. As illustrated, when the dead zone control approach enters the valley current mode (e.g., valley current mode 1312 of FIG. 13 A) the voltage drops at 1352, and then settles at the target voltage 1354 when the target current is reached. In the next cycle, if the dead zone control approach enters the valley current modeDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTagain (e.g., valley current mode 1320), then the voltage drops again at 1356 and then settles at the target voltage 1358 when the target current is reached. In the next cycle, if the dead zone control approach enters the peak current mode (e.g., peak current mode 1328), then the voltage goes up a level 1360 and then settles at the target voltage 1362 when the target current is reached.

[0131] In various implementations, the dead zone control approach of FIGs. 13A-B may be more efficient than the implementations of FIGs. 12A-B, for example, because it uses two states after settling instead of always using three states. For example, the dead zone control approach of FIGs. 12A-B may be implemented by providing an average inductor current that closely approximates the target current every cycle. In the dead zone approach of FIGs. 13A-B, however, the average current may be higher or lower than the target current as the average current rises and / or falls with the valley current mode and the peak current mode. Another advantage of the dead zone approach of FIGs. 13A-B is that the dead zone may be entered earlier than in the approach of FIGs. 12A-B without hurting efficiency, for example, because the wave forms are the same or substantially the same regardless of whether the output is in the dead zone, and, once settled, only two states are used - dead zone and peak current mode, or dead zone and valley current mode.

[0132] FIG. 14 illustrates example control circuitry 1400 that may be used to implement the dead zone control of FIGs. 13A-B, according to some embodiments. In various embodiments, the control circuitry 1400 may be implemented within the controller 1002 of FIG. 10, within other control circuitry described herein in FIGs. 1-10, or in other implementations consistent with the teachings of the present disclosure. Control circuitry 1400 may regulate and control different system variables, including output voltage (Vour), average current (IAVE), and peak current (IPEAK). An output voltage (VOUT) may be an output voltage of the multi-level converter. An average current (IAVE) may be a current measured or sensed across one or more switches of the multi-level converter over a predetermined amount of time. An instantaneous current (ISENSE INSTANTANEOUS) may be a current measured across one or more switches of the multi-level converter at a certain time. Multiple peak current measurements may be used to determine the average current over a predetermined amount of time. In particular, control circuitry 1400 may regulate and control different system variables of the multi-level power converter.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0133] The control circuitry 1400 may include multiple amplifiers, such as a first amplifier and a second amplifier. The first amplifier may be a voltage error amplifier 1402 and a second amplifier may be an average current error amplifier 1404. Voltage error amplifier 1402 and average current error amplifier 1404 may be operational transconductance amplifiers in some embodiments. Voltage error amplifier 1402 may determine an error between voltage inputs, such as output voltage 1408 (VOUT) that may be an output voltage of the multi-level converter and a reference voltage 1410 (VREF) that may be sensed using a sensor or a load. The average current error amplifier 1404 may be a type of current error amplifier that determines an error between two inputs representing currents. In case of average current error amplifier 1404, the inputs may represent an average current (VAMPJAVE signal 1412) that passes through the multilevel converter and may be regulated and an average sensed current 1414 (ISENSE AVG) that may be sensed using one of the sensors.

[0134] The control circuitry 1400 may further include a comparator, such as pulse width modulated (PWM) comparator 1406. The PWM comparator 1406 may be configured to compare two inputs and generate a PWM signal 1422 that may be used to set a duty cycle. In case of PWM comparator 1406 the inputs may represent a target current signal 1416 that may be regulated and a sensed instantaneous current 1420 (ISENSE INSTANTANEOUS) that may be sensed using one or more sensors and representing a present current value. The voltage error amplifier 1402, the average current error amplifier 1404, and the PWM comparator 1406 may be arranged in sequence, such that an output signal of the voltage error amplifier 1402 may be an input signal into the average current error amplifier 1404, and an output signal of the average current error amplifier 1404 may be an input signal into PWM comparator 1406.

[0135] In some embodiments, voltage error amplifier 1402, average current error amplifier 1404, and PWM comparator 1406 may receive a signal representing a system variable to be regulated and a signal representing a reference value for the system variable that may be sensed using one or more sensors. For example, voltage error amplifier 1402 may receive a system variable that may be an output voltage 1408 (VOUT) and a reference voltage 1410 (VREF) and determine an error between output voltage 1408 (VOUT) and a reference voltage 1410 (VREF). Output voltage (VOUT) may be an output voltage to be regulated by the multi-level converter. The reference voltage 1410 (VREF) may be a reference voltage that is a voltage across a load, e.g., a battery. The voltage error amplifier 1402 may use output voltage 1408 (VOUT) and reference voltage 1410 (VREF) to generate an output signal. The output signal may correspondDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTto an error between output voltage 1408 (VOUT) and reference voltage 1410 (VREF) and represent an average current (IAVG) and may be referred to as a VAMP IAVG signal 1412. The VAMP i A VG signal 1412 may represent an error between the output voltage 1408 (VOUT) and reference voltage 1410 (VREF), and may correspond to an average current (IAVG) to be regulated by the multi-level converter. The value corresponding to the VAMP IAVG signal 1412 may be measured at the comparison node or comp node 1415. When comp node 1415 represents an average current, the error between output voltage 1408 (VOUT) and reference voltage 1410 (VREF) may be an indication to controller 1002 to increase the average current (IAVG).

[0136] In some embodiments, voltage error amplifier 1402 may be included in a circuit referred to as a voltage control loop 1424. Voltage control loop 1424 may control the output voltage (VOUT) generated by the multi-level converter. Typically, voltage control loop 1424 may be a more precise but a slow loop when compared to other loops in control circuitry 1400.

[0137] As discussed above, VAMP IAVG signal 1412 that is an output of voltage error amplifier 1402 may be an input to average current error amplifier 1404. For example, average current error amplifier 1404 may receive the VAMP IAVG signal 1412 that may correspond to an average current (IAVG) to be regulated and an average sensed current signal 1414 (ISENSE AVG) and determine an error between average current (IAVG) and average sensed current (ISENSE AVG). The average sensed current (ISENSE AVG) may be sensed using a sensor that senses an average current across one or more switches of the multi-level converter. For example, switches S3 and S4 of the 3-level converter discussed in FIG. 8A and switches S5 and S6 of the 4-level converter discussed in FIG. 8B may be sensed to determine the average sensed current (ISENSE AVG).

[0138] The average current error amplifier 1404 may use VAMP IAVG signal 1412 and average sensed current signal 1414 (ISENSE AVG) to generate an output signal that corresponds to an error between average current (IAVG) and average sensed current (ISENSE AVG). The output signal may represent target current signal 1416 that is used for dead zone control. The target current signal 1416 may be a peak current to be regulated by the multi-level converter. The target current signal 1416 may be a minimum of or an error between the average current (IAVG) corresponding to the VAMP IAVG signal 1412 and an average sensed current (ISENSE AVG) corresponding to average sensed current signal 1414 (ISENSE AVG). The value corresponding to the target current signal 1416 may be measured at the comparison node or comp node 1418. The error between the average current (IAVG) and the sensed average current (ISENSE AVG) mayDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTbe an indication to controller to increase or decrease the current using a valley current mode or peak current mode, respectively.

[0139] In some embodiments, average current error amplifier 1404 may be included in a circuit referred to as a current control loop 1426. The current control loop 1426 may regulate the average current (IAVG) used by a system, such as the multi-level converter. Typically, current control loop 1426 may be a less precise but a faster loop when compared to other loops in control circuitry 1400, such as voltage control loop 1424.

[0140] As discussed above, target current signal 1416 that is an output of average current error amplifier 1404 may be an input to PWM comparator 1406. For example, PWM comparator 1406 may receive target current signal 1416 that may correspond to the current to be regulated and a sensed instantaneous current 1420 (ISENSE INSTANTANEOUS). PWM comparator 1406 may compare the target current signal 1416 to the sensed instantaneous current (ISENSE INSTANTANEOUS) and generate a PWM signal based on the comparison. The sensed instantaneous current may be sensed using sensors that sense current across switches of multilevel converters discussed in FIGs. 8A and 8B. In some instances, the sensed current may also be mixed with a slope compensation waveform. In various embodiments described herein, slope compensation may be turned off when the control system is operating in a dead zone control mode (e.g., to provide enhanced ripple control) and switching between peak current mode and valley current mode.

[0141] The PWM comparator 1406 may use the target current signal 1416 and sensed instantaneous current 1420 to generate a PWM signal 1422. The PWM signal 1422 may be a pulse width modulation signal that indicates whether the target current signal 1416 or sensed instantaneous current 1420 is greater. For example, PWM signal 1422 may set a duty cycle when the multi-level converter circuit changes zones, such as from a first zone to a second zone, from the second zone to a third zone, from the third zone to a fourth zone, or vice versa. In some embodiments, PWM comparator 1406 may be included in a circuit referred to as a current control loop 1428. The current control loop 1428 may regulate the current used by a system, such as the multi-level converter.

[0142] In operation, the PWM comparator 1406 is configured to receive the target current signal 1416 and the sensed instantaneous current 1420. In a peak current mode, the PWM signal 1422 starts high and goes low when the sensed instantaneous current 1420 reaches the targetDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTcurrent 1416 (representing a peak target current). In valley current mode, the PWM signal 1422 starts low and goes high when the sensed instantaneous current 1420 reaches the target current 1416 (representing a valley target current). In some embodiments, an inverter 1430 is provided and controlled to switch the PWM signal 1422 between valley current mode and peak current mode. In some embodiments, the controller makes a determination at the end of a previous cycle whether the sensed current is above the target current, in which case the dead zone control enters valley current mode in the next cycle, or below the target current, in which case the dead zone control enters the peak current mode in the next cycle.

[0143] As discussed above, average sensed current 1414 (ISENSE AVG) and sensed instantaneous current 1420 (ISENSE INSTANTANEOUS) may be measured at switches of the multilevel converter. For simplicity, the embodiments disclosed herein discuss measuring average sensed current and sensed instantaneous current using a four-level converter illustrated in FIG.8B, though the embodiments are applicable to other M-Level converters. As illustrated in FIG.8B, the four-level converter includes six switches, S1-S6. The average sensed current 1414 (ISENSE AVG) and sensed instantaneous current 1420 (ISENSE INSTANTANEOUS) may be measured using the first and last outer switches S5 and S6 that may operate as a pair. In some embodiments, the average sensed current (ISENSE AVG) and sensed instantaneous current (ISENSE INSTANTANEOUS) correspond to the current across the inductor of the multi-level converter. In the multi-level converter switches S5 and S5 operate as a pair, such that when S5 switch is on, S6 switch is off, and vice versa. Accordingly, either switch S5 or switch S6 is alternatively conducting current that passes through the inductor. Further, the current that passes through switch S5 and S6 also passes through the inductor. Thus, it is possible to continuously measure the average current and instantaneous current at switches S5 and S6 instead of the inductor.

[0144] It will be appreciated that the circuitry of FIG. 14 is one example of control circuitry that can be used to implement the dead zone control as described herein, and that other circuitry and logic may be used in other embodiments consistent with the teachings herein. For example, some embodiments may include separate valley current mode and peak current mode control circuitry and / or logic components.

[0145] FIG. 15 illustrates an example dead zone control process 1500, according to some embodiments. The dead zone control process 1500 may be implemented using AT-level power converter circuitry and a controller as described herein with reference to FIGs. 1-10, using theDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTcircuitry 1400 as described with reference to FIG. 14, and / or other combinations of circuitry and logic as appropriate.

[0146] The process 1500 begins at operation 1502, which includes operating the power converter circuitry in a multi-level mode. On startup, the output voltage of the power converter circuitry may be driven to a desired target voltage level. In operation 1504, the controller monitors whether the voltage has entered a dead zone region associated with the desired target voltage level. The dead zone region is defined as a range of voltages (also referred to herein as a dead zone window) above and / or below each target voltage level. In some embodiments, the dead zone region may be symmetrical, having the same voltage range above and below the target voltage level. In some embodiments, the dead zone region may be shifted down (resulting in an asymmetrical region around the target voltage level) to accommodate for voltage droop. In some embodiments, the dead zone region is selected to encompass voltage ranges to account for ripple and / or other variations that affect control of the voltage at the target voltage level.

[0147] If the voltage is in a dead zone region, then control passes to operation 1506. Otherwise, operation 1504 continues to monitor the voltage level until the dead zone region is reached. In some embodiments, the power converter circuitry may be operated without operation 1504, using the dead zone control process described herein even when the voltage is not in a defined dead zone region.

[0148] In operation 1506, the sensed current is compared against a target current. In some embodiments, this is an instantaneous current value that is compared against an output of an average current error amplifier (e.g., as illustrated in FIG. 14). If the sensed current is greater than the target current, then control passes to operation 1508, where the controller enters into a valley current mode to drop the output current level. In various embodiments, the current may be sensed from both a high side switch and a low side switch of the M-level converter to provide continuous current sensing in both peak current mode and valley current mode.

[0149] In optional operation 1510, a valley mode target offset may be applied to adjust the target current value. For example, it is recognized that a delay between sensing the current, comparing the current to the target current, and entering either the peak current mode or valley current mode may cause the sensed current to overshoot the target current. An offset may be added to the valley current mode setting the target current a little higher such that the targetDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTcurrent equals the target current plus an offset to compensate for the delay. In some embodiments, the offset may be applied to offset for other errors in a particular implementation. For example, in some implementations, there may be a difference between an output voltage and a target output voltage (e.g., a target voltage of 4 volts may generate an output of 3.8 volts) that may be compensated for using an offset to park closer to the output voltage. In some embodiments, the offset may be adjusted during operation to minimize error by monitoring, for example, capacitor ripple or other errors to provide feedback to adjust the offset to minimize the detected error.

[0150] In operation 1512, the output current is decreased until the sensed current is approximately equal to the target current or adjusted target current. In some embodiments, the current may be decreased until the sensed current falls below the target current, is within a range of the target current, or via other comparison indicative of the sensed current achieving a desired target current value. In some embodiments, the target current value is reached during a single switching cycle of the power converter circuitry, and the process repeats at operation 1506 during the next cycle 1520.

[0151] Referring back to operation 1506, if the sensed current is less than the target current, then control passes to operation 1514, where the controller enters into a peak current mode to raise the output current level. In optional operation 1516, a peak current mode target offset may be applied to adjust the target current value. An offset may be applied to the peak current mode setting the target current a little lower such that the target current equals the target current minus an offset to compensate for the delay. In some embodiments, the offset may be applied to offset for other errors in a particular implementation. For example, in some implementations, there may be a difference between an output voltage and a target output voltage (e.g., a target voltage of 4 volts may generate an output of 4.2 volts) that may be compensated for using an offset to park closer to the output voltage. In some embodiments, the offset may be adjusted during operation to minimize error by monitoring, for example, capacitor ripple or other errors to provide feedback to adjust the offset to minimize the detected error.

[0152] In operation 1518, the current is increased until the sensed current is approximately equal to the target current value or adjusted target current value. In some embodiments, the output current may be increased until the sensed current rises above the target current value, is within a defined range of the target current value, or via other comparison indicative of the sensed current achieving a desired target current value or range. In some embodiments, theDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTtarget current value is reached during a single switching cycle of the power converter circuitry, and the process repeats at operation 1506 during the next cycle 1520.

[0153] Further aspects of the present disclosure include the following:

[0154] Aspect 1 includes a method comprising controlling switching circuitry of a multilevel power converter circuit to generate an output voltage at a target voltage level; and entering a dead zone control mode when the output voltage is within a dead zone window associated with the target voltage level, the dead zone control mode comprising, during each switching cycle: comparing a sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level; entering a valley current mode during the cycle when sensed current is higher than the target current, the valley current mode configured to control the switching circuitry to decrease the sensed current to the target current and settle at the target current; and entering a peak current mode when sensed current is lower than the target current, the peak current mode configured to control the switching circuitry to increase the sensed current to the target current and settle at the target current.

[0155] Aspect 2 includes the method of aspect 1, wherein entering a valley current mode and / or entering a peak current mode further comprise adjusting the target current based on an offset value.

[0156] Aspect 3 includes the method of any of aspects 1-2, further comprising sensing an instantaneous current of the multi-level power converter circuit, the instantaneous current based at least in part on a sensed current associated with a high-side switch of the multi-level power converter circuit and a low-side switch of the multi-level power converter circuit.

[0157] Aspect 4 includes the method of any of aspects 1-3, wherein each level of the multi-level power converter circuit has a corresponding dead zone window.

[0158] Aspect 5 includes the method of any of aspects 1-4, wherein controlling the switching cycle of a multi-level power converter circuit to generate an output voltage at a target voltage level further comprises operating the multi-level power converter circuit in a buck mode and / or boost mode.

[0159] Aspect 6 includes the method of any of aspects 1-5, wherein comparing the sensed current of the multi-level power converter circuit with a target current corresponding to theDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTtarget voltage level further comprises: receiving the sensed current at a first input of a pulsewidth modulation circuit; receiving a target current as a second input of a pulse-width modulation circuit; and generating a pulse-width modulation signal based on a comparison of the sensed current and the target current.

[0160] Aspect 7 includes a system that may implement any of aspects 1-6, the system comprising: control circuitry configured to control switching circuitry of a multi-level power converter circuit to generate an output voltage at a target voltage level, the control circuitry further configured to enter a dead zone control mode when the output voltage is within a dead zone window associated with the target voltage level, the dead zone control mode configured to, during each switching cycle: compare a sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level; enter a valley current mode during the cycle when sensed current is higher than the target current, the valley current mode configured to control the switching circuitry to decrease the sensed current to the target current and settle at the target current; and enter a peak current mode when sensed current is lower than the target current, the peak current mode configured to control the switching circuitry to increase the sensed current to the target current and settle at the target current.

[0161] Aspect 8 includes the system of aspect 7, wherein the control circuitry is further configured to adjust the target current based on an offset value and wherein the multi-level power converter circuit is driven towards the adjusted target current.

[0162] Aspect 9 includes the system of any of aspects 7-8, wherein the multi-level power converter circuit comprises the switching circuitry; wherein the control circuitry is configured to operate the switching circuitry to charge and / or discharge one or more of a plurality of fly capacitors; and wherein the control circuitry is further configured to sense an instantaneous current of the multi-level power converter circuit, the instantaneous current based at least in part on a sensed current associated with a high-side switch of the switching circuitry and a low-side switch of the switching circuitry.

[0163] Aspect 10 includes the system of any of aspects 7-9, further comprising the plurality of fly capacitors.

[0164] Aspect 11 includes the system of any of aspects 7-10, wherein each level of the multi-level power converter circuit has a corresponding dead zone window.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0165] Aspect 12 includes the system of any of aspects 7-11, wherein the control circuitry is further configured to control the switching cycle of the multi-level power converter circuit by operating the multi-level power converter circuit in a buck mode and / or boost mode.

[0166] Aspect 13 include the system of any of aspects 7-12, wherein the control circuitry further comprises: a pulse-width modulation circuit configured to receive the sensed current at a first input and a target current at a second input, wherein the pulse-width modulation circuit is further configured to generate a pulse-width modulation signal based on a comparison of the sensed current and the target current; and an inverter circuit coupled to receive and invert the pulse-width modulation signal.

[0167] Aspect 14 includes an integrated circuit that may implement the method of any of aspects 1-6 and / or may be implemented in the system of aspects 7-13, comprising: control circuitry couplable to a plurality of switches and a plurality of fly capacitors forming a network of interconnected switches and fly capacitors, wherein the control circuitry is configurable to control the plurality of switches to cycle the network between at least two switching configurations to generate an output voltage; wherein the control circuitry is further configured to enter a dead zone control mode when the output voltage is within a dead zone window associated with a target level, the dead zone control mode configured to, during each switching cycle: compare a sensed current of the network with a target current corresponding to the target level; and drive an output current of the network towards the target current.

[0168] Aspect 15 includes the integrated circuit of aspect 14, wherein the control circuitry is further configured to drive the output current by: entering a valley current mode during the switching cycle when the sensed current is higher than the target current, the valley current mode configured to control the plurality of switches to decrease the sensed current to the target current and settle at the target current; and entering a peak current mode during the switching cycle when the sensed current is lower than the target current, the peak current mode configured to control the network to increase the sensed current to the target current and settle at the target current.

[0169] Aspect 16 includes the integrated circuit of any of aspects 14-15, wherein the control circuitry is further configured to drive the current of the network towards the target current by adjusting the target current based on an offset value and wherein output current is driven towards the adjusted target current.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0170] Aspect 17 includes the integrated circuit of any of aspects 14-16, further comprising the plurality of switches; wherein the control circuitry is configured to operate the network to charge and / or discharge one or more of the plurality of fly capacitors; and wherein the control circuitry is further configured to sense an instantaneous current of the network, the instantaneous current based at least in part on a sensed current associated with a high-side switch of the network and a low-side switch of the network.

[0171] Aspect 18 includes the integrated circuit of any of aspects 14-17, wherein the control circuitry is further configured to control the switching cycle of the network by operating the network in a buck mode and / or boost mode.

[0172] Aspect 19 includes the integrated circuit of any of aspects 14-18, wherein the control circuitry further comprises: a pulse-width modulation circuit configured to receive the sensed current at a first input and a target current at a second input, wherein the pulse-width modulation circuit is further configured to generate a pulse-width modulation signal based on a comparison of the sensed current and the target current.

[0173] Aspect 20 includes the integrated circuit of any of aspects 14-19, further comprising an inverter circuit coupled to receive and invert the pulse-width modulation signal.

[0174] General Benefits and Advantages of Multi-Level Power Converters

[0175] Embodiments of the current invention improve the power density and / or power efficiency of incorporating circuits and circuit modules or blocks. As a person of ordinary skill in the art should understand, a system architecture is beneficially impacted utilizing embodiments of the current invention in critical ways, including lower power and / or longer battery life. The current invention therefore specifically encompasses system-level embodiments that are creatively enabled by inclusion in a large system design and application.

[0176] More particularly, multi-level power converters provide or enable numerous benefits and advantages, including:

[0177] - adaptability to applications in which input and / or output voltages may have a wide dynamic-range (e.g., varying battery input voltage levels, varying output voltages);Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0178] - efficiency improvements on the run-time of devices operating on portable electrical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, efc.);

[0179] - efficiency improvements where efficiency is important for thermal management, particularly to protect other components (e.g., displays, nearby ICs) from excessive heat;

[0180] - enabling design optimizations for power efficiency, power density, and formfactor of the power converter - for example, smaller-size multi-level power converters may allow placing power converters in close proximity to loads, thus increasing efficiency, and / or to lower an overall bill of materials;

[0181] - the ability to take advantage of the performance of smaller, low voltage transistors;

[0182] - adaptability to applications in which power sources can vary widely, such as batteries, other power converters, generators or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g., USB, USB-C, power-over Ethernet, efc.);

[0183] - adaptability to applications in which loads may vary widely, such as ICs in general (including microprocessors and memory ICs), electrical motors and actuators, transducers, sensors, and displays (e.g., LCDs and LEDs of all types);

[0184] - the ability to be implemented in a number of IC technologies (e.g., MOSFETs, GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chips, ball-grid arrays, wafer level scale chip packages, wide-fan out packaging, and embedded packaging).

[0185] The advantages and benefits of multi-level power converters enable usage in a wide array of applications. For example, applications of multi-level power converters include portable and mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, and cell phones), displays (e.g., LCDs, LEDs), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z-Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., for battery -backup systems and / or power conversion for processing systems and / or electronic / optical networking systems), intemet-of-things (IOT) devices (e.g., smart switchesDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTand lights, safety sensors, and security cameras), household appliances and electronics (e.g., set-top boxes, battery-operated vacuum cleaners, appliances with built-in radio transceivers such as washers, dryers, and refrigerators), AC / DC power converters, electric vehicles of all types (e.g., for drive trains, control systems, and / or infotainment systems), and other devices and systems that utilize portable electricity generating sources and / or require power conversion.

[0186] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.1 la, b, g, ac, ax), as well as other radio communication standards and protocols.

[0187] Programmable Embodiments

[0188] Some or all aspects of the invention, particularly the Multi-Level Switch State Selector 1014 of FIG. 10, may be implemented in hardware or software, or a combination of both (e.g., programmable logic arrays). Unless otherwise specified, the algorithms included as part of the invention are not inherently related to any particular computer or other apparatus. In particular, various general purpose computing machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to use a special purpose computer or special-purpose hardware (such as integrated circuits) to perform particular functions. Thus, embodiments of the invention may be implemented in one or more computer programs (i.e., a set of instructions or codes) executing on one or more programmed or programmable computer systems (which may be of various architectures, such as distributed, client / server, or grid) each comprising at least one processor, at least one data storage system (which may include volatile and non-volatile memory and / or storage elements), at least one input device or port, and at least one output device or port. Program instructions or code may be applied to input data to perform the functions described in this disclosure and generate output information. The output information may be applied to one or more output devices in known fashion.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT

[0189] Each such computer program may be implemented in any desired computer language (including machine, assembly, or high-level procedural, logical, or object-oriented programming languages) to communicate with a computer system, and may be implemented in a distributed manner in which different parts of the computation specified by the software are performed by different computers or processors. In any case, the computer language may be a compiled or interpreted language. Computer programs implementing some or all of the invention may form one or more modules of a larger program or system of programs. Some or all of the elements of the computer program can be implemented as data structures stored in a computer readable medium or other organized data conforming to a data model stored in a data repository.

[0190] Each such computer program may be stored on or downloaded to (for example, by being encoded in a propagated signal and delivered over a communication medium such as a network) a tangible, non-transitory storage media or device (e.g., solid state memory media or devices, or magnetic or optical media) for a period of time (e.g., the time between refresh periods of a dynamic memory device, such as a dynamic RAM, or semi-permanently or permanently), the storage media or device being readable by a general or special purpose programmable computer or processor for configuring and operating the computer or processor when the storage media or device is read by the computer or processor to perform the procedures described above. The inventive system may also be considered to be implemented as a non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer or processor to operate in a specific or predefined manner to perform the functions described in this disclosure.

[0191] Fabrication Technologies & Options

[0192] In various embodiments of multi-level power converters, it may be beneficial to use specific types of capacitors, particularly for the fly capacitors. For example, it is generally useful for such capacitors to have low equivalent series resistance (ESR), low DC bias degradation, high capacitance, and small volume. Low ESR is especially important for multilevel power converters that incorporate additional switches and fly capacitors to increase the number of voltage levels. Selection of a particular capacitor should be made after consideration of specifications for power level, efficiency, size, etc. Various types of capacitor technologies may be used, including ceramic (including multi-layer ceramicDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTcapacitors), electrolytic capacitors, film capacitors (including power film capacitors), and IC-based capacitors. Capacitor dielectrics may vary as needed for particular applications, and may include dielectrics that are paraelectric, such as silicon dioxide (SiCh), hafnium dioxide (HFO2), or aluminum oxide AI2O3. In addition, multi-level power converter designs may beneficially utilize intrinsic parasitic capacitances (e.g., intrinsic to the power FETs) in conjunction with or in lieu of designed capacitors to reduce circuit size and / or increase circuit performance. Selection of capacitors for multi-level power converters may also take into account such factors as capacitor component variations, reduced effective capacitance with DC bias, and ceramic capacitor temperature coefficients (minimum and maximum temperature operating limits, and capacitance variation with temperature).

[0193] Similarly, in various embodiments of multi-level power converters, it may be beneficial to use specific types of inductors. For example, it is generally useful for the inductors to have low DC equivalent resistance, high inductance, and small volume.

[0194] The controlled s) used to control startup and operation of a multi-level power converter may be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), register-transfer level (RTL) circuitry, and / or combinatorial logic.

[0195] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0196] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0197] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations andDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTdirections (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0198] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0199] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0200] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTIn particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0201] A number of embodiments of the disclosure have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0202] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the disclosure, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the disclosure includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTCLAIMSWHAT IS CLAIMED IS:

1. A method compri sing :controlling switching circuitry of a multi-level power converter circuit to generate an output voltage at a target voltage level; andentering a dead zone control mode when the output voltage is within a dead zone window associated with the target voltage level, the dead zone control mode comprising, during each switching cycle:comparing a sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level;entering a valley current mode during the cycle when sensed current is higher than the target current, the valley current mode configured to control the switching circuitry to decrease the sensed current to the target current and settle at the target current; and entering a peak current mode when sensed current is lower than the target current, the peak current mode configured to control the switching circuitry to increase the sensed current to the target current and settle at the target current.

2. The method of claim 1, wherein entering a valley current mode and / or entering a peak current mode further comprise adjusting the target current based on an offset value.

3. The method of claim 1, further comprising sensing an instantaneous current of the multi-level power converter circuit, the instantaneous current based at least in part on a sensed current associated with a high-side switch of the multi-level power converter circuit and a low-side switch of the multi-level power converter circuit.

4. The method of claim 1, wherein each level of the multi-level power converter circuit has a corresponding dead zone window.

5. The method of claim 1 , wherein controlling the switching cycle of a multi-level power converter circuit to generate an output voltage at a target voltage level further comprises operating the multi-level power converter circuit in a buck mode and / or boost mode.Docket No. 61658.146WO01 Client Ref. No. PER-560-PCT6. The method of claim 1, wherein comparing the sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level further comprises:receiving the sensed current at a first input of a pulse-width modulation circuit; receiving a target current as a second input of a pulse-width modulation circuit; and generating a pulse-width modulation signal based on a comparison of the sensed current and the target current.

7. A system comprising:control circuitry configured to control switching circuitry of a multi-level power converter circuit to generate an output voltage at a target voltage level, the control circuitry further configured to enter a dead zone control mode when the output voltage is within a dead zone window associated with the target voltage level, the dead zone control mode configured to, during each switching cycle:compare a sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level;enter a valley current mode during the cycle when sensed current is higher than the target current, the valley current mode configured to control the switching circuitry to decrease the sensed current to the target current and settle at the target current; andenter a peak current mode when sensed current is lower than the target current, the peak current mode configured to control the switching circuitry to increase the sensed current to the target current and settle at the target current.

8. The system of claim 7, wherein the control circuitry is further configured to adjust the target current based on an offset value and wherein the multi-level power converter circuit is driven towards the adjusted target current.

9. The system of claim 7, wherein the multi-level power converter circuit comprises the switching circuitry;wherein the control circuitry is configured to operate the switching circuitry to charge and / or discharge one or more of a plurality of fly capacitors; andwherein the control circuitry is further configured to sense an instantaneous current of the multi-level power converter circuit, the instantaneous current based at least inDocket No. 61658.146WO01 Client Ref. No. PER-560-PCTpart on a sensed current associated with a high-side switch of the switching circuitry and a low-side switch of the switching circuitry.

10. The system of claim 9, further comprising the plurality of fly capacitors.

11. The system of claim 7, wherein each level of the multi-level power converter circuit has a corresponding dead zone window.

12. The system of claim 7, wherein the control circuitry is further configured to control the switching cycle of the multi-level power converter circuit by operating the multi-level power converter circuit in a buck mode and / or boost mode.

13. The system of claim 7, wherein the control circuitry further comprises:a pulse-width modulation circuit configured to receive the sensed current at a first input and a target current at a second input, wherein the pulse-width modulation circuit is further configured to generate a pulse-width modulation signal based on a comparison of the sensed current and the target current; andan inverter circuit coupled to receive and invert the pulse-width modulation signal.

14. An integrated circuit comprising:control circuitry couplable to a plurality of switches and a plurality of fly capacitors forming a network of interconnected switches and fly capacitors, wherein the control circuitry is configurable to control the plurality of switches to cycle the network between at least two switching configurations to generate an output voltage;wherein the control circuitry is further configured to enter a dead zone control mode when the output voltage is within a dead zone window associated with a target level, the dead zone control mode configured to, during each switching cycle:compare a sensed current of the network with a target current corresponding to the target level; anddrive an output current of the network towards the target current.

15. The integrated circuit of claim 14, wherein the control circuitry is further configured to drive the output current by:Docket No. 61658.146WO01 Client Ref. No. PER-560-PCTentering a valley current mode during the switching cycle when the sensed current is higher than the target current, the valley current mode configured to control the plurality of switches to decrease the sensed current to the target current and settle at the target current; and entering a peak current mode during the switching cycle when the sensed current is lower than the target current, the peak current mode configured to control the network to increase the sensed current to the target current and settle at the target current.

16. The integrated circuit of claim 14, wherein the control circuitry is further configured to drive the current of the network towards the target current by:adjusting the target current based on an offset value and wherein output current is driven towards the adjusted target current.

17. The integrated circuit of claim 14, further comprising the plurality of switches; wherein the control circuitry is configured to operate the network to charge and / or discharge one or more of the plurality of fly capacitors; andwherein the control circuitry is further configured to sense an instantaneous current of the network, the instantaneous current based at least in part on a sensed current associated with a high-side switch of the network and a low-side switch of the network.

18. The integrated circuit of claim 14, wherein the control circuitry is further configured to control the switching cycle of the network by operating the network in a buck mode and / or boost mode.

19. The integrated circuit of claim 14, wherein the control circuitry further comprises: a pulse-width modulation circuit configured to receive the sensed current at a first input and a target current at a second input, wherein the pulse-width modulation circuit is further configured to generate a pulse-width modulation signal based on a comparison of the sensed current and the target current.

20. The integrated circuit of claim 19, further comprising an inverter circuit coupled to receive and invert the pulse-width modulation signal.

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