Data processing method and apparatus, and chip and system

Abstract

Disclosed in the embodiments of the present application are a data processing method and apparatus, a chip and a system. The data processing method comprises: performing data processing on acquired kin bits, so as to obtain n output bits, wherein the kin bits comprise one first set including a bits, two second sets each including b bits, four third sets each including c bits, eight fourth sets each including d bits, and sixteen fifth sets each including e bits, and 0<kin<n; and dividing the kin input bits into a plurality of sets, performing multi-step processing, and giving the number of bits comprised in each set. Therefore, each step of processing can be implemented in a simple manner, such that the overall complexity is very low, and hardware implementation is facilitated.

Description

A data processing method, apparatus, chip, and system thereof

[0001] This application claims the priority of a Chinese patent application with the application number 202510086910.4 and the application title "A data processing method, apparatus, chip, and system thereof", which was filed with the National Intellectual Property Administration on January 17, 2025. The entire content of this application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technologies, and in particular, to a data processing method, apparatus, chip, and system thereof. Background Art

[0003] Driven by 5G, cloud computing, big data, artificial intelligence, etc., high-speed optical transmission networks are developing towards the direction of large capacity, packetization, and intelligence. Coherent optical communication systems use the amplitude, phase, polarization, or frequency of light waves to carry information. In order to combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and maintain long-distance transmission, coherent optical communication systems usually need to adopt efficient forward error correction (FEC) codes to combat optical impairments during optical transmission, so as to keep the bit error rate low enough during long-distance transmission. In order to improve spectral efficiency, multi-level quadrature amplitude modulation (QAM), such as 16QAM, 32QAM, 64QAM, or even higher-order QAM, is usually adopted. Each constellation point on the signal constellation diagram corresponding to traditional QAM modulation appears with the same probability. Probabilistic constellation shaping (PCS) technology changes the probability of constellation points appearing while keeping the positions of the constellation points unchanged, making them non-uniformly distributed, thereby improving the system transmission performance. As a modulation format optimization technology, PCS technology has the advantages of approaching the Shannon limit and being flexible and variable, and has been widely studied and applied. A core operation in PCS technology is to perform sequence processing on k0 input sequences with the same probability of 0 and 1 to obtain n0 output sequences with different probabilities of 0 and 1, where k0 and n0 are integers and k0 < n0. As n0 increases, the complexity of the above sequence processing grows.

[0004] The sequence processing complexity in the existing related technologies is very high or the performance is poor, and it cannot be applied to high-speed metropolitan area telecom transmission systems and metropolitan area data center interconnection (DCI) scenarios that require low complexity and low power consumption. Summary of the Invention

[0005] The embodiments of this application provide a data processing method, apparatus, chip, and system, which can process input bits with equal 0 and 1 bit probabilities to obtain output bits with unequal 0 and 1 bit probabilities, and are used to implement PCS technology to improve the system transmission performance.

[0006] In the first aspect, a data processing method is provided, including: performing data processing on k in bits obtained to obtain n output bits, where the k in bits include 1 first set containing a bits, 2 second sets each containing b bits, 4 third sets each containing c bits, 8 fourth sets each containing d bits, and 16 fifth sets each containing e bits, 0 < k in [ < n; the first set is subjected to first processing to obtain a sixth set; 2 of the second sets are respectively subjected to second processing with half of the bits of the sixth set to obtain 2 seventh sets; 4 of the third sets are respectively subjected to third processing with half of the bits of each of the seventh sets to obtain 4 eighth sets; 8 of the fourth sets are respectively subjected to fourth processing with half of the bits of each of the eighth sets to obtain 8 ninth sets; 16 of the fifth sets are respectively subjected to fifth processing with half of the bits of each of the ninth sets to obtain a total of 16 tenth sets, and the 16 tenth sets constitute the n output bits, where k in The values of a, b, c, d, and e are shown in any of the following rows:

[0007] In the second aspect, a data processing method is provided, including: performing data processing on k in bits obtained to obtain n output bits, where the k in bits include 1 first set containing a bits, 2 second sets each containing b bits, 4 third sets each containing c bits, and 8 fourth sets each containing d bits, 0 < k in < n; the first set is subjected to first processing to obtain a sixth set; 2 of the second sets are respectively subjected to second processing with half of the bits of the sixth set to obtain 2 seventh sets; 4 of the third sets are respectively subjected to third processing with half of the bits of each of the seventh sets to obtain 4 eighth sets; 8 of the fourth sets are respectively subjected to fourth processing with half of the bits of each of the eighth sets to obtain 8 ninth sets; half of the bits of each of the ninth sets are all subjected to fifth processing to obtain a total of 16 tenth sets, and the 16 tenth sets constitute the n output bits, where k in The values of a, b, c, d are shown in any of the following rows:

[0008] In this embodiment, any bit in the 6th set participates in the second processing only once, any bit in each 7th set participates in the third processing only once, any bit in each 8th set participates in the fourth processing only once, and any bit in each 9th set participates in the fifth processing only once. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each processing step can be implemented in a simple way, resulting in low overall complexity and ease of hardware implementation.

[0009] In one possible implementation, combining the first or second aspect, the first, second, third, fourth, and fifth processes are implemented using lookup tables. This simplifies hardware implementation and results in lower overall power consumption.

[0010] In conjunction with the first or second aspect and any possible implementation, in one possible implementation, the sixth set includes 10 bits, the seventh set includes 10 bits, the eighth set includes 10 bits, the ninth set includes 10 bits, and the tenth set includes 8 bits.

[0011] Combining the first or second aspect and any possible implementation, in one possible implementation, n is 128. Further, the method includes: performing FEC encoding on the 16 groups of the n output bits and the acquired 1504 bits to obtain 4096 encoded bits; then, performing symbol mapping on the obtained encoded bits to obtain a symbol sequence. This allows the probability of the symbols corresponding to the constellation points to be changed while keeping the constellation point positions unchanged, making them non-uniformly distributed, thus achieving PCS and improving system transmission performance.

[0012] In combination with the first or second aspect and any possible implementation, in one possible implementation, the data processing is a probabilistic constellation shaping (PCS) process, in which the probability of a bit being 0 among the n output bits is not equal to the probability of a bit being 1.

[0013] It should be understood that in the first or second aspect, k in The values ​​of a, b, c, d, and e can also be other combinations of values ​​in this embodiment. Some combinations with good performance are given below; for more combinations, please refer to the embodiments in the specification. For example, in one possible implementation, k... in =50, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0014] For example, in one possible implementation, k in =51, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0015] For example, in one possible implementation, k in =52, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0016] For example, in one possible implementation, k in =53, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0017] For example, in one possible implementation, k in =54, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0018] For example, in one possible implementation, k in =55, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0019] For example, in one possible implementation, k in =56, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0020] For example, in one possible implementation, k in =57, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0021] For example, in one possible implementation, k in =58, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0022] For example, in one possible implementation, k in =59, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0023] For example, in one possible implementation, k in=60, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0024] For example, in one possible implementation, k in =61, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0025] For example, in one possible implementation, k in =62, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0026] For example, in one possible implementation, k in =63, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0027] For example, in one possible implementation, k in =64, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0028] For example, in one possible implementation, k in =65, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0029] For example, in one possible implementation, k in =66, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0030] For example, in one possible implementation, k in =67, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0031] For example, in one possible implementation, k in =68, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0032] For example, in one possible implementation, k in =69, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0033] For example, in one possible implementation, k in =70, and the values ​​of a, b, c, d, and e are shown in any of the following rows:

[0034] Combining the first aspect and any possible implementation, in one possible implementation, the first process processes the first set containing 'a' bits to obtain the sixth set containing 10 bits. The second process combines a second set containing 'b' bits with 5 bits from the sixth set (a total of b+5 bits) to obtain the seventh set containing 10 bits. The third process combines a third set containing 'c' bits with 5 bits from the seventh set (a total of c+5 bits) to obtain the eighth set containing 10 bits. The fourth process combines a fourth set containing 'd' bits with 5 bits from the eighth set (a total of d+5 bits) to obtain the ninth set containing 10 bits. The fifth process combines a fifth set containing 'e' bits with 5 bits from the ninth set (a total of e+5 bits) to obtain the tenth set containing 8 bits. in = a + 2 × b + 4 × c + 8 × d + 16 × e.

[0035] Combining the second aspect and any possible implementation, in one possible implementation, the first process processes the first set containing 'a' bits to obtain the sixth set containing 10 bits. The second process combines a second set containing 'b' bits with 5 bits from the sixth set (a total of b+5 bits) to obtain the seventh set containing 10 bits. The third process combines a third set containing 'c' bits with 5 bits from the seventh set (a total of c+5 bits) to obtain the eighth set containing 10 bits. The fourth process combines a fourth set containing 'd' bits with 5 bits from the eighth set (a total of d+5 bits) to obtain the ninth set containing 10 bits. The fifth process processes 5 bits from the ninth set to obtain the tenth set containing 8 bits. in = a + 2 × b + 4 × c + 8 × d.

[0036] Thirdly, a data processing method is provided, the method comprising: receiving n output bits, wherein the n output bits are a subset of k. in The k is obtained by processing data from bits. inThe k bits include a first set of a bits, two second sets each of b bits, four third sets each of c bits, eight fourth sets each of d bits, and sixteen fifth sets each of e bits, where 0 < k in <n; the first set is subjected to a first process to obtain a sixth set; two of the second sets are each subjected to a second process with half of the bits of the sixth set to obtain two seventh sets; four of the third sets are each subjected to a third process with half of the bits of each seventh set to obtain four eighth sets; eight of the fourth sets are each subjected to a fourth process with half of the bits of each eighth set to obtain eight ninth sets; sixteen of the fifth sets are each subjected to a fifth process with half of the bits of each ninth set to obtain a total of sixteen tenth sets, and the sixteen tenth sets constitute the n output bits, where k in The values of a, b, c, d, and e are as shown in any one of the following rows:

[0037] In a fourth aspect, a data processing method is provided. The method includes: receiving n output bits, where the n output bits are obtained by performing data processing on k in bits, where the k in bits include a first set of a bits, two second sets each of b bits, four third sets each of c bits, and eight fourth sets each of d bits, where 0 < k in <n; the first set is subjected to a first process to obtain a sixth set; two of the second sets are each subjected to a second process with half of the bits of the sixth set to obtain two seventh sets; four of the third sets are each subjected to a third process with half of the bits of each seventh set to obtain four eighth sets; eight of the fourth sets are each subjected to a fourth process with half of the bits of each eighth set to obtain eight ninth sets; half of the bits of each ninth set are each subjected to a fifth process to obtain a total of sixteen tenth sets, and the sixteen tenth sets constitute the n output bits, where k in The values of a, b, c, and d are as shown in any one of the following rows:

[0038] In combination with the third aspect or the fourth aspect, in a possible implementation, the first process, the second process, the third process, the fourth process, and the fifth process are implemented using a look-up table.

[0039] Combined with the third aspect or the fourth aspect and any possible implementation manner, in a possible implementation manner, the 6th set includes 10 bits, the 7th set includes 10 bits, the 8th set includes 10 bits, the 9th set includes 10 bits, and the 10th set includes 8 bits.

[0040] Combined with the third aspect or the fourth aspect and any possible implementation manner, in a possible implementation manner, n is 128.

[0041] Combined with the third aspect or the fourth aspect and any possible implementation manner, in a possible implementation manner, the data processing is probability constellation shaping (PCS) processing, and among the n output bits, the probability that a bit is 0 is not equal to the probability that a bit is 1.

[0042] In a fifth aspect, a data processing apparatus is provided, including: a processing module configured to perform data processing on the obtained k in bits to obtain n output bits, where the k in bits include 1 first set containing a bits, 2 second sets each containing b bits, 4 third sets each containing c bits, 8 fourth sets each containing d bits, and 16 fifth sets each containing e bits, 0 < k in < n; the first set undergoes first processing to obtain a 6th set; the 2 second sets respectively perform second processing with half of the bits of the 6th set to obtain 2 7th sets; the 4 third sets respectively perform third processing with half of the bits of each 7th set to obtain 4 8th sets; the 8 fourth sets respectively perform fourth processing with half of the bits of each 8th set to obtain 8 9th sets; the 16 fifth sets respectively perform fifth processing with half of the bits of each 9th set to obtain a total of 16 10th sets, and the 16 10th sets constitute the n output bits, where k in , a, b, c, d, and e take values shown in any one of the following rows:

[0043] In a sixth aspect, a data processing apparatus is provided, including: a processing module configured to perform data processing on the obtained k in bits to obtain n output bits, where the k in bits include 1 first set containing a bits, 2 second sets each containing b bits, 4 third sets each containing c bits, and 8 fourth sets each containing d bits, 0 < k in<n; The first set is subjected to a first process to obtain a sixth set; Two of the second sets are respectively subjected to a second process with half of the bits of the sixth set to obtain two seventh sets; Four of the third sets are respectively subjected to a third process with half of the bits of each seventh set to obtain four eighth sets; Eight of the fourth sets are respectively subjected to a fourth process with half of the bits of each eighth set to obtain eight ninth sets; Half of the bits of each ninth set are all subjected to a fifth process to obtain a total of sixteen tenth sets, and the sixteen tenth sets constitute the n output bits, where, k in The values of k, a, b, c, and d are as shown in any one of the following rows:

[0044] Combined with the fifth aspect or the sixth aspect, in a possible implementation manner, the first process, the second process, the third process, the fourth process, and the fifth process are implemented by using a look-up table.

[0045] Combined with the fifth aspect or the sixth aspect and any possible implementation manner, in a possible implementation manner, the sixth set includes 10 bits, the seventh set includes 10 bits, the eighth set includes 10 bits, the ninth set includes 10 bits, and the tenth set includes 8 bits.

[0046] Combined with the fifth aspect or the sixth aspect and any possible implementation manner, in a possible implementation manner, n is 128. Further, the processing module is further configured to: perform FEC encoding on 16 groups of the n output bits and the obtained 1504 bits to obtain 4096 encoded bits. Further, the apparatus further includes a mapping module, and the mapping module is configured to perform symbol mapping on the obtained encoded bits to obtain a symbol sequence.

[0047] Combined with the fifth aspect or the sixth aspect and any possible implementation manner, in a possible implementation manner, the data processing is probability constellation shaping PCS processing, and in the n output bits, the probability that a bit is 0 is not equal to the probability that a bit is 1.

[0048] In a seventh aspect, a data processing apparatus is provided, including: a receiving module, configured to receive n output bits, and the n output bits are obtained by performing data processing on k in bits, and the k in bits include one first set including a bits, two second sets each including b bits, four third sets each including c bits, eight fourth sets each including d bits, and sixteen fifth sets each including e bits, 0 < k in<n; The first set is subjected to a first process to obtain a sixth set; Two of the second sets are respectively subjected to a second process with half of the bits of the sixth set to obtain two seventh sets; Four of the third sets are respectively subjected to a third process with half of the bits of each seventh set to obtain four eighth sets; Eight of the fourth sets are respectively subjected to a fourth process with half of the bits of each eighth set to obtain eight ninth sets; Sixteen of the fifth sets are respectively subjected to a fifth process with half of the bits of each ninth set to obtain a total of sixteen tenth sets, and the sixteen tenth sets constitute the n output bits, where, k in , the values of a, b, c, d, e are as shown in any one of the following rows:

[0049] In an eighth aspect, a data processing apparatus is provided, including: a receiving module, configured to receive n output bits, where the n output bits are obtained by performing data processing on k in bits, where the k in bits include one first set including a bits, two second sets each including b bits, four third sets each including c bits, and eight fourth sets each including d bits, 0 < k in <n; The first set is subjected to a first process to obtain a sixth set; Two of the second sets are respectively subjected to a second process with half of the bits of the sixth set to obtain two seventh sets; Four of the third sets are respectively subjected to a third process with half of the bits of each seventh set to obtain four eighth sets; Eight of the fourth sets are respectively subjected to a fourth process with half of the bits of each eighth set to obtain eight ninth sets; Half of the bits of each ninth set are respectively subjected to a fifth process to obtain a total of sixteen tenth sets, and the sixteen tenth sets constitute the n output bits, where, k in , the values of a, b, c, d are as shown in any one of the following rows:

[0050] Combined with the seventh aspect or the eighth aspect, in a possible implementation, the first process, the second process, the third process, the fourth process, and the fifth process are implemented by using a look-up table.

[0051] Combined with the seventh aspect or the eighth aspect and any possible implementation, in a possible implementation, the sixth set includes 10 bits, the seventh set includes 10 bits, the eighth set includes 10 bits, the ninth set includes 10 bits, and the tenth set includes 8 bits.

[0052] Combining the seventh or eighth aspect and any possible implementation, in one possible implementation, n is 128.

[0053] In conjunction with the seventh or eighth aspect and any possible implementation, in one possible implementation, the data processing is probabilistic constellation shaping (PCS) processing, where the probability of a bit being 0 among the n output bits is not equal to the probability of a bit being 1.

[0054] Ninth aspect, a chip is provided for performing the methods described in the first to fourth aspects, and any one of their implementations.

[0055] In a tenth aspect, an optical module is provided, the optical module including a processor and an interface, the processor being configured to execute the methods described in the first to fourth aspects and any one of their implementations, and to transmit and receive signals through the interface.

[0056] In an eleventh aspect, a communication device is provided, the communication device comprising a host-side device and an optical module as described in the tenth aspect, the optical module being connected to the host-side device.

[0057] In a twelfth aspect, a communication system is provided, comprising: a first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is the communication device as described in the eleventh aspect, and the first communication device and the second communication device are connected.

[0058] The beneficial effects of the above aspects can be referred to the beneficial effects of the first aspect, and will not be repeated here. Attached Figure Description

[0059] Figure 1 is a schematic diagram of a communication system provided in an embodiment of this application;

[0060] Figure 2 is a schematic diagram of the sequence processing module provided in an embodiment of this application;

[0061] Figure 3 is a schematic diagram of a data processing method provided in an embodiment of this application;

[0062] Figure 4 is a schematic diagram of another data processing method provided in an embodiment of this application;

[0063] Figure 5 is a structural schematic diagram of an optical module provided in an embodiment of this application;

[0064] Figure 6 is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0065] This application provides a sequence processing method, chip, and optical module, which can solve the problems of high complexity or poor performance in related technologies. It has the advantages of low complexity and good performance, and can be well applied to future high-speed metropolitan area telecommunications transmission systems and metropolitan area data center interconnection transmission scenarios.

[0066] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0067] As shown in Figure 1, the communication system includes a transmitting node 01 and a receiving node 02, which establish a communication connection through channel 03. Both the transmitting node 01 and the receiving node 02 can be communication devices (such as routers, optical transmission devices (such as optical line terminals (OLTs), optical network terminals (ONTs), etc.)), or parts of communication devices, such as chips (such as optical signal digital signal processing (ODSP) chips) and optical modules (which can be pluggable optical modules, non-pluggable optical modules, or coherent communication optical modules).

[0068] Channel 03 can be a wired channel, such as an optical fiber.

[0069] Taking an example where both transmitting node 01 and receiving node 02 are optical modules in a communication device, transmitting node 01 can send signals to receiving node 02 via channel 03 to achieve communication between them. For example, transmitting node 01 can process a bit sequence to obtain a data frame, and then send an optical signal to channel 03 based on the data frame; receiving node 02 can receive the optical signal sent by transmitting node 01 from channel 03, recover the data frame from the optical signal, and process the data frame to obtain the bit sequence. This receiving process is the reverse of the transmitting process.

[0070] Referring to Figure 1, the transmitting node 01 includes: a source 011, a first sequence processing module 012, a first signal processing module 013, and an optical transmitter 014. The source 011, the first sequence processing module 012, the first signal processing module 013, the optical transmitter 014, and the channel 03 are connected sequentially. The source 011 provides a bit sequence to the first sequence processing module 012. This bit sequence includes multiple bits, which can be 0 bits or 1 bits, and the values ​​of different bits in the bit sequence can be the same or different. The first sequence processing module 012 performs sequence processing on the bit sequence (including encoding, interleaving, symbol mapping, etc.) to obtain multiple symbols, and transmits these multiple symbols to the first signal processing module 013. The first signal processing module 013 performs framing processing on these multiple symbols to obtain a data frame; the optical transmitter 014 transmits an optical signal to the channel 03 according to the data frame, so that the optical signal can be transmitted to the receiving node 02 through the channel 03.

[0071] The receiving node 02 includes: a sink 021, a second sequence processing module 022, a second signal processing module 023, and an optical receiver 024. The sink 021, the second sequence processing module 022, the second signal processing module 023, the optical receiver 024, and channel 03 are connected in sequence. The optical receiver 024 can receive the optical signal transmitted by the transmitting node 01 from channel 03 and recover the data frame based on the optical signal. The second signal processing module 023 can perform operations such as dispersion compensation, synchronization, and phase recovery on the data frame, and then perform inverse framing processing to obtain multiple symbols, which are then transmitted to the second sequence processing module 022. The second sequence processing module 022 can perform inverse sequence processing (including decoding, deinterleaving, and symbol demapping) on ​​the multiple symbols to obtain a bit sequence, which is then transmitted to the sink 021.

[0072] It is understood that transmitting node 01 can also have the function of receiving node 02, therefore transmitting node 01 can also act as a receiving node; receiving node 02 can also have the function of transmitting node 01, therefore receiving node 02 can also act as a transmitting node, and this application does not limit this. When a node simultaneously has the functions of a transmitting node and a receiving node, the node includes the signal source 011, the first sequence processing module 012, the first signal processing module 013, the optical transmitter 014, the signal sink 021, the second sequence processing module 022, the second signal processing module 023, and the optical receiver 024 in Figure 1, and the optical transmitter 014 and the optical receiver 024 can be integrated into an optical transceiver. The signal source 011, the first sequence processing module 012, the first signal processing module 013, the signal sink 021, the second sequence processing module 022, and the second signal processing module 023 can be integrated into a chip.

[0073] Furthermore, the probabilistic constellation shaping (PCS) technology is introduced in the sending node. For example, before the first sequence processing module 012 processes the sequence to obtain QAM symbols, the first sequence processing module 012 first performs PCS processing on the input sequence with the same probability of 0 and 1 to obtain an output sequence with different probabilities of 0 and 1, and then performs encoding, interleaving, and symbol mapping to obtain QAM symbols. At this time, the probabilities of the QAM symbols corresponding to each constellation point are non-uniformly distributed, and the probability of the symbol with a higher amplitude decreases. The PCS technology changes the probability of the constellation point symbols while keeping the positions of the constellation point symbols (referred to as symbols for short) unchanged on the signal constellation diagram, improves the transmission effect of the signal, enhances the transmission performance of the communication system, and achieves a larger baud rate or a longer transmission distance.

[0074] Exemplarily, the structure of the first sequence processing module in the sending node can be shown in Figure 2. Referring to Figure 2, the first sequence processing module 012 includes: a PCS processing module 0121, a forward error correction (FEC) encoding module 0122, and a symbol mapping module 0123. Among them, the PCS processing module 0121 can perform PCS processing on the PCS input bit sequence including k0 bits in the bit sequence provided by the data source to obtain a PCS output bit sequence including n0 bits, where 1 < k0 < n0. The above-mentioned bit sequence provided by the data source contains m bits and is composed of the above-mentioned PCS input bit sequence including k0 bits and the remaining bit sequence including m - k0 bits. The FEC encoding module 0122 performs FEC encoding on the above-mentioned PCS output bit sequence including n0 bits and the above-mentioned remaining bit sequence including m - k0 bits, and transmits the bit sequence obtained by FEC encoding to the symbol mapping module 0123. The symbol mapping module 0123 can perform symbol mapping according to the bit sequence obtained by FEC encoding to obtain multiple symbols. Among them, the bits in the bit sequence obtained by PCS processing will be mapped to the amplitude bits of the symbols by the symbol mapping module 0123.

[0075] It should be noted that the above PCS processing can also be called distribution match (DM) processing; interleaving can also be performed before the above FEC encoding, which is called pre-FEC interleaving; interleaving can also be performed after the above FEC encoding, which is called post-FEC interleaving.

[0076] This application considers a 16QAM symbol mapping, with 16 constellation point symbols: 1+1j, 1-1j, -1+1j, -1-1j, 1+3j, 1-3j, -1+3j, -1-3j, 3+1j, 3-1j, -3+1j, -3-1j, 3+3j, 3-3j, -3+3j, and -3-3j, where j represents the imaginary unit. In some scenarios, the imaginary unit may also be represented by other symbols such as i, which is not limited here. In the embodiments of this application, the imaginary unit is uniformly represented by j.

[0077] In the above symbol mapping, 4 bits are mapped to 1 symbol using 16QAM. Two of these four bits are mapped to the in-phase component (I-path component) of the symbol, and the other two bits are mapped to the quadrature-phase component (Q-path component). Of the two bits mapped to the I-path (or Q-path) component, one bit is the sign bit, and the other bit is the amplitude bit.

[0078] In some applications, a value of 0 for the amplitude bit corresponds to a high-level symbol amplitude (also called high amplitude); a value of 1 for the amplitude bit corresponds to a low-level symbol amplitude (also called low amplitude). That is, the probability that the amplitude bit is 0 (i.e., the probability that the amplitude of the I-channel component (or Q-channel component) of the symbol is high) is P. H The probability that the amplitude bit is 1 (that is, the probability that the amplitude of the I-channel component (or Q-channel component) of the symbol is low) is P. L .

[0079] In other applications, a value of 1 for the amplitude bit corresponds to a high-level symbol amplitude (also called high amplitude); a value of 0 for the amplitude bit corresponds to a low-level symbol amplitude (also called low amplitude). That is, the probability that the amplitude bit is 1 (i.e., the probability that the amplitude of the I-channel component (or Q-channel component) of the symbol is high) is P. H The probability that the amplitude bit is 0 (that is, the probability that the amplitude of the I-channel component (or Q-channel component) of the symbol is low) is P. L .

[0080] For 16QAM mapping, the symbol amplitude has only two levels: high (amplitude 3) or low (amplitude 1). There is P H +P L =1, and P H <P LThe probability that the amplitude of the I-channel component of a symbol is high is equal to the probability that the amplitude of the Q-channel component of the symbol is high; the probability that the amplitude of the I-channel component of a symbol is low is equal to the probability that the amplitude of the Q-channel component of the symbol is low.

[0081] Understandably, P H Also known as the amplitude probability (or simply Amp Probability) corresponding to a high amplitude, P L Also known as the amplitude probability corresponding to a low amplitude. P H and P L These are parameters for PCS processing, which is used to make P H <P L Additionally, P H and P L It can also have other forms of expression, such as P H The probability, P, that the amplitude of the I-path component (or Q-path component) of a 16QAM symbol is 3. H It can be represented as P3, or it can be represented as P. +3 ;P L P is the probability that the amplitude of the I-path component (or Q-path component) of a 16QAM symbol is 1. L It can be represented as P1, or it can be represented as P. +1 .

[0082] It is understandable that, since the receiving process performed by the receiving node and the sending process performed by the sending node are inverse processes of each other, the processing performed by the second sequence processing module in the receiving node includes the inverse processing of the PCS process.

[0083] The sequence processing method provided in this application embodiment is executed by a sequence processing device (referred to as a first sequence processing device) in the sending node and a sequence processing device (referred to as a second sequence processing device) in the receiving node. The first sequence processing device may be the sending node, or it may be a first sequence processing module or a PCS processing module, or other modules, in the sending node; the second sequence processing device may be the receiving node, or it may be a second sequence processing module or other modules, in the receiving node. For example, Figure 3 illustrates a processing method provided in this application embodiment:

[0084] Will contain k in Data processing of 128 input bits yields 128 output bits, where:

[0085] 1) Contains k inThe input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5.

[0086] 2) The first set mentioned above contains a bits, where 0 ≤ a ≤ 10.

[0087] 3) Each of the two second sets (i.e., second set 1 and second set 2) contains b bits, where 0 ≤ b ≤ 5.

[0088] 4) Each of the above four sets of the third (i.e. set 1, set 2, set 3, and set 4) contains c bits, where 0 ≤ c ≤ 5.

[0089] 5) Each of the above 8 fourth sets (i.e., fourth set 1, fourth set 2, fourth set 3, fourth set 4, fourth set 5, fourth set 6, fourth set 7, and fourth set 8) contains d bits, where 0 ≤ d ≤ 5.

[0090] 6) Each of the above 16 fifth sets (i.e., fifth set 1, fifth set 2, fifth set 3, fifth set 4, fifth set 5, fifth set 6, fifth set 7, fifth set 8, fifth set 9, fifth set 10, fifth set 11, fifth set 12, fifth set 13, fifth set 14, fifth set 15, and fifth set 16) contains e bits, where 0 ≤ e ≤ 3.

[0091] 7) There is k in = a + 2 × b + 4 × c + 8 × d + 16 × e.

[0092] 8) The first process is: the first set containing a bits is processed to obtain the sixth set containing 10 bits.

[0093] 9) The second processing step is:

[0094] ● The second set 1, containing b bits, is combined with the 5 bits in the sixth set, totaling b+5 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0095] ● The second set containing b bits, combined with the remaining 5 bits from the sixth set, totaling b+5 bits, is processed in the second step to obtain the seventh set containing 10 bits.

[0096] 10) The third processing step is:

[0097] ● The third set 1, containing c bits, is combined with the 5 bits from the seventh set 1, totaling c+5 bits. After the third processing step, the eighth set 1, containing 10 bits, is obtained.

[0098] ● The third set 2, containing c bits, combined with the remaining 5 bits from the seventh set 1, totaling c+5 bits, is processed by the third step to obtain the eighth set 2, containing 10 bits;

[0099] ● The third set containing c bits, combined with the 5 bits in the seventh set 2, totaling c+5 bits, is processed by the third step to obtain the eighth set containing 10 bits;

[0100] ● The third set 4, containing c bits, is combined with the remaining 5 bits from the seventh set 2, totaling c+5 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0101] 11) The fourth process is:

[0102] ● The 4th set 1, containing d bits, combined with the 5 bits from the 8th set 1, totaling d+5 bits, is processed by the 4th step to obtain the 9th set 1, containing 10 bits;

[0103] ● The fourth set 2, containing d bits, combined with the remaining 5 bits from the eighth set 1, totaling d+5 bits, is processed by the fourth step to obtain the ninth set 2, containing 10 bits;

[0104] ● The fourth set 3, containing d bits, is combined with the 5 bits in the eighth set 2, totaling d+5 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0105] ● The fourth set containing d bits, combined with the remaining 5 bits from the eighth set 2, totaling d+5 bits, is processed by the fourth step to obtain the ninth set containing 10 bits;

[0106] ● The fourth set 5, containing d bits, is combined with the 5 bits in the eighth set 3, totaling d+5 bits. After the fourth processing step, the ninth set 5, containing 10 bits, is obtained.

[0107] ● The fourth set 6, containing d bits, is combined with the remaining 5 bits from the eighth set 3, totaling d+5 bits. After the fourth processing step, the ninth set 6, containing 10 bits, is obtained.

[0108] ● The fourth set 7, containing d bits, is combined with the 5 bits in the eighth set 4, totaling d+5 bits. After the fourth processing step, the ninth set 7, containing 10 bits, is obtained.

[0109] ● The fourth set 8, containing d bits, is combined with the remaining 5 bits from the eighth set 4, totaling d+5 bits. After the fourth processing step, the ninth set 8, containing 10 bits, is obtained.

[0110] 12) The fifth step is:

[0111] ● The fifth set 1, containing e bits, is combined with the 5 bits in the ninth set 1, totaling e+5 bits. After the fifth processing step, the tenth set 1, containing 8 bits, is obtained.

[0112] ● The fifth set 2, containing e bits, combined with the remaining 5 bits from the ninth set 1, totaling e+5 bits, is processed by the fifth step to obtain the tenth set 2, containing 8 bits;

[0113] ● The fifth set 3, containing e bits, is combined with the 5 bits in the ninth set 2, totaling e+5 bits. After the fifth processing step, the tenth set 3, containing 8 bits, is obtained.

[0114] ● The fifth set 4, containing e bits, is combined with the remaining 5 bits from the ninth set 2, totaling e+5 bits. After the fifth processing step, the tenth set 4, containing 8 bits, is obtained.

[0115] ● The fifth set containing e bits, combined with the 5 bits in the ninth set 3, totaling e+5 bits, is processed by the fifth step to obtain the tenth set containing 8 bits;

[0116] ● The fifth set 6, containing e bits, is combined with the remaining 5 bits from the ninth set 3, totaling e+5 bits. After the fifth processing step, the tenth set 6, containing 8 bits, is obtained.

[0117] ● The fifth set 7, containing e bits, is combined with the 5 bits in the ninth set 4, totaling e+5 bits. After the fifth processing step, the tenth set 7, containing 8 bits, is obtained.

[0118] ● The fifth set 8, containing e bits, is combined with the remaining 5 bits from the ninth set 4, totaling e+5 bits. After the fifth processing step, the tenth set 8, containing 8 bits, is obtained.

[0119] ● The fifth set 9, containing e bits, is combined with the 5 bits in the ninth set 5, totaling e+5 bits. After the fifth processing step, the tenth set 9, containing 8 bits, is obtained.

[0120] ● The fifth set 10, containing e bits, is combined with the remaining 5 bits from the ninth set 5, totaling e+5 bits. After processing by the fifth step, the tenth set 10, containing 8 bits, is obtained.

[0121] ● The fifth set 11, containing e bits, is combined with the 5 bits from the ninth set 6, totaling e+5 bits. After the fifth processing step, the tenth set 11, containing 8 bits, is obtained.

[0122] ● The fifth set 12, containing e bits, is combined with the remaining 5 bits from the ninth set 6, totaling e+5 bits. After the fifth processing step, the tenth set 12, containing 8 bits, is obtained.

[0123] ● The 5 bits in the 9th set 7 combined with the 5 bits in the 5th set 13 containing e bits total e + 5 bits, and after the 5th processing, the 10th set 13 containing 8 bits is obtained;

[0124] ● The remaining 5 bits in the 9th set 7 combined with the 5 bits in the 5th set 14 containing e bits total e + 5 bits, and after the 5th processing, the 10th set 14 containing 8 bits is obtained;

[0125] ● The 5 bits in the 9th set 8 combined with the 5 bits in the 5th set 15 containing e bits total e + 5 bits, and after the 5th processing, the 10th set 15 containing 8 bits is obtained;

[0126] ● The remaining 5 bits in the 9th set 8 combined with the 5 bits in the 5th set 16 containing e bits total e + 5 bits, and after the 5th processing, the 10th set 16 containing 8 bits is obtained.

[0127] 13) The output bits containing 128 bits are composed of the above 16 10th sets.

[0128] When a = 0, each 1st set does not contain any bits. At this time, the above 1st processing is not performed, and the above 2nd processing processes a 2nd set to obtain a 7th set.

[0129] When b = 0, each 2nd set does not contain any bits. At this time, the above 2nd processing processes 5 bits in a 6th set to obtain a 7th set.

[0130] When c = 0, each 3rd set does not contain any bits. At this time, the above 3rd processing processes 5 bits in a 7th set to obtain an 8th set.

[0131] When d = 0, each 4th set does not contain any bits. At this time, the above 4th processing processes 5 bits in an 8th set to obtain a 9th set.

[0132] When e = 0, each 5th set does not contain any bits. At this time, the above 5th processing processes 5 bits in a 9th set to obtain a 10th set.

[0133] In some specific embodiments, further consider 0 < a ≤ 10, 0 < b ≤ 5, 0 < c ≤ 5, 0 < d ≤ 5, e = 0. FIG. 4 shows the corresponding processing method, where the above 5th processing is specifically represented as follows:

[0134] ● The 5 bits in the 9th set 1 pass through the 5th processing to obtain the 10th set 1 containing 8 bits;

[0135] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0136] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0137] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0138] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0139] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0140] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0141] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0142] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0143] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0144] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0145] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0146] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0147] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0148] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0149] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0150] In some specific implementations, the first, second, third, fourth, and fifth processes described above are implemented using look-up tables (LUTs). In this case, the first, second, third, fourth, and fifth processes can also be referred to as LUT A, LUT B, LUT C, LUT D, and LUT E, respectively.

[0151] Given the parameter combination {a, b, c, d, e}, by designing the specific operations of the first, second, third, fourth, and fifth processes described above, the probabilities of 0 and 1 in the 128-bit output bits can be made unequal. This allows us to obtain the probability of the output bit being 0 and the probability of the output bit being 1 for the parameter combination {a, b, c, d, e}. Specifically, the greater the difference between the probabilities of the output bit being 0 and the output bit being 1, the better the PCS effect obtained by the data processing. That is, the magnitude of this probability difference can be used to judge the quality of the PCS effect for any two sets of parameter combinations {a, b, c, d, e}. The probability value with the larger value between the probability of the output bit being 0 and the probability of the output bit being 1 is P. L The smaller probability value is P. H .

[0152] The effectiveness of PCS can also be measured by the average power of PCS output bits (in dB), which is specifically taken as 10×log 10 (P L +9×P H ).

[0153] For a given process (process 1, process 2, process 3, process 4, or process 5) implemented using a lookup table, its complexity can be expressed as: Integer LUT in Indicates the input bit length of the lookup table, an integer LUT. out This indicates the output bit length of the lookup table. For example, at the sending end, the complexity of the first process described above is 2^n. (a) ×10; Correspondingly, at the receiving end, the inverse process of the first step is to look up 10 bits in a table and output 'a' bits, with a complexity of 2^n. 10 ×a=1024×a.

[0154] Therefore, the complexity of the sending end using the above method is:

[0155] M Tx =2 (a) ×10+2 (b+5) ×10×2+2 (c+5) ×10×4+2 (d+5) ×10×8+2(e+5) ×8×16

[0156] The receiver complexity using the above method is:

[0157] M Rx =2 (10) ×a+2 (10) ×2 (b+5) ×2+2 (10) ×(c+5)×4+2 (10) ×(d+5)×8+2 (8) ×(e+5)×16

[0158] The overall complexity of the sending and receiving ends (simply referred to as the transceiver ends) using the above method is M. TR =M Tx +M Rx .

[0159] Below, we combine k in The specific values ​​of the above five parameters a, b, c, d, and e are given as better combinations.

[0160] Examples 1-50: Considering k in =50, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0161] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0162] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0163] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0164] Example 1-51: Considering k in =51, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0165] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0166] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0167] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0168] Example 1-52: Considering k in =52, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity MTR .

[0169] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0170] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0171] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0172] Example 1-53: Considering k in =53, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0173] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0174] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0175] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0176] Example 1-54: Considering k in =54. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0177] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0178] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0179] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0180] Example 1-55: Considering k in =55, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0181] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0182] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0183] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0184] Examples 1-56: Considering k in =56. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0185] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P HThe greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0186] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0187] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0188] Example 1-57: Considering k in =57. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0189] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0190] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0191] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0192] Example 1-58: Considering k in =58. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0193] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0194] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0195] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0196] Examples 1-59: Considering k in =59, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P HPCS output bit average power (power), overall complexity M TR .

[0197] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0198] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0199] Furthermore, there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations. Using the method provided in this embodiment, the input bits are divided into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and lower average power of the corresponding PCS output bits, leading to better PCS implementation performance.

[0200] Examples 1-60: Considering k in =60, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0201] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TRAs can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0202] In some specific applications, considering that the parameter combinations in numbers 30-41 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0203] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 41 {a=6, b=3, c=4, d=4, e=0}, which will include k. in = 60 input bits are processed to produce an output of 128 bits, which includes k in The 60-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0204] 1) The first processing is: the first set containing a = 6 bits is processed to obtain the sixth set containing 10 bits.

[0205] 2) The second process is as follows:

[0206] ● The second set 1, containing b = 3 bits, combined with the 5 bits in the sixth set, totals b + 5 = 8 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0207] ● The second set, containing b = 3 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 8 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0208] 3) The third process is:

[0209] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0210] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0211] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0212] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0213] 4) The fourth process is:

[0214] ● The fourth set 1, containing d = 4 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0215] ● The fourth set 2, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0216] ● The fourth set 3, containing d = 4 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 9 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0217] ● The fourth set 4, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 2, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 4, containing 10 bits, is obtained.

[0218] ● The fourth set 5, containing d = 4 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0219] ● The fourth set 6, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0220] ● The fourth set 7, containing d = 4 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0221] ● The fourth set 8, containing d = 4 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0222] 5) The fifth step is:

[0223] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0224] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0225] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0226] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0227] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0228] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0229] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0230] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0231] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0232] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0233] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0234] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0235] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0236] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0237] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0238] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0239] Using the method provided in this embodiment, k inThe 60-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=6, b=3, c=4, d=4, e=0}, the first process converts every 6 bits into 10 bits, the second process converts every 8 bits into 10 bits, the third process converts every 9 bits into 10 bits, the fourth process converts every 9 bits into 10 bits, and the fifth process converts every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit in the corresponding PCS output, indicating good PCS implementation performance.

[0240] Example 1-61: Consider k in =61, the table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0241] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0242] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0243] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=7, b=3, c=4, d=4, e=0}, which will include k. in = 61 input bits are processed to produce an output of 128 bits, which includes k inThe 61-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0244] 1) The first processing is: the first set containing a = 7 bits is processed to obtain the sixth set containing 10 bits.

[0245] 2) The second process is as follows:

[0246] ● The second set 1, containing b = 3 bits, combined with the 5 bits in the sixth set, totals b + 5 = 8 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0247] ● The second set, containing b = 3 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 8 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0248] 3) The third process is:

[0249] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0250] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0251] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0252] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0253] 4) The fourth process is:

[0254] ● The fourth set 1, containing d = 4 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0255] ● The fourth set 2, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0256] ● The fourth set 3, containing d = 4 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 9 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0257] ● The fourth set 4, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 2, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 4, containing 10 bits, is obtained.

[0258] ● The fourth set 5, containing d = 4 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0259] ● The fourth set 6, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0260] ● The fourth set 7, containing d = 4 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0261] ● The fourth set 8, containing d = 4 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0262] 5) The fifth step is:

[0263] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0264] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0265] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0266] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0267] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0268] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0269] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0270] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0271] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0272] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0273] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0274] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0275] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0276] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0277] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0278] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0279] Using the method provided in this embodiment, k in The 61-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=7, b=3, c=4, d=4, e=0}, the first process processes every 7 bits into 10 bits, the second process processes every 8 bits into 10 bits, the third process processes every 9 bits into 10 bits, the fourth process processes every 9 bits into 10 bits, and the fifth process processes every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit of the corresponding PCS output, indicating good PCS implementation performance.

[0280] Example 1-62: Considering k in =62. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0281] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0282] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0283] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=6, b=4, c=4, d=4, e=0}, which will include k. in = 62 bits of input bits are processed to produce 128 bits of output bits, including k in The 62-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order (1st, 2nd, 3rd, 4th, and 5th) is as follows:

[0284] 1) The first processing is: the first set containing a = 6 bits is processed to obtain the sixth set containing 10 bits.

[0285] 2) The second process is as follows:

[0286] ● The second set 1, containing b = 4 bits, combined with the 5 bits in the sixth set, totals b + 5 = 9 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0287] ● The second set, containing b = 4 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 9 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0288] 3) The third process is:

[0289] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0290] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0291] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0292] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0293] 4) The fourth process is:

[0294] ● The fourth set 1, containing d = 4 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0295] ● The fourth set 2, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0296] ● The fourth set 3, containing d = 4 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 9 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0297] ● The fourth set 4, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 2, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 4, containing 10 bits, is obtained.

[0298] ● The fourth set 5, containing d = 4 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0299] ● The fourth set 6, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0300] ● The fourth set 7, containing d = 4 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0301] ● The fourth set 8, containing d = 4 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0302] 5) The fifth step is:

[0303] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0304] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0305] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0306] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0307] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0308] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0309] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0310] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0311] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0312] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0313] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0314] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0315] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0316] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0317] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0318] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0319] Using the method provided in this embodiment, k in The 62-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=6, b=4, c=4, d=4, e=0}, the first process converts every 6 bits into 10 bits, the second process converts every 9 bits into 10 bits, the third process converts every 9 bits into 10 bits, the fourth process converts every 9 bits into 10 bits, and the fifth process converts every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit of the corresponding PCS output, indicating good PCS implementation performance.

[0320] Example 1-63: Considering k in =63. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0321] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0322] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0323] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=7, b=4, c=4, d=4, e=0}, which will include k. in = 63 input bits are processed to produce an output of 128 bits, which includes k in The 63-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0324] 1) The first processing is: the first set containing a = 7 bits is processed to obtain the sixth set containing 10 bits.

[0325] 2) The second process is as follows:

[0326] ● The second set 1, containing b = 4 bits, combined with the 5 bits in the sixth set, totals b + 5 = 9 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0327] ● The second set, containing b = 4 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 9 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0328] 3) The third process is:

[0329] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0330] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0331] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0332] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0333] 4) The fourth process is:

[0334] ● The fourth set 1, containing d = 4 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0335] ● The fourth set 2, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0336] ● The fourth set 3, containing d = 4 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 9 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0337] ● The fourth set 4, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 2, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 4, containing 10 bits, is obtained.

[0338] ● The fourth set 5, containing d = 4 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0339] ● The fourth set 6, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0340] ● The fourth set 7, containing d = 4 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0341] ● The fourth set 8, containing d = 4 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0342] 5) The fifth step is:

[0343] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0344] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0345] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0346] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0347] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0348] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0349] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0350] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0351] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0352] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0353] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0354] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0355] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0356] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0357] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0358] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0359] Using the method provided in this embodiment, k in The 63-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=7, b=4, c=4, d=4, e=0}, the first process converts every 7 bits into 10 bits, the second process converts every 9 bits into 10 bits, the third process converts every 9 bits into 10 bits, the fourth process converts every 9 bits into 10 bits, and the fifth process converts every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit of the corresponding PCS output, indicating good PCS implementation performance.

[0360] Example 1-64: Considering k in =64. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0361] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0362] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0363] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=8, b=4, c=4, d=4, e=0}, which will include k. in = 64 input bits are processed to produce 128 output bits, which include k in The 64-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0364] 1) The first processing is: the first set containing a = 8 bits is processed to obtain the sixth set containing 10 bits.

[0365] 2) The second process is as follows:

[0366] ● The second set 1, containing b = 4 bits, combined with the 5 bits in the sixth set, totals b + 5 = 9 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0367] ● The second set, containing b = 4 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 9 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0368] 3) The third process is:

[0369] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0370] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0371] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0372] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0373] 4) The fourth process is:

[0374] ● The fourth set 1, containing d = 4 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0375] ● The fourth set 2, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0376] ● The fourth set 3, containing d = 4 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 9 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0377] ● The fourth set 4, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 2, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 4, containing 10 bits, is obtained.

[0378] ● The fourth set 5, containing d = 4 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0379] ● The fourth set 6, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0380] ● The fourth set 7, containing d = 4 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0381] ● The fourth set 8, containing d = 4 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0382] 5) The fifth step is:

[0383] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0384] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0385] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0386] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0387] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0388] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0389] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0390] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0391] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0392] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0393] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0394] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0395] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0396] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0397] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0398] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0399] Using the method provided in this embodiment, k in The 64-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=8, b=4, c=4, d=4, e=0}, the first process converts every 8 bits into 10 bits, the second process converts every 9 bits into 10 bits, the third process converts every 9 bits into 10 bits, the fourth process converts every 9 bits into 10 bits, and the fifth process converts every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit of the corresponding PCS output, indicating good PCS implementation performance.

[0400] Example 1-65: Considering k in =65. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0401] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0402] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0403] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=7, b=3, c=5, d=4, e=0}, which will include k. in = 65 input bits are processed to produce 128 output bits, which include k in The 65-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0404] 1) The first processing is: the first set containing a = 7 bits is processed to obtain the sixth set containing 10 bits.

[0405] 2) The second process is as follows:

[0406] ● The second set 1, containing b = 3 bits, combined with the 5 bits in the sixth set, totals b + 5 = 8 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0407] ● The second set, containing b = 3 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 8 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0408] 3) The third process is:

[0409] ● The third set 1, containing c = 5 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 10 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0410] ● The third set 2, containing c = 5 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 10 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0411] ● The third set, containing c = 5 bits, combined with the 5 bits in the seventh set, totals c + 5 = 10 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0412] ● The third set 4, containing c = 5 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 10 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0413] 4) The fourth process is:

[0414] ● The fourth set 1, containing d = 4 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0415] ● The fourth set 2, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0416] ● The fourth set 3, containing d = 4 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 9 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0417] ● The fourth set 4, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 2, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 4, containing 10 bits, is obtained.

[0418] ● The fourth set 5, containing d = 4 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0419] ● The fourth set 6, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0420] ● The fourth set 7, containing d = 4 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0421] ● The fourth set 8, containing d = 4 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0422] 5) The fifth step is:

[0423] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0424] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0425] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0426] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0427] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0428] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0429] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0430] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0431] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0432] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0433] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0434] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0435] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0436] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0437] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0438] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0439] Using the method provided in this embodiment, k inThe 65-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=7, b=3, c=5, d=4, e=0}, the first process processes every 7 bits into 10 bits, the second process processes every 8 bits into 10 bits, the third process processes every 10 bits into 10 bits, the fourth process processes every 9 bits into 10 bits, and the fifth process processes every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit in the corresponding PCS output, indicating good PCS implementation performance.

[0440] Example 1-66: Consider k in =66. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0441] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0442] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0443] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=6, b=4, c=5, d=4, e=0}, which will include k. in = 66 input bits are processed to produce an output of 128 bits, which includes k inThe 66-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0444] 1) The first processing is: the first set containing a = 6 bits is processed to obtain the sixth set containing 10 bits.

[0445] 2) The second process is as follows:

[0446] ● The second set 1, containing b = 4 bits, combined with the 5 bits in the sixth set, totals b + 5 = 9 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0447] ● The second set, containing b = 4 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 9 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0448] 3) The third process is:

[0449] ● The third set 1, containing c = 5 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 10 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0450] ● The third set 2, containing c = 5 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 10 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0451] ● The third set, containing c = 5 bits, combined with the 5 bits in the seventh set, totals c + 5 = 10 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0452] ● The third set 4, containing c = 5 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 10 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0453] 4) The fourth process is:

[0454] ● The fourth set 1, containing d = 4 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0455] ● The fourth set 2, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0456] ● The fourth set 3, containing d = 4 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 9 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0457] ● The fourth set 4, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 2, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 4, containing 10 bits, is obtained.

[0458] ● The fourth set 5, containing d = 4 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0459] ● The fourth set 6, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0460] ● The fourth set 7, containing d = 4 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0461] ● The fourth set 8, containing d = 4 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0462] 5) The fifth step is:

[0463] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0464] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0465] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0466] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0467] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0468] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0469] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0470] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0471] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0472] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0473] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0474] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0475] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0476] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0477] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0478] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0479] Using the method provided in this embodiment, k in The 66-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=6, b=4, c=5, d=4, e=0}, the first process converts every 6 bits into 10 bits, the second process converts every 9 bits into 10 bits, the third process converts every 10 bits into 10 bits, the fourth process converts every 9 bits into 10 bits, and the fifth process converts every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit of the corresponding PCS output, indicating good PCS implementation performance.

[0480] Examples 1-67: Considering k in =67. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0481] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0482] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0483] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=7, b=2, c=4, d=5, e=0}, which will include k. in = 67 input bits are processed to produce an output of 128 bits, which includes k in The 67-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0484] 1) The first processing is: the first set containing a = 7 bits is processed to obtain the sixth set containing 10 bits.

[0485] 2) The second process is as follows:

[0486] ● The second set 1, containing b = 2 bits, combined with the 5 bits in the sixth set, totals b + 5 = 7 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0487] ● The second set, containing b = 2 bits, combined with the remaining 5 bits from the sixth set, totals b + 5 = 7 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0488] 3) The third process is:

[0489] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0490] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0491] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0492] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0493] 4) The fourth process is:

[0494] ● The fourth set 1, containing d = 5 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 10 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0495] ● The fourth set 2, containing d = 5 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 10 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0496] ● The fourth set 3, containing d = 5 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 10 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0497] ● The fourth set containing d = 5 bits, combined with the remaining 5 bits in the eighth set 2, totals d + 5 = 10 bits. After the fourth processing, the ninth set containing 10 bits is obtained.

[0498] ● The fourth set 5, containing d = 5 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 10 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0499] ● The fourth set 6, containing d = 5 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 10 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0500] ● The fourth set 7, containing d = 5 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 10 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0501] ● The fourth set 8, containing d = 5 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 10 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0502] 5) The fifth step is:

[0503] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0504] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0505] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0506] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0507] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0508] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0509] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0510] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0511] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0512] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0513] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0514] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0515] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0516] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0517] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0518] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0519] Using the method provided in this embodiment, k in The 67-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=7, b=2, c=4, d=5, e=0}, the first process processes every 7 bits into 10 bits, the second process processes every 7 bits into 10 bits, the third process processes every 9 bits into 10 bits, the fourth process processes every 10 bits into 10 bits, and the fifth process processes every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit of the corresponding PCS output, indicating good PCS implementation performance.

[0520] Example 1-68: Considering k in =68. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0521] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0522] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0523] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=6, b=3, c=4, d=5, e=0}, which will include k. in = 68 bits of input bits are processed to produce 128 bits of output bits, which include k in The 68-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order 1, 2, 3, 4, and 5 is as follows:

[0524] 1) The first processing is: the first set containing a = 6 bits is processed to obtain the sixth set containing 10 bits.

[0525] 2) The second process is as follows:

[0526] ● The second set 1, containing b = 3 bits, combined with the 5 bits in the sixth set, totals b + 5 = 8 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0527] ● The second set, containing b = 3 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 8 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0528] 3) The third process is:

[0529] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0530] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0531] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0532] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0533] 4) The fourth process is:

[0534] ● The fourth set 1, containing d = 5 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 10 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0535] ● The fourth set 2, containing d = 5 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 10 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0536] ● The fourth set 3, containing d = 5 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 10 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0537] ● The fourth set containing d = 5 bits, combined with the remaining 5 bits in the eighth set 2, totals d + 5 = 10 bits. After the fourth processing, the ninth set containing 10 bits is obtained.

[0538] ● The fourth set 5, containing d = 5 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 10 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0539] ● The fourth set 6, containing d = 5 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 10 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0540] ● The fourth set 7, containing d = 5 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 10 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0541] ● The fourth set 8, containing d = 5 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 10 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0542] 5) The fifth step is:

[0543] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0544] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0545] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0546] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0547] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0548] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0549] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0550] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0551] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0552] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0553] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0554] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0555] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0556] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0557] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0558] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0559] Using the method provided in this embodiment, k in The 68-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=6, b=3, c=4, d=5, e=0}, the first process converts every 6 bits into 10 bits, the second process converts every 8 bits into 10 bits, the third process converts every 9 bits into 10 bits, the fourth process converts every 10 bits into 10 bits, and the fifth process converts every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit in the corresponding PCS output, indicating good PCS implementation performance.

[0560] Examples 1-69: Considering k in =69. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0561] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0562] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0563] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=7, b=3, c=4, d=5, e=0}, which will include k. in = 69 input bits are processed to produce an output of 128 bits, which includes k in The 69-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0564] 1) The first processing is: the first set containing a = 7 bits is processed to obtain the sixth set containing 10 bits.

[0565] 2) The second process is as follows:

[0566] ● The second set 1, containing b = 3 bits, combined with the 5 bits in the sixth set, totals b + 5 = 8 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0567] ● The second set, containing b = 3 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 8 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0568] 3) The third process is:

[0569] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0570] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0571] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0572] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0573] 4) The fourth process is:

[0574] ● The fourth set 1, containing d = 5 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 10 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0575] ● The fourth set 2, containing d = 5 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 10 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0576] ● The fourth set 3, containing d = 5 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 10 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0577] ● The fourth set containing d = 5 bits, combined with the remaining 5 bits in the eighth set 2, totals d + 5 = 10 bits. After the fourth processing, the ninth set containing 10 bits is obtained.

[0578] ● The fourth set 5, containing d = 5 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 10 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0579] ● The fourth set 6, containing d = 5 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 10 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0580] ● The fourth set 7, containing d = 5 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 10 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0581] ● The fourth set 8, containing d = 5 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 10 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0582] 5) The fifth step is:

[0583] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0584] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0585] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0586] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0587] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0588] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0589] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0590] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0591] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0592] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0593] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0594] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0595] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0596] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0597] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0598] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0599] Using the method provided in this embodiment, k in The 69-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=7, b=3, c=4, d=5, e=0}, the first process processes every 7 bits into 10 bits, the second process processes every 8 bits into 10 bits, the third process processes every 9 bits into 10 bits, the fourth process processes every 10 bits into 10 bits, and the fifth process processes every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit in the corresponding PCS output, indicating good PCS implementation performance.

[0600] Examples 1-70: Considering k in =70. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0601] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0602] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0603] In other specific applications, consider the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=6, b=4, c=4, d=5, e=0}, which will include k. in =70 input bits are processed to produce an output of 128 bits, which includes k in The 70-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0604] 1) The first processing is: the first set containing a = 6 bits is processed to obtain the sixth set containing 10 bits.

[0605] 2) The second process is as follows:

[0606] ● The second set 1, containing b = 4 bits, combined with the 5 bits in the sixth set, totals b + 5 = 9 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0607] ● The second set, containing b = 4 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 9 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0608] 3) The third process is:

[0609] ● The third set 1, containing c = 4 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0610] ● The third set 2, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 9 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0611] ● The third set, containing c = 4 bits, combined with the 5 bits in the seventh set, totals c + 5 = 9 bits. After the third processing, the eighth set, containing 10 bits, is obtained.

[0612] ● The third set 4, containing c = 4 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 9 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0613] 4) The fourth process is:

[0614] ● The fourth set 1, containing d = 5 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 10 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0615] ● The fourth set 2, containing d = 5 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 10 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0616] ● The fourth set 3, containing d = 5 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 10 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0617] ● The fourth set containing d = 5 bits, combined with the remaining 5 bits in the eighth set 2, totals d + 5 = 10 bits. After the fourth processing, the ninth set containing 10 bits is obtained.

[0618] ● The fourth set 5, containing d = 5 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 10 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0619] ● The fourth set 6, containing d = 5 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 10 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0620] ● The fourth set 7, containing d = 5 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 10 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0621] ● The fourth set 8, containing d = 5 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 10 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0622] 5) The fifth step is:

[0623] ●The 5 bits in set 91 are processed by the 5th step to obtain set 101, which contains 8 bits;

[0624] ●The remaining 5 bits in set 9, 1 are processed by step 5 to obtain set 10, 2, which contains 8 bits;

[0625] ●The 5 bits in set 2 of the 9th set are processed by the 5th step to obtain set 3 of the 10th set, which contains 8 bits;

[0626] ●The remaining 5 bits in set 9, 2 are processed by step 5 to obtain set 10, 4, which contains 8 bits;

[0627] ● Five bits from set 3 of the 9th set are processed by the 5th set to obtain set 5 of the 10th set, which contains 8 bits;

[0628] ●The remaining 5 bits in set 3 of the 9th set are processed by the 5th set to obtain set 6 of the 10th set, which contains 8 bits;

[0629] ●The 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 7 of the 10th set, which contains 8 bits;

[0630] ●The remaining 5 bits in set 4 of the 9th set are processed by the 5th set to obtain set 8 of the 10th set, which contains 8 bits;

[0631] ● The 5 bits in set 9 are processed by step 5 to obtain set 10, which contains 8 bits;

[0632] ●The remaining 5 bits in set 9, 5 are processed by step 5 to obtain set 10, 10, which contains 8 bits;

[0633] ● Five bits from set 6 of the 9th set are processed by the 5th step to obtain set 11 of the 10th set, which contains 8 bits;

[0634] ●The remaining 5 bits in set 6 of the 9th set are processed by the 5th set to obtain set 12 of the 10th set, which contains 8 bits;

[0635] ● Five bits from set 7 of the 9th set are processed by the 5th step to obtain set 13 of the 10th set, which contains 8 bits;

[0636] ●The remaining 5 bits in set 7 of the 9th set are processed by the 5th set to obtain set 14 of the 10th set, which contains 8 bits;

[0637] ● Five bits from set 9, 8 are processed by step 5 to obtain set 10, 15, which contains eight bits;

[0638] ●The remaining 5 bits in set 8 of the 9th set are processed by the 5th set to obtain set 16 of the 10th set, which contains 8 bits.

[0639] Using the method provided in this embodiment, k inThe 70-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=6, b=4, c=4, d=5, e=0}, the first process converts every 6 bits into 10 bits, the second process converts every 9 bits into 10 bits, the third process converts every 9 bits into 10 bits, the fourth process converts every 10 bits into 10 bits, and the fifth process converts every 5 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit in the corresponding PCS output, indicating good PCS implementation performance.

[0640] Example 1-71: Considering k in =71, the table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0641] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0642] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0643] Furthermore, considering the optimal PCS combination in the table above, namely the parameter combination in row 40 {a=7, b=4, c=2, d=4, e=1}, this will include k. in =71 bits of input bits are processed to produce 128 bits of output bits, including k inThe 71-bit input bits consist of 1 set 1, 2 sets 2, 4 sets 3, 8 sets 4, and 16 sets 5. The 128-bit output bits consist of 16 sets 10. The processing order is as follows:

[0644] 1) The first processing is: the first set containing a = 7 bits is processed to obtain the sixth set containing 10 bits.

[0645] 2) The second process is as follows:

[0646] ● The second set 1, containing b = 4 bits, combined with the 5 bits in the sixth set, totals b + 5 = 9 bits. After the second processing, the seventh set 1, containing 10 bits, is obtained.

[0647] ● The second set, containing b = 4 bits, is combined with the remaining 5 bits from the sixth set, totaling b + 5 = 9 bits. After the second processing, the seventh set, containing 10 bits, is obtained.

[0648] 3) The third process is:

[0649] ● The third set 1, containing c = 2 bits, combined with the 5 bits in the seventh set 1, totals c + 5 = 7 bits. After the third processing, the eighth set 1, containing 10 bits, is obtained.

[0650] ● The third set 2, containing c = 2 bits, combined with the remaining 5 bits from the seventh set 1, totals c + 5 = 7 bits. After the third processing, the eighth set 2, containing 10 bits, is obtained.

[0651] ● The third set 3, containing c = 2 bits, combined with the 5 bits in the seventh set 2, totals c + 5 = 7 bits. After the third processing, the eighth set 3, containing 10 bits, is obtained.

[0652] ● The third set 4, containing c = 2 bits, combined with the remaining 5 bits from the seventh set 2, totals c + 5 = 7 bits. After the third processing, the eighth set 4, containing 10 bits, is obtained.

[0653] 4) The fourth process is:

[0654] ● The fourth set 1, containing d = 4 bits, combined with the 5 bits in the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 1, containing 10 bits, is obtained.

[0655] ● The fourth set 2, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 1, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 2, containing 10 bits, is obtained.

[0656] ● The fourth set 3, containing d = 4 bits, combined with the 5 bits in the eighth set 2, totals d + 5 = 9 bits. After the fourth processing, the ninth set 3, containing 10 bits, is obtained.

[0657] ● The fourth set 4, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 2, totals d + 5 = 9 bits. After the fourth processing step, the ninth set 4, containing 10 bits, is obtained.

[0658] ● The fourth set 5, containing d = 4 bits, combined with the 5 bits in the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 5, containing 10 bits, is obtained.

[0659] ● The fourth set 6, containing d = 4 bits, combined with the remaining 5 bits from the eighth set 3, totals d + 5 = 9 bits. After the fourth processing, the ninth set 6, containing 10 bits, is obtained.

[0660] ● The fourth set 7, containing d = 4 bits, combined with the 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 7, containing 10 bits, is obtained.

[0661] ● The fourth set 8, containing d = 4 bits, combined with the remaining 5 bits in the eighth set 4, totals d + 5 = 9 bits. After the fourth processing, the ninth set 8, containing 10 bits, is obtained.

[0662] 5) The fifth step is:

[0663] ● The fifth set 1, containing e = 1 bit, combined with the 5 bits in the ninth set 1, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 1, containing 8 bits, is obtained.

[0664] ● The fifth set 2, containing e = 1 bit, combined with the remaining 5 bits in the ninth set 1, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 2, containing 8 bits, is obtained.

[0665] ● The fifth set 3, containing e = 1 bit, combined with the 5 bits in the ninth set 2, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 3, containing 8 bits, is obtained.

[0666] ● The fifth set 4, containing e = 1 bit, combined with the remaining 5 bits in the ninth set 2, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 4, containing 8 bits, is obtained.

[0667] ● The fifth set, containing e = 1 bit, combined with the 5 bits in the ninth set, totals e + 5 = 6 bits. After processing by the fifth set, the tenth set, containing 8 bits, is obtained.

[0668] ● The fifth set 6, containing e = 1 bit, combined with the remaining 5 bits from the ninth set 3, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 6, containing 8 bits, is obtained.

[0669] ● The fifth set 7, containing e = 1 bit, combined with the 5 bits in the ninth set 4, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 7, containing 8 bits, is obtained.

[0670] ● The fifth set 8, containing e = 1 bit, combined with the remaining 5 bits in the ninth set 4, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 8, containing 8 bits, is obtained.

[0671] ● The fifth set 9, containing e = 1 bit, combined with the 5 bits in the ninth set 5, totals e + 5 = 6 bits. After processing by the fifth step, the tenth set 9, containing 8 bits, is obtained.

[0672] ● The fifth set 10, containing e = 1 bit, combined with the remaining 5 bits from the ninth set 5, totals e + 5 = 6 bits. After processing by the fifth set, the tenth set 10, containing 8 bits, is obtained.

[0673] ● The fifth set 11, containing e = 1 bit, combined with the 5 bits in the ninth set 6, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 11, containing 8 bits, is obtained.

[0674] ● The fifth set 12, containing e = 1 bit, combined with the remaining 5 bits from the ninth set 6, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 12, containing 8 bits, is obtained.

[0675] ● The fifth set 13, containing e = 1 bit, combined with the 5 bits in the ninth set 7, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 13, containing 8 bits, is obtained.

[0676] ● The fifth set 14, containing e = 1 bit, combined with the remaining 5 bits from the ninth set 7, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 14, containing 8 bits, is obtained.

[0677] ● The fifth set 15, containing e = 1 bit, combined with the 5 bits in the ninth set 8, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 15, containing 8 bits, is obtained.

[0678] ● The fifth set 16, containing e = 1 bit, combined with the remaining 5 bits from the ninth set 8, totals e + 5 = 6 bits. After the fifth processing step, the tenth set 16, containing 8 bits, is obtained.

[0679] Using the method provided in this embodiment, kin The 71-bit input bits are divided into multiple sets and processed in multiple steps. For example, in the data processing corresponding to the parameter combination {a=7, b=4, c=2, d=4, e=1}, the first process converts every 7 bits into 10 bits, the second process converts every 9 bits into 10 bits, the third process converts every 7 bits into 10 bits, the fourth process converts every 9 bits into 10 bits, and the fifth process converts every 6 bits into 10 bits. It can be seen that each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and a low average power per bit in the corresponding PCS output, indicating good PCS implementation performance.

[0680] Example 1-73: Considering k in =73. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0681] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0682] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0683] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0684] Example 1-74: Considering k in =74. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P HPCS output bit average power, overall complexity M TR .

[0685] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0686] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0687] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0688] Example 1-75: Considering k in =75. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0689] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0690] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0691] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0692] Example 1-76: Considering k in =76. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0693] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0694] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0695] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0696] Example 1-77: Considering k in =77. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0697] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0698] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0699] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0700] Example 1-78: Considering k in =78. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0701] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0702] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0703] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0704] Example 1-79: Considering k in =79. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0705] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0706] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0707] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0708] Example 1-80: Considering k in =80, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0709] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0710] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0711] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0712] Example 1-81: Considering k in =81, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0713] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0714] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0715] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0716] Example 1-82: Considering k in =82. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0717] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0718] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0719] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0720] Example 1-83: Considering k in =83. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P HPCS output bit average power, overall complexity M TR .

[0721] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0722] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0723] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0724] Example 1-84: Considering k in =84. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0725] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0726] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0727] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0728] Example 1-85: Considering k in =85. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0729] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0730] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0731] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0732] Example 1-86: Considering k in =86. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0733] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0734] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0735] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0736] Example 1-87: Considering k in =87. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0737] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0738] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0739] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0740] Example 1-88: Considering k in =88. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0741] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0742] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0743] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0744] Examples 1-89: Considering k in =89, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0745] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0746] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0747] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0748] Example 1-90: Considering k in =90, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0749] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0750] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0751] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0752] Example 1-91: Considering k in =91, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0753] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0754] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0755] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0756] Example 1-92: Considering k in =92. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0757] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0758] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0759] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0760] Example 1-93: Considering k in =93. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0761] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0762] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0763] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0764] Example 1-94: Considering k in =94. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0765] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0766] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0767] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0768] Example 1-95: Considering k in =95. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0769] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0770] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0771] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0772] Example 1-96: Considering k in =96. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0773] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0774] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0775] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0776] Example 1-97: Considering k in =97. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0777] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0778] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0779] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0780] Example 1-98: Considering k in =98. The table below shows the parameter combinations of a, b, c, d, and e, and their corresponding low-amplitude probabilities P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0781] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0782] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0783] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0784] Example 1-99: Considering k in =99, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0785] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0786] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0787] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0788] Example 1-100: Considering k in =100, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0789] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0790] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0791] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0792] Example 1-101: Considering k in =101. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0793] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0794] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0795] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0796] Example 1-102: Considering k in =102. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0797] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0798] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0799] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0800] Example 1-103: Considering k in =103. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0801] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0802] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0803] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0804] Example 1-104: Considering k in =104. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability PH PCS output bit average power, overall complexity M TR .

[0805] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0806] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0807] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0808] Example 1-105: Considering k in =105. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0809] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0810] In some specific applications, considering that the parameter combinations in numbers 30-40 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use. It should also be noted that there are many possible parameter combinations {a, b, c, d, e}, and this embodiment provides some better parameter combinations.

[0811] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0812] Example 1-106: Considering k in =106. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0813] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0814] In some specific applications, the PCS performance corresponding to the parameter combinations in numbers 30-40 is better and the complexity is lower, so one set of parameter combinations is selected for use.

[0815] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0816] Example 1-107: Considering k in =107. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0817] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0818] In some specific applications, considering that the parameter combinations in numbers 30-36 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use.

[0819] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0820] Example 1-108: Considering k in =108. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0821] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0822] In some specific applications, the PCS performance corresponding to the parameter combinations in numbers 30-40 is better and the complexity is lower, so one set of parameter combinations is selected for use.

[0823] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0824] Example 1-109: Considering k in =109. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0825] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0826] In some specific applications, the PCS performance corresponding to the parameter combinations in numbers 25-30 is better and the complexity is lower, so one set of parameter combinations is selected for use.

[0827] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0828] Example 1-110: Considering k in =110. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0829] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P HThe greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0830] In some specific applications, considering that the parameter combinations in numbers 30-34 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use.

[0831] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0832] Example 1-111: Considering k in =111, the table below shows the parameter combinations of a, b, c, d, and e above, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0833] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0834] In some specific applications, the PCS performance corresponding to the parameter combinations in numbers 20-26 is better and the complexity is lower, so one set of parameter combinations is selected for use.

[0835] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0836] Example 1-112: Considering kin =112. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0837] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0838] In some specific applications, considering that the parameter combinations in numbers 20-28 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use.

[0839] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0840] Example 1-113: Considering k in =113. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0841] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0842] In some specific applications, the PCS performance corresponding to the parameter combinations in numbers 15-20 is better and the complexity is lower, so one set of parameter combinations is selected for use.

[0843] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0844] Example 1-115: Considering k in =115. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0845] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0846] In some specific applications, considering that the parameter combinations in numbers 12-17 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use.

[0847] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0848] Example 1-116: Considering k in =116. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0849] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0850] In some specific applications, considering that the parameter combinations in numbers 13-18 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use.

[0851] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0852] Example 1-117: Considering k in =117. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0853] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0854] In some specific applications, considering that the parameter combinations in numbers 10-13 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use.

[0855] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0856] Example 1-118: Considering k in =118. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0857] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0858] In some specific applications, considering that the parameter combinations in numbers 10-14 correspond to better PCS performance and lower complexity, one set of parameter combinations is selected for use.

[0859] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0860] Example 1-119: Considering k in =119. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0861] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P HThe greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0862] In some specific applications, the PCS performance corresponding to the parameter combinations in numbers 8-10 is better and the complexity is lower, so one set of parameter combinations is selected for use.

[0863] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0864] Example 1-120: Considering k in =120. The table below shows the parameter combinations of a, b, c, d, and e, and the corresponding low-amplitude probabilities P. L High amplitude probability P H PCS output bit average power, overall complexity M TR .

[0865] It should be understood that in the table above, the parameter combination {a, b, c, d, e} corresponds to P. L and P H The greater the difference in probability and the lower the signal power, the better the PCS effect obtained from the data processing. It should be understood that the table above also gives the overall complexity M of the transceiver for each parameter combination {a, b, c, d, e}. TR As can be seen, better PCS performance does not necessarily mean lower complexity. Therefore, it is necessary to choose an effective trade-off between PCS performance (also known as performance) and complexity based on the specific application scenario.

[0866] In some specific applications, the PCS performance corresponding to the parameter combinations in numbers 8-10 is better and the complexity is lower, so one set of parameter combinations is selected for use.

[0867] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0868] Example 1 - Summary: This implementation is based on the above multiple examples, and addresses different k...in The values ​​were selected, and the parameter combinations that yielded the best PCS performance were obtained, as shown in the table below for the input bit k. in The above combinations of parameters a, b, c, d, and e, and the corresponding low-amplitude probability P. L High amplitude probability P H PCS output bit average power (power), overall complexity M TR .

[0869] It should be understood that for k in When ≤70, the optimal parameter combination is e=0; for 71≤k in When ≤76, the optimal parameter combination is e=1; for 77≤k in When ≤94, the optimal parameter combination is e=2; for 95≤k in In this case, the optimal parameter combination is e = 3.

[0870] The method provided in this embodiment divides the input bits into multiple sets for multi-step processing. Each process can be implemented using a simple LUT, resulting in low overall complexity, ease of hardware implementation, and low average power of the corresponding PCS output bits, leading to good PCS implementation performance.

[0871] This application also describes a data processing apparatus, which is applied at a sending end and includes: a processing module for executing the data processing method described in the above embodiments, for processing the acquired k in The data is processed by each bit to obtain an output bit sequence of n bits, for example, n is 128; the specific implementation method has been described in the previous embodiments and will not be repeated here.

[0872] The data processing device also includes an encoding module, an interleaving module, and a mapping module. The encoding module performs FEC encoding, the interleaving module performs interleaving operations, and the mapping module performs symbol mapping, etc. These functions may also be implemented using a single processor.

[0873] The processing device can also be applied to the receiving end, which can be understood as performing the inverse processing of the data processing method of the sending end; this application will not elaborate further. It should be understood that the data transmission device of this embodiment can also be implemented in other ways. For example, the unit division in the above device is merely a logical functional division; in actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0874] Figure 5 is a schematic diagram of an optical module in an embodiment of this application. As shown in Figure 5, the optical module includes a processor 501 and an interface 502. The interface 502 can be a transceiver or an input / output interface, and is used to receive signals from other devices and transmit them to the processor 501 or to send signals from the processor 501 to other devices. Optionally, the optical module may also include a memory 503, wherein the memory 503 is used to store program instructions and data.

[0875] In one possible scenario, the optical module is applied at the transmitting end, and the processor 501 is used to execute the PCS processing method described in the above embodiments for processing the acquired k. in The processor processes each bit to obtain an n-bit output bit sequence, for example, n = 128. Optionally, it is also used to perform FEC coding, interleaving, symbol mapping, and other functions. Specific implementation methods have been described in previous embodiments and will not be repeated here. As an example, the processor 501 executes the operations described in the above embodiments, then performs symbol mapping and framing operations to obtain a data frame, and sends the data frame through interface 502. In this example, interface 502 can specifically refer to an electrical interface. As another example, the processor 501 executes the operations described in the above embodiments, then performs symbol mapping and framing operations to obtain a data frame. The modulator in the optical module performs electro-optic conversion and other signal processing based on the data frame to obtain an optical signal, and then sends the optical signal through interface 502. In this example, interface 502 can specifically refer to an optical interface. In one possible scenario, the optical module is applied at the receiving end, which can be understood as performing the inverse processing of the data processing method performed by the optical module located at the transmitting end. This will not be repeated here.

[0876] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0877] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0878] Figure 6 is a schematic diagram of a communication device according to an embodiment of this application. As shown in Figure 6, the communication device includes a host-side device 601 and an optical module 602. This communication device can function as a transmitting device. In this case, the host-side device 601 sends an electrical signal to the optical module 602, which converts the electrical signal into an optical signal and transmits it through a channel. For example, the host-side device 601 can be a switch, router, or server. This communication device can be a communication device including the host-side device 601 and the optical module 602. This communication device can also function as a receiving device. In this case, the optical module 602 converts the received optical signal into an electrical signal and sends the electrical signal to the host-side device 601. For example, the host-side device 601 can be a switch, router, or server. This communication device can be a communication device including the host-side device 601 and the optical module 602.

[0879] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. In one possible scenario, the OTN device is used at the transmitting end, and the processor is used to perform the data processing operations described in the above embodiments. In another possible scenario, the OTN device is used at the receiving end, and the processor is used to perform the inverse operation of the data processing described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices besides the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices besides the line-side equipment.

[0880] This application also provides a chip. This chip integrates circuitry for implementing the functions of the processor 501 described above, and may also include one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via an interface. This chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the processing and transmission device in the foregoing embodiments based on program code stored in the memory.

[0881] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0882] This application also provides a computer-readable storage medium including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0883] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0884] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0885] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0886] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0887] When implemented in hardware, the data transmission method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0888] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0889] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

A data processing method, characterized in that, include: For the obtained k in Data is processed using k bits to obtain n output bits, where k in The bits include a set of 1 containing 'a' bits, two sets of 2 each containing 'b' bits, four sets of 4 each containing 'c' bits, eight sets of 8 each containing 'd' bits, and sixteen sets of 16 each containing 'e' bits. 0 <k in <n; The first set undergoes a first process to obtain the sixth set; The two sets of the second are respectively processed with half a bit of the set of the sixth to obtain two sets of the seventh; The four sets of the third are each processed with half a bit of each set of the seventh to obtain four sets of the eighth. The eight fourth sets are each processed with half a bit of each eighth set to obtain eight ninth sets; The 16 fifth sets are each processed with half a bit of each ninth set to obtain a total of 16 tenth sets, which constitute the n output bits, where k in The values ​​of a, b, c, d, and e are shown in any of the following rows: A data processing method, characterized in that, include: For the obtained k in Data is processed using k bits to obtain n output bits, where k in The bits include a set of 1 containing 'a' bits, two sets of 2 each containing 'b' bits, a set of 4 each containing 'c' bits, and a set of 8 each containing 'd' bits. 0 <k in <n; The first set undergoes a first process to obtain the sixth set; The two sets of the second are respectively processed with half a bit of the set of the sixth to obtain two sets of the seventh; The four sets of the third are each processed with half a bit of each set of the seventh to obtain four sets of the eighth. The eight fourth sets are each processed with half a bit of each eighth set to obtain eight ninth sets; Half of the bits in each of the 9th sets are processed a fifth time to obtain a total of 16 10th sets, which constitute the n output bits, where k in The values ​​of a, b, c, and d are shown in any of the following rows: The method according to claim 2, characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively, with a low probability of 0.8762 and a high probability of 0.1238. The method according to claim 2 or 3, characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively. In the output bits of the data processing, the probability of a bit being 1 is 0.8762, and the probability of a bit being 0 is 0.1238. The method according to any one of claims 1-4, characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively, and the average power of the output bits of the data processing is 2.9892 dB. The method according to any one of claims 1-5 is characterized in that, The first process, the second process, the third process, the fourth process, and the fifth process are implemented using lookup tables. The method according to any one of claims 1-6, characterized in that, The sixth set includes 10 bits, the seventh set includes 10 bits, the eighth set includes 10 bits, the ninth set includes 10 bits, and the tenth set includes 8 bits. The method according to any one of claims 1-7 is characterized in that, n is 128. The method according to claim 8, characterized in that, The method further includes: The 16 groups of n output bits and the acquired 1504 bits are subjected to FEC encoding to obtain 4096 encoded bits. The method according to claim 9, characterized in that, The method further includes: The encoded bits are then symbol-mapped to obtain a symbol sequence. The method according to any one of claims 1-10, characterized in that, The data processing is a probabilistic constellation shaping (PCS) process, in which the probability of a bit being 0 among the n output bits is not equal to the probability of a bit being 1. A data processing method, characterized in that, The method includes: Receive n output bits, where the n output bits are a subset of k. in The k is obtained by processing data from bits. in The bits include a set of 1 containing 'a' bits, two sets of 2 each containing 'b' bits, four sets of 4 each containing 'c' bits, eight sets of 8 each containing 'd' bits, and sixteen sets of 16 each containing 'e' bits. 0 <kin<n; The first set undergoes a first process to obtain the sixth set; The two sets of the second are respectively processed with half a bit of the set of the sixth to obtain two sets of the seventh; The four sets of the third are each processed with half a bit of each set of the seventh to obtain four sets of the eighth. The eight fourth sets are each processed with half a bit of each eighth set to obtain eight ninth sets; The 16 fifth sets are each processed with half a bit of each ninth set to obtain a total of 16 tenth sets, which constitute the n output bits, where k in The values ​​of a, b, c, d, and e are shown in any of the following rows: A data processing method, characterized in that, The method includes: Receive n output bits, where the n output bits are a subset of k. in The data is obtained by processing k bits, where k is... in The bits include a set of 1 containing 'a' bits, two sets of 2 each containing 'b' bits, a set of 4 each containing 'c' bits, and a set of 8 each containing 'd' bits. 0 <kin<n; The first set undergoes a first process to obtain the sixth set; The two sets of the second are respectively processed with half a bit of the set of the sixth to obtain two sets of the seventh; The four sets of the third are each processed with half a bit of each set of the seventh to obtain four sets of the eighth. The eight fourth sets are each processed with half a bit of each eighth set to obtain eight ninth sets; Half of the bits in each of the 9th sets are processed a fifth time to obtain a total of 16 10th sets, which constitute the n output bits, where k in The values ​​of a, b, c, and d are shown in any of the following rows: The method according to claim 13, characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively, with a low probability of 0.8762 and a high probability of 0.1238. The method according to claim 13 or 14 is characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively. In the output bits of the data processing, the probability of a bit being 1 is 0.8762, and the probability of a bit being 0 is 0.1238. The method according to any one of claims 13-15 is characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively, and the average power of the output bits of the data processing is 2.9892 dB. The method according to any one of claims 12-16 is characterized in that, The first process, the second process, the third process, the fourth process, and the fifth process are implemented using lookup tables. The method according to any one of claims 12-17 is characterized in that, The sixth set includes 10 bits, the seventh set includes 10 bits, the eighth set includes 10 bits, the ninth set includes 10 bits, and the tenth set includes 8 bits. The method according to any one of claims 12-18 is characterized in that, n is 128. The method according to any one of claims 12-19 is characterized in that, The data processing is a probabilistic constellation shaping (PCS) process, in which the probability of a bit being 0 among the n output bits is not equal to the probability of a bit being 1. A data processing device, characterized in that, include: The processing module is used to process the acquired k in Data is processed using k bits to obtain n output bits, where k in The bits include a set of 1 containing 'a' bits, two sets of 2 each containing 'b' bits, four sets of 4 each containing 'c' bits, eight sets of 8 each containing 'd' bits, and sixteen sets of 16 each containing 'e' bits. 0 <kin<n; The first set undergoes a first process to obtain the sixth set; The two sets of the second are respectively processed with half a bit of the set of the sixth to obtain two sets of the seventh; The four sets of the third are each processed with half a bit of each set of the seventh to obtain four sets of the eighth. The eight fourth sets are each processed with half a bit of each eighth set to obtain eight ninth sets; The 16 fifth sets are each processed with half a bit of each ninth set to obtain a total of 16 tenth sets, which constitute the n output bits, where k in The values ​​of a, b, c, d, and e are shown in any of the following rows: A data processing device, characterized in that, include: The processing module is used to process the acquired k in Data is processed using k bits to obtain n output bits, where k in The bits include a set of 1 containing 'a' bits, two sets of 2 each containing 'b' bits, a set of 4 each containing 'c' bits, and a set of 8 each containing 'd' bits. 0 <kin<n; The first set undergoes a first process to obtain the sixth set; The two sets of the second are respectively processed with half a bit of the set of the sixth to obtain two sets of the seventh; The four sets of the third are each processed with half a bit of each set of the seventh to obtain four sets of the eighth. The eight fourth sets are each processed with half a bit of each eighth set to obtain eight ninth sets; Half of the bits in each of the 9th sets are processed a fifth time to obtain a total of 16 10th sets, which constitute the n output bits, where k in The values ​​of a, b, c, and d are shown in any of the following rows: The apparatus according to claim 22 is characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively, with a low probability of 0.8762 and a high probability of 0.1238. The apparatus according to claim 22 or 23 is characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively. In the output bits of the data processing, the probability of a bit being 1 is 0.8762, and the probability of a bit being 0 is 0.1238. The apparatus according to any one of claims 22-24 is characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively, and the average power of the output bits of the data processing is 2.9892 dB. The apparatus according to any one of claims 21-25 is characterized in that, The first process, the second process, the third process, the fourth process, and the fifth process are implemented using lookup tables. The apparatus according to any one of claims 21-26 is characterized in that, The sixth set includes 10 bits, the seventh set includes 10 bits, the eighth set includes 10 bits, the ninth set includes 10 bits, and the tenth set includes 8 bits. The apparatus according to any one of claims 21-27 is characterized in that, n is 128. The apparatus according to claim 28 is characterized in that, The processing module is further configured to: The 16 groups of n output bits and the acquired 1504 bits are subjected to FEC encoding to obtain 4096 encoded bits. The apparatus according to claim 29 is characterized in that, The device also includes a mapping module. The mapping module is used to perform symbol mapping on the obtained encoded bits to obtain a symbol sequence. The apparatus according to any one of claims 21-30 is characterized in that, The data processing is a probabilistic constellation shaping (PCS) process, in which the probability of a bit being 0 among the n output bits is not equal to the probability of a bit being 1. A data processing device, characterized in that, include: The receiving module is used to receive n output bits, wherein the n output bits are a subset of k. in The k is obtained by processing data from bits. in The bits include a set of 1 containing 'a' bits, two sets of 2 each containing 'b' bits, four sets of 4 each containing 'c' bits, eight sets of 8 each containing 'd' bits, and sixteen sets of 16 each containing 'e' bits. 0 <kin<n; The first set undergoes a first process to obtain the sixth set; The two sets of the second are respectively processed with half a bit of the set of the sixth to obtain two sets of the seventh; The four sets of the third are each processed with half a bit of each set of the seventh to obtain four sets of the eighth. The eight fourth sets are each processed with half a bit of each eighth set to obtain eight ninth sets; The 16 fifth sets are each processed with half a bit of each ninth set to obtain a total of 16 tenth sets, which constitute the n output bits, where k in The values ​​of a, b, c, d, and e are shown in any of the following rows: A data processing device, characterized in that, include: The receiving module is used to receive n output bits, wherein the n output bits are a subset of k. in The data is obtained by processing k bits, where k is... in The bits include a set of 1 containing 'a' bits, two sets of 2 each containing 'b' bits, a set of 4 each containing 'c' bits, and a set of 8 each containing 'd' bits. 0 <kin<n; The first set undergoes a first process to obtain the sixth set; The two sets of the second are respectively processed with half a bit of the set of the sixth to obtain two sets of the seventh; The four sets of the third are each processed with half a bit of each set of the seventh to obtain four sets of the eighth. The eight fourth sets are each processed with half a bit of each eighth set to obtain eight ninth sets; Half of the bits in each of the 9th sets are processed a fifth time to obtain a total of 16 10th sets, which constitute the n output bits, where k in The values ​​of a, b, c, and d are shown in any of the following rows: The apparatus according to claim 33 is characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively, with a low probability of 0.8762 and a high probability of 0.1238. The apparatus according to claim 33 or 34 is characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively. In the output bits of the data processing, the probability of a bit being 1 is 0.8762, and the probability of a bit being 0 is 0.1238. The apparatus according to any one of claims 33-35 is characterized in that, k in The values ​​of a, b, c, and d are 62, 6, 4, 4, and 4, respectively, and the average power of the output bits of the data processing is 2.9892 dB. The apparatus according to any one of claims 32-36 is characterized in that, The first process, the second process, the third process, the fourth process, and the fifth process are implemented using lookup tables. The apparatus according to any one of claims 32-37 is characterized in that, The sixth set includes 10 bits, the seventh set includes 10 bits, the eighth set includes 10 bits, the ninth set includes 10 bits, and the tenth set includes 8 bits. The apparatus according to any one of claims 32-38 is characterized in that, n is 128. The apparatus according to any one of claims 32-39 is characterized in that, The data processing is a probabilistic constellation shaping (PCS) process, in which the probability of a bit being 0 among the n output bits is not equal to the probability of a bit being 1. A chip characterized in that, The chip is used to perform the method as described in any one of claims 1 to 20. An optical module, characterized in that, The optical module includes a processor and an interface, wherein the processor is used to perform the method as described in any one of claims 1 to 20 and to transmit and receive signals through the interface. A communication device, characterized in that, The communication device includes a host-side device and an optical module as described in claim 42, wherein the optical module is connected to the host-side device. A communication system, characterized in that, include: A first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is the communication device as described in claim 43, and the first communication device and the second communication device are connected.

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