Single-photon avalanche diode pixel array and method for manufacturing same

Abstract

The purpose of an embodiment of the present invention is to provide a single-photon avalanche diode pixel array comprising: a substrate including an avalanche amplification region; a first insulating layer disposed on the substrate and having a trench formed in a region corresponding to the avalanche amplification region; a short-wavelength absorption layer filling the inside of the trench; and a first metal oxide layer formed between the first insulating layer and the short-wavelength absorption layer inside the trench .

Description

Single-photon avalanche diode pixel array and method for manufacturing the same

[0001] The present invention relates to an image sensor, and more specifically, to an image sensor comprising a single-photon avalanche diode pixel array.

[0002] Time of Flight (TOF) technology calculates distance based on the law of the constancy of the speed of light by measuring the time between irradiating pulsed light from a light source placed within or near a sensor and receiving the reflected light. To measure TOF precisely, a highly sensitive photoelectric conversion device is required because a reaction must occur as soon as the light reaches the light-receiving element. To this end, research on Single Photon Avalanche Diodes (SPADs), which can be fabricated using CMOS process technology, is actively underway.

[0003] A single-photon avalanche diode is a structure that repeatedly operates and recovers (quenching) in Geiger mode by applying a reverse voltage to the photodiode that is much higher than the breakdown voltage of the single-photon avalanche diode, also referred to as the avalanche voltage. Since a reverse voltage exceeding the breakdown voltage is applied to the single-photon avalanche diode, an electron avalanche occurs due to carriers generated by photoelectric conversion, and the single-photon avalanche diode enters a breakdown state. As a result, carrier amplification by photoelectric conversion occurs, and the sensitivity of the imaging device can be improved.

[0004] Germanium (Ge) provides enhanced absorption of short wavelength infrared (SWIR) compared to silicon because it has a smaller band gap. However, when implementing single-photon avalanche diodes based on silicon-germanium (Si-Ge), dark count rate (DCR) characteristics may deteriorate due to plasma damage during the dry etching process. Dark count rate (DCR) refers to the rate at which an electrical signal (count) is generated in the absence of light or in complete darkness.

[0005] Recently, research has been continuously conducted to improve the deterioration of Dark Count Rate (DCR) characteristics caused by plasma damage.

[0006] One embodiment of the present invention provides a single-photon avalanche diode pixel array with improved DCR characteristics.

[0007] One embodiment of the present invention provides a single-photon avalanche diode pixel array in which crosstalk phenomena are suppressed or prevented.

[0008] One embodiment of the present invention provides a single-photon avalanche diode pixel array having high photon detection efficiency (PDE).

[0009] One embodiment of the present invention for achieving the aforementioned technical problem aims to provide a single-photon avalanche diode pixel array comprising: a substrate including an avalanche amplification region; a first insulating layer disposed on the substrate and having a trench formed in a region corresponding to the avalanche amplification region; a short wavelength absorption layer filled inside the trench; and a first metal oxide layer formed between the first insulating layer and the short wavelength absorption layer inside the trench.

[0010] Another embodiment of the present invention provides a method for manufacturing a single-photon avalanche diode pixel array, comprising the steps of: forming a substrate including an avalanche amplification region; forming a first insulating material layer on the substrate; etching a portion of the first insulating material layer by a dry etching process to form a first insulating layer in which a trench is formed; forming a metal oxide material layer inside the trench and on the first insulating layer; forming a first photoresist pattern inside the trench; etching the metal oxide material layer that does not overlap with the first photoresist pattern; forming a second photoresist pattern on the first insulating layer so as not to be placed inside the trench; etching the metal oxide material layer that does not overlap with the second photoresist pattern to form a first metal oxide layer; and epitaxially growing a short wavelength absorption layer inside the trench.

[0011] A single-photon avalanche diode pixel array according to one embodiment of the present invention can improve DCR characteristics by placing a first metal oxide layer between a first insulating layer and a short-wavelength absorption layer inside a trench.

[0012] A single-photon avalanche diode pixel array according to one embodiment of the present invention can suppress or prevent crosstalk phenomena by including a metal grid.

[0013] A single-photon avalanche diode pixel array according to one embodiment of the present invention may have high photon detection efficiency (PDE) and improved photon detection probability (PDP) by including plasmonic patterns.

[0014] In addition to the effects mentioned above, other features and advantages of the present invention are described below, or will be clearly understood by those skilled in the art from such description and explanation.

[0015] FIG. 1 is a plan view of a single-photon avalanche diode pixel array according to one embodiment of the present invention.

[0016] Figure 2 is a cross-sectional view taken along I-I' of Figure 1.

[0017] FIG. 3 is a plan view of a single-photon avalanche diode pixel array according to another embodiment of the present invention.

[0018] Figure 4 is a cross-sectional view taken along II-II' of Figure 3.

[0019] FIG. 5 is a plan view of a single-photon avalanche diode pixel array according to another embodiment of the present invention.

[0020] Figure 6 is a cross-sectional view taken along III-III' of Figure 5.

[0021] FIG. 7 is a plan view of a single-photon avalanche diode pixel array according to another embodiment of the present invention.

[0022] Fig. 8a is a cross-sectional view taken along IV-IV' of Fig. 7.

[0023] FIG. 8b is a cross-sectional view of a single-photon avalanche diode pixel array according to another embodiment of the present invention.

[0024] FIG. 9 is a block diagram of an image sensor having a single-photon avalanche diode pixel array as shown in FIG. 1 and FIG. 2.

[0025] FIGS. 10a to 10m are process diagrams showing the manufacturing process of a single-photon avalanche diode pixel array according to one embodiment of the present invention.

[0026] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to make the disclosure of the present invention complete and to inform those skilled in the art of the scope of the invention.

[0027] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Throughout the specification, identical components may be referred to by the same reference numerals. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted.

[0028] Where terms such as 'comprising,' 'having,' 'consisting of,' etc. are used in this specification, other parts may be added unless the expression 'only' is used. Where a component is expressed in the singular, it includes the plural unless specifically stated otherwise.

[0029] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0030] For example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless expressions such as 'immediately' or 'directly' are used.

[0031] Spatially relative terms such as "below" or "beneath," "lower," "above," and "upper" may be used to facilitate the description of the relationship between one element or component and another, as illustrated in the drawings. Spatially relative terms should be understood as terms that include different orientations of the element during use or operation, in addition to the orientations illustrated in the drawings. For example, if an element illustrated in the drawings is flipped, an element described as "below" or "beneath" of another element may be placed "above" of that other element. Therefore, the exemplary term "below" may include both the lower and upper directions. Similarly, the exemplary terms "above" or "upper" may include both the upper and lower directions.

[0032] In the case of an explanation of a temporal relationship, for example, when the temporal sequence is explained using expressions such as 'after', 'following', 'next', or 'before', it may include cases where the sequence is not continuous unless expressions such as 'immediately' or 'directly' are used.

[0033] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0034] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item and the third item” may mean not only the first item, the second item or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item and the third item.

[0035] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0036] In assigning reference numerals to the components of each drawing describing the embodiments of the present invention, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings.

[0037] FIG. 1 is a plan view of a single-photon avalanche diode pixel array (100) according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along I-I' of FIG. 1.

[0038] According to one embodiment of the present invention, a single-photon avalanche diode pixel array (100) may include a substrate (101), a first insulating layer (161), a short-wavelength absorption layer (150), and a first metal oxide layer (155a). The substrate (101), the first insulating layer (161), the short-wavelength absorption layer (150), and the first metal oxide layer (155a) are described in detail below.

[0039] According to one embodiment of the present invention, the upper surface (101a) of the substrate (101) may be a surface into which light is incident from the outside, and the lower surface (101b) may be a surface opposite to the surface into which light is incident from the outside.

[0040] According to one embodiment of the present invention, a substrate (101) comprises a first region (110) doped with a first conductive type dopant, a deep well region (120) doped with a second conductive type dopant opposite to the first conductive type, a first well region (130) formed by doping with a first conductive type dopant, a second well region (140) formed by doping with a second conductive type dopant, and a first high-concentration doping region (131) formed by high-concentration doping with a second conductive type dopant. The substrate (101) may comprise silicon (Si).

[0041] According to one embodiment of the present invention, the first conductive type dopant may be a P-type dopant and the second conductive type dopant may be an N-type dopant. However, as another example, the first conductive type dopant may be an N-type dopant and the second conductive type dopant may be a P-type dopant.

[0042] When the first conductive type dopant is a P-type dopant and the second conductive type dopant is an N-type dopant, the P-type dopant may include at least one of boron, aluminum, gallium, and indium, and the N-type dopant may include at least one of phosphorus, arsenic, and antimony.

[0043] According to one embodiment of the present invention, the first region (110) is a region in which a first conductive type dopant or a second conductive type dopant is doped at a low concentration and can be formed by epitaxial growth.

[0044] According to one embodiment of the present invention, a deep well region (120) may be disposed on a first region (110). The deep well region (120) according to the present invention may be formed by doping the upper surface (101a) of a substrate (101) with a dopant of a second conductivity type opposite to the first conductivity type. The deep well region (120) may be formed over the entire upper surface of the first region (110). The deep well region (120) according to the present invention may have retrograde doping that can be formed by ion implantation. Retrograde doping according to the present invention means that the dopant concentration increases in the depth direction on the upper surface (120a) of the deep well region (120).

[0045] According to one embodiment of the present invention, the upper surface (120a) of the deep well region (120) may correspond to the upper surface (101a) of the substrate (101).

[0046] According to one embodiment of the present invention, the substrate (101) may include an avalanche amplification region (145). The avalanche amplification region (145) is formed on the side of the PN junction region with the first well region (130), which is formed by doping with a dopant of a first conductive type opposite to the second conductive type within the deep well region (120). The avalanche amplification region (145) may be formed at the boundary between the deep well region (120) and the first well region (130).

[0047] According to the present invention, the first well region (130) can be formed by doping the upper surface (120a) of the deep well region (120) with a first conductive type dopant.

[0048] According to the present invention, the second well region (140) can be formed by doping the upper surface (120a) of the deep well region (120) with a dopant of a second conductive type opposite to the first conductive type.

[0049] The avalanche amplification region (145) is a region where the multiplication of electrons and holes occurs. In the avalanche amplification region (145), a very strong electric field is formed in the reverse bias state, so that electrons can move quickly. As a result, an electron-hole pair generated by a single photon generates additional electrons, and the generated electrons are accelerated by this electric field and collide with other atoms to generate additional electron-hole pairs, causing a chain reaction in which a very high current is generated.

[0050] Due to this avalanche amplification region (145), the single-photon avalanche diode is capable of detecting a single photon, and thus can detect extremely low light signals, and can be usefully applied for sensing, especially in low light environments.

[0051] According to one embodiment of the present invention, the first well region (130) and the second well region (140) may be arranged in a row. Specifically, the first well region (130) and the second well region (140) may be arranged in a horizontal relationship rather than a vertical relationship.

[0052] According to one embodiment of the present invention, a first high-concentration doping region (131) may be formed by high-concentration doping with a second conductive type dopant on the upper surface of a second well region (140). The first high-concentration doping region (131) may be formed with a constant thickness not greater than the thickness of the second well region (140).

[0053] Referring to FIGS. 1 and 2, the first high-concentration doping region (131) in a planar shape may be a closed-loop shape surrounding the first well region (130), and the second well region (140) may be a closed-loop shape surrounding the first well region (130).

[0054] According to one embodiment of the present invention, a separation structure (135) for electrically isolating a first well region (130) and a second well region (140) may be formed.

[0055] According to one embodiment of the present invention, the separation structure (135) may be formed as a shallow trench isolation (STI) formed by filling an insulating film within a deep trench formed by penetrating the second well region (140) and the first high-concentration doping region (131) from the upper surface (120a) of the deep well region (120) toward the lower surface (120b). According to one embodiment of the present invention, the separation structure (135) may extend from the upper surface (120a) of the deep well region (120) toward the lower surface (120b) of the deep well region (120). At this time, the separation structure (135) may not be positioned below the lower surface (120b) of the second well region (140). Additionally, the thickness of the separation structure (135) may not be greater than the thickness of the second well region (140).

[0056] According to one embodiment of the present invention, the separation structure (135) may include a first separation structure (135a) and a second separation structure (135b).

[0057] Referring to FIGS. 1 and 2, a first separation structure (135a) may be positioned on one side of the second well region (140) and between the first well region (130) and the second well region (140). A second separation structure (135b) may be positioned on the other side of the second well region (140). The second well region (140) may be positioned between the first separation structure (135a) and the second separation structure (135b).

[0058] Referring to FIGS. 1 and 2, the first separation structure (135a) may be a closed-loop shape surrounding the first well region (130) in a planar view, and the second separation structure (135b) may be a closed-loop shape surrounding the first well region (130) and the second well region (140). Additionally, the second well region (140) may be a closed-loop shape surrounding the first separation structure (135a).

[0059] According to one embodiment of the present invention, a first insulating layer (161) and a short wavelength absorption layer (150) may be formed on a deep well region (120).

[0060] The first insulating layer (161) may include an oxide such as SiO2. A trench (T) may be formed in the first insulating layer (161). The trench (T) may be formed by etching through a dry etching process. A portion of the first well region (130) may be exposed by the trench (T). Additionally, the trench (T) may be formed in a region corresponding to the avalanche amplification region (145).

[0061] According to one embodiment of the present invention, a short wavelength absorption layer (150) doped with a first conductive type dopant may be formed on a deep well region (120). The short wavelength absorption layer (150) may be formed by filling inside a trench (T). Specifically, the short wavelength absorption layer (150) is formed by a damascene process. More specifically, the short wavelength absorption layer (150) may be formed by epitaxial growth. The short wavelength absorption layer (150) may contain germanium (Ge). By containing germanium, the short wavelength absorption layer (150) provides enhanced absorption for short wavelength infrared (SWIR).

[0062] According to one embodiment of the present invention, the short wavelength absorption layer (150) may be surrounded by a first insulating layer (161).

[0063] According to one embodiment of the present invention, a second high-concentration doping region (151) formed by high-concentration doping with a first conductive type dopant may be formed on the upper surface (150a) of the short-wavelength absorption layer (150). The second high-concentration doping region (151) may be formed with a constant thickness not greater than the thickness of the short-wavelength absorption layer (150).

[0064] According to one embodiment of the present invention, the second well region (140) may be a closed-loop shape surrounding the second high-concentration doping region (151) in a planar manner.

[0065] Generally, when the first insulating layer (161) and the short-wavelength absorption layer (150) are formed by a damascene process, a trench (T) may be formed in the first insulating layer (161) by dry etching. The dry etching process uses high-energy plasma, at which time plasma particles may damage the interface between the first insulating layer (161) and the short-wavelength absorption layer (150). Due to such damage, the Dark Count Rate (DCR) characteristics of the single-photon avalanche diode pixel array (100) may be degraded. The Dark Count Rate (DCR) refers to the rate at which an electrical signal (count) is generated in the absence of light or in a completely dark state.

[0066] Accordingly, to suppress or prevent damage to the interface between the first insulating layer (161) and the short wavelength absorption layer (150), the single-photon avalanche diode pixel array (100) according to the present invention may further include a first metal oxide layer (155a).

[0067] According to one embodiment of the present invention, the first metal oxide layer (155a) may comprise at least one of hafnium oxide (HfO2), titanium oxide (TiO2), aluminum oxide (Al2O3), and tantalum oxide (TaO). However, the material of the first metal oxide layer (155a) is not limited thereto and may be varied in many ways.

[0068] The first metal oxide layer (155a) is formed between the first insulating layer (161) and the short-wavelength absorption layer (150), so that electrons remaining in the first insulating layer (161) can be removed by recombination in the first metal oxide layer (155a) through a dry etching process. As a result, surface defects of the first insulating layer (161) caused by high-energy plasma can be suppressed or prevented. Consequently, the single-photon avalanche diode pixel array (100) can have improved DCR characteristics.

[0069] More specifically, according to the present invention, a single-photon avalanche diode pixel array (100) can have improved DCR characteristics because a first metal oxide layer (155a) is formed on the side (SS) of the first insulating layer (161) and then a short wavelength absorption layer (150) is formed.

[0070] Referring to FIGS. 1 and 2, the first metal oxide layer (155a) may have a closed-loop shape surrounding the short-wavelength absorption layer (150) in a planar manner. Specifically, the short-wavelength absorption layer (150) may be disposed on the first well region (130) exposed by the first metal oxide layer (155a).

[0071] According to one embodiment of the present invention, the upper surface of the first insulating layer (161), the upper surface (150a) of the short wavelength absorption layer (150), and the upper surface of the first metal oxide layer (155a) may form a single plane.

[0072] According to one embodiment of the present invention, a second insulating layer (162) may be formed on a first insulating layer (161). The second insulating layer (162) may be disposed over the entire upper surface of the first insulating layer (161). The second insulating layer (162) may include an oxide such as SiO2. The second insulating layer (162) may or may not be made of the same material as the first insulating layer (161).

[0073] According to one embodiment of the present invention, the first contact portion (170a) can penetrate the first insulating layer (161) and the second insulating layer (162), and the second contact portion (170b) can penetrate the second insulating layer (162).

[0074] According to one embodiment of the present invention, a first metal pad (180a) and a second metal pad (180b) may be formed on a second insulating layer (162). For example, the first metal pad (180a) and the second metal pad (180b) may be connected to a first high-concentration doping region (131) and a second high-concentration doping region (151) using a first contact portion (170a) and a second contact portion (170b), respectively. Referring to FIG. 2, the first metal pad (180a) is connected to the first high-concentration doping region (131) using the first contact portion (170a), and the second metal pad (180b) is connected to the second high-concentration doping region (151) using the second contact portion (170b).

[0075] According to one embodiment of the present invention, the first high-concentration doping region (131) may be the cathode region of a single-photon avalanche diode, and the second high-concentration doping region (151) may be the anode region of a single-photon avalanche diode. For example, the first metal pad (180a) may be the cathode region, and the second metal pad (180b) may be the anode region.

[0076] According to one embodiment of the present invention, one end of the second metal pad (180b) may be electrically connected to a driving circuit (not shown) for driving an image sensor. The driving circuit may be a quench circuit or a photodetector output circuit (ROIC: ReadOut Integrated Circuit). The quench circuit is used to cut off the avalanche effect and reset the single-photon avalanche diode pixel. The photodetector output circuit receives and transmits signal current.

[0077] FIG. 3 is a plan view of a single-photon avalanche diode pixel array (200) according to another embodiment of the present invention. FIG. 4 is a cross-sectional view taken along II-II' of FIG. 3.

[0078] The single-photon avalanche diode pixel array (200) shown in FIGS. 3 and 4 may further include a second metal oxide layer (155b) compared to the single-photon avalanche diode pixel array (100) shown in FIGS. 1 and 2.

[0079] According to one embodiment of the present invention, the second metal oxide layer (155b) may be disposed on the upper surface (161a) of the first insulating layer (161). Specifically, the second metal oxide layer (155b) may be disposed between the first insulating layer (161) and the second insulating layer (162). More specifically, the second metal oxide layer (155b) may be disposed over the entire upper surface of the first insulating layer (161).

[0080] According to one embodiment of the present invention, the first metal oxide layer (155a) and the second metal oxide layer (155b) may be formed integrally. Specifically, the first metal oxide layer (155a) and the second metal oxide layer (155b) may be made of the same material and formed by the same process.

[0081] A second metal oxide layer (155b) is placed on the upper surface (161a) of the first insulating layer (161) so that electrons remaining in the first insulating layer (161) can be removed by recombination in the second metal oxide layer (155b) through a dry etching process. As a result, surface defects of the first insulating layer (161) caused by high-energy plasma can be suppressed or prevented. Consequently, the single-photon avalanche diode pixel array (200) can have improved DCR characteristics.

[0082] FIG. 5 is a plan view of a single-photon avalanche diode pixel array (300) according to another embodiment of the present invention. FIG. 6 is a cross-sectional view taken along III-III' of FIG. 5.

[0083] The single-photon avalanche diode pixel array (300) shown in FIGS. 5 and 6 may further include a pixel separation structure (125a), a metal grid (126), and a microlens (190) compared to the single-photon avalanche diode pixel array (100) shown in FIGS. 1 and 2.

[0084] According to one embodiment of the present invention, the pixel isolation structure (125a) is intended to isolate photoelectrons. Photoelectrons may refer to electrons additionally generated in the avalanche amplification region (145). The pixel isolation structure (125a) may be formed as a Deep Trench Isolation (DTI) structure formed by filling an insulating film within a deep trench formed by penetrating from the upper surface (120a) of the deep well region (120) toward the lower surface (101b) of the substrate (101). According to one embodiment of the present invention, the pixel isolation structure (125a) may extend from the upper surface (120a) of the deep well region (120) to the lower surface (101b) of the substrate (101). At this time, the thickness of the pixel isolation structure (125a) may be the same as the thickness of the substrate (101). The pixel isolation structure (125a) can electrically isolate the first well region (130) and the second well region (140).

[0085] According to one embodiment of the present invention, the pixel separation structure (125a) can prevent light incident from the outside from moving in a lateral direction.

[0086] According to one embodiment of the present invention, a metal grid (126) may be placed on a pixel separation structure (125a). Specifically, the metal grid (126) may overlap with the pixel separation structure (125a). More specifically, the metal grid (126) may have a greater width than the pixel separation structure (125a). However, the present invention is not limited thereto.

[0087] According to one embodiment of the present invention, the metal grid (126) may have a closed-loop shape surrounding the first well region (130) in a planar shape. Additionally, the second well region (140) may have a closed-loop shape surrounding the metal grid (126) in a planar shape.

[0088] According to one embodiment of the present invention, light incident from the outside that does not enter the microlens (190) is reflected by the metal grid (126), thereby preventing the light incident from the outside from moving in a lateral direction. As a result, an image sensor (600) with improved light efficiency can be provided by reducing cross talk between pixels (P).

[0089] According to one embodiment of the present invention, the metal grid (126) may include tungsten (W). By including tungsten (W) in the metal grid (126), it may have a high refractive index or reflectivity, thereby effectively preventing light incident from the outside from moving in a lateral direction. However, the material of the metal grid (126) is not limited thereto and may be varied to a metal having high reflectivity.

[0090] According to one embodiment of the present invention, a third insulating layer (163) may be formed on a second insulating layer (162). Specifically, the third insulating layer (163) may be disposed on a first metal pad (180a) and a second metal pad (180b). The third insulating layer (163) may include an oxide such as SiO2. The third insulating layer (163) may or may not be made of the same material as the first insulating layer (161) and the second insulating layer (162).

[0091] According to one embodiment of the present invention, a micro lens (190) may be formed on a first insulating layer (161). Specifically, the micro lens (190) may be disposed on a third insulating layer (163). The micro lens (190) collects light incident from the outside. The micro lens (190) may be disposed to correspond to each pixel (P). That is, one micro lens (190) may be disposed on one pixel (P). The upper surface of the micro lens (190) may have a curved surface.

[0092] According to the present invention, visible light incident through a microlens (190) can be absorbed in an avalanche amplification region (145). At this time, short wavelength infrared (SWIR) may not be absorbed in the avalanche amplification region (145). The unabsorbed short wavelength infrared can be absorbed in a short wavelength absorption layer (150).

[0093] FIG. 7 is a plan view of a single-photon avalanche diode pixel array (400) according to another embodiment of the present invention. FIG. 8a is a cross-sectional view taken along IV-IV' of FIG. 7. FIG. 8b is a cross-sectional view of a single-photon avalanche diode pixel array (500) according to another embodiment of the present invention. The cross-sectional view of FIG. 8b corresponds to the cross-sectional view of FIG. 8a.

[0094] The single-photon avalanche diode pixel array (400) shown in FIGS. 7 and 8a may further include a pixel separation structure (125a), a metal grid (126), and plasmonic patterns (195) compared to the single-photon avalanche diode pixel array (100) shown in FIGS. 1 and 2.

[0095] The pixel separation structure (125a) and metal grid (126) shown in FIGS. 7 and 8a correspond to the pixel separation structure (125a) and metal grid (126) shown in FIGS. 5 and 6, and redundant descriptions are omitted.

[0096] According to one embodiment of the present invention, a single-photon avalanche diode pixel array (400) may further include plasmonic patterns (195) disposed on a third insulating layer (163) and a fourth insulating layer (164).

[0097] Referring to FIGS. 7 and FIGS. 8a, the plasmonic patterns (195) may be arranged in a grid pattern along a certain direction. However, the arrangement of the plasmonic patterns (195) is not limited and can be determined as needed. The spacing of the plasmonic patterns (195) may be several nanometers (nm) to several micrometers (μm). The plasmonic patterns (195) may be ultrathin metal films. The thickness of the plasmonic patterns (195) may be determined as needed. The plasmonic patterns (195) may include a material having a high free charge density to excite plasmons. For example, the plasmonic patterns (195) may include aluminum (Al) or titanium (Ti). The plasmonic patterns (195) may be formed using an atomic layer deposition (ALD) process.

[0098] The plasmonic patterns (195) can form a Schottky junction with the third insulating layer (163). Accordingly, a Schottky barrier can be formed between the plasmonic patterns (195) and the third insulating layer (163). When light is irradiated onto the plasmonic patterns (195), electrons or holes within the plasmonic patterns (195) may become excited. Among the excited charges, those with energy greater than the Schottky barrier may be hot electrons or hot holes. Hot electrons or hot holes may move beyond the Schottky barrier to the third insulating layer (163).

[0099] In order to form a large number of hot electrons or hot holes, it is required that the plasmonic patterns (195) have a high absorption rate. According to the present invention, the absorption rate can be increased by generating plasmons on the surfaces of the plasmonic patterns (195). For example, when short-wavelength infrared light is incident on the plasmonic patterns (195), plasmons, which are collective vibrations of charges (electrons or holes), can be generated on the surfaces of the plasmonic patterns (195) that are in contact with the third insulating layer (163). Some of the vibrating charges can become hot charges (hot electrons or hot holes) having energy greater than that of the Schottky barrier. The hot charges can move beyond the Schottky barrier to the third insulating layer (163). Specifically, the hot charges can move from the plasmonic patterns (195) to the third insulating layer (163). Hot charges injected into the third insulating layer (163) beyond the Schottky barrier can generate a large amount of charges in the avalanche amplification region (145).

[0100] The single-photon avalanche diode pixel array (500) illustrated in FIG. 8b can be formed such that, compared to the single-photon avalanche diode pixel array (400) illustrated in FIG. 8a, the pixel separation structure (125b) penetrates from the upper surface (161a) of the first insulating layer (161) toward the lower surface (101b) of the substrate (101). At this time, the metal grid (126) can be formed on the upper surface (161a) of the first insulating layer (161).

[0101] FIG. 9 is a block diagram of an image sensor having a single-photon avalanche diode pixel array (100) as illustrated in FIG. 1 and FIG. 2. As illustrated in FIG. 9, an image sensor (600) including a single-photon avalanche diode pixel array (100) according to one embodiment of the present invention emits a light signal to an object and converts the light signal reflected from the object into an electrical signal and outputs it to a processor (610) of an electronic device (not shown) to which the image sensor (600) is applied.

[0102] At this time, as described above, the electronic device may include, in addition to automotive LiDAR sensors, tablet PCs, or portable terminals, cameras, wearable devices, Internet of Things (IoT) devices, home appliances, robots, robot vacuum cleaners, portable Multimedia Players (PMPs), navigation systems, drones, Advanced Driver Assistance Systems (ADAS), etc. Additionally, the electronic device may be an electronic device provided as a component in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, etc.

[0103] As illustrated in FIG. 9, the image sensor (600) includes a single-photon avalanche diode pixel array (100), a row driver (630), a timing generator (640), an analog processing circuit (650), an analog-to-digital converter (660), and an output buffer (670).

[0104] A single-photon avalanche diode pixel array (100) includes a plurality of pixels (P). The plurality of pixels (P) may be arranged in two dimensions. For example, the plurality of pixels (P) may be arranged in a matrix form consisting of M (where M is an integer greater than or equal to 2) rows and N (where N is an integer greater than or equal to 2) columns. Each pixel (P) included in the single-photon avalanche diode pixel array (100) detects an optical signal using a single-photon avalanche diode and converts it into an electrical signal, which is a pixel signal.

[0105] A detailed description of the single-photon avalanche diode pixel array (100) will be omitted as it has already been described in the description section of Figures 1 and 2.

[0106] Each pixel (P) can be driven by control signals received from the row driver (630). The signal converted by each pixel (P) and the reset signal corresponding to the reset component are provided to the analog processing circuit (650).

[0107] The row driver (630) drives each pixel (P) included in the single-photon avalanche diode pixel array (100) based on the control of the timing generator (640). In one embodiment, the row driver (630) may control all pixels (P) of the single-photon avalanche diode pixel array (100) simultaneously or control unit pixels (P) of the single-photon avalanche diode pixel array (100) in row units. To this end, the row driver (630) may transmit control signals to the pixels (P).

[0108] In one embodiment, the row driver (630) can transmit a control signal to each pixel (P) based on the control of the timing generator (640).

[0109] The timing generator (640) can control the single-photon avalanche diode pixel array (100) through the low driver (630) and output a control signal that controls the analog processing circuit (650), the analog-to-digital converter (660), and the output buffer (670).

[0110] The analog processing circuit (650) can sample and hold the output signal provided from the pixel (P) according to the Correlated Double Sampling (CDS) method, and can double-sample the level of a specific noise, such as the reset level and the signal level.

[0111] The analog processing circuit (650) can generate a comparison result signal corresponding to a reset level and a comparison result signal corresponding to a signal level. Here, the method of reading out the signal level after reading out the reset level is referred to as a complete CDS method, and the method of reading out the reset level after reading out the signal level can be referred to as an incomplete CDS method or a Delta Reset Sampling (DRS) method.

[0112] The analog-to-digital converter (660) can convert an output signal output from the analog processing circuit (650) into a digital signal and provide it to the output buffer (670). Although FIG. 5 shows the analog processing circuit (650) and the analog-to-digital converter (660) as independent components, in other embodiments, the analog-to-digital converter (660) may be included in or integrated with the analog processing circuit (650).

[0113] The output buffer (670) can latch the digital signal transmitted from the analog-to-digital converter (660) and output the latched signal sequentially.

[0114] The processor (610) of the electronic device can process the digital signal output from the output buffer (670) and output it to an external device or store it in a storage device such as memory.

[0115] FIGS. 10a to 10m are process diagrams showing the manufacturing process of a single-photon avalanche diode pixel array (100) according to one embodiment of the present invention.

[0116] The cross-sectional view of the single-photon avalanche diode pixel array (100) shown in FIGS. 10a to 10m corresponds to the cross-sectional view of the single-photon avalanche diode pixel array (100) shown in FIG. 2.

[0117] Description of configurations that overlap with the configurations shown in FIGS. 1 and FIGS. 2 is omitted.

[0118] Referring to FIG. 10a, a deep well region (120) doped with a second conductive type dopant opposite to the first conductive type may be disposed on a first region (110) doped with a first conductive type dopant. The first region (110) may be formed by epitaxial growth. The deep well region (120) may be formed by doping the upper surface (101a) of the substrate (101) with a second conductive type dopant opposite to the first conductive type.

[0119] Referring to FIG. 10b, a first well region (130) and a second well region (140) can be formed by doping the upper surface (120a) of a deep well region (120) with a second conductive type dopant. The first well region (130) and the second well region (140) can be formed using ion implant technology. The PN junction region side with the first well region (130), which is formed by doping with a first conductive type dopant opposite to the second conductive type within the deep well region (120), becomes an avalanche amplification region (145) (see FIG. 10m).

[0120] Referring to FIG. 10c, a first high-concentration doping region (131) can be formed by high-concentration doping of a second conductive type dopant on the upper surface of the second well region (140).

[0121] Referring to FIG. 10d, a separation structure (135) can be formed by etching a portion of the second well region (140) and the first high-concentration doping region (131). The separation structure (135) may include a first separation structure (135a) and a second separation structure (135b). Afterward, a first insulating material layer (161m) can be formed on the deep well region (120). The separation structure (135) may be formed as a shallow trench isolation structure (STI) formed by filling an insulating film within a deep trench formed by penetrating the second well region (140) and the first high-concentration doping region (131) in a direction from the upper surface (120a) of the deep well region (120) toward the lower surface (120b).

[0122] Referring to FIG. 10e, a first insulating layer (161) with a trench (T) formed can be formed by etching a portion of the first insulating material layer (161m) using a dry etching process. Through this dry etching process, the first insulating layer (161) can expose a first well region (130). At this time, the width of the trench (T) may be smaller than the width of the first well region (130).

[0123] Referring to FIG. 10f, a metal oxide material layer (155m) can be formed on the first insulating layer (161) and the exposed first well region (130). The metal oxide material layer (155m) can be formed throughout the interior of the trench (T) and the upper surface (161a) of the first insulating layer (161), and can be disposed on the side (SS) of the first insulating layer (161). The metal oxide material layer (155m) may comprise at least one of hafnium oxide (HfO2) and tantalum oxide (TaO). However, the material of the metal oxide material layer (155m) is not limited thereto and can be varied in many ways.

[0124] Referring to FIG. 10f and FIG. 10g, a first photoresist pattern (PR1) can be formed within a trench (T). Referring to FIG. 10g, the first photoresist pattern (PR1) may not be placed on the upper surface (161a) of the first insulating layer (161). Specifically, the first photoresist pattern (PR1) may not overlap with the first insulating layer (161).

[0125] Referring to Fig. 10g, a metal oxide material layer (155m) that does not overlap with the first photoresist pattern (PR1) can be etched.

[0126] Referring to FIG. 10h, the first photoresist pattern (PR1) can be removed. Due to the manufacturing steps of FIG. 10f and FIG. 10g, the metal oxide material layer (155m) is not placed on the upper surface (161a) of the first insulating layer (161), but is placed on the side (SS) of the first insulating layer (161) and can be placed on the upper surface of the exposed first well region (130).

[0127] Referring to FIG. 10i, a second photoresist material layer (PR2) can be formed on the first insulating layer (161). The second photoresist material layer (PR2) may overlap with the first insulating layer (161), overlap with a portion of the metal oxide material layer (155m), and may not be placed within the trench (T).

[0128] Referring to FIGS. 10i and 10j, a metal oxide material layer (155m) that does not overlap with the second photoresist material layer (PR2) can be etched. By removing the metal oxide material layer (155m) through etching to form a first metal oxide layer (155a), the first well region (130) can be exposed. The first metal oxide layer (155a) can be placed only on the side (SS) of the first insulating layer (161).

[0129] Referring to FIG. 10j and FIG. 10k, a short-wavelength absorption layer (150) can be formed within a trench (T) by epitaxial growth. The short-wavelength absorption layer (150) can be in contact with a first well region (130). A first metal oxide layer (155a) can be disposed between the short-wavelength absorption layer (150) and the first insulating layer (161).

[0130] Referring to FIG. 10L, a second high-concentration doping region (151) can be formed by high-concentration doping of a first conductive type dopant on the upper surface (150a) of the short-wavelength absorption layer (150).

[0131] Referring to FIG. 10m, a second insulating layer (162) can be formed on a first insulating layer (161), a first contact portion (170a) and a second contact portion (170b) penetrating the second insulating layer (162) can be formed, and a first metal pad (180a) and a second metal pad (180b) disposed on the second insulating layer (162) can be formed.

[0132] The present invention described above is not limited by the aforementioned embodiments and attached drawings, and it will be obvious to those skilled in the art that various substitutions, modifications, and changes are possible within the scope of the technical aspects of the present invention. Therefore, the scope of the present invention is defined by the claims set forth below, and all modifications or variations derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of the present invention.

Claims

1. A substrate including an avalanche amplification region; A first insulating layer disposed on the substrate and having a trench formed in a region corresponding to the avalanche amplification region; A short-wavelength absorption layer filled inside the above trench; and A single-photon avalanche diode pixel array comprising a first metal oxide layer formed between the first insulating layer and the short wavelength absorption layer within the trench.

2. In Paragraph 1, It further includes a second metal oxide layer disposed on the upper surface of the first insulating layer, and A single-photon avalanche diode pixel array in which the first metal oxide layer and the second metal oxide layer are integrally formed.

3. In Paragraph 1, A single-photon avalanche diode pixel array, wherein the substrate comprises silicon (Si) and the short-wavelength absorption layer comprises germanium (Ge).

4. In Paragraph 1, The above substrate is, A first region doped with a first conductive type dopant; A deep well region disposed on the first region and doped with a dopant of a second conductivity type opposite to the first conductivity type; and It includes a first well region formed by doping the upper surface of the deep well region with the first conductive type dopant, and The avalanche amplification region is a single-photon avalanche diode pixel array formed at the boundary between the deep well region and the first well region.

5. In Paragraph 1, The above substrate is, A first well region formed by doping with a first conductive type dopant; A second well region formed spaced apart from the first well region and doped with a second conductive type dopant; and It includes a first high-concentration doping region formed by high-concentration doping with the second conductive type dopant on the upper surface of the second well region, and The above short wavelength absorption layer includes a second high-concentration doping region formed by high-concentration doping with the first conductive type dopant, and A single-photon avalanche diode pixel array in which the first high-concentration doping region in a planar plane is a closed-loop shape surrounding the second high-concentration doping region.

6. In Paragraph 5, It further includes a separation structure for electrically isolating the first well region and the second well region, and The above separation structure is, A first separation structure disposed between the first well region and the second well region, and It includes a second separation structure disposed on the other side of the second well region, and In a planar view, the first separation structure is a closed-loop shape surrounding the first well region, and In a planar view, the second separation structure is a closed-loop shape surrounding the first well region and the second well region, and The above substrate further includes a deep well region in which the first well region and the second well region are formed and doped with the second conductive type dopant. The above separation structure is a single-photon avalanche diode pixel array extending from the upper surface of the deep well region toward the lower surface of the deep well region.

7. In Paragraph 5, The first high-concentration doping region is the cathode region of the single-photon avalanche diode, and the second high-concentration doping region is the anode region of the single-photon avalanche diode, and A single-photon avalanche diode pixel array in which the first conductivity type is P type and the second conductivity type is N type.

8. In Paragraph 5, The substrate includes a deep well region doped with a dopant of a second conductivity type opposite to the first conductivity type, and A pixel isolation structure disposed between the first well region and the second well region for isolating photoelectrons; A metal grid disposed on the pixel separation structure above; and It includes a micro lens disposed on the first insulating layer, and The pixel separation structure extends from the upper surface of the deep well region to the lower surface of the substrate, and The metal grid above is a single-photon avalanche diode pixel array that reflects light incident from the outside.

9. In Paragraph 8, The above metal grid includes a metal with a high refractive index, and A single-photon avalanche diode pixel array, wherein the metal oxide layer comprises at least one of hafnium oxide (HfO2), titanium oxide (TiO2), aluminum oxide (Al2O3), and tantalum oxide (TaO).

10. In Paragraph 1, A third insulating layer disposed on the first insulating layer; A single-photon avalanche diode pixel array further comprising plasmonic patterns disposed on the third insulating layer to form a Schottky barrier between the third insulating layers.

11. In Paragraph 10, The above plasmonic patterns are single-photon avalanche diode pixel arrays comprising aluminum or titanium.

12. A step of forming a substrate including an avalanche amplification region; A step of forming a first insulating layer on the substrate having a trench formed therein that exposes the upper surface of the substrate corresponding to the avalanche amplification region; A step of forming a metal oxide material layer on the first insulating layer including the trench; A step of selectively patterning the metal oxide material layer to form a first metal oxide layer formed inside the trench; A method for manufacturing a single-photon avalanche diode pixel array, comprising the step of forming a short-wavelength absorption layer inside the trench by epitaxial growth.

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