Decoding a codeword based on higher order information

Abstract

This disclosure describes techniques regarding improving the decoding performance of a code word, such as an LDPC code word. In an example, the error correction capability of a decoding layer is improved, where the improvement can include lowering the error floor. To this end, high order information is used in the decoding. High order information refers to information used during the decoding of a variable node that has an error, which is not limited to that variable node and the check nodes connected to it, but includes information about variable nodes that also have an error and are connected to the variable node via satisfied check nodes, and about unsatisfied check nodes connected to these variable nodes.

Description

Technical Field

[0001] This disclosure relates to a technique for improving the decoding performance of codewords (e.g., LDPC codewords). Background Technology

[0002] Error correction codes (ECC) are commonly used in various types of data storage devices, including NAND flash memory. ECC is also frequently used during data transmission. ECC refers to adding redundant or parity data to a message so that the message can be recovered by the receiver even if some errors are introduced during transmission or storage. Typically, ECC can correct errors based on the capabilities of the code being used. ECC decoding can include software decoding, such as low-density parity code (LDPC) decoding, where the logical values ​​stored in the memory cells can be represented as a probability distribution.

[0003] In many decoding systems, different types of decoders can be used, each with different error correction capabilities. For example, in LDPC decoding, bit-flipping (BF) can be implemented in the first decoding layer, which handles the majority of the read traffic. Minimum-sum (MS) decoders can be implemented in deeper decoding layers, handling the smaller portion of the read traffic that the BF decoder does not decode correctly. Although the BF decoder is weaker than the MS decoder, it is used because it has much lower decoding latency at very high signal-to-noise ratios (SNR). In these systems, much of the code design focuses on improving the error correction capabilities of deeper layers of the defense stream, such as enhancing the error correction capabilities of the MS decoder. Summary of the Invention

[0004] A technique for improving the decoding performance of codewords (e.g., LDPC codewords) is described. In the example, the error correction capability of the decoding layer of the first decoding layer in a multi-decoding-layer system is improved. This improvement may include lowering the lower error bound, thereby enabling the decoding layer to decode codewords that would otherwise fail to decode. For this purpose, higher-order information is used in decoding. Higher-order information refers to information used during the decoding of a variable node that has an error; this information is not limited to the variable node and its connected check nodes, but includes information relating to variable nodes that also have errors and are connected to the variable node via satisfied check nodes, and information relating to unsatisfied check nodes connected to these variable nodes.

[0005] In the example, a method for decoding LDPC codewords is disclosed. The method is implemented by a computer system and includes: determining a first set of parity nodes connected to a first variable node and satisfying a parity condition, and a second set of parity nodes connected to the first variable node and not satisfying a parity condition, wherein the first variable node represents at least one bit of an LDPC codeword that is erroneous; determining a second variable node connected to the first variable node via the parity nodes of the first set and located at least two edges from the first variable node; determining a third set of parity nodes connected to the second variable node and not satisfying a parity condition; determining, based on the second and third sets, whether to flip at least one bit represented by the first variable node; and decoding the LDPC codeword based on the determination of whether to flip the at least one bit.

[0006] In the example, the method further includes: determining a checksum associated with the first variable node in a decoding iteration, wherein a third set is determined based on the value of the checksum. In this example, the method may further include: in another decoding iteration, determining an updated value of the checksum, omitting the determination of a second variable node based on the updated value, determining a second set of updated check nodes connected to the first variable node and not satisfied, determining, based on the updated second set and independently of the third set, whether to flip at least one bit represented by the first variable node, and decoding the LDPC codeword based on the determination of whether to flip at least one bit in a further decoding iteration.

[0007] In the example, determining whether to flip at least one bit includes: determining the total number of non-compliant nodes based on the sizes of the second and third sets, and comparing the total number with a threshold. In this example, the threshold can be defined based on the degree of the first variable node, and determining whether to flip at least one bit can include determining whether to flip at least one bit based on the total number of nodes greater than the threshold.

[0008] In the example, determining whether to flip at least one bit includes: in the decoding iteration, determining the first energy of the first variable node. Among them: First energy equal degv is the degree of the first variable node; It is a verification node from the second set with index i; It is an unsatisfied set of nodes that are at least l edges away from the first variable node and each of them is connected to a variable node. The fourth set of the check nodes of the variable nodes; l is at least 3; set This includes variable nodes that have errors and are at least l-1 edges away from the first variable node; and Based on the first energy To update the energy E of the first variable node v And will the energy E v A comparison is made with a threshold, which is defined based on the degree of the first variable node. In this example, the method may further include, in another decoding iteration, determining whether at least one bit should be flipped by at least: determining a second energy of the first variable node. Instead of primary energy Energy E v Equal to the second energy And will the energy E v The energy is compared with a threshold. Furthermore, the second energy is calculated based on the checksum associated with the first variable node. Instead of primary energy

[0009] In one embodiment, a computer system is disclosed. The computer system includes: a memory for storing LDPC codewords; and an LDPC decoder connected to the memory and configured to perform examples of the methods described above.

[0010] In the example, a non-transitory computer-readable storage medium is disclosed. The non-transitory computer-readable storage medium stores instructions that, when executed on a computer system, cause the computer system to perform the operations of the example methods described above.

[0011] Consider the following illustrative example. A conventional BF decoder uses a message-passing algorithm to pass messages between variable nodes and parity nodes to decode LDPC codewords. A decision is made to flip the bits represented by the variable node that has an error (e.g., connected to an unsatisfied parity node, such as a parity equation not equal to zero). This decision depends on the degree of the variable node (e.g., how many parity nodes are connected to it) and the energy of the variable node (e.g., how many of the connected parity nodes are unsatisfied). For example, when the energy is greater than half the degree, the decision is to flip the bit. A conventional BF decoder suffers from a trapping issue: as the lower error bound approaches a specific code failure rate (CFR), the energy of the variable node may not change significantly in additional decoding iterations, so additional bit-flipping decisions cannot be meaningfully made by performing additional decoding iterations.

[0012] In contrast, the BF decoder disclosed herein overcomes this dilemma. In particular, the energy of computation for a variable node is not limited to that variable node alone, but can also take into account the energy of other variable nodes that have errors and are indirectly connected to that variable node.

[0013] For example, a first variable node is connected to five check nodes, two of which are not satisfied. The degree and energy of this first variable node are 5 and 2, respectively. One of the satisfied check nodes is connected to the second variable node that had the error. The energy of this second variable node is 1. Summing these two energies gives a total energy of 3, which is associated with the first variable node. Because the total energy is greater than half the degree (e.g., greater than 2.5), the decision is to flip the bit represented by the first variable node. If a regular BF decoder were used, the energy of the first variable node would be 2 and less than half the degree; therefore, the decision would be not to flip the bit.

[0014] These illustrative examples are mentioned not to limit or restrict this disclosure, but to provide examples to aid in understanding it. Other embodiments and examples are discussed in the detailed description, and further description is provided therein. Attached Figure Description

[0015] The nature and advantages of the various embodiments can be understood by referring to the following figures.

[0016] Figure 1 An example high-level block diagram of an error correction system according to certain embodiments of the present disclosure is shown.

[0017] Figures 2A to 2B Example parity matrices and example diagrams representing parity matrices are shown according to certain embodiments of the present disclosure.

[0018] Figure 3 An example diagram is shown illustrating the decoding of LDPC codewords using low-order information.

[0019] Figure 4 Showing the use of combination Figure 3 Example error lower bound for decoders of publicly available low-level information.

[0020] Figure 5 An example diagram is shown illustrating the decoding of LDPC codewords using higher-order information.

[0021] Figure 6 Showing the use of combination Figure 5 Example error floor for decoders of publicly available high-order information.

[0022] Figure 7 An example flow of codeword decoding based on higher-order information according to certain embodiments of this disclosure is shown.

[0023] Figure 8 A more detailed example flow of LDPC codeword decoding based on higher-order information according to certain embodiments of this disclosure is shown.

[0024] Figure 9 This indicates a computer system capable of implementing the present disclosure. Detailed Implementation

[0025] Techniques for improving the decoding performance of codewords (e.g., LDPC codewords) are described. In the example, decoding uses a message-passing algorithm, such as the bit-flipping (BF) algorithm, that iteratively passes information between variable nodes and check nodes. In conventional systems, after some decoding iterations of a codeword, the message-passing algorithm may fail to determine useful additional information for decoding the codeword, and decoding may fail even when the maximum number of iterations is reached. In these cases, decoding can be described as stuck and may unnecessarily perform additional decoding iterations, resulting in decoding latency and wasted power without any decoding gain. In contrast, this disclosure proposes a decoding system that intelligently and selectively determines higher-order information during decoding. Specifically, the message-passing algorithm of the disclosed decoding system can determine information for erroneous variable nodes, which is not limited to the variable node and the check nodes connected to it, but includes information related to variable nodes that also erroneously occur and are connected to the variable node via satisfying check nodes, and information related to unsatisfied check nodes connected to these variable nodes. This information is used in the decoding of the variable nodes.

[0026] To illustrate, consider an example of a BF decoder. Typically, a BF decoder determines whether to flip a bit represented by a first variable node. In conventional systems, bit-flipping decisions are based on low-order information—that is, only information about the check nodes directly connected to the first variable node. Specifically, the degree of the first variable node (e.g., the number of directly connected check nodes) is determined. The number of unsatisfied check nodes connected to the first variable node is also determined. If this number is greater than half the degree, the BF decoder flips the bit. Otherwise, it does not flip the bit. In such conventional systems, a dilemma can arise where the first variable node is faulty and the number of unsatisfied check nodes remains less than half the degree after multiple decoding iterations. This dilemma is further described in the accompanying figures below. Thus, a conventional BF decoder continues performing decoding iterations without obtaining useful information for determining whether to flip the bit.

[0027] In contrast, the BF decoder of this disclosure avoids this predicament. Specifically, the BF decoder can consider satisfying check nodes directly connected to the first variable node. Next, the BF decoder identifies a second variable node that has an error and is connected to a satisfying check node (e.g., the second variable node is indirectly connected to the first variable node via a satisfying check node). In this illustration, the distance between the second variable node and the first variable node is two (e.g., indirectly connected to the first variable node along two edges). For the second variable node, the BF decoder determines the number of unsatisfied check nodes connected to it. This number, together with the number of unsatisfied check nodes directly connected to the first variable node, is used to determine whether to flip the bit represented by the first variable node. The number of unsatisfied check nodes connected to the second variable node is an example of higher-order information about the first variable node, as this information pertains to both the second variable node and the check nodes indirectly connected to the first variable node. This higher-order information is not necessarily limited to the second variable node, but, depending on the actual decoding, can include one or more variable nodes at least two edges away from the first variable node (e.g., at least 2 edges) and one or more check nodes at least three edges away from the first variable node (e.g., at least 3 edges).

[0028] Several technical improvements have been achieved by avoiding this predicament. For example, higher-order information improves the performance of message-passing algorithms implemented in the decoder, thereby lowering the lower bound of decoding errors. When such a decoder is implemented in the decoding layer of a multi-layer decoding system, the overall decoding latency of the system can be improved, thus enhancing Quality of Service (QoS), because a relatively large volume of read traffic can be successfully decoded at the decoding layer, eliminating the need for deeper and more complex decoding layers. When such a decoder is implemented in a single-layer decoding system, throughput and decoding latency can be improved due to the enhanced error correction capability of the decoder.

[0029] For clarity, various embodiments of this disclosure are described in conjunction with LDPC codeword decoding using BF decoding. However, these embodiments can be similarly applied to other decoder types that rely on message passing algorithms. Additionally, various embodiments of this disclosure are described in conjunction with quasi-cyclic LPDC (QC-LDPC) codes. However, these embodiments can be similarly applied to other code types, including other types of LDPC codes.

[0030] Figure 1 An example high-level block diagram of an error correction system 100 according to certain embodiments of the present disclosure is shown. In this example, LDPC codes are described in conjunction with data storage. However, embodiments of the present disclosure are not limited thereto. Rather, embodiments are similarly applied to other uses of LDPC codes, including, for example, data transmission.

[0031] LDPC codes are linear block codes defined by a sparse parity check matrix H, consisting of 0s and 1s. The term "sparse matrix" in this paper refers to a matrix where the number of non-zero values ​​in each column and each row is much lower than its dimension. The term "column weight" in this paper refers to the number of non-zero values ​​in a specific column of the parity check matrix H. The term "row weight" in this paper refers to the number of non-zero values ​​in a specific row of the parity check matrix H. Generally, if the column weights of all columns in the parity check matrix corresponding to the LDPC code are similar, the code is called a "regular" LDPC code. On the other hand, if at least one of the column weights differs from the others, the LDPC code is called an "irregular" LDPC code. Generally, irregular LDPC codes offer better error correction capabilities than regular LDPC codes.

[0032] LDPC codes are also described based on the methods used to construct them. Code construction can utilize density evolution (DE) schemes to create sparse parity-check matrices with a target distribution. Random computer search or algebraic construction are possible. Random computer search construction describes LDPC codes with parity-check matrices designed by a random computer program. Algebraic construction implies that the parity-check matrix has been constructed based on combinatorial methods. QC-LDPC codes belong to the latter construction method. One advantage of QC-LDPC codes is their relative ease of implementation in terms of the encoding process. A key feature of QC-LDPC codes is that the parity-check matrix consists of cyclic submatrices, which can be based on an identity matrix or a small random matrix. Permutation vectors can also be used to create cyclic submatrices.

[0033] As shown in the figure, the LDPC encoder 110 receives information bits including data that is intended to be stored in the storage system 120. The LDPC-encoded data is output by the LDPC encoder 110 and written to the storage system 120.

[0034] In various embodiments, the storage system 120 may include various storage types or media, such as magnetic, solid-state, disk drives, or flash memory. In some embodiments, these technologies are employed in the transceiver, and data is transmitted and received via wired and / or wireless channels rather than being written to or read from the storage system. In this case, errors may be introduced into the received codewords during codeword transmission.

[0035] When the stored data is requested or otherwise needed (e.g., by an application or user storing the data), detector 130 receives data from storage system 120. The received data may include some noise or errors. Detector 130 performs detection on the received data and outputs a decision and / or reliability information. For example, a soft-output detector outputs reliability information and a decision (e.g., a logic value "1" or "0") for each detected bit. On the other hand, a hard-output detector may output a decision for each bit without providing corresponding reliability information. As an example, a hard-output detector may output a decision that a particular bit is "1" or "0" without indicating how certain the detector is about that decision. In contrast, a soft-output detector outputs a decision and the reliability information associated with that decision. Typically, the reliability value indicates how certain the detector is about a given decision. In one example, a soft-output detector outputs a log-likelihood ratio (LLR), where the sign indicates the decision (e.g., a positive value corresponds to a "1" decision and a negative value corresponds to a "0" decision), and the magnitude indicates how certain the detector is about that decision (e.g., larger smaller larger indicates higher reliability or certainty).

[0036] The decision and / or reliability information is passed to the LDPC decoder 140, which performs LDPC decoding using the decision and reliability information. The soft input decoder uses both the decision and reliability information to decode the codeword. The hard decoder decodes the codeword using only the decision value from the decoder. The decoded bits generated by the LDPC decoder 140 are passed to the appropriate entity (e.g., the user or application requesting the decoded bits). Through correct encoding and decoding, the information bits match the decoded bits.

[0037] In various embodiments, the illustrated system can be implemented using a variety of technologies, including application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and / or general-purpose processors (e.g., advanced RISC machine (ARM) cores).

[0038] LDPC codes are typically represented by a bipartite graph. One set of nodes, such as variable nodes or bit nodes, corresponds to the elements of the codeword, while another set of nodes, such as check nodes, corresponds to the set of parity constraints satisfied by the codeword. Edge connections are usually randomly selected. The error correction capability of LDPC codes is improved if shorter cycles are avoided in the graph. In a (r, c) regular code, each of the n variable nodes (V1, V2, ..., Vn) is connected to r check nodes, and each of the m check nodes (C1, C2, ..., Cm) is connected to c bit nodes. In irregular LDPC codes, the degree of check nodes is not uniform. Similarly, the degree of variable nodes is not uniform. In QC-LDPC codes, the parity matrix H is constructed as p×p matrix blocks such that the bits in a block participate in only one check equation within that block, and each check equation in a block involves only one bit of that block. In QC-LDPC codes, a codeword is cyclically shifted p to produce another codeword. Here, p is the size of a square matrix that is either a zero matrix or a cyclic matrix. This is a generalization of the cyclic code that generates another codeword by cyclically shifting a codeword by 1. A p×p matrix block can be a zero matrix of size p×p or a cyclically shifted identity matrix.

[0039] Figure 2A An example parity check matrix H200 is shown, and Figure 2B An example bipartite graph corresponding to parity matrix 200 is shown. In this example, parity matrix 200 has six column vectors and four row vectors, but embodiments of this disclosure are not limited thereto and can be similarly applied to parity matrices with hundreds or even thousands of column and row vectors. Network 202 shows a network corresponding to parity matrix 200 and represents a bipartite graph. Various types of bipartite graphs can exist, including, for example, Tanner graphs.

[0040] Typically, the variable nodes in network 202 correspond to column vectors in parity check matrix 200. The parity nodes in network 202 correspond to row vectors in parity check matrix 200. The values ​​of parity check matrix 200 determine the interconnections between nodes. Specifically, a "1" indicates that the corresponding parity node and variable node are connected. A "0" indicates that there is no connection. For example, the "1" in the leftmost column vector and the second row vector from the top of parity check matrix 200 corresponds to the connection between variable node 204 and parity node 210.

[0041] Message passing algorithms are commonly used for decoding LDPC codes. Several variations of message passing algorithms exist in the prior art, such as the BF algorithm, the MS algorithm, and the scaled MS algorithm. Generally, any variation of the message passing algorithm can be used in the LDPC decoder without departing from the teachings of this disclosure. Message passing utilizes a network of variable nodes and check nodes, such as... Figure 2BAs shown. The connection between the variable node and the parity node is described by and corresponds to the values ​​of the parity matrix 200, such as... Figure 2A As shown.

[0042] A hard-decision message passing algorithm can be executed. In the first step, each variable node sends a message to one or more check nodes connected to that variable node. In this case, the message is the value that each variable node considers to be its correct value.

[0043] In the second step, each check node uses the information previously received from the variable nodes to calculate a response to send to the variable nodes connected to it. The response message corresponds to the value that the check node believes the variable node should have based on information received from other variable nodes connected to it. This response is calculated using a parity check equation that forces the sum of the values ​​of all variable nodes connected to a particular check node to zero (modulo 2).

[0044] At this point, if all equations of all check nodes are satisfied, the decoding algorithm declares that the correct codeword has been found and terminates. If the correct codeword is not found, the iteration continues by using the message received by the variable node from the check node to perform another update on the variable node, determining whether the bit at the variable node's position should be 0 or 1 by majority rule. The variable node then sends this hard-decision message to the check nodes connected to these variable nodes. The iteration continues until the correct codeword is found or the maximum number of iterations has been performed without finding the correct codeword. It should be noted that the soft-decision decoder works similarly; however, each message passed between the check node and the variable node also includes the reliability of each bit.

[0045] The example message passing algorithm can be executed. In this example, L(q) ij ) indicates that the variable node v i Send to verification node c j Message; L(r) ji ) indicates that it is verified by node c j Send to variable node v i The message; and L(c i ) represents each variable node v i The initial LLR value.

[0046] Each L(q) can be executed through the following steps. ij Variable node processing:

[0047] (1) Read L(c) from memory i ) and L(r ji ).

[0048] (2) Calculation

[0049] (3) Calculate each L(Qi-sum)-L(r) ij ).

[0050] (4) Output L(Qi-sum) and write it back to memory.

[0051] (5) If this is not the last column of memory, go to step 1 and increment i by 1.

[0052] (6) Calculate the parity check sum (e.g., checksum); if they are all equal to 0, the number of iterations has reached a threshold, and the parity check sum is greater than another threshold, or the number of iterations is equal to the maximum limit, then stop; otherwise, perform check node processing.

[0053] Each L(r) can be executed as follows: ji Verification node processing:

[0054] (7) Read a line q from memory ij .

[0055] (8) Calculate L(Rj-sum) as follows:

[0056]

[0057] α ij =sign(L(q) ij )), β ij =|L(q) ij )|,

[0058]

[0059] (9) Calculate the individual verification node

[0060] (10) L(r) ji Write back to memory.

[0061] (11) If this is not the last line of memory, go to step one and increment j by 1.

[0062] Figure 3 Example Figure 300 is shown for decoding LDPC codewords using low-order information. A dilemma may arise by using only low-order information. "Low-order information" refers to information about the variable node, which is obtainable from the check node directly connected to the variable node. "Directly connected" refers to a check node that is 1 unit away from the variable node (e.g., connected to the variable node via a single edge between the two nodes). "Distance" refers to the number of edges along the path connecting the two nodes.

[0063] As shown in the figure, variable node 310 has an error and represents at least one bit of the LDPC codeword. It may have an error because at least one of the parity check nodes directly connected to it is not satisfied (e.g., the parity check equation associated with that parity check node is not equal to zero). Figure 3 In the illustrative example, variable node 310 has a degree of 5 because it is directly connected to five check nodes. This degree is equal to the number of edges 312 that connect variable node 310 to these check nodes.

[0064] Of the five parity nodes, three parity nodes 320 are satisfied (e.g., the parity equation associated with the parity node is equal to 0), as shown in the blank box, and the remaining two parity nodes 330 are not satisfied, as shown in the dashed box. The total number of unsatisfied parity nodes 330 directly connected to variable node 310 is 2. This total number can represent the low-order energy of variable node 310. The low-order energy (e.g., 2) can be compared to a threshold, where the threshold can be defined based on the degree of variable node 310 (e.g., the threshold is equal to half the degree). When the low-order energy is greater than the threshold, at least one bit represented by variable node 310 can be flipped. Otherwise, the bit is not flipped.

[0065] A dilemma may arise where the low-order energy may remain constant during decoding iterations, or even if updated, may not exceed a threshold, thus potentially preventing BF from being performed. The reason behind this dilemma may relate to another variable node that has erred and is indirectly connected to variable node 310 via a satisfying check node, where this other variable node also has a smaller low-order energy. Specifically, consider the most satisfying check node 330. To its right is a second variable node (shown as a dashed circle) that is erroneous and located 2 units away from the first variable node 310. If the bits represented by these two variable nodes are flipped, the top check node 330 still satisfies (e.g., in the parity equation, and before BF, the bit of the variable node is "1" and the bit of the other variable node is "0"; by flipping the two bits to "0" and "1" respectively, the parity equation remains equal to zero). Thus, a bit dilemma may occur when variable node 310 is faulty and has a small low-order energy (e.g., less than half its degree), and when at least the second variable node also has a small low-order energy, wherein the second variable is faulty, is at least two edges away from variable node 310, and is connected to variable node 310 via a satisfying check node.

[0066] The positional dilemma can be summarized as follows. Let L v，w This represents the length (number of edges) of the path connecting two variable nodes v and w. When considering the failure bits represented by variable nodes v and w, L... v，wWhen the number of failure bits is small, the BF decoder is more likely to fail. This problem can prevent the BF decoder from successfully decoding even when the number of failure bits in the sequence is within the range of the intermediate failure bit count (FBC). In this case, the failure bits represented by variable node w misleadingly help reduce the energy function of another variable node v, and vice versa.

[0067] use Figure 3 The diagram shows that n and m represent the code length and the number of parity checks, respectively (n and m are very large numbers). Figure 3 Only the variable nodes 310 and 340 that have errors are shown, along with all the check nodes 320, 330 and 350 connected to them. This represents the set of variable nodes 340 that have encountered errors, each 2 units away from variable node 310, and each connected to a valid check node 320 1 unit away from variable node 310. Typically, L represents v，w =l is the set of failed variable nodes w. gather It can be called the set of "hidden nodes that are at a distance l from the variable node v".

[0068] In the diagram, five check nodes out of all check nodes fail to meet the requirement (e.g., two check nodes 330 at a distance of 1 from variable node 310 and three check nodes 350 at a distance of 3 from variable node 310). A problematic issue arises because, for each failure bit represented by variable node v, when at least one L... v，w The variable node w is equal to 2. In this case, E v This represents the energy function of variable node v (e.g., low-order energy, such as the number of unsatisfied check nodes 330 directly connected to variable node v). For variable node 310, this E... v =2. If the flipping threshold is Therefore, the BF decoder will not flip variable node 310 because E v ≤T d When higher-order information is not used, after multiple decoding iterations, the E of the variable node... v It is unlikely to be updated, thus making E a problem due to the dilemma. v >T d .

[0069] Figure 4 Showing the use of combination Figure 3 The lower limit of the example error for decoders of publicly available low-level information is 410. Figure 4The curve 400 shown represents the FBC on the horizontal axis and the CFR on the vertical axis, and is generated based on an simulation of decoding the QC-LDPC code using a BF decoder. For variable nodes, the BF decoder uses the low-order energy of the variable node in the relevant BF decision. When the CFR is close to 10... -3 The lower error bound begins at 410. At this lower error bound of 410, even when the BF decoder uses the maximum number of decoding iterations (which in turn increases decoding latency), the performance of the BF decoder may degrade, and thus decoding of QC-LDPC codewords may fail (e.g., at a rate higher than 10). -3 (ratio).

[0070] Figure 5 Figure 500 illustrates an example of decoding LDPC codewords using higher-order information. For clarity and conciseness, Figure 500 is similar to Figure 300, and these similarities are not repeated herein. The difference lies in the use of higher-order information instead of lower-order information. The use of higher-order information overcomes the limitations of the preceding text. Figure 3 The dilemma of discussion can be addressed and the lower bound of error can be reduced, such as Figure 6 As further shown in the diagram, this improves decoding performance.

[0071] "Higher-order information" refers to information about second variable nodes indirectly connected to the first variable node and / or information about check nodes indirectly connected to the first variable node. The message passing algorithm can use higher-order information in decoding a codeword with at least one bit represented by the first variable node. "Indirect connection" refers to a node that is 2 or more bits away from the first variable node. For example, a second variable node can be indirectly connected to the first variable node at a distance of 2, 4, or another even number. In contrast, a check node can be indirectly connected to the first variable node at a distance of 3, 5, or another odd number greater than 1 (e.g., a distance of 1 indicates that the check node is directly connected to the first variable node).

[0072] As shown in the figure, variable node 510 (for example, with...) Figure 3 The variable node 510 (which is the same as or similar to the variable node 310) has an error and represents at least one bit of the LDPC codeword. Variable node 510 is directly connected to the five check nodes and therefore has a degree of 5. As shown in the blank box, three of the five check nodes are satisfied (e.g., with...). Figure 3 The check node 320 is the same as or similar to the check node 320. The other two check nodes are not satisfied (e.g., with the check node 320). Figure 3 (The verification node 330 is the same as or similar to the variable node 510). Therefore, the low-order energy of the variable node 510 is 2.

[0073] Consider the first validating node 520a out of three validating nodes. This validating node 520a is also connected to the set of variable nodes that have encountered errors. The second variable node 540a is an error node that is 2 units away from variable node 510. Instead, variable node 540a is connected to the set of the satisfying check node 520a and the check nodes from the non-satisfied check nodes that are 3 units away from variable node 510. The unsatisfied check node 550a. Variable node 520a has a degree of 2 and a low-order energy of 1 (through direct connection to a satisfying check node 520a and an unsatisfied check node 550a). The low-order energy of this indirectly connected variable node 520a is an example of high-order information that can be used in the BF decision of variable node 510. For example, the low-order energy of variable node 520a (e.g., 1) can be added to the low-order energy of variable node 510 (e.g., 2) or added as a weighted sum to the low-order energy of variable node 510 (e.g., 2) to calculate the total energy of variable node 510. The BF decoder can then use the total energy, instead of the low-order energy of variable node 510, with a threshold T. d A comparison is made to determine whether the bit represented by variable node 510 should be flipped (e.g., when the total energy exceeds the threshold T). d (Time-flipped bits). Of course, you can use data from a set. (and / or other sets with an even distance l greater than 2) The remaining indirectly connected variable nodes and / or those from the set (and / or from other sets with an odd distance greater than 3) The total energy is calculated using the higher-order information of the remaining indirectly connected check nodes. If a weighted sum is used, the weights can be static or dynamic. Static weights can be predefined (e.g., as the reciprocal or fraction of the distance l). Dynamic weights can be calculated dynamically using one or more factors, including, for example, the distance l of the indirectly connected nodes, the LLR of the indirectly connected nodes, and / or the decoding iterations. v It is the degree of the first variable node. It is a verification node from the second set with index i. It is the set of unsatisfied check nodes that are at least l edges away from the first variable node, where each node is connected to the set of variable nodes. The variable nodes, where l is at least 3. This set This includes variable nodes that have errors and are at least l-1 edges away from the first variable node.

[0074] Thus, to overcome this predicament, while the BF decoder is calculating the energy function of a variable node (e.g., variable node 510), the BF decoder is unaware of the set S of indirectly connected variable nodes with erroneous even distances l greater than 2. v However, in some cases, the existence of an unsatisfied check node at a distance of l+1 from variable node v can indicate a hidden state where such variable nodes exist at a distance of l (e.g., it can indicate a dilemma).

[0075] set up This is the set of unsatisfied check nodes that are at a distance of l+1 from the variable node. This is to help the decoder decode even when there are difficulties (e.g., such as...). Figure 3 As shown), you can view deeper layers of unmet validation nodes. To modify the energy function E for variable node v v . Figure 4 It can be shown as The indicator of existence

[0076] Therefore, instead of calculating the energy function using only a distance of 1 (e.g., low-order energy), Unlike traditional BF decoders, higher-order energy functions are used and expressed as... It can be any combinational logic and can include static and / or dynamic weights. The function g can be defined based on the observed set of dilemmas and hardware complexity. An example of function g is... (For example, the first part of the equation represents the check nodes that are not directly connected to the variable node v; the second part of the equation represents the number of check nodes that are indirectly connected to the variable node v and do not satisfy the condition.)

[0077] BF decoders can be based on low-order energy. and higher-order energy To calculate the total energy E of variable node v v For example, total energy E v It is the sum or weighted sum of two energies. The BF decoder can also output the total energy E. v With threshold T d Compare, and when E v ≤T d If the variable node v does not flip, the bit represented by the variable node v is flipped; otherwise, the bit is flipped. If the variable node v represents multiple bits and a flip decision is made, one or more such bits may be flipped.

[0078] In the optimization of the BF decoder, higher-order energies can be calculated intelligently and selectively. Instead of calculating for all variable nodes and at each decoding iteration, a checksum can be calculated for a variable node that has an error and is directly connected to a non-satisfied check node. Higher-order energies are then calculated for that variable node only if the checksum is small (e.g., less than a predefined value). Otherwise, calculate the low-order energy only for that variable node. High-order information markers (hoif) can be used v Indicates whether the node v is a variable and whether higher-order computation is performed. Energy, where "1" can indicate the need for higher order. Calculations are performed; "0" represents the opposite. The array hoif can be used for different variable nodes.

[0079] In other words, one way to reduce the hardware complexity of higher-order information is to use higher-order energy in a finite number of decoding cycles. Therefore, the hoif array is used to identify which decoding cycles and for which set of variable nodes higher-order energy is used.

[0080] Figure 6 Showing the use of combination Figure 5 Example lower bound of errors for decoders of publicly available high-order information. (Compared to...) Figure 4 The curve 400 is the same. Figure 6 The curve 600 shown represents the FBC on the horizontal axis and the CFR on the vertical axis, and was generated based on two simulations of decoding the QC-LDPC code, each simulation producing the curve. The first simulation uses the low-order energy of the variable node in the relevant BF decision for that variable node. And corresponding to the first curve 610 (and) Figure 4 The curve shown in curve 400 is the same. At CFR close to 10 -3 The lower bound of the error begins to appear at this point. The second simulation additionally uses the higher-order energies of the variable nodes in the relevant BF decision. (Where, for indirectly connected check nodes, l is 3), and corresponds to the second curve 620. When CFR approaches 10... -5 Its error lower bound begins to appear at this point. Therefore, by using higher-order energies... The error lower bound was reduced by approximately two orders of magnitude, thereby significantly improving decoding performance.

[0081] Figures 7 to 8 An example flow is shown that partially uses higher-order information to decode codewords. A computer system including an ECC decoder such as an LDPC decoder is described as performing the specific operations of this example flow. The system is... Figure 1An example of an error correction system 100 is provided. In this example, the computer system includes one or more processors and one or more memories. The memories store computer-readable instructions to implement functions specific to the computer system. When executed by the processor of the computer system, the instructions cause the computer system to perform the functions. The instructions stored in the memories, along with the underlying processor, represent the means of performing the functions. Although the operations are shown in a specific order, other arrangements of the operations are possible and some operations may be skipped, as will be apparent to those skilled in the art.

[0082] Figure 7 An example flow 700 for codeword decoding based on higher-order information according to certain embodiments of this disclosure is shown. For clarity, flow 700 is described along with the decoding of variable nodes and references are made to... Figure 3 and Figure 5 The elements. However, process 700 is similarly applicable to the iterative decoding of this variable node and other variable nodes, where higher-order information can span multiple indirectly connected variable nodes and / or multiple indirectly connected check nodes at one or more distances.

[0083] As shown in the figure, process 700 includes operation 702, in which the computer system receives an LDPC codeword. In one example, the LDPC codeword is accessed from a data storage device. In another example, the LDPC codeword is received during data transmission. In both examples, the LDPC codeword can be a QC-LDPC codeword.

[0084] Process 700 also includes operation 704, in which the computer system determines a set of satisfying check nodes and a set of unsatisfied check nodes for a first variable node (e.g., variable node 310 or 510). In the example, the first set (e.g., set 320) is determined and corresponds to the satisfying check nodes that are directly connected to the first variable node (e.g., at a distance of 1). The second set (e.g., set 330) is also determined and corresponds to the unsatisfied check nodes that are directly connected to the first variable node. The degree of the first variable node may be equal to the sum of the size of the first set and the size of the second set (e.g., the total number of directly connected check nodes). The low-order energy of the first variable node may be equal to the size of the second set (e.g., the total number of directly connected, unsatisfied check nodes). When the low-order energy is not equal to zero (e.g., the first variable node is directly connected to at least one unsatisfied check node), the first variable node may be faulty.

[0085] Process 700 also includes operation 706, in which the computer system determines for the first variable node a second variable node (e.g., variable node 540a) that has encountered an error, is connected to the first variable node, and is at least two edges away from the first variable node. In the example, the second variable node is indirectly connected to the first variable node along a path having a distance l, wherein the path includes nodes from the first set that satisfy the check (e.g., check node 520a).

[0086] Process 700 also includes operation 708, in which the computer system determines a third set (e.g., set of nodes that do not meet the checksum) connected to the second variable node. If a check node from the third set (e.g., check node 550a) is not satisfied, it is indirectly connected to the first variable node along a path with a distance of l+1, wherein the path includes the second variable node (e.g., variable node 540a) and a satisfying check node from the first set (e.g., check node 520a).

[0087] Process 700 also includes operation 710, in which the computer system determines whether to flip at least one bit represented by the first variable node. This determination may be based on a second set and a third set. For example, the low-order energy of the first variable node may be calculated as a function of the size of the second set (e.g., equal to the total number of directly connected, unsatisfied nodes). The high-order energy of the first variable node may be calculated as a function of the size of the third set (e.g., equal to the total number of unsatisfied nodes in the third set). The total energy of the first variable node may be calculated as a function of the two energies (e.g., as the sum or weighted sum of the low-order and high-order energies). The total energy may be calculated as a threshold defined based on the degree of the first variable node (e.g., half the degree). If the total energy is greater than the threshold, at least one bit is flipped; otherwise, at least one bit is not flipped.

[0088] In the example, and for optimization purposes, low-order energies can be calculated, while high-order energies can be calculated selectively. For example, in the current decoding iteration, the checksums of check nodes directly connected to the first variable node and not satisfied are calculated. If the checksum is small (e.g., its value is less than a predefined value), high-order energy is calculated. Otherwise, the energy is not calculated. Of course, as the checksum changes between iterations, the decision to calculate high-order energy will change accordingly. For example, in the current decoding iteration, the checksum value is small, so high-order energy is calculated. In another decoding iteration, the updated value of the checksum is determined and is greater than the predefined value. In this case, the calculation of high-order energy is omitted. Therefore, the determination of the second variable node is omitted. Similarly, the determination of the third set is omitted. Instead, only the updated low-order energies are calculated. Therefore, an updated second set of check nodes directly connected to the first variable node and not satisfied is determined. Bit-flip decisions are based on this updated second set and are performed independently of the third set. For example, the size of the updated second set represents the total energy of the first variable node in this decoding iteration and is compared with a threshold.

[0089] Process 700 also includes operation 712, in which the computer system decodes the LDPC codeword based on the determination at operation 710 whether at least one bit should be flipped. For example, if the determination at operation 710 is to flip at least one bit, the bit is flipped, the checksum of the LDPC codeword is updated, the soft information is updated, and if applicable (e.g., the checksum is not zero and the maximum number of iterations has not been reached), another decoding iteration is performed. If decoding fails (e.g., the checksum is not zero and the maximum number of iterations has been reached), decoding can be attempted again with another decoder (e.g., an MS decoder) that has higher error correction capabilities.

[0090] Figure 8 A more detailed example flow 800 of LDPC codeword decoding based on higher-order information according to certain embodiments of the present disclosure is shown. The LDPC codeword is decoded using a BF decoder of a computer system. The operation of flow 800 can be implemented as some or all of the sub-operations of flow 700. In flow 800, "i" denotes a counter tracking of decoding iterations (e.g., the value of the counter represents the number of decoding iterations). Assume i (0 ≤ i ≤ i) max ), This represents the decision of variable node j in the i-th iteration and Assumption (For example, a decision made before the decoding iteration begins). This represents the checksum at iteration i. (i) =||s (i) || represents the checksum of LDPC codeword iteration i. Let cs thLet cs be the checksum threshold used to compute higher-order energy functions with a distance of at least 2. Let hoif denote the checksum threshold cs. th An array of higher-order information flags that identify which energy function should be used. For example... Figure 8 As shown, process 800 represents the following steps:

[0091] Step 0: Set i = 0, calculate s (-1) And proceed to step 1;

[0092] Step 1: i = i + 1. If the maximum number of iterations is reached, stop decoding. Otherwise, go to Step 2.

[0093] Step 2: If cs (i) =0, then stop decoding. Otherwise, proceed to step 3;

[0094] Step 3: For 1≤j≤n circ ,

[0095] If (hoif(i,j)==1):

[0096] use For each calculated energy,

[0097] otherwise:

[0098] use For each calculated energy,

[0099] Flip E v >T v Those bits in the j-loop (e.g., in the case of QC-LDPC codewords),

[0100] Calculate and update s (i) ;

[0101] Proceed to step 1.

[0102] As shown in the figure, process 800 begins with operation 802, in which the computer system sets the counter "i" to zero and calculates the checksum s. (-1) Process 800 also includes operation 804, in which the computer system increments the counter "i" (e.g., i = i + 1).

[0103] Process 800 also includes operation 806, in which the computer system determines whether the counter "i" has reached the maximum number of decoding iterations (e.g., i = i max If the condition has been met, then execute operation 810 after operation 806. Otherwise, execute operation 820.

[0104] Process 800 also includes operation 810, in which the computer system stops decoding the LDPC codeword using the BF decoder. In this operation, if the checksum... If the value equals zero, decoding is successful. Otherwise, decoding fails, and the LDPC codeword can be decoded in another attempt using another LDPC decoder (e.g., an MS decoder) with higher error correction capabilities.

[0105] Process 800 also includes operation 820, in which the computer system calculates the checksum cs( i) Process 800 also includes operation 822, in which the computer system will verify the CS... (i) Compare with zero. If the checksum is cs (i) If the result is zero, then operation 830 is executed after operation 822. Otherwise, operation 824 is executed after operation 822.

[0106] Process 800 also includes operation 830, in which the computer system outputs the decoded bits. This is because the checksum cs of the LDPC codeword is calculated during the i-th decoding iteration. (i) The result is zero, so decoding was successful and no further decoding iterations are needed.

[0107] Process 800 also includes operations 824 to 854. These operations can be repeated for different variable nodes. In a process with n... cir In the case of QC-LDPC codes for cyclic matrices, different cyclic matrices j can be repeatedly decoded, where 0 ≤ j ≤ n. cir In operation 824, the checksum cs of the LDPC codeword during the i-th decoding iteration. (i) The value is not zero. In this operation, the computer system determines whether to compute the higher-order energy of the variable node (with index j, where, in the case of a QC-LDPC codeword, the variable node may correspond to a cyclic matrix j). This determination can be based on the value of a flag in the hoif array. If hoif(i, j) equals 1, the higher-order energy is computed and operation 840 is performed after operation 824. Otherwise, it is sufficient to compute the lower-order energy, and operation 850 is performed after operation 824.

[0108] Process 800 also includes operation 840, in which the computer system calculates the higher-order energies of the variable nodes. For example, the higher-order energy is...

[0109] Process 800 also includes operation 850, in which the computer system calculates the low-order energy of the variable nodes. For example, the low-order energy is... exist Figure 8 In the diagram, operation 850 is executed after operation 840. In this way, when calculating higher-order energies, the energy can be combined with lower-order energies to determine the total energy of the variable nodes.

[0110] Process 800 also includes operation 852, wherein when the total energy is greater than a threshold, the computer system flips one or more bits of the variable node (or one or more bits of the j-th cyclic matrix in the case of QC-LDPC codes). Process 800 also includes operation 854, wherein the computer system calculates the updated s after BF. (i) When j becomes equal to n circ At that time, operation 854 loops back to operation 804.

[0111] Figure 9 This indicates a computer system 900 that embodies the present disclosure. Figure 9 This is merely illustrative of embodiments of the present disclosure and does not limit the scope of the disclosure as described in the claims. In one embodiment, the system is a computer system 900 that generally includes a display screen 910, a computer 920, a user output device 930, a user input device 940, a communication interface 950, etc. Figure 1 The error correction system 100 implements some or all of the components of the computer system 900.

[0112] like Figure 9 As shown, the computer 920 may include a processor 960 that communicates with a plurality of peripheral devices via a bus subsystem 990. These peripheral devices may include a user output device 930, a user input device 940, a communication interface 950, and a storage subsystem such as random access memory (RAM) 970 and a disk drive 980.

[0113] User input device 940 includes all possible types of means and mechanisms for inputting information into computer system 920. These may include keyboards, keypads, touchscreens integrated into displays, audio input devices (such as voice recognition systems, microphones), and other types of input devices. In various embodiments, user input device 940 is typically implemented as a computer mouse, trackball, trackpad, joystick, wireless remote control, drawing tablet, voice command system, eye-tracking system, etc. User input device 940 typically allows a user to select objects, icons, text, etc., appearing on display screen 910 via commands such as clicking buttons.

[0114] User output device 930 includes all possible types of devices and mechanisms for outputting information from computer 920. These may include displays (e.g., screen 910) and non-visual displays such as audio output devices.

[0115] Communication interface 950 provides an interface to other communication networks and devices. Communication interface 950 can serve as an interface for receiving data from and transmitting data to other systems. Embodiments of communication interface 950 typically include Ethernet cards, modems (telephone, satellite, cable, ISDN), (asynchronous) digital subscriber line (DSL) units, FireWire interfaces, USB interfaces, etc. For example, communication interface 950 can be connected to computer networks, FireWire buses, etc. In other embodiments, communication interface 950 can be physically integrated onto the motherboard of computer 920 and can be software programs such as softDSL.

[0116] In various embodiments, the computer system 900 may further include software capable of communicating over a network such as HTTP, TCP / IP, RTP / RTSP protocols. In alternative embodiments of this disclosure, other communication software and transport protocols, such as IPX, UDP, etc., may also be used. In some embodiments, the computer 920 includes one or more Xeon microprocessors from Intel as processor 960. Further, in one embodiment, the computer 920 includes a UNIX-based operating system.

[0117] RAM 970 and disk drive 980 are examples of tangible media, such as those in embodiments of this disclosure, configured to store data including executable computer code, human-readable code, etc. Other types of tangible media include: floppy disks, removable hard disks, optical storage media such as CD-ROMs, DVDs, and barcodes, semiconductor memory such as flash memory, non-transitory read-only memory (ROMs), battery-powered volatile memory, network storage devices, etc. RAM 970 and disk drive 980 may be configured to store basic programs and data structures that provide the functionality of this disclosure.

[0118] The software code modules and instructions that provide the functionality of this disclosure can be stored in RAM 970 and disk drive 980. These software modules can be executed by processor 960. RAM 970 and disk drive 980 may also provide a repository for storing data used according to this disclosure.

[0119] The RAM 970 and disk drive 980 may include multiple memories, including main random access memory (RAM) that stores instructions and data during program execution and read-only memory (ROM) that stores fixed, non-transitory instructions. The RAM 970 and disk drive 980 may include a file storage subsystem that provides persistent (non-volatile) storage for programs and data files. The RAM 970 and disk drive 980 may also include removable storage systems, such as removable flash memory.

[0120] The bus subsystem 990 provides a mechanism for enabling the various components and subsystems of the computer 920 to communicate with each other as intended. Although the bus subsystem 990 is schematically shown as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses.

[0121] Figure 9 This describes a computer system capable of implementing the present disclosure. It will be apparent to those skilled in the art that many other hardware and software configurations are suitable for this disclosure. For example, the computer may be a desktop, portable, rack-mount, or tablet computer configuration. Furthermore, the computer may be a network of networked computers. Further, the use of other microprocessors, such as the Pentium... TM or Itanium TM Microprocessor; Opteron from AMD (Advanced MicroDevices, Inc.) TM Or Athlon XP TM Microprocessors, etc. Furthermore, consider other types of operating systems, such as those from Microsoft... Examples include Solaris, LINUX, and UNIX from Sun Microsystems, Inc. In other embodiments, the above techniques can be implemented on a chip or auxiliary processing board.

[0122] The various embodiments of this disclosure can be implemented in the form of logic in software, hardware, or a combination of both. This logic can be stored as a set of instructions in a computer-readable or machine-readable non-transitory storage medium, adapted to instruct a processor of a computer system to perform a set of steps disclosed in the embodiments of this disclosure. This logic can form part of a computer program product adapted to instruct an information processing apparatus to perform a set of steps disclosed in the embodiments of this disclosure. Based on the disclosure and teachings provided herein, those skilled in the art will appreciate other ways and / or methods for implementing this disclosure.

[0123] The data structures and code described herein may be stored, in whole or in part, on computer-readable storage media and / or hardware modules and / or hardware devices. Computer-readable storage media include, but are not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tapes, CDs (optical discs), DVDs (digital versatile optical discs or digital video optical discs), or other media now known or hereafter developed capable of storing code and / or data. Hardware modules or devices described herein include, but are not limited to, ASICs, FPGAs, dedicated or shared processors, and / or other hardware modules or devices now known or hereafter developed.

[0124] The methods and processes described herein can be implemented, in part or in whole, as code and / or data stored in a computer-readable storage medium or device, such that when a computer system reads and runs the code and / or data, the computer system performs the associated methods and processes. These methods and processes can also be implemented, in part or in whole, in hardware modules or devices, such that when the hardware modules or devices are activated, they perform the associated methods and processes. A combination of code, data, and hardware modules or devices can be used to implement the methods and processes disclosed herein.

[0125] Although the foregoing embodiments have been described in detail for purposes of clarity, this disclosure is not limited to the details provided. Many alternative ways of implementing this disclosure exist. The disclosed embodiments are illustrative and not restrictive.

Claims

1. A method for decoding low-density parity-check codewords, i.e., LDPC codewords, said method being implemented by a computer system and comprising: For a first variable node, a first set of check nodes connected to the first variable node and whose parity is satisfied and a second set of check nodes connected to the first variable node and whose parity is not satisfied are determined, wherein the first variable node represents at least one bit of the LDPC codeword and an error has occurred; For the first variable node, determine a second variable node that has an error, is connected to the first variable node via the check node of the first set, and is at least two edges away from the first variable node; Determine a third set of check nodes that are connected to the second variable node and whose parity check is not satisfied; Based on the second set and the third set, determine whether to flip at least one bit represented by the first variable node; and The LDPC codeword is decoded based on whether to flip at least one bit.

2. The method according to claim 1, further comprising: In the decoding iteration, a checksum associated with the first variable node is determined, wherein the third set is determined based on the value of the checksum.

3. The method according to claim 2, further comprising: In another decoding iteration, Determine the updated value of the checksum; The determination of the second variable node is omitted based on the updated value; Determine the updated second set of check nodes that are connected to the first variable node and whose parity check is not satisfied; Based on the updated second set and independently of the third set, determine whether to flip at least one bit represented by the first variable node; and The LDPC codeword is decoded based on a determination of whether to flip at least one bit in a subsequent decoding iteration.

4. The method of claim 1, wherein determining whether to flip the at least one bit comprises: The total number of parity check nodes that have not been satisfied is determined based on the size of the second set and the size of the third set; and The total quantity is compared with a threshold.

5. The method of claim 4, wherein the threshold is defined based on the degree of the first variable node, and wherein determining whether to flip the at least one bit includes determining to flip the at least one bit based on the total number greater than the threshold.

6. The method of claim 1, wherein determining whether to flip the at least one bit comprises: In the decoding iteration: Determine the first energy of the first variable node. ,in: The first energy equal , It is the degree of the first variable node. It comes from the second set and has an index. i The verification node, It is the parity check that is not satisfied and the distance from the first variable node is at least There are 10 edges, and each edge is connected to a set of variable nodes. The fourth set of the check nodes of the variable nodes, At least 3, The set Including those that have errors and are at least [distance] from the first variable node The variable nodes of each edge, and ;and Based on the first energy To update the energy of the first variable node ;and The energy The comparison is made with a threshold, which is defined based on the degree of the first variable node.

7. The method of claim 6, further comprising: In another decoding iteration, it is determined whether to flip at least one bit by at least the following methods: Determine the second energy of the first variable node Instead of the first energy The energy mentioned therein Equal to the second energy ;and The energy Compare with the threshold.

8. The method of claim 7, wherein the second energy is calculated based on the checksum associated with the first variable node. Instead of primary energy .

9. A computer system, comprising: The memory stores low-density parity-check codewords, i.e., LDPC codewords. as well as An LDPC decoder is connected to the memory, and: For a first variable node, a first set of check nodes connected to the first variable node and whose parity is satisfied and a second set of check nodes connected to the first variable node and whose parity is not satisfied are determined, wherein the first variable node represents at least one bit of the LDPC codeword and an error has occurred; For the first variable node, determine a second variable node that has an error, is connected to the first variable node via the check node of the first set, and is at least two edges away from the first variable node; Determine a third set of check nodes that are connected to the second variable node and whose parity check is not satisfied; Based on the second set and the third set, determine whether to flip at least one bit represented by the first variable node; and The LDPC codeword is decoded based on whether to flip at least one bit.

10. The computer system of claim 9, wherein the LDPC decoder further includes: In the decoding iteration, a checksum associated with the first variable node is determined, wherein the third set is determined based on the value of the checksum.

11. The computer system of claim 10, wherein the LDPC decoder further includes: In another decoding iteration, Determine the updated value of the checksum; The determination of the second variable node is omitted based on the updated value; Determine the updated second set of check nodes that are connected to the first variable node and whose parity check is not satisfied; Based on the updated second set and independently of the third set, determine whether to flip at least one bit represented by the first variable node; and The LDPC codeword is decoded based on a determination of whether to flip at least one bit in a subsequent decoding iteration.

12. The computer system of claim 9, wherein determining whether to flip the at least one bit comprises: The total number of parity check nodes that have not been satisfied is determined based on the size of the second set and the size of the third set; and The total quantity is compared with a threshold.

13. The computer system of claim 12, wherein the threshold is defined based on the degree of the first variable node, and wherein determining whether to flip the at least one bit includes determining to flip the at least one bit based on the total number greater than the threshold.

14. The computer system of claim 9, wherein determining whether to flip the at least one bit comprises: During the decoding iteration, Determine the first energy of the first variable node. ,in: The first energy equal , It is the degree of the first variable node. It comes from the second set and has an index. i The verification node, It is the parity check that is not satisfied and the distance from the first variable node is at least There are 10 edges, and each edge is connected to a set of variable nodes. The fourth set of the check nodes of the variable nodes, At least 3, The set Including those that have errors and are at least [distance] from the first variable node The variable nodes of each edge, and ;and Based on the first energy To update the energy of the first variable node ;and The energy The comparison is made with a threshold, which is defined based on the degree of the first variable node.

15. The computer system of claim 14, wherein the LDPC decoder further includes: In another decoding iteration, it is determined whether to flip at least one bit by at least the following methods: Determine the second energy of the first variable node Instead of the first energy The energy mentioned therein Equal to the second energy ;and The energy Compare with the threshold.

16. The computer system of claim 15, wherein the second energy is calculated based on the checksum associated with the first variable node. Instead of primary energy .

17. A non-transitory computer-readable storage medium that stores instructions, when executed on a computer system, causes the computer system to perform operations including: For a first variable node, determine a first set of check nodes connected to the first variable node and whose parity is satisfied, and a second set of check nodes connected to the first variable node and whose parity is not satisfied, wherein the first variable node represents at least one bit of a low-density parity check codeword, i.e., an LDPC codeword, and an error has occurred; For the first variable node, determine a second variable node that has an error, is connected to the first variable node via the check node of the first set, and is at least two edges away from the first variable node; Determine a third set of check nodes that are connected to the second variable node and whose parity check is not satisfied; Based on the second set and the third set, determine whether to flip at least one bit represented by the first variable node; and The LDPC codeword is decoded based on whether to flip at least one bit.

18. The non-transitory computer-readable storage medium of claim 17, wherein the operation further comprises: In the decoding iteration, a checksum associated with the first variable node is determined, wherein the third set is determined based on the value of the checksum.

19. The non-transitory computer-readable storage medium of claim 18, wherein the operation further comprises: In another decoding iteration, Determine the updated value of the checksum; The determination of the second variable node is omitted based on the updated value; Determine the updated second set of check nodes that are connected to the first variable node and whose parity check is not satisfied; Based on the updated second set and independently of the third set, determine whether to flip at least one bit represented by the first variable node; and The LDPC codeword is decoded based on a determination of whether to flip at least one bit in a subsequent decoding iteration.

20. The non-transitory computer-readable storage medium of claim 17, wherein determining whether to flip the at least one bit comprises: The total number of parity check nodes that have not been satisfied is determined based on the size of the second set and the size of the third set; and The total quantity is compared with a threshold, wherein the threshold is defined based on the degree of the first variable node.

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