A new display screen driver power-off method

By controlling the signal timing, especially in the AGO blackout and GIP discharge stages in the driving power-down method of the new display screen, the Q point and Gout are fully discharged, solving the problem of mischarge in the power-down timing of the display panel, and improving the display quality.

CN115547228BActive Publication Date: 2025-04-25CPT TECH GRP
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Patent Information

Application Number
CN202211285788.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-10-20
Publication Date
2025-04-25
Estimated Expiration
2042-10-20

AI Technical Summary

Technical Problem

Existing display panels are prone to mischarge during the down-off timing, resulting in charge residue and display quality degradation.

Method used

By controlling the timing of the signal, especially in the AGO blackening stage and the GIP discharge stage, the full discharge of the Q point and Gout is ensured. The specific method includes opening all Gates for discharge during the AGO black brushing stage, setting the CK signal to GND, the VGL signal to low level, and setting other signals to low level or GND.

Benefits of technology

It effectively reduces the risk of mischarge on the display screen, ensures complete discharge of charge, and improves the display quality of the display screen.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present invention discloses a method for driving and powering off a new display screen, and relates to the technical field of display screen driving. The method comprises: in the AGO black brushing stage, performing black brushing and powering off, setting the CK signal, STV signal, RST signal, FW signal, BW signal and VGL signal to a high level, and discharging the charge in the surface; in the GIP discharge stage, setting the voltage level of the CK signal to GND, setting the voltage level of the VGL signal to a low level, setting the STV signal, RST signal, FW signal, BW signal to a low level and / or GND, to achieve full discharge of the Q point and Gout; after powering off, all signals whose levels are not GND slowly return to GND. The present invention provides a method for driving and powering off a new display screen, which reduces the risk of mischarging of the display screen by controlling the timing setting of the signal and achieving full discharge of the Q point and Gout.
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Description

Technical Field

[0001] The invention relates to the technical field of display screen driving, and in particular to a novel method for driving and powering down a display screen. Background Art

[0002] The gate circuit of the display panel in the prior art is usually divided into three parts, such as Figure 1 As shown, they are: 1. Pre-circuit; 2. Voltage doubling and output circuit; 3. Shutdown and steady-state circuit. In the pre-circuit, the output signals of the previous and next stages of GIP control the switches of T1 and T7, and the FW and BW signals can pass through after turning on. In the voltage doubling and output circuit, the Q point controls the T4 switch. The gate voltage in the display area is after the T4 device is turned on, the current gate CK signal becomes the gate output signal after passing through the T4 device, usually referred to as Gout or G(n). The shutdown and steady-state circuit is used to shut down the GIP circuit and maintain the voltage, which plays a vital role in releasing the charge of the Q point and Gout. The driving timing of the traditional gate circuit composed of these three circuits is shown as follows: Figure 2 shown.

[0003] After the display panel goes through the normal power-off sequence of the gate circuit (such as Figure 3 As shown), multipulse (mischarging) phenomenon often occurs. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a new type of display screen driving power-off method, which reduces the risk of mischarging of the display screen by controlling the timing setting of the signal and achieving sufficient discharge of the Q point and Gout.

[0005] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:

[0006] A novel method for driving and powering off a display screen is applied to a gate circuit, wherein the gate circuit includes a pre-circuit, a voltage doubling and output circuit, and a shutdown and steady-state circuit; in the pre-circuit, a control end of a thin film transistor T1 is connected to an STV signal, and an input end is connected to an FW signal; a control end of a thin film transistor T7 is connected to an RST signal, and an input end is connected to a BW signal; in the voltage doubling and output circuit, a control end of a thin film transistor T4 and one end of a capacitor C1 are both connected to a Q point, an input end of the thin film transistor T4 is connected to a CK signal, and an output end of the thin film transistor T4 and the other end of the capacitor C1 are both connected to Gout; a VGL signal and a CK signal are respectively input to the shutdown and steady-state circuit;

[0007] The method comprises:

[0008] In the AGO black-brushing stage, the black-brushing power-off is executed, and the CK signal, STV signal, RST signal, FW signal, BW signal and VGL signal are all set to high level, and all gates are opened to discharge the charge in the surface;

[0009] In the GIP discharge phase, the voltage level of the CK signal is set to GND, the voltage level of the VGL signal is set to a low level, and the STV signal, the RST signal, the FW signal, and the BW signal are set to a low level and / or GND to achieve full discharge of the Q point and Gout;

[0010] After power off, all signals whose levels are not GND slowly return to GND;

[0011] VCOM and Data are the Source signals input to the display and are set to GND in all power-off stages.

[0012] Optionally, in the GIP discharge phase, the voltage levels of the STV signal and the RST signal are set to GND, and the voltage levels of the FW signal and the BW signal are set to a low level.

[0013] Optionally, in the GIP discharge phase, the voltage levels of the STV signal and the RST signal are set to a low level, and the voltage levels of the FW signal and the BW signal are set to GND.

[0014] Optionally, in the GIP discharge phase, the voltage levels of the STV signal, the RST signal, the FW signal, and the BW signal are all set to low levels.

[0015] Optionally, in the GIP discharge phase, the voltage levels of the STV signal, the RST signal, the FW signal, and the BW signal are all set to GND.

[0016] Optionally, in the GIP discharge phase, the voltage level of any one of the STV signal, the RST signal, the FW signal, and the BW signal is set to GND, and the voltage levels of the other three signals are set to low levels.

[0017] Optionally, in the GIP discharge phase, the voltage level of any one of the STV signal, the RST signal, the FW signal, and the BW signal is set to a low level, and the voltage levels of the other three signals are set to GND.

[0018] The technical solution provided by the present invention has at least the following advantages:

[0019] By opening all Gates during the AGO black-brushing phase of the new power-off sequence, the charge inside the surface can be better discharged. During the GIP discharge phase, it is only necessary to keep the voltage level of the VGL signal at a low level and the CK signal at GND. Regardless of whether the voltage levels of other FW / BW / STV / RST signals are set to GND or a low level, the Q point and Gout can be fully discharged, reducing the risk of mischarging. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0021] Figure 1 It is a schematic diagram of the structure of a gate-level circuit in the prior art;

[0022] Figure 2 It is a schematic diagram of the driving timing of the gate circuit in the prior art;

[0023] Figure 3 It is a schematic diagram of the power-off timing of the gate circuit in the prior art;

[0024] Figure 4 Schematic diagram of power-off timing of the gate circuit in the first embodiment of the present invention;

[0025] Figure 5 FIG. 4 is a schematic diagram of a power-off timing of a gate circuit in a second embodiment of the present invention. DETAILED DESCRIPTION

[0026] The embodiment of the present invention provides a novel method for driving and powering off a display screen, controls the timing setting of signals, and achieves sufficient discharge of the Q point and Gout, thereby reducing the risk of mischarging of the display screen.

[0027] The technical solution in the embodiment of the present invention has the following general idea:

[0028] like Figure 1 As shown in FIG. 1 , the traditional gate circuit is usually divided into three parts: 1. Pre-circuit; 2. Voltage doubling and output circuit; 3. Shutdown and steady-state circuit.

[0029] In the preamplifier circuit, the output signals of the previous and next stages of the GIP circuit control the switches of T1 and T7, and after they are turned on, the FW and BW signals can pass through.

[0030] In the voltage doubling and output circuit, the Q point controls the T4 switch. The gate voltage in the display area is the gate output signal after the T4 device is turned on, which is usually called Gout or G(n).

[0031] The shutdown and steady-state circuits are used to shut down the GIP circuit and maintain the voltage, which is crucial for releasing the charge of the Q point and Gout.

[0032] From the existing gate circuit driving timing ( Figure 2 ) and its general power-off sequence ( Figure 3 ) As can be seen, the panel first uses the SCAN screen to discharge in Stage 1; in Stage 2, except for the FW signal level which is always VGH, all other signals are VGL; in the last stage, all signals return to GND. The inventors found that the Q point and Gout of this power-off sequence are prone to residual charges, which may cause the panel to have a multipulse (wrong charging) phenomenon, affecting the normal display of the panel.

[0033] The defects existing in the above schemes are the results obtained by the inventors after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of the present invention for the above problems below should be the contributions made by the inventors to the present invention during the process of the present invention.

[0034] In order to overcome the defects in the above-mentioned prior art, the inventor provides the following embodiments to provide solutions through research.

[0035] A novel method for driving and powering off a display screen is applied to a gate circuit, wherein the gate circuit includes a pre-circuit, a voltage doubling and output circuit, and a shutdown and steady-state circuit; in the pre-circuit, a control end of a thin film transistor T1 is connected to an STV signal, and an input end is connected to an FW signal; a control end of a thin film transistor T7 is connected to an RST signal, and an input end is connected to a BW signal; in the voltage doubling and output circuit, a control end of a thin film transistor T4 and one end of a capacitor C1 are both connected to a Q point, an input end of the thin film transistor T4 is connected to a CK signal, and an output end of the thin film transistor T4 and the other end of the capacitor C1 are both connected to Gout; a VGL signal and a CK signal are respectively input to the shutdown and steady-state circuit;

[0036] The method comprises:

[0037] In the AGO black-brushing stage, the black-brushing power-off is executed, and the CK signal, STV signal, RST signal, FW signal, BW signal and VGL signal are all set to high level, and all gates are opened to discharge the charge in the surface;

[0038] In the GIP discharge phase, the voltage level of the CK signal is set to GND, the voltage level of the VGL signal is set to a low level, and the STV signal, the RST signal, the FW signal, and the BW signal are set to a low level and / or GND to achieve full discharge of the Q point and Gout;

[0039] After power off, all signals whose levels are not GND slowly return to GND;

[0040] VCOM and Data are the Source signals input to the display screen and are set to GND in all power-off stages to keep the panel free of input.

[0041] In the new drive power-off timing, Stage1 (AGO black brush stage) sets the CK signal, STV signal, RST signal, FW signal, BW signal and VGL signal to a high level (VGH), realizing black brush power-off with all gates open, which can discharge the charge inside the surface better. In Stage2 (GIP discharge stage), the voltage level of FW&BW&VGL signals is a low level (VGL), the CK signal is GND, and the voltage level of STV and RST is GND. At this time, Vgs of T1 and T7>0, both can be turned on, and the Q point is pulled low by the FW and BW signals to fully discharge, and T4 is turned off, Gout stops outputting, and at the same time, the VGL signal can also be used to pull Gout low in the shutdown and steady-state circuits to fully discharge, and finally all signals return to GND, thereby reducing the risk of multipulse (wrong charging).

[0042] In a possible implementation, during the GIP discharge phase, the voltage levels of the STV signal and the RST signal are set to GND, and the voltage levels of the FW signal and the BW signal are set to a low level, such as Figure 4 As shown, this power-off timing can achieve full discharge of Q point and Gout without the occurrence of wrong charging.

[0043] In another possible implementation, during the GIP discharge phase, the voltage levels of the STV signal and the RST signal are set to a low level, and the voltage levels of the FW signal and the BW signal are set to GND. Figure 5 As shown, this power-down timing can still achieve full discharge of Q point and Gout without the occurrence of wrong charging.

[0044] In addition to the above two implementations, setting the voltage levels of any two of the STV signal, RST signal, FW signal, and BW signal to a low level and the other two to GND can achieve sufficient discharge of the Q point and Gout without causing incorrect charging.

[0045] The inventors also verified the above through the following implementations:

[0046] In the GIP discharge phase, the voltage levels of the STV signal, the RST signal, the FW signal, and the BW signal are all set to low levels.

[0047] In the GIP discharge phase, the voltage levels of the STV signal, the RST signal, the FW signal, and the BW signal are all set to GND.

[0048] In the GIP discharge phase, the voltage level of any one of the STV signal, the RST signal, the FW signal, and the BW signal is set to GND, and the voltage levels of the other three signals are set to low levels.

[0049] In the GIP discharge phase, the voltage level of any one of the STV signal, the RST signal, the FW signal, and the BW signal is set to a low level, and the voltage levels of the other three signals are set to GND.

[0050] The verification result shows that the above embodiments can achieve full discharge of Q point and Gout without the occurrence of wrong charging phenomenon.

[0051] The present invention opens all gates in the AGO black brushing stage of the novel power-off timing sequence, thereby better discharging the charges in the surface; in the GIP discharge stage, it is only necessary to keep the voltage level of the VGL signal always at a low level, the CK signal always at GND, and the voltage levels of other FW / BW / STV / RST signals, whether set to GND or a low level, to achieve sufficient discharge of the Q point and Gout and reduce the risk of mischarging.

[0052] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for powering off a display screen, characterized in that: Applied to a gate circuit, the gate circuit includes a preamplifier circuit, a voltage doubling and output circuit, and a shutdown and steady-state circuit; in the preamplifier circuit, the control end of the thin film transistor T1 is connected to the STV signal, and the input end is connected to the FW signal; the control end of the thin film transistor T7 is connected to the RST signal, and the input end is connected to the BW signal; in the voltage doubling and output circuit, the control end of the thin film transistor T4 and one end of the capacitor C1 are both connected to the Q point, the input end of the thin film transistor T4 is connected to the CK signal, and the output end of the thin film transistor T4 and the other end of the capacitor C1 are both connected to Gout; the VGL signal and the CK signal are respectively input into the shutdown and steady-state circuit; The method comprises: In the AGO black-brushing stage, the black-brushing power-off is executed, and the CK signal, STV signal, RST signal, FW signal, BW signal and VGL signal are all set to high level, and all gates are opened to discharge the charge in the surface; In the GIP discharge phase, the voltage level of the CK signal is set to GND, the voltage level of the VGL signal is set to a low level, and the STV signal, the RST signal, the FW signal, and the BW signal are set to a low level and / or GND to achieve full discharge of the Q point and Gout; After power off, all signals whose levels are not GND slowly return to GND; VCOM and Data are the Source signals input to the display and are set to GND in all power-off stages.

2. The method according to claim 1, characterized in that: In the GIP discharge phase, the voltage levels of the STV signal and the RST signal are set to GND, and the voltage levels of the FW signal and the BW signal are set to a low level.

3. The method according to claim 1, characterized in that: In the GIP discharge phase, the voltage levels of the STV signal and the RST signal are set to a low level, and the voltage levels of the FW signal and the BW signal are set to GND.

4. The method according to claim 1, characterized in that: In the GIP discharge phase, the voltage levels of the STV signal, the RST signal, the FW signal, and the BW signal are all set to low levels.

5. The method according to claim 1, characterized in that: In the GIP discharge phase, the voltage levels of the STV signal, the RST signal, the FW signal, and the BW signal are all set to GND.

6. The method according to claim 1, characterized in that: In the GIP discharge phase, the voltage level of any one of the STV signal, the RST signal, the FW signal, and the BW signal is set to GND, and the voltage levels of the other three signals are set to low levels.

7. The method according to claim 1, characterized in that: In the GIP discharge phase, the voltage level of any one of the STV signal, the RST signal, the FW signal, and the BW signal is set to a low level, and the voltage levels of the other three signals are set to GND.

Citation Information

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