Eye pattern judgment circuit applied to memory interface and eye pattern judgment method thereof

Abstract

This application provides an eye diagram determination circuit and method for memory interfaces. The circuit includes: a data comparison control module, a training counting module, an eye diagram determination module, a first register, and a second register. The data comparison control module compares the read data and expected data corresponding to each round of training to obtain the number of error bits in the read data, and generates an increment / decrement control signal for the DQS delay value after each round of comparison. The training counting module adjusts the coarse delay and fine delay based on the increment / decrement control signal, and writes the updated coarse delay and fine delay into the first register. The eye diagram determination module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each round of training and the DQS delay value, and writes them into the second register. This avoids the problems of slow boot speed, high development, debugging, and driver management difficulty, and excessive storage space consumption caused by software-implemented eye diagram determination.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to an eye diagram determination circuit and eye diagram determination method for memory interfaces. Background Technology

[0002] Existing memory interfaces typically use software to implement eye diagram determination during link training to determine the optimal reference voltage and optimal DQS (Bidirectional data strobe) delay during read and write operations. However, the time-consuming software operation significantly impacts system boot speed, and the large amount of software code greatly increases the difficulty of development, debugging, design specifications, and driver management, while also consuming substantial storage space. Summary of the Invention

[0003] This application provides an eye diagram determination circuit and method for memory interfaces to solve the problems of slow system boot speed, high difficulty in development, debugging, design specification and driver management, and large storage space occupation caused by the use of software to implement eye diagram determination in the prior art.

[0004] This application provides an eye diagram determination circuit for a memory interface, the circuit comprising:

[0005] Data comparison control module, training counting module, eye diagram judgment module, first register and second register;

[0006] The data comparison control module is used to compare the difference between the read data and the expected data corresponding to each round of training process to obtain the number of error bits of the read data corresponding to each round of training process, and to generate an increase or decrease control signal for the DQS delay value after each round of comparison.

[0007] The training counting module is used to adjust the coarse delay and fine delay based on the increase / decrease control signal of the DQS delay value, and write the updated coarse delay and fine delay into the first register;

[0008] The eye diagram determination module is used to determine the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each round of training and the DQS delay value, and write the DQS delay values ​​corresponding to the left eye, middle eye, and right eye into the second register.

[0009] According to the eye diagram determination circuit for a memory interface provided in this application, the eye diagram determination module includes:

[0010] Logic switch control circuit, correct count addition / subtraction logic circuit, incorrect count addition / subtraction logic circuit, eye diagram detection and capture logic circuit, and eye diagram dual filtering circuit;

[0011] The logic switch control circuit is used to enable the correct count addition / subtraction logic circuit, the incorrect count addition / subtraction logic circuit, and the eye diagram detection and capture logic circuit based on the eye diagram judgment start signal and the eye diagram judgment end signal.

[0012] The correct count addition / subtraction logic circuit is used to determine the number of consecutive correct data readings during the training process, and the incorrect count addition / subtraction logic circuit is used to determine the number of consecutive incorrect data readings during the training process.

[0013] The eye diagram detection and grasping logic circuit is used to determine the state value of the read data during the training process based on the number of error bits of the read data corresponding to each round of training. The state value includes a first state value corresponding to the correct state and a second state value corresponding to the error state.

[0014] The eye diagram dual filtering circuit is used to filter out abnormal state values ​​caused by faults and determine the DQS delay values ​​corresponding to the left eye, middle eye and right eye respectively, based on the number of consecutive correct data readings, the number of consecutive incorrect data readings, the state value of the data readings, and the DQS delay value corresponding to each round of training.

[0015] According to the eye diagram determination circuit for a memory interface provided in this application, the eye diagram determination circuit further includes a clearing control circuit and an accumulation control circuit;

[0016] The zeroing control circuit is used to zero out the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit based on the eye diagram to determine the end signal and the number of error bits in the read data corresponding to each round of training.

[0017] The accumulation control circuit is used to accumulate and control the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit based on the number of error bits in the read data corresponding to each round of training.

[0018] According to the eye diagram determination circuit for a memory interface provided in this application, the eye diagram determination module further includes a software control circuit, which is used to determine whether to use the eye diagram determination module for automatic eye diagram determination during the training process.

[0019] According to the eye diagram determination circuit for memory interface provided in this application, the first register is a hardware / software readable and writable register, and the second register is a software readable and writable register.

[0020] According to the eye diagram judgment circuit for memory interface provided in this application, each round of training process includes one write operation and one read operation. Accordingly, the expected data is the valid DQ signal corresponding to the write operation, and the read data is the valid DQ signal corresponding to the read operation.

[0021] This application also provides an eye diagram determination method for an eye diagram determination circuit applied to a memory interface, the method comprising:

[0022] Set the number of training iterations, the correct number threshold, and the incorrect number threshold, and start training based on the number of training iterations;

[0023] The data comparison control module compares the differences between the read data and the expected data in each training round to obtain the number of error bits in the read data in each training round and sends it to the eye diagram judgment module.

[0024] The eye diagram determination module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of erroneous bits in the data read during each round of training, the DQS delay value, the correct number threshold, and the error number threshold.

[0025] According to the eye diagram determination method for a memory interface provided in this application, the eye diagram determination module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of erroneous bits of the read data corresponding to each round of training, the DQS delay value, the correct number threshold, and the error number threshold, specifically including:

[0026] The logic switch control circuit enables the correct count addition / subtraction logic circuit, the incorrect count addition / subtraction logic circuit, and the eye diagram detection and capture logic circuit based on the eye diagram judgment start signal and eye diagram judgment end signal.

[0027] The correct count plus / minus logic circuit determines the number of consecutive correct data reads during the training process, and the incorrect count plus / minus logic circuit is used to determine the number of consecutive incorrect data reads during the training process.

[0028] The eye diagram detection and grasping logic circuit determines the state value of the read data during the training process based on the number of error bits of the read data corresponding to each round of training.

[0029] The eye diagram dual filtering circuit filters out abnormal state values ​​caused by faults and determines the DQS delay values ​​corresponding to the left eye, middle eye and right eye respectively, based on the number of consecutive correct data readings, the number of consecutive incorrect data readings, the state value of the data readings, the DQS delay value corresponding to each round of training, as well as the correct number threshold and the incorrect number threshold.

[0030] According to the eye diagram determination method for a memory interface provided in this application, the step of filtering abnormal state values ​​caused by faults and determining the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of consecutive correct data reads, the number of consecutive incorrect data reads, the state value of the read data, the DQS delay value corresponding to each round of training, and the correct number threshold and the incorrect number threshold during training, specifically includes:

[0031] Based on the number of consecutive correct data reads, the number of consecutive incorrect data reads during the training process, and the thresholds for the number of correct reads and the number of incorrect reads, abnormal state values ​​caused by faults are filtered out from the state values ​​of the read data.

[0032] Based on the updated state values ​​of the read data and the DQS delay values ​​corresponding to each round of training, the DQS delay values ​​corresponding to the left eye, middle eye, and right eye are determined respectively.

[0033] According to the eye diagram determination method for a memory interface provided in this application, the determination of the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the updated read data state value and the DQS delay value corresponding to each round of training specifically includes:

[0034] Based on the updated read data state value and the DQS delay value corresponding to each round of training, the DQS delay value corresponding to the left eye and the DQS delay value corresponding to the right eye are determined, and the DQS delay value corresponding to the middle eye is determined based on the comparison result of the DQS delay value corresponding to the left eye and the DQS delay value corresponding to the right eye.

[0035] This application provides an eye diagram determination circuit and method for memory interfaces. The circuit includes a data comparison control module, a training counting module, an eye diagram determination module, a first register, and a second register. The data comparison control module compares the differences between the read data and the expected data corresponding to each round of training to obtain the number of error bits in the read data corresponding to each round of training, and generates an increment / decrement control signal for the DQS delay value after each round of comparison. The training counting module adjusts the coarse delay and fine delay based on the increment / decrement control signal for the DQS delay value, and writes the updated coarse delay and fine delay into the first register. The eye diagram determination module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each round of training and the DQS delay value, and writes the DQS delay values ​​corresponding to the left eye, middle eye, and right eye into the second register. This avoids the problems of slow system boot speed, high difficulty in development, debugging, design specifications, and driver management, and large storage space consumption caused by using software to implement eye diagram determination. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the eye diagram determination circuit for memory interfaces provided in this application;

[0038] Figure 2 This is a schematic diagram of the eye diagram determination module provided in this application;

[0039] Figure 3 This is a comparative diagram of the normal and abnormal situations provided in this application;

[0040] Figure 4 This is a flowchart illustrating the eye diagram determination method for an eye diagram determination circuit applied to a memory interface provided in this application.

[0041] Figure 5 This is a schematic diagram of the physical structure of the electronic device provided in this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] Figure 1 This is a schematic diagram of the eye diagram determination circuit for memory interfaces provided in this application, as shown below. Figure 1 As shown, the circuit includes:

[0044] Data comparison control module, training counting module, eye diagram judgment module, first register and second register;

[0045] The data comparison control module is used to compare the difference between the read data and the expected data corresponding to each round of training process to obtain the number of error bits of the read data corresponding to each round of training process, and to generate an increase or decrease control signal for the DQS delay value after each round of comparison.

[0046] The training counting module is used to adjust the coarse delay and fine delay based on the increase / decrease control signal of the DQS delay value, and write the updated coarse delay and fine delay into the first register;

[0047] The eye diagram determination module is used to determine the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each round of training and the DQS delay value, and write the DQS delay values ​​corresponding to the left eye, middle eye, and right eye into the second register.

[0048] Specifically, the eye diagram determination circuit can be applied to high-speed memory interfaces such as DDR (Double Data Rate SDRAM) and LPDDR (Low Power Double Data Rate SDRAM) to determine the optimal eye diagram during the link training process of the memory interface. Link training includes multiple rounds of training, each round including a corresponding reference voltage value and DQS delay value. That is, for any reference voltage value, training is required under different DQS delay values ​​to obtain the memory scan results. After obtaining the memory scan results corresponding to different DQS delay values ​​under different reference voltage values, a complete memory eye diagram can be generated, thereby determining the optimal reference voltage value and optimal DQS delay value during the read / write process.

[0049] The specific training process for a particular round of training is as follows:

[0050] The memory controller sends a write operation command to the memory and sends a data signal DQ and a data strobe signal DQS to the memory based on the DQS delay value corresponding to the current round. Specifically, the memory controller can adjust the phase of the DQS signal to be written to the memory based on the preset DQS delay value, and then send it to the memory together with the unadjusted DQ signal through the memory interface.

[0051] The memory receives the DQ and DQS signals sent by the memory controller to perform data writing. After the data writing is completed, the memory controller reads the written data from the memory, that is, it obtains the DQ and DQS signals sent by the memory, and then uses the reference voltage value corresponding to the current training round to obtain the memory read operation scan result. Specifically, the acquired DQ signal can be sampled using the acquired DQS signal to obtain a sampling result signal. The voltage of the sampling result signal is compared with the reference voltage value corresponding to the current training round to obtain the memory read operation scan result.

[0052] Based on the above link training process, the eye diagram judgment circuit applied to the memory interface in this embodiment can accurately determine the memory eye diagram and the DQS delay values ​​corresponding to the left eye (i.e., the left boundary of the eye diagram), the middle eye (i.e., the middle position of the eye diagram), and the right eye (i.e., the right boundary of the eye diagram). Specifically:

[0053] After link training begins, the memory controller performs different rounds of write and read operations on the memory based on different combinations of reference voltage and DQS delay values. During a write operation, the memory controller will transmit the data written to the memory (i.e., the valid DQ signal corresponding to the write operation). Figure 1 The data comparison control module sends the exp_data signal (represented by exp_data) to the data comparison control module, so that the data comparison control module compares the exp_data signal as expected data with the read data to determine the number of error bits in the read data corresponding to the current round of training. The read data is the valid DQ signal corresponding to the read operation, that is, the aforementioned sampling result signal. Based on the foregoing, it can be seen that the read data is based on the DQ signal sent by the memory (i.e., Figure 1 (rcv_data) and DQS signal (i.e. Figure 1 The DQ and DQS signals sent by the memory can be forwarded to the data comparison control module by the memory controller, or the data comparison control module can receive them directly from the memory. This embodiment does not specifically limit this. After determining the read data based on the rcv_data and rx_valid signals, the data comparison control module can compare the difference between the read data and the expected data corresponding to the current training round to obtain the number of error bits in the read data corresponding to the current training round. By repeating the above comparison process, the data comparison control module can obtain the number of error bits in the read data corresponding to each training round and transmit the error bit number signal (i.e., rx_valid) of the read data. Figure 1 The bad_cnt value is sent to the eye diagram judgment module.

[0054] After each round of comparison, the data comparison control module is also used to generate control signals for increasing or decreasing the DQS delay value (i.e., Figure 1 The coarse and fine delays (plus and minus) are sent to the training counting module, which adjusts the coarse and fine delays based on the increase / decrease control signal of the DQS delay value, and updates the coarse delay (i.e., the fine delay) to the training counting module. Figure 1 coarse_dly_i) and fine delay (i.e. Figure 1 The `fine_dly_i` signal is written to the first register. The specific writing process is as follows: coarse delayed write enable signals (i.e., `fine_dly_i`) are sent to the first register sequentially. Figure 1 (coarse_dly_i_en) and fine-delay write enable signal (i.e. Figure 1The `fine_dly_i_en` signal enables the coarse and fine delay write functions of the first register. Then, sending `coarse_dly_i` and `fine_dly_i` signals to the first register writes the updated coarse and fine delays. The memory controller determines the DQS delay value for the next training round by reading the updated coarse and fine delays from the first register. It is understood that the coarse delay is used for rapid adjustment of the DQS delay value, and the fine delay is used for fine adjustment. Based on the coarse and fine delays, the DQS delay value for each training round can be accurately controlled. The data comparison control module can also output the case where an error exists (i.e.,...). Figure 1 The middle err) is used to further adjust the coarse and fine delays to ensure the accuracy of the DQS delay value during link training.

[0055] The eye diagram determination module is used to determine the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each training round and the DQS delay value. As can be understood from the foregoing, the number of error bits in the read data corresponding to each training round is obtained by the data comparison control module and sent to the eye diagram determination module. The DQS delay value corresponding to each training round can be determined by the eye diagram determination module by reading the updated coarse and fine delays in the first register. The DQS delay values ​​corresponding to the left eye, middle eye, and right eye are determined based on the number of error bits in the read data and the DQS delay value obtained from different training rounds corresponding to the same reference voltage value. In other words, for different reference voltage values, the DQS delay values ​​corresponding to the left eye, middle eye, and right eye are different. That is, multiple sets of DQS delay values ​​corresponding to the reference voltage value will be generated during link training, and each set of DQS delay values ​​includes the DQS delay values ​​corresponding to the left eye, middle eye, and right eye respectively. Based on this, the optimal reference voltage value and optimal DQS delay value can be accurately determined during the read and write process.

[0056] After determining the DQS delay values ​​for the left, middle, and right eyes based on the number of error bits in the data read during each training round and the DQS delay value, the eye diagram judgment module further writes the DQS delay values ​​for the left, middle, and right eyes into the second register so that the subsequent software can determine the optimal reference voltage value and the optimal DQS delay value based on the DQS delay values ​​for the left, middle, and right eyes.

[0057] Based on the above, it can be seen that the first register needs to support both hardware and software read / write operations, while the second register only needs to support software read / write operations. Therefore, the first register is a hardware and software readable / writable register, and the second register is a software readable / writable register.

[0058] The eye diagram determination circuit for a memory interface provided in this application includes: a data comparison control module, a training counting module, an eye diagram determination module, a first register, and a second register. The data comparison control module compares the difference between the read data and the expected data corresponding to each round of training to obtain the number of error bits in the read data corresponding to each round of training, and generates an increment / decrement control signal for the DQS delay value after each round of comparison. The training counting module adjusts the coarse delay and fine delay based on the increment / decrement control signal for the DQS delay value, and writes the updated coarse delay and fine delay into the first register. The eye diagram determination module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each round of training and the DQS delay value, and writes the DQS delay values ​​corresponding to the left eye, middle eye, and right eye into the second register. This avoids the problems of slow system boot speed, high difficulty in development, debugging, design specifications, and driver management, and large storage space consumption caused by using software to implement eye diagram determination.

[0059] Based on any of the above embodiments Figure 2 This is a schematic diagram of the eye diagram determination module provided in this application, as shown below. Figure 2 As shown, the eye diagram determination module includes:

[0060] Logic switch control circuit, correct count addition / subtraction logic circuit, incorrect count addition / subtraction logic circuit, eye diagram detection and capture logic circuit, and eye diagram dual filtering circuit;

[0061] The logic switch control circuit is used to enable the correct count addition / subtraction logic circuit, the incorrect count addition / subtraction logic circuit, and the eye diagram detection and capture logic circuit based on the eye diagram judgment start signal and the eye diagram judgment end signal.

[0062] The correct count addition / subtraction logic circuit is used to determine the number of consecutive correct data readings during the training process, and the incorrect count addition / subtraction logic circuit is used to determine the number of consecutive incorrect data readings during the training process.

[0063] The eye diagram detection and grasping logic circuit is used to determine the state value of the read data during the training process based on the number of error bits of the read data corresponding to each round of training. The state value includes a first state value corresponding to the correct state and a second state value corresponding to the error state.

[0064] The eye diagram dual filtering circuit is used to filter out abnormal state values ​​caused by faults and determine the DQS delay values ​​corresponding to the left eye, middle eye and right eye respectively, based on the number of consecutive correct data readings, the number of consecutive incorrect data readings, the state value of the data readings, and the DQS delay value corresponding to each round of training.

[0065] Specifically, eye diagrams determine the start signal (i.e.) Figure 2 The eye_margin_judge_start and the eye diagram judgment end signal (i.e. Figure 2 The `eye_margin_judge_done` parameter can be generated by software or hardware based on the progress of link training; this embodiment does not specifically limit this. The logic switch control circuit can determine the time interval for performing eye diagram judgment based on the eye diagram judgment start signal and eye diagram judgment end signal, and generate an eye diagram judgment enable signal (i.e., ...). Figure 2 The `eye_margin_judge_en` function enables the correct count addition / subtraction logic circuit, the incorrect count addition / subtraction logic circuit, and the eye diagram detection and grasping logic circuit.

[0066] The correct count addition / subtraction logic circuit is used to determine the number of consecutive correct data reads during training, and the incorrect count addition / subtraction logic circuit is used to determine the number of consecutive incorrect data reads during training. The correct count addition / subtraction logic circuit can be based on a counter to count the number of correct reads; if bad_cnt (i.e., ...) is detected... Figure 2 rg_bad_cnt_dq0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i[15:0], and Figure 1 In both cases, `bad_cnt` has the same meaning, representing the number of error bits in the read data. When `bad_cnt` is 0, the training result is considered correct. The counter in the correct count increments by 1 until `bad_cnt` is non-zero, at which point the counter is reset to 0. This allows us to obtain the value of the consecutive correct counts. Similarly, the error count increments by a counter. If `bad_cnt` is non-zero, the training result is considered incorrect. The counter in the error count increments by 1 until `bad_cnt` is zero, at which point the counter is reset to 0. This allows us to obtain the value of the consecutive error counts.

[0067] During link training, environmental or circuit failures may cause bad_cnt to deviate from the actual situation. For example, the bad_cnt corresponding to the current DQS delay value may be correct, but when switching to the next DQS delay value, some environmental conditions may cause bad_cnt to be incorrect (i.e., bad_cnt should be 0, but the actual output value is not 0, or bad_cnt should not be 0, but the actual output value is 0). A bad_cnt error will directly lead to an incorrect eye diagram judgment result. Figure 3This is a comparative diagram of normal and abnormal scenarios provided in this application. The normal scenario refers to the case where `bad_cnt` does not contain an error, and the abnormal scenario refers to the case where `bad_cnt` contains an error. For example... Figure 3 As shown, X represents a discrepancy between the alignment result (i.e., the alignment result between the read data and the expected data), and 0 represents a consistent alignment result. Each X or 0 corresponds to one round of training. Based on the received bad_cnt signal, under normal circumstances (i.e., ... Figure 3 The "Normal case" includes the following three situations: 1. Both left and right boundaries exist; 2. Only the right boundary exists; 3. Only the left boundary exists. It is worth noting that in the eye diagrams corresponding to the above normal cases 1-3, there is only one eye. However, when a "bad_cnt" error occurs, such as... Figure 3 As shown, multiple eye abnormalities may occur (i.e.) Figure 3 The abnormal case (comprising three eyes) can lead to situations where the left, middle, and right eyes cannot make a judgment or make an incorrect judgment. Therefore, the hardware design of the eye diagram judgment module not only needs to accurately identify the left, middle, and right boundaries in the normal case, but also needs to identify the abnormal case and filter out false alarms caused by faults or environmental factors. Based on this, the embodiments of this application will pre-set a threshold for the number of correct attempts (i.e., ... Figure 2 (rg_training_eye_margin_gdcnt) and error count threshold (i.e. Figure 2 In the `rg_training_eye_margin_badcnt` parameter, for example, setting `rg_training_eye_margin_gdcnt = 2` means that data will be read correctly at least twice consecutively before being considered correct, while setting `rg_training_eye_margin_badcnt = 3` means that data will be read incorrectly at least three times consecutively before being considered incorrect. Based on this, for... Figure 3 Abnormalities in the diagram can eliminate the two false eyes on the left side caused by abnormalities, thus ensuring the accuracy of eye diagram judgment.

[0068] The eye diagram detection and capture logic circuit is used to determine the number of error bits in the read data corresponding to each round of training (i.e., Figure 2 The `rg_bad_cnt_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i[15:0]` parameter determines the state values ​​of the data read during training. These state values ​​include a first state value corresponding to a correct state (usually represented by a high level, i.e., 1) and a second state value corresponding to an incorrect state (usually represented by a low level, i.e., 0). For example... Figure 2As shown, good_bad_compared_cnt_en_dq0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi is the enable signal. Under the control of the enable signal, the eye diagram detection and capture logic circuit performs an OR logic operation on the input rg_bad_cnt_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i[15:0] signal to generate the dq_err signal. The dq_err signal is 1, which means that the current data read is incorrect, and 0 means that the current data read is correct. Based on this, the eye diagram dual filtering circuit can determine the left eye, middle eye, and right eye based on the dq_err signal. It can be understood that when the dq_err signal changes, it is considered that the left eye or right eye has appeared.

[0069] Based on the foregoing, the eye diagram dual filtering circuit can be based on the number of consecutive correct data reads during training (i.e., Figure 2 (dq_good_cnt[15:0]) and the number of consecutive data read errors (i.e. Figure 2 (dq_bad_cnt[15:0]) and the status value of reading data (i.e. Figure 2 (dq_err) and the DQS delay value corresponding to each round of training (i.e. dq_err) Figure 2 The code snippet shows that `ctc_fine_dly_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i[15:0]` and `ctc_coarse_dly_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i[15:0]` filter out abnormal state values ​​caused by faults and determine the DQS delay values ​​corresponding to the left eye, middle eye, and right eye, respectively. Figure 2 The eye diagram dual filtering circuit is based on the number of consecutive correct data reads, the number of consecutive incorrect data reads, and the threshold for the number of correct reads during training (i.e., rg_left_eye_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i[15:0], rg_mid_eye_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i[15:0]). Figure 2 rg_training_eye_margin_gdcnt[7:0]) and error count threshold (i.e. Figure 2The `rg_training_eye_margin_bdcnt[7:0]` function filters out abnormal state values ​​caused by faults in the state values ​​of the read data. Then, based on the updated state values ​​of the read data and the DQS delay values ​​corresponding to each round of training, the DQS delay values ​​corresponding to the left eye, middle eye, and right eye are determined. It is understood that the filtering can either directly delete the corresponding abnormal state values ​​or mask the abnormal state values, i.e., not use the abnormal state values ​​for eye diagram judgment.

[0070] Simultaneously, the eye diagram dual filtering circuit also includes middle eye calculation logic. The middle eye's delay value is calculated only when the DQS delay value corresponding to the left eye is less than the DQS delay value corresponding to the right eye. Based on the foregoing, when the dq_err signal changes, it indicates the presence of either the left or right eye. Each training round has corresponding coarse and fine delays, allowing for accurate determination of the DQS delay values ​​for the left, middle, and right eyes. It's understood that the DQS delay value corresponding to the left eye is always less than the DQS delay value corresponding to the right eye on the eye diagram. Therefore, if the DQS delay value corresponding to the right eye is determined to be not less than the DQS delay value corresponding to the left eye, it indicates an eye diagram recognition error. This ensures the accuracy of the eye diagram judgment logic.

[0071] The output signal of the eye diagram dual filtering circuit also includes an output enable signal for the eye diagram judgment result (i.e. Figure 2 The parameters rg_left_eye_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i_en, rg_right_eye_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i_en, and rg_mid_eye_dq 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi_i_en are used to instruct the software to read the eye diagram judgment results and determine the optimal reference voltage value and optimal DQS delay value during the read / write process.

[0072] This application provides an eye diagram determination circuit for a memory interface. The eye diagram determination module includes: a logic switch control circuit, a correct count addition / subtraction logic circuit, an incorrect count addition / subtraction logic circuit, an eye diagram detection and capture logic circuit, and an eye diagram dual filtering circuit. The logic switch control circuit enables the correct count addition / subtraction logic circuit, the incorrect count addition / subtraction logic circuit, and the eye diagram detection and capture logic circuit based on an eye diagram determination start signal and an eye diagram determination end signal. The correct count addition / subtraction logic circuit determines the number of consecutive correct data reads during training, and the incorrect count addition / subtraction logic circuit determines the number of consecutive incorrect data reads during training. The eye diagram detection and capture logic circuit... The eye diagram dual filtering circuit is used to determine the state value of the read data during the training process based on the number of error bits of the read data corresponding to each round of training. The state value includes a first state value corresponding to the correct state and a second state value corresponding to the error state. The eye diagram dual filtering circuit is used to filter abnormal state values ​​caused by faults and determine the DQS delay values ​​corresponding to the left eye, middle eye and right eye respectively based on the number of consecutive correct read data, the number of consecutive incorrect read data, the state value of the read data and the DQS delay value corresponding to each round of training. It can accurately determine the DQS delay values ​​corresponding to the left eye, middle eye and right eye in the eye diagram, so as to accurately determine the optimal reference voltage value and the optimal DQS delay value during the read and write process.

[0073] Based on any of the above embodiments, the eye diagram determination circuit further includes a clearing control circuit and an accumulation control circuit;

[0074] The zeroing control circuit is used to zero out the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit based on the eye diagram to determine the end signal and the number of error bits in the read data corresponding to each round of training.

[0075] The accumulation control circuit is used to accumulate and control the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit based on the number of error bits in the read data corresponding to each round of training.

[0076] Specifically, through the enable signal (i.e. Figure 2 The control circuit for good_bad_compared_cnt_en_dq0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / dmi) can, based on the eye diagram to determine the end signal and the number of error bits in the read data corresponding to each round of training, respectively, clear the count values ​​corresponding to the correct count addition / subtraction logic circuit and the error count addition / subtraction logic circuit. At the same time, based on the number of error bits in the read data corresponding to each round of training, it can accumulate the count values ​​corresponding to the correct count addition / subtraction logic circuit and the error count addition / subtraction logic circuit.

[0077] The eye diagram judgment circuit for a memory interface provided in this application embodiment further includes a clearing control circuit and an accumulation control circuit. The clearing control circuit is used to clear the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit based on the eye diagram judgment end signal and the number of error bits of the read data corresponding to each round of training. The accumulation control circuit is used to accumulate the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit based on the number of error bits of the read data corresponding to each round of training. This allows for accurate accumulation control and clearing of the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit, ensuring continuous correct read data and accuracy of the number of errors.

[0078] Based on any of the above embodiments, the eye diagram judgment module further includes a software control circuit, which is used to determine whether to use the eye diagram judgment module to automatically judge the eye diagram during the training process.

[0079] Specifically, the eye diagram judgment circuit not only has the function of hardware eye diagram judgment, but also has software control function. This function is applicable to software judgment methods for eye diagrams. More specifically, in this embodiment, a software control circuit is set in the eye diagram judgment module. The value of the input signal rg_sw_every_step_polling determines whether to use hardware or software for eye diagram judgment. When rg_sw_every_step_polling=0, the hardware automatic eye diagram judgment logic is used; when rg_sw_every_step_polling=1, the value of bad_cnt is read by software and the eye diagram is judged by software, that is, the eye diagram judgment module is not used. The output signal of the software control circuit (i.e. Figure 2 The parameters rg_sw_eye_margin_polling_i and rg_sw_eye_margin_polling_i_en are used to indicate when the software algorithm should intervene. Based on this, the flexibility of eye diagram judgment can be improved.

[0080] Figure 4 This is a flowchart illustrating the eye diagram determination method for an eye diagram determination circuit applied to a memory interface provided in this application. Figure 4 As shown, the method includes:

[0081] Step 101: Set the number of training iterations, the correct number threshold, and the incorrect number threshold, and start training based on the number of training iterations;

[0082] Step 102: The data comparison control module compares the difference between the read data and the expected data corresponding to each round of training to obtain the number of error bits of the read data corresponding to each round of training and sends it to the eye diagram judgment module.

[0083] Step 103: The eye diagram determination module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of erroneous bits in the data read during each round of training, the DQS delay value, the correct number threshold, and the error number threshold.

[0084] Specifically, the number of training rounds refers to the number of training cycles. As can be seen from the foregoing embodiments, link training includes multiple training cycles. Therefore, the start and end conditions of link training can be determined by pre-setting the number of training rounds. The principle and effect of the eye diagram judgment method of this application have been described in detail in the foregoing embodiments and will not be repeated here.

[0085] The method provided in this application embodiment sets the number of training iterations, a correct iteration threshold, and an incorrect iteration threshold, and starts training based on the number of training iterations. The data comparison control module compares the differences between the read data and the expected data corresponding to each round of training to obtain the number of error bits in the read data corresponding to each round of training and sends it to the eye diagram judgment module. The eye diagram judgment module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each round of training, the DQS delay value, the correct iteration threshold, and the incorrect iteration threshold. This method can ensure the accuracy of eye diagram judgment while avoiding the problems of slow system startup speed, high difficulty in development, debugging, design specifications, and driver management, and large storage space consumption caused by using software to implement eye diagram judgment.

[0086] Based on any of the above embodiments, the eye diagram determination module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of erroneous bits in the data read during each round of training, the DQS delay value, the correct number threshold, and the error number threshold, specifically including:

[0087] The logic switch control circuit enables the correct count addition / subtraction logic circuit, the incorrect count addition / subtraction logic circuit, and the eye diagram detection and capture logic circuit based on the eye diagram judgment start signal and eye diagram judgment end signal.

[0088] The correct count plus / minus logic circuit determines the number of consecutive correct data reads during the training process, and the incorrect count plus / minus logic circuit is used to determine the number of consecutive incorrect data reads during the training process.

[0089] The eye diagram detection and grasping logic circuit determines the state value of the read data during the training process based on the number of error bits of the read data corresponding to each round of training.

[0090] The eye diagram dual filtering circuit filters out abnormal state values ​​caused by faults and determines the DQS delay values ​​corresponding to the left eye, middle eye and right eye respectively, based on the number of consecutive correct data readings, the number of consecutive incorrect data readings, the state value of the data readings, the DQS delay value corresponding to each round of training, as well as the correct number threshold and the incorrect number threshold.

[0091] Based on any of the above embodiments, the step of filtering abnormal state values ​​caused by faults and determining the DQS delay values ​​corresponding to the left eye, middle eye, and right eye respectively, based on the number of consecutive correct data readings, the number of consecutive incorrect data readings, the state value of the data readings, the DQS delay value corresponding to each round of training, and the correct number threshold and the incorrect number threshold, specifically includes:

[0092] Based on the number of consecutive correct data reads, the number of consecutive incorrect data reads during the training process, and the thresholds for the number of correct reads and the number of incorrect reads, abnormal state values ​​caused by faults are filtered out from the state values ​​of the read data.

[0093] Based on the updated state values ​​of the read data and the DQS delay values ​​corresponding to each round of training, the DQS delay values ​​corresponding to the left eye, middle eye, and right eye are determined respectively.

[0094] Based on any of the above embodiments, determining the DQS latency values ​​corresponding to the left eye, middle eye, and right eye based on the updated read data state value and the DQS latency values ​​corresponding to each round of training specifically includes:

[0095] Based on the updated read data state value and the DQS delay value corresponding to each round of training, the DQS delay value corresponding to the left eye and the DQS delay value corresponding to the right eye are determined, and the DQS delay value corresponding to the middle eye is determined based on the comparison result of the DQS delay value corresponding to the left eye and the DQS delay value corresponding to the right eye.

[0096] Specifically, the principles and effects have been explained in detail in the foregoing embodiments, and will not be repeated here.

[0097] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5As shown, the electronic device may include: a processor 201, a communication interface 202, a memory 203, and a communication bus 204, wherein the processor 201, the communication interface 202, and the memory 203 communicate with each other through the communication bus 204. The processor 201 can call logic instructions in the memory 203 to execute the eye diagram judgment method for the eye diagram judgment circuit applied to the memory interface provided by the above methods. The method includes: setting the number of training iterations, a correct number threshold, and an incorrect number threshold, and starting training based on the number of training iterations; a data comparison control module comparing the difference between the read data and the expected data corresponding to each round of training to obtain the number of error bits of the read data corresponding to each round of training and sending it to the eye diagram judgment module; the eye diagram judgment module determining the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits of the read data corresponding to each round of training, the DQS delay value, the correct number threshold, and the incorrect number threshold.

[0098] Furthermore, the logical instructions in the aforementioned memory 203 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks.

[0099] On the other hand, this application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the eye diagram judgment method for the eye diagram judgment circuit applied to the memory interface provided by the above methods. The method includes: setting the number of training iterations, a correct iteration threshold, and an incorrect iteration threshold, and starting training based on the number of training iterations; a data comparison control module comparing the difference between the read data and the expected data corresponding to each round of training to obtain the number of error bits of the read data corresponding to each round of training and sending it to the eye diagram judgment module; and the eye diagram judgment module determining the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits of the read data corresponding to each round of training, the DQS delay value, the correct iteration threshold, and the incorrect iteration threshold.

[0100] In another aspect, this application also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements an eye diagram determination method for an eye diagram determination circuit applied to a memory interface, as provided by the methods described above. The method includes: setting a training count, a correct count threshold, and an incorrect count threshold, and starting training based on the training count; a data comparison control module comparing the differences between the read data and the expected data corresponding to each round of training to obtain the number of error bits in the read data corresponding to each round of training and sending it to the eye diagram determination module; and the eye diagram determination module determining the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each round of training, the DQS delay value, the correct count threshold, and the incorrect count threshold.

[0101] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0102] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An eye pattern judgment circuit applied to a memory interface, characterized by, The circuit includes: Data comparison control module, training counting module, eye diagram judgment module, first register and second register; The data comparison control module is used to compare the difference between the read data and the expected data corresponding to each round of training process to obtain the number of error bits of the read data corresponding to each round of training process, and to generate an increase or decrease control signal for the DQS delay value after each round of comparison. The training counting module is used to adjust the coarse delay and fine delay based on the increase / decrease control signal of the DQS delay value, and write the updated coarse delay and fine delay into the first register; The eye diagram determination module is used to determine the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each training round and the DQS delay value. The DQS delay value corresponding to each training round can be determined by the eye diagram determination module by reading the updated coarse delay and fine delay in the first register, and the DQS delay values ​​corresponding to the left eye, middle eye, and right eye are written into the second register. The eye diagram determination module also includes a software control circuit, which is used to determine whether to use the eye diagram determination module for automatic eye diagram determination during the training process.

2. The eye pattern judgment circuit applied to a memory interface according to claim 1, wherein, The eye diagram determination module includes: Logic switch control circuit, correct count addition / subtraction logic circuit, incorrect count addition / subtraction logic circuit, eye diagram detection and capture logic circuit, and eye diagram dual filtering circuit; The logic switch control circuit is used to enable the correct count addition / subtraction logic circuit, the incorrect count addition / subtraction logic circuit, and the eye diagram detection and capture logic circuit based on the eye diagram judgment start signal and the eye diagram judgment end signal. The correct count addition / subtraction logic circuit is used to determine the number of consecutive correct data readings during the training process, and the incorrect count addition / subtraction logic circuit is used to determine the number of consecutive incorrect data readings during the training process. The eye diagram detection and grasping logic circuit is used to determine the state value of the read data during the training process based on the number of error bits of the read data corresponding to each round of training. The state value includes a first state value corresponding to the correct state and a second state value corresponding to the error state. The eye diagram dual filtering circuit is used to filter out abnormal state values ​​caused by faults and determine the DQS delay values ​​corresponding to the left eye, middle eye and right eye respectively, based on the number of consecutive correct data readings, the number of consecutive incorrect data readings, the state value of the data readings, and the DQS delay value corresponding to each round of training.

3. The eye pattern judgment circuit applied to a memory interface according to claim 2, wherein, The eye diagram determination circuit also includes a zeroing control circuit and an accumulation control circuit; The zeroing control circuit is used to zero out the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit based on the eye diagram to determine the end signal and the number of error bits in the read data corresponding to each round of training. The accumulation control circuit is used to accumulate and control the count values ​​corresponding to the correct count addition / subtraction logic circuit and the incorrect count addition / subtraction logic circuit based on the number of error bits in the read data corresponding to each round of training.

4. The eye pattern judgment circuit applied to a memory interface according to claim 3, wherein, The first register is a hardware / software readable and writable register, and the second register is a software readable and writable register.

5. The eye pattern judgment circuit applied to a memory interface according to claim 4, wherein, Each training round includes one write operation and one read operation. Accordingly, the expected data is the valid DQ signal corresponding to the write operation, and the read data is the valid DQ signal corresponding to the read operation.

6. An eye pattern judgment method for an eye pattern judgment circuit applied to a memory interface based on the application of claim 5, characterized by, The method includes: Set the number of training iterations, the correct number threshold, and the incorrect number threshold, and start training based on the number of training iterations; The data comparison control module compares the differences between the read data and the expected data in each training round to obtain the number of error bits in the read data in each training round and sends it to the eye diagram judgment module. The eye diagram determination module determines the DQS delay value based on the number of error bits in the data read during each training round, the DQS delay value, the correct number threshold, and the error number threshold. The DQS delay value for each training round can be determined by the eye diagram determination module by reading the updated coarse and fine delays in the first register, thus determining the DQS delay values ​​for the left eye, middle eye, and right eye respectively.

7. The eye pattern judgment method for the eye pattern judgment circuit applied to the memory interface according to claim 6, wherein The eye diagram determination module determines the DQS latency values ​​for the left eye, middle eye, and right eye based on the number of erroneous bits in the data read during each training round, the DQS latency value, the correct number threshold, and the error number threshold. Specifically, this includes: The logic switch control circuit enables the correct count addition / subtraction logic circuit, the incorrect count addition / subtraction logic circuit, and the eye diagram detection and capture logic circuit based on the eye diagram judgment start signal and eye diagram judgment end signal. The correct count plus / minus logic circuit determines the number of consecutive correct data reads during the training process, and the incorrect count plus / minus logic circuit is used to determine the number of consecutive incorrect data reads during the training process. The eye diagram detection and grasping logic circuit determines the state value of the read data during the training process based on the number of error bits in the read data corresponding to each round of training. The eye diagram dual filtering circuit filters out abnormal state values ​​caused by faults and determines the DQS delay values ​​corresponding to the left eye, middle eye and right eye respectively, based on the number of consecutive correct data readings, the number of consecutive incorrect data readings, the state value of the data readings, the DQS delay value corresponding to each round of training, as well as the correct number threshold and the incorrect number threshold.

8. The eye diagram determination method for an eye diagram determination circuit applied to a memory interface according to claim 7, characterized in that, The method, based on the number of consecutive correct data reads, the number of consecutive incorrect data reads, the state value of the data reads, the DQS latency value corresponding to each round of training, and the correct and incorrect count thresholds, filters out abnormal state values ​​caused by faults and determines the DQS latency values ​​corresponding to the left, middle, and right eyes, specifically includes: Based on the number of consecutive correct data reads, the number of consecutive incorrect data reads during the training process, and the thresholds for the number of correct reads and the number of incorrect reads, abnormal state values ​​caused by faults are filtered out from the state values ​​of the read data. Based on the updated state values ​​of the read data and the DQS delay values ​​corresponding to each round of training, the DQS delay values ​​corresponding to the left eye, middle eye, and right eye are determined respectively.

9. The eye diagram determination method for an eye diagram determination circuit applied to a memory interface according to claim 8, characterized in that, The determination of the DQS latency values ​​for the left eye, middle eye, and right eye based on the updated read data state values ​​and the DQS latency values ​​corresponding to each round of training includes: Based on the updated read data state value and the DQS delay value corresponding to each round of training, the DQS delay value corresponding to the left eye and the DQS delay value corresponding to the right eye are determined, and the DQS delay value corresponding to the middle eye is determined based on the comparison result of the DQS delay value corresponding to the left eye and the DQS delay value corresponding to the right eye.

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