Memory device with multiple input / output interfaces

By introducing multiple I/O interfaces and channel configurations into the memory subsystem, the problem of limited bandwidth of a single I/O interface is solved, achieving optimized bandwidth utilization and physical space saving for both high-density and low-density systems.

CN115933967BActive Publication Date: 2026-06-19MICRON TECHNOLOGY INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
MICRON TECHNOLOGY INC
Filing Date
2022-08-25
Publication Date
2026-06-19

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Abstract

This application relates to a memory device having multiple input / output interfaces. A memory device includes: a first plane group including a first plane; a second plane group including a second plane; a first input / output (I / O) interface configured to access the first plane group; and a second I / O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I / O interface via a first channel and operatively coupled to the second I / O interface via a second channel. The controller can transmit a first command via the first channel to the first I / O interface to perform a first memory access operation associated with the first plane. The controller can transmit a second command via the second channel to the second I / O interface to perform a second memory access operation associated with the second plane.
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Citation Information

Patent Citations

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