An encoding modulation method, a decoding method and related devices

Abstract

This application discloses an encoding and modulation method, a decoding method, and related equipment, which provides an encoding and modulation method that can adjust the spectral efficiency of the encoding system and achieve better encoding performance. The method of this application includes: the encoding device dividing target bit information into a first bit set and a second bit set; the encoding device generating amplitude bits from the first bit set and phase bits from the second bit set using a distribution matching algorithm; and the encoding device transforming the amplitude bits and phase bits into corresponding four-dimensional symbol information according to a D4Lattice isomorphic constellation diagram.

Description

Technical Field

[0001] This application relates to the field of data processing, and in particular to an encoding and modulation method, a decoding method, and related equipment. Background Technology

[0002] Coding and modulation techniques are fundamental to optical transmission, directly determining its capacity and performance limits. For ultra-long-distance, high-performance transmission scenarios, low-order modulation formats are typically used, and appropriate coding and modulation architectures are designed to achieve stable, high-performance transmission with relatively low spectral efficiency (SE).

[0003] For low SE (Sequence Shift) coding and modulation scenarios, existing coding and modulation methods mainly utilize quadrature phase shift keying (QPSK) technology. The constellation diagram of QPSK is an integer lattice (Z2Lattice). Specifically, the encoding device uses a forward error correction (FEC) encoder to obtain coded bits from the input information bits. The coded bits are then passed through a bit interleaver to obtain interleaved bits, which are then mapped to modulation symbols using a Gray mapping.

[0004] When using quadrature phase shift keying (QPSK) for encoding and modulation, on the one hand, because the encoding device cannot adjust redundancy through probabilistic constellation diagram shaping, the transmission rate achievable by the encoding device for a given FEC is also fixed, and the encoding device cannot tune the transmission rate of the entire system. On the other hand, since the constellation diagram of QPSK is based on integer lattice Z2 lattices, and integer lattice Z2 lattices are not the most compact arrangement in a two-dimensional plane, the encoding performance achievable by the encoding device is also limited. Summary of the Invention

[0005] This application provides an encoding modulation method, a decoding method, and related equipment, which are used to provide an encoding modulation method that can adjust the spectral efficiency of the encoding system and has better encoding performance.

[0006] The first aspect of this application provides a coding modulation method, which can adjust the spectral efficiency of the coding system and has better coding performance. The method includes: a coding device dividing target bit information into a first bit set and a second bit set; the coding device generating amplitude bits from the first bit set and generating phase bits from the second bit set using a distribution matching algorithm; and the coding device transforming the amplitude bits and phase bits into corresponding four-dimensional symbol information according to a D4 Lattice isomer constellation diagram.

[0007] In this possible implementation, the encoding device selects a constellation diagram based on 4D space D4 Lattice, which has a higher density and lower average energy than traditional integer lattice points, resulting in better performance of the encoding device. At the same time, the encoding device generates amplitude bits from the first bit set through a distribution matching algorithm. Since the distribution matching algorithm is a probabilistic shaping technique, the encoding device can adjust the redundancy through probabilistic constellation diagram shaping, thereby enabling the encoding device to tune the transmission rate of the entire system and have flexible adjustment capabilities.

[0008] In one possible implementation of the first aspect, the method further includes: the encoding device determining a constellation diagram of D4Lattice isomers.

[0009] In one possible implementation of the first aspect, the encoding device determines the constellation diagram of the D4 Lattice isomer by: the encoding device transforming D4 Lattice into D4 Lattice isomers through a linear transformation, wherein the D4 Lattice isomers do not pass through the origin and are centrally symmetric; and the encoding device determining the two lattice layers with the lowest energy in the D4 Lattice isomers as the constellation diagram of the D4 Lattice isomers.

[0010] This possible implementation specifically provides a method for the encoding device to determine the constellation diagram, improving the feasibility of the embodiments of this application. Furthermore, since the D4 Lattice constellation diagram used is centrally symmetrical with only 1 and 3 coordinates for each dimension of the symbol, it is fully compatible with existing digital signal processing algorithms. Therefore, implementing this application does not require much modification to the encoding system, and the implementation cost is very low.

[0011] In one possible implementation of the first aspect, the encoding device generates amplitude bits based on a first bit set and phase bits based on a second bit set, comprising: the encoding device encoding the first bit set into amplitude bits using a distribution matching algorithm; the encoding device encoding the amplitude bits into parity bits using a first forward error correction code; and the encoding device encoding the second bit set into phase bits using a second forward error correction code, wherein the phase bits include parity bits.

[0012] In this possible implementation, the encoding device generates amplitude bits from the first bit set using a distribution matching algorithm. Since the distribution matching algorithm is a probabilistic shaping technique, the encoding device can adjust the redundancy through probabilistic constellation diagram shaping, thereby enabling the encoding device to tune the transmission rate of the entire system and have flexible adjustment capabilities.

[0013] In one possible implementation of the first aspect, the second bit set includes a first bit block and a second bit block, and the encoding device encodes the second bit set into phase bits using a second forward error correction code, including: the encoding device encodes the first bit block into a first phase bit using a second forward error correction code; the encoding device encodes the second bit block into a second phase bit using a third forward error correction code, the second phase bit including a parity bit; and the encoding device determines the phase bit based on the first phase bit and the second phase bit.

[0014] In this possible implementation, a three-level coding and modulation scheme can be used for the variable-length phase bits. Demodulation and decoding begin with the bit with the highest received quality (lowest pre-correction bit error rate), and prior information from correctly decoded bits assists subsequent decoding. Traditional multi-level coding and modulation systems begin demodulation and decoding with bits having a high pre-correction bit error rate; compared to traditional coding and modulation schemes, this invention can improve overall system performance under the same FEC overhead.

[0015] In one possible implementation of the first aspect, the phase bit includes five bits. If the parity bit is 0, the encoding device transforms the amplitude bit and the phase bit into corresponding four-dimensional symbol information according to the D4 Lattice heterogeneous constellation diagram, including: the encoding device transforms the first to third bits of the phase bit into corresponding four-dimensional symbol information according to the D4 Lattice heterogeneous constellation diagram.

[0016] In this possible implementation, the embodiment of this application uses a non-redundant 3-bit variable-length encoding for the symbol phase, which greatly reduces encoding redundancy. Correspondingly, at the same symbol entropy, the FEC bit throughput is significantly reduced, and the power consumption and complexity of decoding are also significantly reduced.

[0017] In one possible implementation of the first aspect, the phase bit includes five bits. If the parity bit is 1, the encoding device transforms the amplitude bit and the phase bit into corresponding four-dimensional symbol information according to the D4 Lattice heterogeneous constellation diagram, including: the encoding device transforms the first to fifth bits of the phase bit into corresponding four-dimensional symbol information according to the D4 Lattice heterogeneous constellation diagram.

[0018] In this possible implementation, the embodiment of this application uses a non-redundant 5-bit variable-length encoding for the symbol phase, which greatly reduces encoding redundancy. Correspondingly, with the same symbol entropy, the FEC bit throughput is significantly reduced, and the power consumption and complexity of decoding are also significantly reduced.

[0019] A second aspect of this application provides a decoding modulation method. This method is used to provide a decoding modulation method that can adjust the spectral efficiency of the coding system and has better decoding performance. The method includes: a decoding device demodulating received four-dimensional symbol information into the log-likelihood ratio of amplitude bits through first-level demodulation; the decoding device decoding the log-likelihood ratio of amplitude bits into amplitude bits through a first forward error correction code; the decoding device decoding the amplitude bits into a first bit set through a distribution matching algorithm; the decoding device demodulating the log-likelihood ratio of phase bits from the amplitude bits as prior information through second-level demodulation; the decoding device decoding the log-likelihood ratio of phase bits into a second bit set through a second forward error correction code; and the decoding device determining target bit information based on the first bit set and the second bit set.

[0020] A third aspect of this application provides a decoding modulation method. This method is used to provide a decoding modulation method that can adjust the spectral efficiency of the coding system and has better decoding performance. The second bit set includes a first bit block and a second bit block. The method includes: a decoding device demodulating the received four-dimensional symbol information into the log-likelihood ratio of the first phase bits through a first-level demodulation; the decoding device decoding the log-likelihood ratio of the first phase bits into the first phase bits through a second forward error correction code; the decoding device demodulating the first phase bits as prior information to obtain the log-likelihood ratio of the amplitude bits through a second-level demodulation; the decoding device decoding the log-likelihood ratio of the amplitude bits into the amplitude bits through a first forward error correction code; the decoding device decoding the amplitude bits into the first bit set through a distribution matching algorithm; the decoding device demodulating the first phase bits as prior information to obtain the log-likelihood ratio of the second phase bits through a third-level demodulation; the decoding device decoding the log-likelihood ratio of the second phase bits to determine the second bit set through a third forward error correction code; and the decoding device determining target bit information based on the first bit set and the second bit set.

[0021] A fourth aspect of this application provides an encoding device that has the function of implementing the method described in the first aspect or any possible implementation of the first aspect. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described function, such as a transformation module.

[0022] A fifth aspect of this application provides a testing device that has the function of implementing the method of the second aspect or any possible implementation of the second aspect described above. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above function, such as a determination module.

[0023] A sixth aspect of this application provides a testing device that has the function of implementing the method of the third aspect or any possible implementation of the third aspect. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described function, such as a determination module.

[0024] The seventh aspect of this application provides a detection device, which includes at least one processor, a memory, an input / output (I / O) interface, and computer-executable instructions stored in the memory and executable on the processor. When the computer-executable instructions are executed by the processor, the processor executes a method as described in the first aspect or any possible implementation thereof.

[0025] The eighth aspect of this application provides a detection device, which includes at least one processor, a memory, an input / output (I / O) interface, and computer-executable instructions stored in the memory and executable on the processor. When the computer-executable instructions are executed by the processor, the processor executes the method as described in the second aspect above.

[0026] The ninth aspect of this application provides a detection device, which includes at least one processor, a memory, an input / output (I / O) interface, and computer-executable instructions stored in the memory and executable on the processor. When the computer-executable instructions are executed by the processor, the processor executes the method as described in the third aspect above.

[0027] The tenth aspect of this application provides a computer-readable storage medium storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor performs a method as described in the first aspect or any possible implementation thereof.

[0028] The eleventh aspect of this application provides a computer-readable storage medium for storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor performs the method as described in the second aspect above.

[0029] The twelfth aspect of this application provides a computer-readable storage medium storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor performs the method as described in the third aspect above.

[0030] The thirteenth aspect of this application provides a computer program product that stores one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor executes a method as described in the first aspect or any possible implementation thereof.

[0031] The fourteenth aspect of this application provides a computer program product that stores one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor executes the method of the second aspect described above.

[0032] The fifteenth aspect of this application provides a computer program product that stores one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor executes the method described in the third aspect above.

[0033] The sixteenth aspect of this application provides a chip system including at least one processor for implementing the functions involved in the first aspect or any possible implementation thereof. In one possible design, the chip system may further include a memory for storing program instructions and data necessary for processing artificial intelligence models. The chip system may be composed of chips or may include chips and other discrete devices.

[0034] The seventeenth aspect of this application provides a chip system including at least one processor for implementing the functions described in the second aspect above. In one possible design, the chip system may further include a memory for storing program instructions and data necessary for processing artificial intelligence models. This chip system may be composed of chips or may include chips and other discrete devices.

[0035] The eighteenth aspect of this application provides a chip system including at least one processor for implementing the functions described in the third aspect above. In one possible design, the chip system may further include a memory for storing program instructions and data necessary for processing artificial intelligence models. This chip system may be composed of chips or may include chips and other discrete devices.

[0036] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0037] In this embodiment, the encoding device divides the target bit information into a first bit set and a second bit set. The encoding device generates amplitude bits from the first bit set and phase bits from the second bit set using a distributed matching algorithm. The encoding device then transforms the amplitude bits and phase bits into corresponding four-dimensional symbol information based on a D4 Lattice heterogeneous constellation diagram. The encoding device selects a constellation diagram based on 4D D4 Lattice, which has a higher density and lower average energy compared to traditional integer lattice points, resulting in superior encoding performance. Simultaneously, the encoding device generates amplitude bits from the first bit set using a distributed matching algorithm. Since the distributed matching algorithm is a probabilistic shaping technique, the encoding device can adjust redundancy through probabilistic constellation diagram shaping, thereby enabling the encoding device to tune the transmission rate of the entire system and providing flexible adjustment capabilities. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating a quadrature amplitude modulation (QAM) coding system.

[0039] Figure 2 constellations for orthogonal phase-shift keying Figure 1 A schematic diagram of a scene;

[0040] Figure 3 This is a schematic diagram of a scenario of the coding and modulation method in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of another scenario of the coding and modulation method in the embodiments of this application;

[0042] Figure 5 This is a flowchart illustrating the encoding and modulation method in an embodiment of this application;

[0043] Figure 6 This is a schematic diagram of a scenario of the coding and modulation method in an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of another scenario of the coding and modulation method in the embodiments of this application;

[0045] Figure 8 This is a schematic diagram of another scenario of the coding and modulation method in the embodiments of this application;

[0046] Figure 9 This is a schematic diagram of another scenario of the coding and modulation method in the embodiments of this application;

[0047] Figure 10 This is a flowchart illustrating the decoding and modulation method in an embodiment of this application;

[0048] Figure 11 This is a schematic diagram of a scenario of the decoding and modulation method in an embodiment of this application;

[0049] Figure 12 This is another flowchart illustrating the decoding and modulation method in an embodiment of this application;

[0050] Figure 13 This is a schematic diagram of another scenario of the decoding and modulation method in the embodiments of this application;

[0051] Figure 14 This is a schematic diagram of the structure of an encoding device in an embodiment of this application;

[0052] Figure 15 This is a schematic diagram of the decoding device in an embodiment of this application;

[0053] Figure 16 This is a schematic diagram of the decoding device in an embodiment of this application;

[0054] Figure 17 This is another structural schematic diagram of the encoding device in an embodiment of this application;

[0055] Figure 18 This is another structural schematic diagram of the decoding device in this application embodiment;

[0056] Figure 19 This is another structural schematic diagram of the decoding device in this application embodiment;

[0057] Figure 20 This is a schematic diagram of the optical transmission system in an embodiment of this application. Detailed Implementation

[0058] This application provides an encoding modulation method, a decoding method, and related equipment, which are used to provide an encoding modulation method that can adjust the spectral efficiency of the encoding system and has better encoding performance.

[0059] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present application, rather than all the embodiments. Those skilled in the art will appreciate that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0060] The terms "first," "second," and the like in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0061] like Figure 1 As shown, coding and modulation technology is the foundation of optical transmission, directly determining the transmission capacity and performance limits. For ultra-long-distance, high-performance transmission scenarios, low-order modulation formats are typically used, and appropriate coding and modulation architectures are designed to achieve stable high-performance transmission with lower spectral efficiency (SE). For low-SE coding and modulation scenarios, existing coding and modulation mainly utilizes quadrature phase shift keying (QPSK) technology. The constellation diagram of QPSK is an integer lattice Z2 Lattice. Specifically, the encoding device obtains coded bits from the input information bits through a forward error correction (FEC) encoder, the coded bits are then passed through a bit interleaver to obtain interleaved bits, and the interleaved bits are mapped to modulation symbols using Gray mapping. When using QPSK for coding and modulation, on the one hand, since the encoding device cannot adjust redundancy through probabilistic constellation diagram shaping, the transmission rate achievable by the encoding device is fixed for a given FEC, and the encoding device cannot tune the transmission rate of the entire system. On the other hand, as... Figure 2 As shown, since the constellation diagram of QPSK is based on integer lattice Z2 Lattice, and integer lattice Z2 Lattice is not the densest arrangement in a 2D plane, but A2 Lattice is the densest arrangement in a 2D plane, the coding performance that the coding device can achieve is also limited.

[0062] like Figure 3 As shown, the first aspect of this application provides a coding modulation method. This method is used to provide a coding modulation method that can adjust the spectral efficiency of the coding system and has better coding performance. This method determines the constellation diagram based on D4Lattice isomers. Figure 3 As shown, D4 Lattice constitutes the densest sphere-filled topology in 4-dimensional space. Figure 3The diagram illustrates the generation process from integer lattice (Z4 Lattice) to D4 Lattice and its isomers. It can be seen that the symbol spacing remains unchanged compared to Z4 Lattice, but the density of D4 Lattice lattice is higher than that of Z4 Lattice. Quantitatively, the average energy of D4 Lattice is 2.10 dB lower than that of traditional integer lattice in 4 dimensions. By selecting a constellation diagram based on the D4 Lattice isomer, the topological properties remain unchanged, preserving the benefit in symbol energy. Furthermore, the D4 Lattice isomer can be combined with probability constellation shaping (pcs) to adjust the symbol information entropy, and further, combined with a multi-level coding modulation architecture design, to achieve even better performance. The specific implementation of this invention is described below.

[0063] First, a coordinate linear transformation is performed on the D4 Lattice to obtain a centrally symmetric D4 Lattice isomer that does not pass through the origin. The lattice points in the D4 Lattice isomer are arranged in ascending order of energy, and the two sets of lattice points with the lowest energy are selected as a constellation diagram. Each lattice point is called a symbol in the constellation diagram. The first layer has 8 symbols, the second layer has 32 symbols, for a total of 40 symbols. The coordinates of the four-dimensional symbols are denoted as [x,y,z,w], and their symbol energy is x² + y² + z² + w². These four-dimensional symbols correspond precisely to the polarization-multiplexed IQ modulation symbols in coherent optical communication, or two IQ modulation symbols in time-division multiplexing.

[0064] In the D4 Lattice isomer, the first layer symbol energy is 4, and the coordinates of the eight symbols are as follows:

[0065] ±{(1,1,1,1)(1,1,-1,-1)(1,-1,1,-1)(1,-1,-1,1)}.

[0066] The second layer of symbols has an energy of 12, and the coordinates of the 32 symbols are as follows:

[0067] ±{(3,-1,1,1)(3,1,-1,1)(3,1,1,-1)(-3,1,1,1)};

[0068] ±{(-1,3,1,1)(1,-3,1,1)(1,3,-1,1)(1,3,1,-1)};

[0069] ±{(-1,3,1,1)(1,-3,1,1)(1,3,-1,1)(1,3,1,-1)};

[0070] ±{(-1,1,1,3)(1,-1,1,3)(1,1,-1,3)(1,1,1,-3)}.

[0071] The above symbols are first labeled with 1 bit to indicate the layer in which the symbol belongs (for example, bit 0 indicates the first layer symbol and bit 1 indicates the second layer symbol). Based on the known layer information, the first layer of 8 symbols is mapped and encoded with 3 bits, and the second layer of 32 symbols is mapped and encoded with 5 bits.

[0072] Typical frame structure as follows Figure 4 As shown, b0 is used to mark the layer where the symbol belongs, and is called the amplitude bit. b1-b5 are used for mapping and coding, and are called the phase bits. For b0=0, 3 bits (b1-b3) are selected to map to the transmitted symbol in the first layer. For b0=1, 5 bits (b1-b5) are selected to map to the transmitted symbol in the second layer.

[0073] Based on the above frame structure design, the coding and modulation method in the embodiments of this application is described below:

[0074] Please see Figure 5 One step of the coding and modulation method in this application embodiment includes:

[0075] 501. The encoding device divides the target bit information into a first bit set and a second bit set.

[0076] The encoding device divides the bit information source, i.e., the target bit information, into a first bit set Data1 and a second bit set Data2, which include all the target bit information. The first bit set Data1 is used to generate amplitude bits, and the second bit set Data2 is used to generate phase bits.

[0077] In one possible implementation, the encoding device divides the target bit information into three parts: Data1, Data2, and Data3. The first bit set, Data1, is used to generate amplitude bits, and the second bit sets, Data2 and Data3, are used to generate phase bits.

[0078] 502. The encoding device generates amplitude bits from the first bit set using a distribution matching algorithm.

[0079] The encoding device encodes the first bit set using a constant composite distribution match (CCDM) algorithm to obtain amplitude bits b0, which is a bit sequence that satisfies the probability distribution requirements. This CCDM belongs to the probability constellation shaping (pcs) technique.

[0080] In this embodiment, by combining probabilistic shaping technology to adjust symbol probability, the symbol entropy can be flexibly adjusted, and the encoding device can have flexible adjustment capability for spectral efficiency (SE), which can meet greater application needs and make full use of bandwidth resources.

[0081] 503. The encoding device generates phase bits from the second bit set.

[0082] like Figure 6 As shown, the encoding device first encodes the amplitude bits into parity bits using a first forward error correction code (FEC1), and then encodes the second bit set into phase bits using a second forward error correction code, the phase bits including the parity bits. Figure 7 As shown, the phase bit includes five bits (b1-b5), where b1 includes the parity bit.

[0083] like Figure 8 As shown, in one possible implementation, the encoding device divides the target bit information into three parts: Data1, Data2, and Data3. The first bit set includes Data1, which is used to generate amplitude bits. The second bit set includes a first bit block Data2 and a second bit block Data3, which are used to generate phase bits. In this possible implementation, the encoding device generates phase bits in the following ways:

[0084] The encoding device first encodes the first bit block Data2 into first phase bits (b1, b2) using the second forward error correction code FEC2. Then, the encoding device encodes the second bit block Data3 into second phase bits (b3, b4, b5) using the third forward error correction code FEC3, where the second phase bits include parity bits. Finally, the encoding device determines the phase bits (b1-b5) based on the first phase bits (b1, b2) and the second phase bits (b3, b4, b5). Figure 9 As shown, b3 in the second phase bit includes a parity bit.

[0085] 504. The encoding device transforms the amplitude bits and phase bits into corresponding four-dimensional symbol information.

[0086] The encoding device transforms the amplitude bits and phase bits into corresponding four-dimensional symbol information based on the D4 Lattice heterogeneous constellation diagram. Specifically, the encoding device transforms the amplitude bits and phase bits into corresponding four-dimensional symbol information based on the D4 Lattice heterogeneous constellation diagram and the variable-length mapping coding frame design, and then outputs and transmits the information.

[0087] In one possible implementation, if the value of the amplitude bit b0 is 0, the encoding device selects three bits (b1-b3) out of the five phase bits (b1-b5) to map as the first layer transmission symbol.

[0088] In one possible implementation, if the amplitude bit b0 has a value of 1, the encoding device selects five bits (b1-b5) of the five phase bits to map as the second-layer transmission symbol.

[0089] In this embodiment, the encoding device selects a constellation diagram based on 4D space D4 Lattice, which has a higher density and lower average energy than traditional integer lattice points, resulting in better performance of the encoding device. At the same time, the encoding device generates amplitude bits from the first bit set through a distribution matching algorithm. Since the distribution matching algorithm is a probabilistic shaping technique, the encoding device can adjust the redundancy through probabilistic constellation diagram shaping, thereby enabling the encoding device to tune the transmission rate of the entire system and have flexible adjustment capabilities.

[0090] The decoding method in the embodiments of this application is described below. In the embodiments of this application, the encoding device can use two-level encoding or three-level encoding. Correspondingly, the decoding device may need to perform two-level decoding or three-level decoding, which will be explained below:

[0091] First, the decoding device performs two-stage decoding.

[0092] Please see Figure 10 One step of the decoding and modulation method in this application embodiment includes:

[0093] 1001. The decoding device determines the first bit set.

[0094] Please see Figure 11 The decoding device first demodulates the received four-dimensional symbol information into the log-likelihood ratio (llr) of amplitude bits b0 through a first-level demodulation. Then, the decoding device decodes the log-likelihood ratio of amplitude bits b0 into amplitude bits b0 through a first forward error correction code. Finally, the decoding device decodes the amplitude bits into the first bit set through a distribution matching algorithm.

[0095] 1002. The decoding device determines the second bit set.

[0096] The decoding device uses the amplitude bit b0 as prior information and demodulates it through a second-level demodulation process to obtain the log-likelihood ratio of the phase bits. Then, the decoding device decodes the log-likelihood ratio of the phase bits into a second bit set using a second forward error correction code.

[0097] 1003. The decoding device determines the target bit information.

[0098] The decoding device determines the target bit information based on the first bit set and the second bit set.

[0099] In this embodiment, the decoding device performs two-stage decoding. It can be understood that the process of the decoding device performing two-stage decoding is the reverse process of the encoding device performing two-stage encoding. For specific details, please refer to [reference needed]. Figure 5 Steps 501-504 are shown in the diagram; the specifics will not be repeated here.

[0100] In this embodiment of the application, the encoding device can use three-level encoding or two-level encoding. Correspondingly, the decoding device may need to perform two-level decoding or three-level decoding. These are described in detail below:

[0101] Please see Figure 12 One step of the decoding and modulation method in this application embodiment includes:

[0102] Second, the decoding device performs three-level decoding.

[0103] 1201. The decoding device determines the first bit set.

[0104] Please see Figure 13 The decoding device first demodulates the received four-dimensional symbol information through a first-level demodulation to obtain the log-likelihood ratio of the first phase bits (b1, b2). Then, the decoding device decodes the log-likelihood ratio of the first phase bits (b1, b2) into the first phase bits through a second forward error correction code. The decoding device then demodulates the first phase bits as prior information to obtain the log-likelihood ratio of the amplitude bits through a second-level demodulation. The decoding device then decodes the log-likelihood ratio of the amplitude bits into the amplitude bits through a first forward error correction code. Finally, the decoding device decodes the amplitude bits into the first bit set through a distribution matching algorithm.

[0105] 1202. The decoding device determines the second bit set.

[0106] The decoding device uses the first phase bit as prior information to perform three-level demodulation, thereby demodulating the log-likelihood ratio of the second phase bit (b3, b4, b5). Then, the decoding device uses the log-likelihood ratio of the second phase bit to decode the second phase bit through the third forward error correction code to determine the second phase bit. Finally, the decoding device determines the second bit set based on the first phase bit (b1, b2) and the second phase bit (b3, b4, b5).

[0107] 1203. The decoding device determines the target bit information.

[0108] The decoding device determines the target bit information based on the first bit set and the second bit set.

[0109] In this embodiment, the decoding device performs three-level decoding. It can be understood that the process of the decoding device performing three-level decoding is the reverse process of the encoding device performing three-level encoding. For specific details, please refer to [reference needed]. Figure 5Steps 501-504 are shown in the diagram; the specifics will not be repeated here.

[0110] The encoding device in the embodiments of this application is described below. Please refer to [link / reference]. Figure 14 This application provides an encoding device 1400, which can be the encoding device described above. Figure 5 The encoding device 1400 includes:

[0111] The determination module 1401 is used to determine the constellation diagram of the D4 Lattice isomers. For specific implementation details, please refer to [reference needed]. Figure 3 The formation process of the D4 Lattice isomer shown will not be described in detail here.

[0112] The determining module 1401 includes:

[0113] Transformation unit 1402 is used to transform D4 Lattice into a D4 Lattice isomer through a linear transformation. The D4 Lattice isomer does not pass through the origin and is centrally symmetric. For specific implementation details, please refer to [reference needed]. Figure 3 The formation process of the D4 Lattice isomer shown will not be described in detail here.

[0114] Unit 1403 is used to determine the two lowest-energy lattice layers in the D4 Lattice isomer constellation diagram. For specific implementation details, please refer to [reference needed]. Figure 3 The formation process of the D4 Lattice isomer shown will not be described in detail here.

[0115] The partitioning module 1404 is used to partition the target bit information into a first bit set and a second bit set; for details on its implementation, please refer to [reference needed]. Figure 5 Step 501 shown: The encoding device divides the target bit information into a first bit set and a second bit set, which will not be described in detail here.

[0116] Generation module 1405 is used to generate amplitude bits from the first bit set and phase bits from the second bit set using a distribution matching algorithm; for specific implementation details, please refer to [reference needed]. Figure 5 Step 502: The encoding device generates amplitude bits from the first bit set using a distribution matching algorithm. Step 503: The encoding device generates phase bits from the second bit set. These steps will not be elaborated further here.

[0117] Generation module 1405 includes:

[0118] The first encoding unit 1406 is used to encode the first bit set into amplitude bits using a distribution matching algorithm; for specific implementation details, please refer to [reference needed]. Figure 5Step 502 shown: The encoding device generates amplitude bits from the first bit set using a distribution matching algorithm, which will not be described in detail here.

[0119] The second encoding unit 1407 is used to encode the amplitude bits into check bits using the first forward error correction code; for specific implementation details, please refer to [reference needed]. Figure 5 Step 503 shown: The encoding device generates phase bits from the second bit set, which will not be described in detail here.

[0120] The third encoding unit 1408 is used to encode the second bit set into phase bits using a second forward error correction code, wherein the phase bits include the parity bits. For specific implementation details, please refer to [reference needed]. Figure 5 Step 503 shown: The encoding device generates phase bits from the second bit set, which will not be described in detail here.

[0121] In one possible implementation, the second bit set includes the first bit block and the second bit block, and the third coding unit 1408 includes:

[0122] The first encoding subunit 1409 is used to encode the first bit block into a first phase bit using a second forward error correction code; for details, please refer to [reference needed]. Figure 5 Step 503 shown: The encoding device generates phase bits from the second bit set, which will not be described in detail here.

[0123] The second encoding subunit 1410 is used to encode the second bit block into a second phase bit using a third forward error correction code, wherein the second phase bit includes the parity bit; for specific implementation details, please refer to [reference needed]. Figure 5 Step 503 shown: The encoding device generates phase bits from the second bit set, which will not be described in detail here.

[0124] The determining subunit 1411 is used to determine the phase bit based on the first phase bit and the second phase bit. For specific implementation details, please refer to [reference needed]. Figure 5 Step 503 shown: The encoding device generates phase bits from the second bit set, which will not be described in detail here.

[0125] Transformation module 1412 is used to transform the amplitude bits and the phase bits into corresponding four-dimensional symbol information according to the D4 Lattice isomorphic constellation diagram. For specific implementation details, please refer to [reference needed]. Figure 5 Step 504 shown: The encoding device transforms the amplitude bits and phase bits into corresponding four-dimensional symbol information, which will not be described in detail here.

[0126] In this embodiment, the encoding device can perform the aforementioned... Figure 5 The specific operations performed by the encoding device in any of the embodiments shown are not described here.

[0127] The decoding device in the embodiments of this application is described below. Please refer to [link / reference]. Figure 15 This application provides a decoding device 1500, which can be the aforementioned... Figure 10 The decoding device 1500 includes:

[0128] The first demodulation module 1501 is used to demodulate the received four-dimensional symbol information into the log-likelihood ratio of amplitude bits through a single-stage demodulation process; for specific implementation details, please refer to [reference needed]. Figure 10 Step 1001 shown: The decoding device determines the first bit set, which will not be described in detail here.

[0129] The first decoding module 1502 is used to decode the log-likelihood ratio of the amplitude bits into the amplitude bits using a first forward error correction code; for specific implementation details, please refer to [reference needed]. Figure 10 Step 1001 shown: The decoding device determines the first bit set, which will not be described in detail here.

[0130] The second decoding module 1503 is used to decode the amplitude bits into a first bit set using a distribution matching algorithm; for specific implementation details, please refer to [reference needed]. Figure 10 Step 1001 shown: The decoding device determines the first bit set, which will not be described in detail here.

[0131] The second demodulation module 1504 is used to demodulate the log-likelihood ratio of the phase bits using the amplitude bits as prior information through two-stage demodulation; for specific implementation details, please refer to [reference needed]. Figure 10 Step 1002 shown: The decoding device determines the second bit set, which will not be described in detail here.

[0132] The third decoding module 1505 is used to decode the log-likelihood ratio of the phase bits into a second bit set using a second forward error correction code; for specific implementation details, please refer to [reference needed]. Figure 10 Step 1002 shown: The decoding device determines the second bit set, which will not be described in detail here.

[0133] The determining module 1506 is used to determine the target bit information based on the first bit set and the second bit set. For specific implementation details, please refer to [reference needed]. Figure 10 Step 1003 shown: The decoding device determines the standard bit information, which will not be described in detail here.

[0134] In this embodiment, the decoding device can perform the aforementioned... Figure 10 The specific operations performed by the decoding device in any of the embodiments shown are not described here.

[0135] The decoding device in the embodiments of this application is described below. Please refer to [link / reference]. Figure 16 This application provides a decoding device 1600, which can be the aforementioned... Figure 12 The decoding device 1600 includes:

[0136] The first demodulation module 1601 is used to demodulate the received four-dimensional symbol information into the log-likelihood ratio of the first phase bits through primary demodulation; for specific implementation details, please refer to [reference needed]. Figure 12 Step 1201 shown: The decoding device determines the first bit set, which will not be described in detail here.

[0137] The first decoding module 1602 is used to decode the log-likelihood ratio of the first phase bit into the first phase bit using a second forward error correction code; for specific implementation details, please refer to [reference needed]. Figure 12 Step 1201 shown: The decoding device determines the first bit set, which will not be described in detail here.

[0138] The second demodulation module 1603 is used to demodulate the first phase bit as prior information into the log-likelihood ratio of the amplitude bit through two-stage demodulation; for specific implementation details, please refer to [reference needed]. Figure 12 Step 1201 shown: The decoding device determines the first bit set, which will not be described in detail here.

[0139] The second decoding module 1604 is used to decode the log-likelihood ratio of the amplitude bits into the amplitude bits using the first forward error correction code; for specific implementation details, please refer to [reference needed]. Figure 12 Step 1201 shown: The decoding device determines the first bit set, which will not be described in detail here.

[0140] The third decoding module 1605 is used to decode the amplitude bits into a first bit set using a distribution matching algorithm; for specific implementation details, please refer to [reference needed]. Figure 12 Step 1201 shown: The decoding device determines the first bit set, which will not be described in detail here.

[0141] The third demodulation module 1606 is used to demodulate the log-likelihood ratio of the second phase bit by using the first phase bit as prior information through three-stage demodulation; for specific implementation details, please refer to [reference needed]. Figure 12 Step 1202 shown: The decoding device determines the second bit set, which will not be described in detail here.

[0142] The fourth decoding module 1607 is used to determine the second bit set by decoding the log-likelihood ratio of the second phase bits using the third forward error correction code; for specific implementation details, please refer to [reference needed]. Figure 12 Step 1202 shown: The decoding device determines the second bit set, which will not be described in detail here.

[0143] The determining module 1608 is used to determine the target bit information based on the first bit set and the second bit set. For specific implementation details, please refer to [reference needed]. Figure 12Step 1203 shown: The decoding device determines the third bit set, which will not be described in detail here.

[0144] In this embodiment, the decoding device can perform the aforementioned... Figure 12 The specific operations performed by the decoding device in any of the embodiments shown are not described here.

[0145] Figure 17 This is a schematic diagram of an encoding device structure provided in an embodiment of this application. The encoding device 1700 may include one or more central processing units (CPUs) 1701 and a memory 1705, in which one or more application programs or data are stored.

[0146] The memory 1705 can be volatile or persistent storage. The program stored in the memory 1705 can include one or more modules, each module including a series of instruction operations on the encoding device. Furthermore, the central processing unit 1701 can be configured to communicate with the memory 1705 and execute the series of instruction operations in the memory 1705 on the encoding device 1700.

[0147] The central processing unit 1701 executes the computer program stored in memory 1705, enabling the encoding device 1700 to perform the following: the encoding device divides the target bit information into a first bit set and a second bit set; the encoding device generates amplitude bits from the first bit set and phase bits from the second bit set using a distribution matching algorithm; the encoding device transforms the amplitude bits and phase bits into corresponding four-dimensional symbol information according to the D4Lattice isomorphic constellation diagram. For specific implementation details, please refer to [reference needed]. Figure 5 Steps 501-504 in the illustrated embodiment will not be repeated here.

[0148] The encoding device 1700 may also include one or more power supplies 1702, one or more wired or wireless network interfaces 1703, one or more input / output interfaces 1704, and / or one or more operating systems, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0149] The encoding device 1700 can perform the aforementioned... Figure 5 The operations performed by the encoding device in the illustrated embodiment will not be described in detail here.

[0150] Figure 18This is a schematic diagram of a decoding device structure provided in an embodiment of this application. The decoding device 1800 may include one or more central processing units (CPUs) 1801 and a memory 1805, in which one or more application programs or data are stored.

[0151] The memory 1805 can be volatile or persistent storage. The program stored in the memory 1805 can include one or more modules, each module including a series of instruction operations on the decoding device. Furthermore, the central processing unit 1801 can be configured to communicate with the memory 1805 and execute the series of instruction operations in the memory 1805 on the decoding device 1800.

[0152] The central processing unit 1801 executes the computer program stored in the memory 1805, enabling the decoding device 1800 to perform the following: The decoding device demodulates the received four-dimensional symbol information into the log-likelihood ratio of amplitude bits through a first-level demodulation; the decoding device decodes the log-likelihood ratio of amplitude bits into amplitude bits using a first forward error correction code; the decoding device decodes the amplitude bits into a first bit set using a distribution matching algorithm; the decoding device demodulates the log-likelihood ratio of phase bits from the amplitude bits as prior information through a second-level demodulation; the decoding device decodes the log-likelihood ratio of phase bits into a second bit set using a second forward error correction code; and the decoding device determines the target bit information based on the first and second bit sets. For specific implementation details, please refer to [reference needed]. Figure 10 Steps 1001-1003 in the illustrated embodiment will not be repeated here.

[0153] The decoding device 1800 may also include one or more power supplies 1802, one or more wired or wireless network interfaces 1803, one or more input / output interfaces 1804, and / or one or more operating systems, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0154] The decoding device 1800 can perform the aforementioned... Figure 10 The specific operations performed by the decoding device in the illustrated embodiment will not be described in detail here.

[0155] Figure 19 This is a schematic diagram of a decoding device structure provided in an embodiment of this application. The decoding device 1900 may include one or more central processing units (CPUs) 1901 and a memory 1905, in which one or more application programs or data are stored.

[0156] The memory 1905 can be volatile or persistent storage. The program stored in the memory 1905 can include one or more modules, each module including a series of instruction operations on the decoding device. Furthermore, the central processing unit 1901 can be configured to communicate with the memory 1905 and execute the series of instruction operations in the memory 1905 on the decoding device 1900.

[0157] The central processing unit 1901 executes the computer program in the memory 1905, enabling the decoding device 1900 to perform the following: The decoding device demodulates the received four-dimensional symbol information into the log-likelihood ratio of the first phase bits through a first-level demodulation; the decoding device decodes the log-likelihood ratio of the first phase bits into the first phase bits using a second forward error correction code; the decoding device demodulates the first phase bits as prior information to obtain the log-likelihood ratio of the amplitude bits through a second-level demodulation; the decoding device decodes the log-likelihood ratio of the amplitude bits into the amplitude bits using a first forward error correction code; the decoding device decodes the amplitude bits into the first bit set using a distribution matching algorithm; the decoding device demodulates the first phase bits as prior information to obtain the log-likelihood ratio of the second phase bits through a third-level demodulation; the decoding device decodes the log-likelihood ratio of the second phase bits to determine the second bit set using a third forward error correction code; the decoding device determines the target bit information based on the first bit set and the second bit set. For specific implementation details, please refer to [reference needed]. Figure 12 Steps 1201-1203 in the illustrated embodiment will not be repeated here.

[0158] The decoding device 1900 may also include one or more power supplies 1902, one or more wired or wireless network interfaces 1903, one or more input / output interfaces 1904, and / or one or more operating systems, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0159] The decoding device 1900 can perform the aforementioned... Figure 12 The specific operations performed by the decoding device in the illustrated embodiment will not be described in detail here.

[0160] Figure 20 This is a schematic diagram of an optical transmission system provided in an embodiment of this application, including an encoding device 2001 and a decoding device 2002. The encoding device 2001 can perform the aforementioned... Figure 5 The operations performed by the encoding device in the illustrated embodiment can be performed by the decoding device 2002 as described above. Figure 10 and Figure 12 The specific operations performed by the decoding device in the illustrated embodiment will not be described in detail here.

[0161] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0162] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0163] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0164] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0165] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A coding modulation method, characterized in that, The method includes: The encoding device divides the target bit information into a first bit set and a second bit set; The encoding device generates amplitude bits from the first bit set and phase bits from the second bit set using a distribution matching algorithm; generating phase bits from the second bit set includes: the encoding device encodes the amplitude bits into parity bits using a first forward error correction code; the encoding device encodes the second bit set into phase bits using a second forward error correction code, the phase bits including the parity bits; The encoding device transforms the amplitude bits and the phase bits into corresponding four-dimensional symbol information according to the D4 Lattice heterogeneous constellation diagram.

2. The method according to claim 1, characterized in that, The method further includes: The encoding device determines the constellation diagram of the D4 Lattice isomer.

3. The method according to claim 2, characterized in that, The encoding device determines the constellation diagram of the D4 Lattice isomers, including: The encoding device transforms D4 Lattice into a D4 Lattice isomer through a linear transformation. The D4 Lattice isomer does not pass through the origin and is centrally symmetric. The encoding device determines the two lowest-energy lattice points in the D4 Lattice isomer as the D4 Lattice isomer constellation diagram.

4. The method according to claim 3, characterized in that, The encoding device generates amplitude bits from the first bit set using a distribution matching algorithm, including: The encoding device encodes the first bit set into amplitude bits using a distribution matching algorithm.

5. The method according to claim 4, characterized in that, The second bit set includes a first bit block and a second bit block. The encoding device encodes the second bit set into phase bits using a second forward error correction code, including: The encoding device encodes the first bit block into a first phase bit using a second forward error correction code; The encoding device encodes the second bit block into a second phase bit using a third forward error correction code, the second phase bit including the parity bit; The encoding device determines the phase bit based on the first phase bit and the second phase bit.

6. The method according to claim 4, characterized in that, The phase bits include five bits. If the check bit is 0, the encoding device transforms the amplitude bits and the phase bits into corresponding four-dimensional symbol information according to the D4 Lattice heterogeneous constellation diagram, including: The encoding device transforms the first to third bits of the phase bits into corresponding four-dimensional symbol information according to the D4 Lattice isomorphic constellation diagram.

7. The method according to claim 4, characterized in that, The phase bits include five bits. If the check bit is 1, the encoding device transforms the amplitude bits and the phase bits into corresponding four-dimensional symbol information according to the D4 Lattice isomorphic constellation diagram, including: The encoding device transforms the first to fifth bits of the phase bits into corresponding four-dimensional symbol information according to the D4 Lattice isomorphic constellation diagram.

8. A decoding modulation method, characterized in that, The method includes: The decoding device demodulates the received four-dimensional symbol information into the log-likelihood ratio of amplitude bits through a first-level demodulation. The decoding device decodes the log-likelihood ratio of the amplitude bits into the amplitude bits using a first forward error correction code; The decoding device decodes the amplitude bits into a first bit set using a distribution matching algorithm; The decoding device uses the amplitude bits as prior information to demodulate the log-likelihood ratio of the phase bits through two-stage demodulation; The decoding device decodes the log-likelihood ratio of the phase bits into a second bit set using a second forward error correction code; The decoding device determines the target bit information based on the first bit set and the second bit set.

9. A decoding modulation method, characterized in that, The second bit set includes the first bit block and the second bit block, and the method includes: The decoding device demodulates the received four-dimensional symbol information into the log-likelihood ratio of the first phase bit through a first-stage demodulation. The decoding device decodes the log-likelihood ratio of the first phase bit into the first phase bit using a second forward error correction code; The decoding device uses the first phase bit as prior information to demodulate the log-likelihood ratio of the amplitude bit through two-stage demodulation; The decoding device decodes the log-likelihood ratio of the amplitude bits into the amplitude bits using a first forward error correction code; The decoding device decodes the amplitude bits into a first bit set using a distribution matching algorithm; The decoding device uses the first phase bit as prior information to demodulate the log-likelihood ratio of the second phase bit through three-level demodulation; The decoding device determines the second bit set by decoding the log-likelihood ratio of the second phase bits using a third forward error correction code; The decoding device determines the target bit information based on the first bit set and the second bit set.

10. An encoding device, characterized in that, The encoding device includes: The partitioning module is used to divide the target bit information into a first bit set and a second bit set; The generation module is used to generate amplitude bits from the first bit set and phase bits from the second bit set using a distribution matching algorithm. The transformation module is used to transform the amplitude bits and the phase bits into corresponding four-dimensional symbol information according to the D4 Lattice isomorphic constellation diagram; The generation module includes: The second encoding unit is used to encode the amplitude bit into a check bit using a first forward error correction code; The third encoding unit is used to encode the second bit set into phase bits using a second forward error correction code, wherein the phase bits include the check bits.

11. The encoding device according to claim 10, characterized in that, The encoding device further includes a determining module, the determining module comprising: A transformation unit is used to transform D4 Lattice into a D4 Lattice isomer through a linear transformation, wherein the D4 Lattice isomer does not pass through the origin and is centrally symmetric. The determination unit is used to identify the two lowest-energy lattice points in the D4 Lattice isomer as the constellation diagram of the D4 Lattice isomer.

12. The encoding device according to claim 11, characterized in that, The generation module further includes: The first encoding unit is used to encode the first bit set into amplitude bits using a distribution matching algorithm.

13. The encoding device according to claim 12, characterized in that, The second bit set includes a first bit block and a second bit block, and the third coding unit includes: The first encoding subunit is used to encode the first bit block into a first phase bit using a second forward error correction code; The second encoding subunit is used to encode the second bit block into a second phase bit using a third forward error correction code, wherein the second phase bit includes the parity bit; A determining subunit is used to determine the phase bit based on the first phase bit and the second phase bit.

14. A decoding device, characterized in that, The decoding device includes: The first demodulation module is used to demodulate the received four-dimensional symbol information into the log-likelihood ratio of amplitude bits through first-level demodulation; The first decoding module is used to decode the log-likelihood ratio of the amplitude bits into the amplitude bits through a first forward error correction code; The second decoding module is used to decode the amplitude bits into a first bit set using a distribution matching algorithm; The second demodulation module is used to demodulate the log-likelihood ratio of the phase bits as prior information through two-stage demodulation; The third decoding module is used to decode the log-likelihood ratio of the phase bits into a second bit set through the second forward error correction code; The determination module is used to determine the target bit information based on the first bit set and the second bit set.

15. A decoding device, characterized in that, The second bit set includes the first bit block and the second bit block, and the decoding device includes: The first demodulation module is used to demodulate the received four-dimensional symbol information into the log-likelihood ratio of the first phase bit through first-level demodulation; The first decoding module is used to decode the log-likelihood ratio of the first phase bit into the first phase bit through the second forward error correction code; The second demodulation module is used to demodulate the first phase bit as prior information into the log-likelihood ratio of the amplitude bit through two-stage demodulation; The second decoding module is used to decode the log-likelihood ratio of the amplitude bits into the amplitude bits through the first forward error correction code; The third decoding module is used to decode the amplitude bits into a first bit set using a distribution matching algorithm; The third demodulation module is used to demodulate the log-likelihood ratio of the second phase bit by using the first phase bit as prior information through three-level demodulation. The fourth decoding module is used to determine the second bit set by decoding the log-likelihood ratio of the second phase bits using the third forward error correction code; The determination module is used to determine the target bit information based on the first bit set and the second bit set.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-7.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 8.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 9.

19. A controller, characterized in that, Includes a processor and a computer-readable storage medium storing a computer program; The processor is coupled to the computer-readable storage medium, and the computer program, when executed by the processor, implements the method as described in any one of claims 1-7.

20. A controller, characterized in that, Includes a processor and a computer-readable storage medium storing a computer program; The processor is coupled to the computer-readable storage medium, and the computer program, when executed by the processor, implements the method as described in claim 8.

21. A controller, characterized in that, Includes a processor and a computer-readable storage medium storing a computer program; The processor is coupled to the computer-readable storage medium, and the computer program, when executed by the processor, implements the method as described in claim 9.

22. A chip system, characterized in that, Includes a processor, which is invoked to perform the method as described in any one of claims 1-7.

23. A chip system, characterized in that, Includes a processor, which is invoked to perform the method as described in claim 8.

24. A chip system, characterized in that, Includes a processor, which is invoked to perform the method of claim 9.

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