Cycle detection for DFS-based pregel model

Abstract

A method, system, and computer program product for reducing memory consumption in a depth-first search (DFS)-based cycle detection process for detecting n-length cycles on a Pregel model is provided. The method includes generating a graph comprising a plurality of vertices and edges connecting the plurality of vertices, starting a cycle from a first vertex in the plurality of vertices, setting an ID of the first vertex to a path and the first vertex as a target vertex, and iterating the following n-1 times: sending the path to an outgoing edge from the first vertex, and transmitting the path n-1 times by a subsequently received vertex via the outgoing edge, finding a vertex before returning to the target vertex, adding an ID of the found vertex to the path, and setting the found vertex as the target vertex, such that n = n-1, where n is a number of iterations.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to cycle detection in directed graphs, and more specifically to depth-first search (DFS) based cycle detection for Pregel model. BACKGROUND

[0002] Many practical computational problems involve large graphs. Standard examples include Web graphs and various social networks. In some cases these graphs have sizes of tens of billions of vertices, trillions of edges, posing challenges for their efficient processing. Graph algorithms often exhibit poor locality of memory accesses, very little work per vertex, and varying degree of parallelism during execution. Distribution over many machines exacerbates locality problems and increases the probability of machines failing during computation. SUMMARY

[0003] According to an embodiment, a method for reducing memory consumption in a cycle detection process based on depth-first search (DFS) for detecting n-length cycles on a Pregel model is provided. The method includes generating a graph comprising a plurality of vertices and edges connecting the plurality of vertices, starting a cycle from a first vertex in the plurality of vertices, setting an ID of the first vertex to a path and setting the first vertex as a target vertex, and iterating the following n-1 times: sending the path from the first vertex to out-edges, and transmitting the path n-1 times by a subsequently received vertex via the out-edges, finding one vertex before returning to the target vertex, adding an ID of the found vertex to the path, and setting the found vertex as the target vertex, such that n = n-1, where n is a number of iterations.

[0004] According to another embodiment, a method for reducing memory consumption in a cycle detection process is provided. The method includes employing a depth-first search (DFS) method to detect n-length cycles of a Pregel model, the method implemented by: generating a graph comprising a plurality of vertices and edges connecting the plurality of vertices; starting a cycle from a first vertex in the plurality of vertices; setting an ID of the first vertex to a path and setting the first vertex as a target vertex; and iterating a DFS process n-1 times, where n is a number of iterations.

[0005] A computer program product is proposed to reduce the memory consumption of loops of length n in a detection process based on depth-first search (DFS) for detecting Pregel models. The computer program product includes a computer-readable storage medium thereon containing program instructions executable by a computer to generate a graph comprising multiple vertices and edges connecting the multiple vertices, looping from the first vertex among the multiple vertices, setting the ID of the first vertex to the path and setting the first vertex as the target vertex, and iterating n-1 times as follows: sending the path from the first vertex to the outside, and transmitting the path n-1 times via the outside by the subsequently received vertices, finding a vertex before returning to the target vertex, adding the ID of the found vertex to the path, and setting the found vertex as the target vertex, such that n = n-1, where n is the number of iterations.

[0006] It should be noted that exemplary embodiments have been described with reference to different subjects. In particular, some embodiments are described with reference to method-type claims, while others are described with reference to apparatus-type claims. However, those skilled in the art will understand from the above and below description that, unless otherwise indicated, any combination of features related to different subjects, in particular any combination of features between features of method-type claims and features of apparatus-type claims, is also considered to be described herein, except for any combination of features belonging to one type of subject matter.

[0007] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention, which is read in conjunction with the accompanying drawings. Attached Figure Description

[0008] The present invention will be provided in detail in the following description of preferred embodiments with reference to the accompanying drawings, wherein:

[0009] Figure 1 This is an exemplary directed graph according to an embodiment of the present invention, wherein all four cycles of length including vertex 0 and vertex 6 are detected in the first iteration;

[0010] Figure 2 This is according to an embodiment of the present invention. Figure 1 An exemplary directed graph in which a second iteration occurs to detect an ID;

[0011] Figure 3 This is according to an embodiment of the present invention. Figure 2 An exemplary directed graph in which a third iteration occurs to detect the ID;

[0012] Figure 4 This is according to an embodiment of the present invention. Figure 3 An exemplary directed graph in which a fourth iteration occurs to detect an ID;

[0013] Figure 5 is an exemplary directed graph of Figure 4 in which a fifth iteration occurs to detect IDs according to an embodiment of the present application;

[0014] Figure 6 is an exemplary directed graph of Figure 5 in which a sixth iteration occurs to detect IDs according to an embodiment of the present application;

[0015] Figure 7 is an exemplary directed graph of Figure 6 in which a seventh iteration occurs to detect IDs according to an embodiment of the present application;

[0016] Figure 8 is an exemplary directed graph of Figure 7 in which an eighth iteration occurs to detect IDs according to an embodiment of the present application;

[0017] Figure 9 is an exemplary directed graph of Figure 8 in which a ninth iteration occurs to detect IDs according to an embodiment of the present application;

[0018] Figure 10 is an exemplary directed graph of Figure 9 in which a tenth iteration occurs to detect IDs according to an embodiment of the present application;

[0019] Figure 11 is an exemplary directed graph of Figure 10 in which an eleventh iteration occurs to detect IDs according to an embodiment of the present application;

[0020] Figure 12 is a block diagram / flowchart of an exemplary method for applying depth-first search (DFS) based cycle detection on a Pregel model according to an embodiment of the present application;

[0021] Figure 13 is a block diagram / flowchart of an exemplary cloud computing environment according to an embodiment of the present application;

[0022] Figure 14 is a schematic diagram of exemplary abstraction model layers according to an embodiment of the present application; and

[0023] Figure 15 is a block diagram / flowchart of an actual application for applying depth-first search (DFS) based cycle detection on a Pregel model according to an embodiment of the present application.

[0024] In all of the drawings, the same or similar reference numerals designate the same or similar elements throughout. DETAILED DESCRIPTION

[0025] Exemplary embodiments according to the present application provide depth-first search (DFS) based cycle detection for Pregel model. Graph learning is defined as a type of machine learning that leverages graph-based features to add richer context to data by first linking data together as a graph structure and then deriving features from different metrics on the graph. Various graph features can be defined by leveraging a set of graph analytics such as connectivity, centrality, community detection, pattern matching. Graph features can also be combined with non-graph features (e.g., features about attributes of particular data points). After a set of features including graph features and non-graph features are defined, the problem can be formulated as a supervised machine learning problem (assuming labeled data is provided). However, if labeled data is not provided, this can be an unsupervised machine learning problem, such that the method can apply, for example, clustering or outlier detection.

[0026] However, to address distributed processing of large-scale graphs, the Pregel model is constructed as a scalable and fault-tolerant platform with an application programming interface (API) flexible enough to express arbitrary graph algorithms. The Pregel model is a programming model that enables bulk-synchronous parallelism for graph analytics.

[0027] The high-level organization of Pregel programs is inspired by Valiant's bulk-synchronous parallel model. A Pregel computation consists of a sequence of iterations, called supersteps. During a superstep, the framework conceptually invokes a user-defined function for each vertex in parallel. The function specifies the behavior at a single vertex V and a single superstep S, which can read messages sent to V in superstep S-1, send messages to be received at superstep S+1 to other vertices, and modify V and its outgoing edges. Messages are typically sent along outgoing edges, but a message can be sent to any vertex whose identifier is known.

[0028] The vertex-centric approach is reminiscent of MapReduce, as users focus on local actions, process each item independently, and the system composes these actions to lift the computation to large datasets. By design, the model is well-suited for distributed implementation, i.e., the model does not exhibit any mechanism for detecting the order of execution within a superstep, and all communication is from superstep S to superstep S+1.

[0029] The synchronicity of this model makes it easier to reason about the program semantics when implementing the algorithm and ensures that Pregel programs are inherently free of the deadlocks and data races common in asynchronous systems. In principle, the performance of a Pregel program can compete with that of an asynchronous system given enough parallel slack. Because graph computations have many more vertices than machines, users can be able to balance the machine load so that the synchronization between supersteps does not add much latency.

[0030] The Pregel model employs a breadth-first search (BFS) approach. BFS is an algorithm for traversing or searching tree or graph data structures. BFS starts at the root of the tree (or some arbitrary node of the graph, sometimes called the "search key") and explores all neighbor nodes at the present depth before moving on to nodes at the next depth level. However, because existing cycle detection algorithms for the Pregel model employ a BFS approach, the algorithm requires many messages. In other words, the total size of the messages increases exponentially based on the number of iterations. As a result, while the Pregel model provides ease of development with parallelization, existing cycle detection algorithms for the Pregel model require too many messages because of the use of BFS.

[0031] Exemplary embodiments of the present invention disclose methods and systems that alleviate these problems by employing a depth-first search (DFS) approach. DFS is an algorithm for traversing or searching tree or graph data structures. The algorithm starts at the root node (choosing some arbitrary node as the root node in the case of a graph) and explores as far as possible along each branch before backtracking. Thus, employing a DFS approach significantly reduces the number of messages per iteration in detecting cycles.

[0032] It should be appreciated that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrates, materials, and process features and steps / blocks can be varied within the scope of the present invention. It should be noted that in the description and drawings of embodiments, details overshadowing the concept of the present invention are not described. This should not be construed as limiting the scope of any particular embodiment or claim, however.

[0033] The following describes various illustrative embodiments of the present invention. For the sake of brevity and clarity, all features of an actual implementation can not be described in this specification. It should be appreciated that those skilled in the art, having the benefit of the present description, can implement the present invention using any number of different architectures, structures, substrates, materials, and process features and steps / blocks without departing from the spirit of the present invention. Furthermore, it should be understood that the development of the exemplary embodiments of the present invention can be complex and time-consuming, but can also be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill in the art having the benefit of this disclosure.

[0034] Figure 1is an exemplary directed graph according to an embodiment of the application in which all 4-length cycles including vertex 0 and vertex 6 are detected in the first iteration.

[0035] The input to a Pregel computation is a directed graph, where each vertex is uniquely identified by a string vertex identifier. Each vertex is associated with a modifiable user-defined value. A directed edge is associated with its source vertex, and each edge includes a modifiable user-defined value and a destination vertex identifier. A Pregel computation includes an input, when the graph is initialized, followed by a sequence of supersteps separated by global synchronization points, until the algorithm terminates, and ends with an output.

[0036] Within each superstep, vertices are computed in parallel, each vertex executing the same user-defined function expressing the logic of a given algorithm. A vertex can modify its state or the state of its outgoing edges, receive messages sent to it in the previous superstep, send messages to other vertices (to be received in the next superstep), or even change the topology of the graph. In this model, edges are not first-class citizens and have no associated computation.

[0037] The algorithm terminates on a per-vertex basis based on a voting stop. In superstep 0, every vertex is in active state and all active vertices participate in the computation of any given superstep. A vertex deactivates itself by voting stop. This means that the vertex has no further work to do, unless triggered from the outside, and the Pregel framework will not execute the vertex in subsequent supersteps, unless it receives a message. If a vertex is reactivated by a message, the vertex has to explicitly deactivate itself again. The algorithm as a whole terminates when all vertices are deactivated simultaneously and there are no messages in transit.

[0038] The output of a Pregel program is a set of values that the vertices explicitly output. It is typically a directed graph that is isomorphic to the input, but because vertices and edges can be added and removed during the computation, this is not a necessary property of the system. For example, a clustering algorithm can generate a disconnected set of small vertices selected from a large graph. A graph mining algorithm can simply output aggregate statistics mined from the graph.

[0039] Vertices directly communicate with each other by sending messages, each message including a message value and the name of the destination vertex. The type of the message value is specified by the user as a template parameter of the vertex class.

[0040] A vertex can send any number of messages in a superstep. When the compute() method of V is invoked in superstep S+1, all messages sent to vertex V in superstep S are available via an iterator. There is no guaranteed order of messages in the iterator, but it is guaranteed that the messages will be delivered and that they will not be duplicated.

[0041] The Pregel aggregator is a mechanism for global communication, monitoring, and data. Each vertex can provide a value to the aggregator in a superstep S, the system combines these values using a reduction operator, and the resulting value is available to all vertices in superstep S+1. The Pregel model includes a number of predefined aggregators, such as min, max, or sum operations on individual integers or string types.

[0042] There are many possible graph file formats, such as a text file, a set of vertices in a relational database, or rows in a table. To avoid imposing a particular choice of file format, the Pregel model separates the task of interpreting the input file as a graph from the task of graph computation. Similarly, the output can be generated in arbitrary format, and stored in a form that is most suitable for the given application. The Pregel library provides a number of generic file formats for readers and writers. The Pregel library divides the graph into partitions, each of which includes a set of vertices and all the vertices' outgoing edges. The assignment of vertices to partitions depends only on the vertex ID, which means that it is possible to know which partition a given vertex belongs to even if the vertex is owned by a different machine, or even if the vertex does not exist yet.

[0043] In Figure 1 , by employing the DFS approach, there are 5 messages or 5 IDs sent by vertices 0 and 6.

[0044] In particular, ID {6} is sent via the edge from vertex 6 to 4, the edge from 6 to 3, and the edge from 6 to 5.

[0045] ID {0} is sent via the edge from vertex 0 to 3 and the edge from 0 to 5.

[0046] Thus, the first iteration includes 5 messages with 5 IDs.

[0047] The target vertices (0 and 6) send their own IDs ({0}, {6}) to their adjacent outgoing edges.

[0048] Note that for Figure 1-4 , by k iterations, only candidates for the last edge in the cycle are identified by redirecting the received IDs. With the kth iteration, the identified edge is informed to the target vertices.

[0049] Figure 2 is an exemplary directed graph of Figure 1 according to an embodiment of the present invention, in which a second iteration takes place to detect IDs.

[0050] By employing the DFS approach, there are 5 messages with 8 IDs sent by vertices 0 and 6.

[0051] In particular, ID {6} is sent through the edges from vertex 3 to 1, from 3 to 4, from 4 to 1, from 4 to 2 and from 5 to 7.

[0052] ID {0} is sent through the edges from vertex 3 to 1, from 3 to 4 and from 5 to 7.

[0053] Thus, the second iteration comprises 5 messages with 8 IDs.

[0054] The received vertices (3, 4 and 5) send the received IDs to their adjacent outer edges.

[0055] Figure 3 is an exemplary directed graph according to an embodiment of the present invention, in which a third iteration takes place to detect IDs. Figure 2

[0056] By employing the DFS approach, there are 6 messages with 11 IDs sent by vertices 0 and 6.

[0057] In particular, ID {6} is sent through the edges from vertex 1 to 0, from 1 to 2, from 2 to 0, from 4 to 1, from 4 to 2 and from 7 to 8.

[0058] ID {0} is sent through the edges from vertex 1 to 0, from 1 to 2, from 4 to 1, from 4 to 2 and from 7 to 8.

[0059] Thus, the third iteration comprises 6 messages with 11 IDs.

[0060] The received vertices (0, 1, 2, 4 and 8) send the received IDs to their adjacent target outer edges, except vertex 0. Vertex 0 ignores the received {0} because vertex 0 is not included twice in the cycle. In addition, vertex 0 ignores {6} because vertices 0 and 6 are target vertices. To avoid detecting the cycle twice, higher IDs are not redirected in target vertices.

[0061] Figure 4 is an exemplary directed graph according to an embodiment of the present invention, in which a fourth iteration takes place to detect IDs. Figure 3

[0062] By employing the DFS approach, there are 6 messages with 6 IDs sent by vertices 0 and 6.

[0063] In particular, ID {6} is sent through the edges from vertex 1 to 0, from 1 to 2, from 2 to 0 and from 8 to 6.

[0064] ID {0} is sent through the edges from vertex 1 to 0, from 1 to 2, from 2 to 0 and from 8 to 6.​​

[0065] Thus, the fourth iteration includes 8 messages with 8 IDs.

[0066] Note that the received target vertices (0 and 6) identify candidates for the last edge in a cycle. For example, vertex 0 knows that the edge from 1 to 0 (0<-1) and the edge from 2 to 0 (0<-2) can be the last edge in one or more cycles, and vertex 6 knows that the edge from 8 to 6 (6<-8) can be the last edge in one or more cycles. To identify the next edge of the cycle with the next k iterations (from 5 to 8), vertices 0 and 6 send the identified edges to their adjacent outer edges.

[0067] Figure 5 is an exemplary directed graph of Figure 4 in which a fifth iteration occurs to detect IDs according to an embodiment of the present invention.

[0068] By employing the DFS approach, there are 4 messages with 12 IDs sent by vertices 0 and 6.

[0069] In particular, the edge {6<-8} is sent by the edge from vertex 6 to 3, the edge from 6 to 4, and the edge from 6 to 5.

[0070] Two edges {0<-1, 0<-2} are sent by the edge from vertex 0 to 3 and the edge from 6 to 5.

[0071] Thus, the fifth iteration includes 4 messages with 12 IDs.

[0072] Figure 6 is an exemplary directed graph of Figure 5 in which a sixth iteration occurs to detect IDs according to an embodiment of the present invention.

[0073] By employing the DFS approach, there are 5 messages with 22 IDs sent by vertices 0 and 6.

[0074] In particular, the edge {6<-8} is sent by the edge from vertex 3 to 1, the edge from 3 to 4, the edge from 4 to 1, the edge from 4 to 2, and the edge from 5 to 7.

[0075] Two edges {0<-1, 0<-2} are sent by the edge from vertex 3 to 1, the edge from 3 to 4, and the edge from 5 to 7.

[0076] Thus, the sixth iteration includes 5 messages with 22 IDs.

[0077] Figure 7 is an exemplary directed graph of Figure 6 in which a seventh iteration occurs to detect IDs according to an embodiment of the present invention. Thus, the seventh iteration includes 5 messages with 22 IDs.

[0078] By employing the DFS method, there are 6 messages with 32 IDs sent by vertices 0 and 6.

[0079] In particular, the path {0<-1<-4} is sent by the edge from vertex 1 to 0 and the edge from 1 to 2.

[0080] The two paths {0<-2<-1, 0<-2<-4} are sent by the edge from vertex 2 to 0.

[0081] Thus, the seventh iteration also includes 6 messages or 32 IDs.

[0082] After the 7th iteration, if a received vertex is the source of a received edge, the received vertex can identify the next edge in the cycle. Because vertex 1 receives {0<-1} from vertex 4, vertex 1 identifies the path from 4 to 1 to 0 (0<-1<-4), because vertex 2 receives {0<-2} from vertices 1 and 4, vertex 2 identifies two paths from 1 to 2 to 0 (0<-2<-1) and from 4 to 2 to 0 (0<-2<-4), and because vertex 8 receives {6<-8} from vertex 7, vertex 8 identifies the path from 7 to 8 to 6 (6<-8<-7).

[0083] Upon detecting a new edge in the cycle, the new edge is announced by sending a new path to the target vertex.

[0084] Figure 8 is an exemplary directed graph according to an embodiment of the application, where an eighth iteration takes place to detect IDs. Figure 7

[0085] By employing the DFS method, there are 4 messages with 15 IDs.

[0086] In particular, the path {0<-1<-4} is sent by the edge from vertex 1 to 0 and the edge from 1 to 2.

[0087] The two paths {0<-2<-1, 0<-2<-4} are sent by the edge from vertex 2 to 0.

[0088] The path {6<-8<-7} is sent by the edge from vertex 8 to 6.

[0089] Thus, the eighth iteration also includes 4 messages or 15 IDs.

[0090] ​Note that vertex 2 ignores the received path {0<-1<-4} because the first ID in the path is not vertex 2, on the other hand, vertices 0 and 6 do not ignore the received path because their first vertices are vertices 0 and 6 respectively.

[0091] Note also that target vertices 0 and 6 here identify two edge candidates in the loop and redirect the received paths ({0<-1<-4, 0<-2<-1, 0<-2<-4}, {6<-8<-7}) to all adjacent vertices to identify third edge candidates in the next iteration.

[0092] Figure 9 is an exemplary directed graph of Figure 8 where a ninth iteration takes place to detect IDs.

[0093] By employing the DFS approach, there are 5 messages or 24 IDs sent by vertices 0 and 6.

[0094] In particular, the path {6<-8<-7} is sent through the edge from vertex 6 to 3, the edge from 6 to 4 and the edge from 6 to 5.

[0095] The path {0<-1<-4, 0<-2<-1, 0<-2<-4} is sent through the edge from vertex 0 to 3 and the edge from 0 to 5.

[0096] Thus, the ninth iteration includes 5 messages or 27 IDs.

[0097] Figure 10 is an exemplary directed graph of Figure 9 where a tenth iteration takes place to detect IDs.

[0098] By employing the DFS approach, there are 5 messages or 42 IDs.

[0099] In particular, the path {6<-8<-7} is sent through the edge from vertex 3 to 1, the edge from 3 to 4, the edge from 4 to 1, the edge from 4 to 2 and the edge from 5 to 7.

[0100] The path {0<-1<-4, 0<-2<-1, 0<-2<-4} is sent through the edge from vertex 3 to 1, the edge from 3 to 4 and the edge from 5 to 7.

[0101] Thus, the tenth iteration includes 5 messages or 42 IDs.

[0102] After the 10th iteration, if the received vertex is the last ID of the received edge, the received vertex can identify the next edge in the cycle. Vertex 1 identifies the edge from 3 to 1 because of its receipt of {0<-2<-1}, vertex 4 identifies the edge from 3 to 4 because of its receipt of {0<-1<-4, 0<-2<-4}, and vertex 7 identifies the edge from 5 to 7 because of its receipt of {6<-8<-7}.

[0103] Figure 11 is an exemplary directed graph according to an embodiment of the present invention after the 10th iteration to detect IDs. Figure 10 Since vertex 1 knows the edge from vertex 3 to 1, it follows the path 0<-2<-1 and identifies the path 0<-2<-1<-3 in the cycle. Because a 4-length cycle is now being detected, vertex 1 can know that there is an edge from 0 to 3 and 0<-2<-1<-3 is the cycle. Similarly, since vertex 4 knows the edge from vertex 3 to 4, it follows the paths 0<-1<-4 and 0<-2<-4 and identifies two cycles 0<-1<-4<-3, 0<-2<-4<-3. Since vertex 5 knows the edge from vertex 6 to 5, it follows the path 6<-8<-7 and identifies the cycle 6<-8<-7<-5.

[0104] Thus, with reference to Figure 1-11 , the Pregel model is a distributed programming framework that focuses on providing users with a natural API for programming graph algorithms while managing invisible distribution details, including message passing and fault tolerance. The Pregel model is conceptually similar to MapReduce, but has a natural graph API and more efficient support for iterative computation on graphs. It also focuses on distinguishing it from other frameworks that hide distribution details. Pregel is also different because it implements a stateful model of long-lived processes that compute, communicate, and modify local state, as opposed to a dataflow model where any process individually computes on input data and produces output data that is input to other processes. Pregel is inspired by the bulk synchronous parallel model, which provides a synchronous superstep model of its computation and communication. However, the BFS approach has been used in the Pregel model. In contrast, exemplary embodiments of the present invention employ a DFS approach to the Pregel model. In exemplary embodiments, through k iterations, only candidates of edges in the cycle are identified by redirecting received IDs. With k-1 iterations, only candidates of next edges of the identified edges in the cycle are identified by redirecting received IDs, and then with the i-th iteration, the identified edges are informed to the target vertex.

[0105] Figure 12is a block diagram / flowchart of an exemplary method for applying depth-first search (DFS) based cycle detection to a Pregel model according to embodiments of the present application.

[0106] At block 1110, the ID of the first vertex is set to the path (information) and the first vertex is set as the target vertex.

[0107] At block 1120, the following steps are repeated n-1 times.

[0108] At block 1130, the path is sent to the outer edge from the first vertex and the path is passed (via the outer edge) n-1 times by the subsequently received vertices.

[0109] At block 1140, one vertex is found before returning to the target vertex.

[0110] At block 1150, the ID of the above found vertex is added to the path.

[0111] At block 1160, the found vertex is set as the target vertex and n = n-1.

[0112] Figure 13 is a block diagram / flowchart of an exemplary cloud computing environment according to embodiments of the present application.

[0113] It should be understood that while the present application includes detailed descriptions of cloud computing, implementation of the teachings described herein are not limited to a cloud computing environment. Rather, embodiments of the present application are capable of being implemented in conjunction with any other type of computing environment now known or later developed.

[0114] Cloud computing is a model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g. networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0115] The characteristics are as follows:

[0116] On-demand self-service: cloud consumers can unilaterally provision computing capabilities, such as server time and network storage, as needed automatically without requiring human interaction with the service's provider.

[0117] Broad network access: capabilities are available over a network and accessed through standard mechanisms that promote use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0118] Resource pooling: the provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to demand. There is a sense of location independence in that the consumer generally has no control or knowledge over the exact location of the provided resources but can be able to specify location at a higher level of abstraction (e.g., country, state, or datacenter).

[0119] Rapid elasticity: in some cases, capabilities can be provisioned and released in a very short period of time (e.g., within minutes). Consumers can have a sense of "location independence" in that the consumer can be able to rapidly provision resources in multiple locations on short notice.

[0120] Measured service: cloud systems automatically control and optimize resource use by leveraging utilization of resources in an efficient manner, such as in ways reflected by "as-a-service" models for each of the categories: storage as a service, processing as a service, etc. This gives the consumers the ability to have different, potentially heterogeneous, and evolving quantities of resources. Cloud systems hide the details of the underlying network infrastructure and create a common abstraction layer, so the consumers have no knowledge of the underlying physical resources.

[0121] Service models are as follows:

[0122] Software as a Service (SaaS): the capability provided to the consumer is to use the provider's applications running on a cloud infrastructure. The applications are accessible from various client devices through a thin client interface such as a web browser (e.g., web-based e-mail). The consumer does not manage or control the underlying cloud infrastructure including network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0123] Platform as a Service (PaaS): the capability provided to the consumer is to deploy onto the cloud infrastructure consumer-created or acquired applications created using programming languages and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly application hosting environment configurations.

[0124] Infrastructure as a Service (IaaS): the capability provided to the consumer is to provision processing, storage, networks, and other fundamental computing resources where the consumer is able to deploy and run arbitrary software, which can include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure but has control over operating systems, storage, deployed applications, and possibly limited control of select networking components (e.g., host firewalls).

[0125] Deployment models are as follows:

[0126] Private cloud: the cloud infrastructure is operated solely for an organization. It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0127] Community cloud: the cloud infrastructure is shared by several organizations and supports mission-critical enterprise resources. It can be managed by the organizations or a third party and can exist on-premises or off-premises.

[0128] Public cloud: the cloud infrastructure is made available to the general public or a large industry group and is owned by an organization selling cloud services.

[0129] Hybrid cloud: the cloud infrastructure is a composition of two or more clouds (private, community, or public) that remain unique entities but are bound together using standard or proprietary technologies that enable data and application portability.

[0130] A cloud computing environment is service-oriented, focusing on stateless, low-coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure comprising a network of interconnected nodes.

[0131] Referring now to the drawing Figure 13 , an illustrative cloud computing environment 1250 for implementing a use case of the present application is described. As shown, cloud computing environment 1250 includes one or more cloud computing nodes 1210 with which local computing devices used by cloud consumers, such as, for example, personal digital assistant (PDA) or cellular telephone 1254A, desktop computer 1254B, laptop computer 1254C, and / or automobile computer system 1254N can communicate. Nodes 1210 can communicate with one another. They can be grouped (not shown) physically or virtually, in one or more networks, such as Private, Community, Public, or Hybrid clouds as described hereinabove, or a combination thereof. This allows cloud computing environment 1250 to offer infrastructure, platforms and / or software as services with Figure 13 The types of computing devices 1254A-N shown in FIG. 12 are intended to be illustrative only and computing nodes 1210 and cloud computing environment 1250 can communicate with any type of computerized devices over any type of network and / or network addressable connection (e.g., using a web browser).

[0132] Figure 14 is a schematic diagram of the exemplary abstraction model layers according to an embodiment of the present application. It should be appreciated that Figure 14 The components, layers, and functions shown in FIG. 12 are intended to be illustrative only and embodiments of the present application are not limited in their scope to what is depicted. As depicted, the following layers and corresponding functionality are provided:

[0133] Hardware and software layer 1360 includes hardware and software components. Examples of hardware components include: mainframes 1361; RISC (Reduced Instruction Set Computer) architecture based servers 1362; servers 1363; blade servers 1364; storage devices 1365; and networks and networking components 1366. In some embodiments, software components include network application server software 1367 and database software 1368.

[0134] Virtualization layer 1370 provides an abstraction layer from which the following examples of virtual entities can be provided:

[0135] Virtual servers 1371; virtual storage 1372; virtual networks 1373, including virtual private networks; virtual applications and operating systems 1374; and virtual clients 1375.

[0136] In one example, management layer 1380 can provide the functions described below. Resource provisioning 1381 provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing 1382 provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources can include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 1383 provides access to the cloud computing environment for consumers and system administrators. Service level management 1384 provides cloud computing resource allocation and management such that required service levels are met. Service Level Agreement (SLA) planning and fulfillment 1385 provide pre-arrangement for, and procurement of, cloud computing resources for which future usage is anticipated in accordance with an SLA.

[0137] Workloads layer 1390 provides examples of functionality for which the cloud computing environment can be utilized. Examples of workloads and functions which can be provided from this layer include: mapping and navigation 1391; software development and lifecycle management 1392; virtual classroom education delivery 1393; data analysis processing 1394; transaction processing 1395; and DFS-based cycle detection in cloud servers 1396.

[0138] Figure 15 is a block diagram / flowchart of a practical application for applying DFS-based cycle detection to a Pregel model according to an embodiment of the present invention.

[0139] Financial crime (e.g., fraud, theft, money laundering) is a large and growing problem that touches almost every financial institution and many individuals, and in some cases the entire society, to some extent. Financial institutions are on the front lines in the war against financial crime, and as such, must invest significant human and technical resources into this effort. Current processes for detecting financial malfeasance, including the technology used, have limitations in their ability to effectively distinguish between malicious behavior and ordinary financial activity. These limitations often result in an overall over-reporting of suspicious activity (often manifested as "alerts") that requires time-intensive and expensive manual review.

[0140] However, the DFS-based cycle detection method of the present invention can help better detect, for example, financial crime. Thus, at least one practical application of the present invention involves detecting fraud, particularly as it relates to banking systems.

[0141] Referring back to Figure 15 , a bank 1420 processes financial transactions 1410. One or more servers 1425 can be used to process such financial transactions 1410 by accessing various databases 1430 that include customer information / data. An example embodiment can be used to generate a graph 1435 that includes a plurality of nodes and a plurality of edges connecting the nodes. Thus, as described above, graph-based feature generation 1440 can be implemented by a DFS method 1442. As shown at 1450, the graph-based feature generation 1440 results in filtering of risk ratings and alerts. Thus, accurate alerts 1460 can be generated based on using the DFS method 1442. The alerts 140 can be analyzed by an investigator 1470.

[0142] Thus, financial crime is a broad and growing class of criminal activity that involves the misuse, misappropriation, or misrepresentation of entities having monetary value. Common sub-classes of financial crime include theft, fraud, and money laundering (i.e., obscuring the true source of a monetary entity to evade regulations or avoid taxes). The monetary value of such crimes can range from tens of dollars to billions of dollars, however, the overall negative consequences of such crimes far exceed their monetary value. In fact, the consequences can even be sociological in scope.

[0143] Financial institutions have been exploring the use of machine learning techniques to augment existing transaction monitoring capabilities. Machine learning techniques offer promising capabilities to identify suspicious activity from incoming transaction streams and filter false positives from alerts generated by current techniques, making existing processes more efficient and ultimately more effective. These machine learning techniques rely on a set of features generated from knowledge about the parties to a transaction, from individual and aggregate transaction metrics, and from a topology of party-to-party relationships derived from static knowledge and transaction history. Topology features can be computed according to a DFS-based cycle detection method that can be proposed according to example embodiments of the present invention. For example, example embodiments of the present invention generate a graph from currency transfers (e.g., accounts = nodes, transfers = edges). If there is a (time) period, the score of accounts in the period goes up. With other scores, e.g., number of transfers, amount of balance, etc., the machine learning informs the operator or investigator of the alert.

[0144] As used herein, the terms "data," "content," "information," and similar terms can be used interchangeably to refer to the data being collected, transmitted, received, displayed, and / or stored according to various example embodiments. Thus, use of any such terms should not be taken to limit the scope of the disclosure. Additionally, where a computing device is described herein to receive data from another computing device, such a receipt of data can be accomplished directly, or indirectly through one or more intermediary computing devices, such as, one or more servers, relays, routers, network access points, base stations, and / or the like.

[0145] To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0146] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0147] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch cards or

[0148] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions into the respective computing / processing device for storage in a computer readable storage medium within the respective computing / processing device.

[0149] Computer readable program instructions for carrying out operations of the present application can be assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0150] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0151] These computer readable program instructions can be provided to at least one processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including

[0152] Computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps / proc- essing steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0153] The flow diagrams and the block diagrams in the drawings are meant as possible implementations of systems, methods, and computer program products according to the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logic functions (s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. Also, it will be noted that each of the blocks of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0154] Reference throughout this specification to “one embodiment” or “an embodiment” or “ex- amples,” and other variations thereof, means that a particular feature, structure, characteristic, and so forth being described in connection with the embodiment is included in at least one embodiment of the present principles. Therefore, appearances of the phrase “in one embodiment” or “in an embodiment” or any other variations thereof appearing throughout this specification, and any other variations thereof, do not necessarily refer to the same embodiment.

[0155] It will be appreciated that any of the following “ / ”, “and / or”, and “at least one of’ are intended to encompass only a selection of the first listed option, or only a selection of the second listed option, or only a selection of the two options. As a further example, in the case of “A, B, and / or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B) only, or the selection of the third listed option (C) only, or the selection of both options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as is clear to one of ordinary skill in this and related arts, for as many items as are chosen in a similar manner.

[0156] Preferred embodiments of systems and methods for depth-first search (DFS) based cycle detection for Pregel model are described (which are intended to be illustrative and not limiting), noting that modifications and variations can be made by those skilled in the art in light of the above teachings. It is therefore to be understood that changes can be made in the particular embodiments described, which will be apparent to those with skill in the art, which fall within the scope of the application as outlined by the claims appended hereto. Accordingly, while the present application is described with reference to the above specific embodiments, it is understood that it is not to be limited by particular examples, but is to include variations and modifications as would be apparent to one of ordinary skill in the art.

[0157] In preferred embodiments of the present application, there is provided a computer- implemented method for reducing memory consumption in a depth-first search (DFS) based cycle detection process to detect n-length cycles on a Pregel model, the computer-implemented method comprising: generating a graph comprising a plurality of vertices and edges connecting the plurality of vertices; starting a cycle from a first vertex in the plurality of vertices; setting an ID of the first vertex onto a path and setting the first vertex as a target vertex; and iterating the following n-1 times: sending the path from the first vertex to an out-edge and transmitting the path n-1 times by a subsequently received vertex via the out-edge; finding a vertex before returning to the target vertex; adding an ID of the found vertex to the path; and setting the found vertex as the target vertex, such that n = n-1, where n is a number of iterations. Preferably, with k iterations, a candidate of a last edge in a cycle is identified by only redirecting received IDs. Preferably, with the kth iteration, the identified edge is notified to the target vertex. Preferably, an output of the Pregel model is a set of values output by the plurality of vertices.

Claims

1. A computer-implemented method for reducing memory consumption during a loop detection process, the computer-implemented method comprising: The depth-first search method is used to detect n-length cycles in the Pregel model as follows: Generate a graph that includes multiple vertices and edges connecting the multiple vertices; The loop begins from the first vertex among the plurality of vertices; Set the identifier of the first vertex to the path, and set the first vertex as the target vertex; as well as The depth-first search process is iterated n-1 times, wherein the depth-first search process includes: sending the path to any vertex outside the first vertex, and the path is transmitted n-1 times by the subsequently received vertex via the outside, where n is the number of iterations; In this process, k iterations are used to identify candidates for the last edge in the loop by redirecting the received identifiers. In the k-th iteration, the identified edge is notified to the target vertex.

2. The computer-implemented method according to claim 1, wherein, The depth-first search process also includes finding a vertex before returning to the target vertex.

3. The computer-implemented method according to claim 2, wherein, The depth-first search process also includes adding the identifiers of the found vertices to the path.

4. The computer-implemented method according to claim 3, wherein, The depth-first search process also includes setting the found vertex as the target vertex, such that n = n-1.

5. The computer-implemented method according to claim 1, wherein, The Pregel model is a programming model that enables batch synchronous parallelism for graph analysis.

6. The computer-implemented method according to claim 1, wherein, The output of the Pregel model is a set of values ​​output by the plurality of vertices.

7. A computer program product for reducing memory consumption during a loop detection process, the computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a computer to cause the computer to perform the method according to any one of claims 1 to 6.

Images