Driving circuit, micro-fluidic driving device and driving method

Abstract

The application discloses a driving circuit, a micro-fluid driving device and a driving method, relates to the field of micro-fluids, and comprises a data writing module, a first inverter and a second inverter. The output end of the data writing module is connected with a first node. The first end of the first inverter is connected with a first power supply end, the second end is connected with a second power supply end, the input end is connected with the first node, and the output end is connected with a second node. The first end of the second inverter is connected with the first power supply end, the second end is connected with the second power supply end, the input end is connected with the second node, and the output end is connected with the input end of the first inverter. The data writing module and the latch circuit composed of inverters are introduced in the driving circuit, a storage capacitor is not needed to be introduced, the speed of driving signal output is improved, the driving signal is quickly written to the driving electrode, and when the application is applied to the micro-fluid driving device, the driving of large-scale array droplets is facilitated.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a driving circuit, a microfluidic driving device, and a driving method. Background Technology

[0002] Microfluidics is an emerging interdisciplinary field involving chemistry, fluid physics, microelectronics, new materials, biology, and biomedical engineering. It enables precise manipulation of droplet movement, facilitating droplet fusion, separation, and various biochemical reactions. It is a technology primarily characterized by the manipulation of fluids at the micrometer scale. In recent years, microfluidic chips have been widely applied in biology, chemistry, and medicine due to their advantages such as small size, low power consumption, low cost, small sample and reagent requirements, ability to perform individual and precise droplet manipulation, short detection time, high sensitivity, and ease of integration with other devices.

[0003] In related technologies, a driving circuit is usually used to drive the droplets. The driving circuit relies on the storage capacitor to hold the signal, which makes it difficult to achieve fast signal writing and makes it difficult to drive droplets in large-scale arrays. Summary of the Invention

[0004] In view of this, the present invention provides a driving circuit, a microfluidic driving device, and a driving method, which aims to achieve rapid signal writing and facilitate the implementation of droplet driving for large-scale arrays.

[0005] In a first aspect, the present invention provides a driving circuit, including a data writing module, a first inverter, and a second inverter;

[0006] The output of the data writing module is connected to the first node;

[0007] The first terminal of the first inverter is connected to the first power supply terminal, the second terminal is connected to the second power supply terminal, the input terminal is connected to the first node, and the output terminal is connected to the second node.

[0008] The first terminal of the second inverter is connected to the first power supply terminal, the second terminal is connected to the second power supply terminal, the input terminal is connected to the second node, and the output terminal is connected to the input terminal of the first inverter.

[0009] In a second aspect, the present invention provides a microfluidic driving device, comprising a substrate, a driving layer and a microfluidic structure layer, wherein the driving layer is located between the substrate and the microfluidic structure layer;

[0010] The driving layer includes a driving circuit, multiple driving electrodes, and a common electrode disposed opposite to the driving electrodes. The output terminal of the driving circuit is electrically connected to the driving electrodes. The microfluidic structure layer includes at least one first channel, and the first channel corresponds to multiple driving electrodes. The driving circuit is the driving circuit provided in the first aspect of the present invention.

[0011] Thirdly, the present invention provides a driving method for a microfluidic driving device, used to drive the microfluidic driving device provided in the second aspect, the driving method comprising:

[0012] A droplet is introduced into the first channel;

[0013] In the first stage, a first control signal is provided to the driving circuit connected to the driving electrode at the location of the droplet, the control data writing module is turned on, the data signal line inputs the first signal, and the microfluidic circuit transmits the driving signal to the driving electrode.

[0014] In the second stage, a second control signal is provided to the drive circuit to turn off the control data writing module. The first inverter and the second inverter control the drive circuit to transmit the drive holding signal to the drive electrode by controlling the signals of the first node and the second node.

[0015] Fourthly, the present invention provides another driving circuit, including a data writing module, a first inverter, a second inverter, and a third inverter;

[0016] The first end of the data writing module is connected to the data signal line, the second end is connected to the input of the first inverter, and the control end is connected to the control signal line.

[0017] The first terminal of the first inverter is connected to the first power supply terminal, the second terminal is connected to the second power supply terminal, and the output terminal is connected to the third node.

[0018] The first terminal of the second inverter is connected to the first power supply terminal, the second terminal is connected to the second power supply terminal, the input terminal is connected to the third node, and the output terminal is connected to the fourth node.

[0019] The input of the third inverter is connected to the fourth node, the output is connected to the third node, the first terminal is connected to the first power supply terminal, and the second terminal is connected to the second power supply terminal.

[0020] The third node serves as the output terminal of the drive circuit and is electrically connected to the drive electrode; alternatively, the third node serves as the control terminal, controlling the output signal of the drive circuit.

[0021] Fifthly, the present invention also provides a microfluidic driving device, comprising a substrate, a driving layer and a microfluidic structure layer, wherein the driving layer is located between the substrate and the microfluidic structure layer;

[0022] The driving layer includes a driving circuit, multiple driving electrodes, and a common electrode disposed opposite to the driving electrodes. The output terminal of the driving circuit is electrically connected to the driving electrodes. The microfluidic structure layer includes at least one first channel, and the first channel corresponds to multiple driving electrodes. The driving circuit is the microfluidic driving circuit provided in the fourth aspect of the present invention.

[0023] Sixthly, the present invention also provides a driving method for a microfluidic driving device, used to drive the microfluidic driving device provided in the fifth aspect of the present invention, the driving method comprising:

[0024] A droplet is introduced into the first channel;

[0025] In the first stage, a first control signal is provided to the microfluidic driving circuit connected to the driving electrode at the location of the droplet, the control data writing module is turned on, and the first signal of the data signal line is transmitted to the driving electrode as a driving signal. The voltage value of the driving signal is Vdata1.

[0026] In the second stage, a second control signal is provided to the microfluidic drive circuit, the control data writing module is turned off, and the signal output by the third node is a drive-hold signal provided by the third inverter to the drive electrode. The voltage value of the drive-hold signal is VDD-Vth, where Vdata1 = VDD-Vth, VDD is the voltage value of the first power supply terminal, and Vth is the threshold voltage of the transistor in the third inverter; or, the voltage value of the drive-hold signal is VEE-Vth, where Vdata1 = VEE-Vth, VEE is the voltage value of the first power supply terminal, and Vth is the threshold voltage of the transistor in the third inverter.

[0027] In a seventh aspect, the present invention also provides a driving method for a microfluidic driving device, used to drive the microfluidic driving device provided in the fifth aspect of the present invention. The microfluidic driving circuit in the microfluidic driving device further includes a gating module, which includes a first gating unit and a second gating unit. The control terminal of the first gating unit is connected to a third node, and the control terminal of the second gating unit is connected to a fourth node. The first terminal of the first gating unit is connected to a first level terminal, and the second terminal is connected to the output terminal of the driving circuit. The first terminal of the second gating unit is connected to a second level terminal, and the second terminal is connected to the output terminal of the driving circuit.

[0028] The driving methods include:

[0029] A droplet is introduced into the first channel;

[0030] In the first stage, a first control signal is provided to the microfluidic driving circuit connected to the driving electrode at the location of the droplet, and the control data writing module is turned on; the signal of the third node controls the first gating unit to turn on and the second gating unit to turn off, and the signal at the first level terminal is used as a driving signal and transmitted to the driving electrode.

[0031] In the second stage, the data writing module is turned off, the signal of the third node is held, the first gating unit is turned on, the second gating unit is turned off, and the signal at the first level terminal is used as a drive holding signal and transmitted to the drive electrode.

[0032] Compared with the prior art, the driving circuit, microfluidic driving device and driving method provided by the present invention achieve at least the following beneficial effects:

[0033] The driving circuit provided in this embodiment of the invention incorporates a data writing module and two inverters. The two inverters form a latching circuit. When the data writing module is on, it writes data to the output of the second inverter. The output of the second inverter serves as the output of the driving circuit, and the signal can be directly provided to the driving electrode to be driven through the output of the second inverter. This eliminates the need for a storage capacitor and the charging process, enabling rapid signal writing. When the data writing module is off, the signal from the output of the second inverter is fed back to the input of the first inverter, achieving signal feedback locking and facilitating long-term signal retention. Therefore, the driving circuit provided in this embodiment of the invention achieves both rapid signal writing and long-term signal retention, which is beneficial for driving large-scale driving electrode arrays. When this driving circuit is applied to a microfluidic driving device, it helps improve the driving efficiency of droplets.

[0034] Of course, any product implementing this invention need not necessarily achieve all of the technical effects described above at the same time.

[0035] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0037] Figure 1 The diagram shown is a schematic of a microfluidic drive circuit provided by related technologies;

[0038] Figure 2 The diagram shown is a schematic representation of a driving circuit provided in an embodiment of the present invention.

[0039] Figure 3 The diagram shown is a schematic diagram of the connection between the driving circuit and the driving electrode provided in an embodiment of the present invention.

[0040] Figure 4 The diagram shown is another connection diagram of the driving circuit and driving electrode provided in an embodiment of the present invention.

[0041] Figure 5 The diagram shown is a schematic diagram of a driving circuit provided in an embodiment of the present invention.

[0042] Figure 6The diagram shown is another schematic diagram of the driving circuit provided in an embodiment of the present invention.

[0043] Figure 7 The diagram shown is another structural schematic of the driving circuit provided in an embodiment of the present invention;

[0044] Figure 8 The diagram shown is a schematic of a drive circuit including a gating module.

[0045] Figure 9 The diagram shown is another circuit diagram when the driving circuit includes a gating module;

[0046] Figure 10 The diagram shown is a structural schematic of a microfluidic drive device provided in an embodiment of the present invention.

[0047] Figure 11 The image shown is a top view of the area where the drive circuit is located in the microfluidic drive device provided in an embodiment of the present invention;

[0048] Figure 12 As shown Figure 11 A cross-sectional view of a microfluidic drive device along the AA' direction;

[0049] Figure 13 The image shown is another top view of the area where the drive circuit is located in the microfluidic drive device provided in the embodiment of the present invention;

[0050] Figure 14 As shown Figure 13 A cross-sectional view of a microfluidic drive device along the BB' direction;

[0051] Figure 15 As shown Figure 11 Another AA'-direction cross-sectional view of the microfluidic drive device;

[0052] Figure 16 The diagram shown is a flowchart of a driving method for a microfluidic driving device provided in an embodiment of the present invention.

[0053] Figure 17 The image shown is related to Figure 5 A timing diagram corresponding to the driving circuit in the diagram;

[0054] Figure 18 The image shown is related to Figure 6 A timing diagram corresponding to the driving circuit in the diagram;

[0055] Figure 19 As shown Figure 8 A timing diagram corresponding to the driving circuit in the middle;

[0056] Figure 20The diagram shown is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0057] Figure 21 The diagram shown is a structural schematic of another driving circuit provided in an embodiment of the present invention, including a gating module;

[0058] Figure 22 The diagram shown is another flowchart of the driving method for the microfluidic driving device provided in an embodiment of the present invention;

[0059] Figure 23 As shown Figure 20 A timing diagram corresponding to the driving circuit in the middle;

[0060] Figure 24 The diagram shown is a flowchart of another driving method for the microfluidic driving device provided in an embodiment of the present invention.

[0061] Figure 25 As shown Figure 24 A timing diagram of a driving circuit. Detailed Implementation

[0062] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0063] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0064] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0065] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0066] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0067] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0068] Figure 1 The diagram shows a microfluidic driving circuit provided by related technologies. This microfluidic driving circuit is used to provide a driving voltage to the driving electrode in a microfluidic driving device, thereby driving the movement of droplets in the microfluidic driving device. The driving circuit includes a transistor T and a storage capacitor C. The first terminal of the transistor T is connected to the data line Data', the second terminal is connected to the driving electrode 90', and the gate is connected to the control line Gate'. One terminal of the storage capacitor C is connected to the common signal line COM, and the other terminal is connected to the driving electrode 90'.

[0069] When the transistor is turned on, the data signal on the data line is transmitted to the driving electrode and the storage capacitor, causing the driving electrode to generate a driving voltage, which drives the droplet forward. When the transistor is turned off, the voltage stored in the storage capacitor is applied to the driving electrode, giving it a certain holding voltage to further drive the droplet movement. It is evident that the driving circuits in related technologies rely on the storage capacitor for signal holding, making it difficult to achieve fast signal writing and thus challenging for driving droplets in large-scale arrays.

[0070] To address this, the present invention provides a driving circuit comprising a data writing module, a first inverter, and a second inverter. The output of the data writing module is connected to a first node. The first inverter has a first terminal connected to a first power supply terminal, a second terminal connected to a second power supply terminal, an input terminal connected to the first node, and an output terminal connected to the second node. The second inverter has a first terminal connected to the first power supply terminal, a second terminal connected to the second power supply terminal, an input terminal connected to the second node, and an output terminal connected to the input terminal of the first inverter. In this way, fast writing of the driving signal can be achieved without the introduction of a storage capacitor, which is beneficial for driving large-scale arrays.

[0071] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the embodiments of this invention.

[0072] Figure 2 The diagram shown is a structural schematic of a driving circuit provided in an embodiment of the present invention. Please refer to it. Figure 2 The driving circuit provided in this embodiment of the invention includes a data writing module 10, a first inverter 20, and a second inverter 30.

[0073] The output of the data writing module 10 is connected to the first node P;

[0074] The first terminal of the first inverter 20 is connected to the first power supply terminal D1, the second terminal is connected to the second power supply terminal D2, the input terminal is connected to the first node P, and the output terminal is connected to the second node NP.

[0075] The first terminal of the second inverter 30 is connected to the first power supply terminal D1, the second terminal is connected to the second power supply terminal D2, the input terminal is connected to the second node NP, and the output terminal is connected to the input terminal of the first inverter 20, i.e., the first node P.

[0076] It should be noted that the data writing module 10, the first inverter 20 and the second inverter 30 mentioned in the embodiments of the present invention do not contain capacitors.

[0077] In the driving circuit provided in this embodiment of the invention, a data writing module 10 and two inverters are introduced. The output terminal of the data writing module 10, the input terminal of the first inverter 20, and the output terminal of the second inverter 30 are all connected to the first node P. The output terminal of the first inverter 20 and the input terminal of the second inverter 30 are connected to the second node NP. The two inverters form a latching circuit. When the data writing module 10 is turned on, it writes data to the output terminal of the second inverter 30. The output terminal of the second inverter 30 can serve as the output terminal of the driving circuit. The signal can be directly provided to the driving electrode to be driven through the output terminal of the second inverter 30, without the need for a storage capacitor or a charging process, thus enabling fast signal writing. After the data writing module 10 is turned off, the signal at the output of the second inverter 30 is fed back to the input of the first inverter 20. This controls the signal at either the first power supply terminal D1 or the second power supply terminal D2 to be transmitted through the second inverter 30 to the output of the drive circuit as a drive hold signal, or controls the output of the drive circuit to output a drive hold signal, thereby achieving signal feedback locking and facilitating long-term holding of the drive signal. Therefore, the drive circuit provided in this embodiment eliminates the storage capacitor, achieving rapid signal writing and long-term signal holding, which is beneficial for driving a large-scale drive electrode array 90. When this drive circuit is applied to a microfluidic drive device, it helps improve the driving efficiency of droplets.

[0078] Continue to refer to Figure 2 In one optional embodiment of the present invention, the driving circuit is used to provide a driving signal to the driving electrode in the microfluidic driving device; the output terminal of the second inverter 30 serves as the output terminal of the driving circuit and is electrically connected to the driving electrode; or, the signals of the first node P and the second node NP serve as control signals to control the output of the signal at the output terminal of the driving circuit.

[0079] Specifically, when the driving circuit provided in this embodiment of the invention is applied to a microfluidic driving device, the driving circuit can be used to provide driving signals to the driving electrodes in the microfluidic driving device. A first implementation is to directly use the output terminal of the second inverter 30 as the output terminal of the driving circuit, for example, please refer to... Figure 3 It is electrically connected to the drive electrode 90 in the microfluidic drive device. Thus, when the data writing module 10 is turned on, the data signal provided by the data writing module 10 can be directly used as a drive signal to the drive electrode 90, thereby effectively improving the driving efficiency of the drive electrode 90. Figure 3 The diagram shown illustrates a connection between the driving circuit and the driving electrode 90 provided in an embodiment of the present invention. A second implementation uses the signals from the first node P and the second node NP as control signals to control the output signal of the driving circuit. For example, please refer to... Figure 4 , Figure 4 The diagram shows another connection between the driving circuit and the driving electrode 90 provided in this embodiment of the invention. In this embodiment, a gating module 80 is introduced into the driving circuit. The output of the gating module 80 is controlled by the signals from the first node P and the second node NP, and the signal output by the gating module 80 is provided as a driving signal to the driving electrode 90. This approach also eliminates the need for a storage capacitor in the driving circuit, which is beneficial for improving the driving efficiency of the driving electrode 90 and for enabling the driving of a large-scale array of driving electrodes 90. The specific configuration of the gating module 80 will be described in detail in subsequent embodiments.

[0080] Figure 5 and Figure 6 The following are schematic diagrams of a driving circuit provided in an embodiment of the present invention. This embodiment details the configuration of the data writing module 10, the first inverter 20, and the second inverter 30 in the driving circuit.

[0081] Please refer to Figure 5 and Figure 6 In an optional embodiment of the present invention, the data writing module 10, the first inverter 20 and the second inverter 30 all include transistors, and the transistors are of the same type.

[0082] Specifically, this embodiment illustrates a scheme where the data writing module 10, the first inverter 20, and the second inverter 30 are all composed of transistors. When the data writing module 10, the first inverter 20, and the second inverter 30 are all composed of transistors, the types of each transistor are the same; for example, please refer to... Figure 5 Each transistor can be considered an N-type transistor, or please refer to [reference needed]. Figure 6Each transistor can be a P-type transistor. Thus, the driving circuit provided in this embodiment of the invention can be formed using transistors of the same structure, without the need to form different transistor structures. This helps to reduce the process complexity of manufacturing the driving circuit and improve production efficiency.

[0083] When all the above transistors are N-type transistors, applying a high-level signal to the control terminal of an N-type transistor turns the corresponding transistor on; conversely, applying a low-level signal to the control terminal of an N-type transistor turns the corresponding transistor off. When all the above transistors are P-type transistors, applying a low-level signal to the control terminal of a P-type transistor turns the corresponding transistor on; conversely, applying a high-level signal to the control terminal of a P-type transistor turns the corresponding transistor off.

[0084] Continue to refer to Figure 5 or Figure 6 In an optional embodiment of the present invention, the data writing module 10 includes a first transistor T1, the gate of the first transistor T1 is connected to a control signal line Gate, the first terminal is connected to a data signal line Data, and the second terminal is connected to a first node P. When a control signal is provided to the gate of the first transistor T1 through the control signal line Gate, the first transistor T1 can be controlled to be turned on or off. Figure 5 In the illustrated embodiment, the first transistor T1 is an N-type transistor. When the control signal line Gate provides a high-level signal to the gate of the first transistor T1, the first transistor T1 is turned on, and the signal on the data signal line Data is transmitted to the first node P. When the control signal line Gate provides a low-level signal to the gate of the first transistor T1, the first transistor T1 is turned off.

[0085] Figure 6 The illustrated embodiment uses a P-type transistor as an example. When the control signal line Gate provides a low-level signal to the gate of the first transistor T1, the first transistor T1 is turned on, and the signal on the data signal line Data is transmitted to the first node P. When the control signal line Gate provides a high-level signal to the gate of the first transistor T1, the first transistor T1 is turned off.

[0086] Continue to refer to Figure 5 or Figure 6 In an optional embodiment of the present invention, the first inverter 20 includes a second transistor T2 and a third transistor T3. The gate and first terminal of the second transistor T2 are both connected to the first power supply terminal D1, and the second terminal is connected to the second node NP. The gate of the third transistor T3 is connected to the first node P, the first terminal is connected to the second power supply terminal D2, and the second terminal is connected to the second node NP.

[0087] Specifically, this embodiment illustrates a scheme where the first inverter 20 includes two transistors, namely a second transistor T2 and a third transistor T3. The second transistor T2 and the third transistor T3 are connected in series between the first power supply terminal D1 and the second power supply terminal D2. The gate and first terminal of the second transistor T2 are connected to the first power supply terminal D1, and the gate of the third transistor T3 is connected to the first node P. That is, the third transistor T3 is turned on or off under the control of the potential of the first node P. Figure 5 In the illustrated embodiment, the third transistor T3 is an N-type transistor. When the potential of the first node P is high, the third transistor T3 is turned on, and the signal transmitted from the second power supply terminal D2 of the third transistor T3 serves as the output signal of the first inverter 20. When the potential of the first node P is low, the third transistor T3 is turned off, and the second transistor T2 is turned on. The signal transmitted from the first power supply terminal D1 of the second transistor T2 serves as the output signal of the first inverter 20. Figure 6 In the illustrated embodiment, the third transistor T3 is a P-type transistor. When the potential of the first node P is low, the third transistor T3 is turned on, and the signal transmitted by the third transistor T3 to the second power supply terminal D2 serves as the output signal of the first inverter 20. When the potential of the first node P is high, the third transistor T3 is turned off, and the second transistor T2 is turned on. The signal transmitted by the second transistor T2 to the first power supply terminal D1 serves as the output signal of the first inverter 20.

[0088] Alternatively, please refer to Figure 5 When the transistor in the driving circuit is an N-type transistor, the signal at the first power supply terminal D1 is the first power supply signal VDD, and the signal at the second power supply terminal D2 is the second power supply signal VEE. Please refer to [reference needed]. Figure 6 When the transistor in the driving circuit is a P-type transistor, the signal at the first power supply terminal D1 is the second power supply signal VEE, and the signal at the second power supply terminal D2 is the first power supply signal VDD.

[0089] In an optional embodiment of the present invention, in the first inverter 20, the width-to-length ratio of the second transistor T2 is A2, and the width-to-length ratio of the third transistor T3 is A3, where A3 = k1 * A2, and k1 ≥ 10. That is, in the first inverter 20, the width-to-length ratio of the third transistor T3 is much larger than that of the second transistor T2. Thus, when the third transistor T3 is turned on, since A3 is much larger than A2, the impedance of the second transistor T2 is much larger than the impedance of the third transistor T3, ensuring that the second transistor T2 is in the off state. Conversely, when the third transistor T3 is turned off, the impedance of the second transistor T2 is much smaller than the impedance of the third transistor T3, ensuring that the second transistor T2 is in the on state. Therefore, this method helps to ensure more reliable performance of the first inverter 20.

[0090] Continue to refer to Figure 5 or Figure 6 In an optional embodiment of the present invention, the second inverter 30 includes a fourth transistor T4 and a fifth transistor T5. The gate and first terminal of the fourth transistor T4 are both connected to the first power supply terminal D1, and the second terminal is connected to the first node P. The gate of the fifth transistor T5 is connected to the second node NP, the first terminal is connected to the second power supply terminal D2, and the second terminal is connected to the first node P.

[0091] Specifically, this embodiment illustrates a scheme where the first inverter 20 includes two transistors, namely a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 and the fifth transistor T5 are connected in series between the first power supply terminal D1 and the second power supply terminal D2. The gate and first terminal of the fourth transistor T4 are connected to the first power supply terminal D1, and the gate of the fifth transistor T5 is connected to the second node NP. That is, the fifth transistor T5 is turned on or off under the control of the potential of the second node NP. Figure 5 In the illustrated embodiment, the fifth transistor T3 is an N-type transistor. When the potential of the second node NP is high, the fifth transistor T5 is turned on, and the signal transmitted from the second power supply terminal D2 of the fifth transistor T5 serves as the output signal of the second inverter 30. When the potential of the second node NP is low, the fifth transistor T5 is turned off, and the fourth transistor T4 is turned on, and the signal transmitted from the first power supply terminal D1 of the fourth transistor T4 serves as the output signal of the second inverter 30. Figure 6 In the illustrated embodiment, the fifth transistor T3 is a P-type transistor. When the potential of the second node NP is low, the fifth transistor T5 is turned on, and the signal transmitted by the fifth transistor T5 to the second power supply terminal D2 serves as the output signal of the second inverter 30. When the potential of the second node NP is high, the fifth transistor T5 is turned off, and the fourth transistor T4 is turned on, and the signal transmitted by the fourth transistor T4 to the first power supply terminal D1 serves as the output signal of the second inverter 30.

[0092] In an optional embodiment of the present invention, in the second inverter 30, the width-to-length ratio of the fourth transistor T4 is A4, and the width-to-length ratio of the fifth transistor T5 is A5, where A5 = k3 * A4, and k3 ≥ 10. That is, in the second inverter 30, the width-to-length ratio of the fifth transistor T5 is much larger than that of the fourth transistor T4. Thus, when the fifth transistor T5 is turned on, since A5 is much larger than A4, the impedance of the fourth transistor T4 is much larger than the impedance of the fifth transistor T5, ensuring that the fourth transistor T4 is in the off state. Conversely, when the fifth transistor T5 is turned off, the impedance of the fourth transistor T4 is much smaller than the impedance of the fifth transistor T5, ensuring that the fourth transistor T4 is in the on state. Therefore, this method helps to ensure more reliable performance of the second inverter 30.

[0093] Optionally, the width-to-length ratio A2 of the second transistor T2 in the first inverter 20 is equal to the width-to-length ratio A4 of the fourth transistor T4 in the second inverter 30, and the width-to-length ratio A3 of the third transistor T3 in the first inverter 20 is equal to the width-to-length ratio A5 of the fifth transistor T5 in the second inverter 30. In this way, in the actual manufacturing process of the drive circuit, the second transistor T2 and the fourth transistor T4 can be manufactured with the same specifications, and the third transistor T3 and the fifth transistor T5 can be manufactured with the same specifications. There is no need to introduce different design specifications for different transistors, which helps to simplify the overall design of the drive circuit.

[0094] Please refer to Figure 5 In one optional embodiment of the present invention, all transistors are N-type transistors, with the first power supply terminal D1 being the positive power supply terminal and the second power supply terminal D2 being the negative power supply terminal.

[0095] Continue to refer to Figure 5When all transistors are N-type transistors, the N-type transistors conduct under the control of a high level. When the first power supply terminal D1 is the positive power supply terminal, the gates of the second transistor T2 and the fourth transistor T4 are both connected to the positive power supply terminal. When the first transistor T1 is turned on, assuming the signal input to the data signal line Data is a high-level signal Vdata, this high-level signal can be used as the output signal of the drive circuit. At this time, T3 is turned on, the signal at the negative power supply terminal is transmitted to the second node NP, the fifth transistor T5 is turned off, and the fourth transistor T4 is turned on. At this time, the signal at the output terminal of the drive circuit is VDD-Vth, where Vth is the threshold voltage of the fourth transistor T4. Optionally, Vdata = VDD-Vth, which helps to ensure the stability of the output signal of the drive circuit. No storage capacitor needs to be introduced in this stage, thus enabling the drive circuit to quickly write data to the drive electrode 90. When the first transistor T1 is turned off, since the first node P is at a high level (VDD-Vth), the third transistor T3 remains on, the signal at the second node NP is still the negative power supply signal, and the fifth transistor T5 remains off. The positive power supply signal is output to the first node P through the fourth transistor T4, keeping the first node P outputting VDD-Vth, which is then supplied to the drive electrode. This achieves the latching function, improving the signal retention rate without the need for a storage capacitor. When the first transistor T1 turns on again, the signal input to the data signal line Data is a low-level signal. When the low-level signal is transmitted to the first node P, the third transistor T3 turns off, and the second transistor T2 turns on. The second transistor T2 transmits the high-level signal from the first power supply terminal D1 to the second node NP, controlling the fifth transistor T5 to turn on. The fifth transistor T5 transmits the low-level signal from the second power supply terminal D2 to the output of the drive signal. During this stage, the drive electrode corresponding to this drive circuit no longer needs to provide a drive signal to propel the droplet forward. Therefore, outputting a low-level signal helps reduce the overall power consumption of the drive circuit.

[0096] Please refer to Figure 6 In one optional embodiment of the present invention, all transistors are P-type transistors, the first power supply terminal D1 is the negative power supply terminal, and the second power supply terminal D2 is the positive power supply terminal.

[0097] Continue to refer to Figure 6When all transistors are P-type transistors, the P-type transistors conduct under low-level control. When the first power supply terminal D1 is the negative power supply terminal, the gates of the second transistor T2 and the fourth transistor T4 are both connected to the negative power supply terminal. When the first transistor T1 is turned on, assuming the signal input to the data signal line Data is a high-level signal Vdata, this high-level signal can be used as the output signal of the drive circuit. At this time, the third transistor T3 is turned off, the second transistor T2 is turned on, the signal at the negative power supply terminal is transmitted to the second node NP, the fifth transistor T5 is turned on, and the fourth transistor T4 is turned off. At this time, the signal at the output terminal of the drive circuit is VDD-Vth, where Vth is the threshold voltage of the fifth transistor T5. Optionally, Vdata = VDD-Vth, which helps to ensure the stability of the output signal of the drive circuit. No storage capacitor needs to be introduced in this stage, thus enabling the drive circuit to quickly write data to the drive electrode 90. When the first transistor T1 is turned off, since the first node P is at a high level (VDD-Vth), the second transistor T2 remains on, and the signal at the second node NP is still the negative power supply signal. The fifth transistor T5 remains on, and the positive power supply signal is output to the first node P through the fifth transistor T5, keeping the first node P outputting VDD-Vth, which is then supplied to the drive electrode. This achieves the latching function, improving the signal retention rate without the need for a storage capacitor. When the first transistor T1 turns on again, the signal input to the data signal line Data is a low-level signal. When the low-level signal is transmitted to the first node P, the third transistor T3 turns on, transmitting the high-level signal from the second power supply terminal D2 to the second node. The fifth transistor T5 turns off, and the fourth transistor T4 turns on, transmitting the low-level signal from the second power supply terminal D2 to the output of the drive signal. During this stage, the drive electrode corresponding to this drive circuit no longer needs to provide a drive signal to propel the droplet forward, thus reducing the overall power consumption of the drive circuit when outputting a low-level signal.

[0098] Figure 7 The diagram shown is another structural schematic of the driving circuit provided in an embodiment of the present invention. This embodiment shows a scheme in which the driving circuit also includes a gating circuit.

[0099] Please refer to Figure 7 In an optional embodiment of the present invention, the driving circuit further includes a gating module 80, which includes a first gating unit 81 and a second gating unit 82. The control terminal of the first gating unit 81 is connected to the first node P, and the control terminal of the second gating unit 82 is connected to the second node NP. The first terminal of the first gating unit 81 is connected to the first level terminal VA, and the second terminal is connected to the output terminal of the driving circuit. The first terminal of the second gating unit 82 is connected to the second level terminal VB, and the second terminal is connected to the output terminal of the driving circuit.

[0100] Specifically, when the signal of the first node P is high, the signal of the second node NP is low; conversely, when the signal of the first node P is low, the signal of the second node NP is high. Therefore, when the signal of the first node P controls the first gating unit 81 to be turned on, the second gating unit 82 is turned off, and the signal of the first level terminal VA is transmitted to the output terminal of the drive circuit; when the signal of the second node NP controls the second gating unit 82 to be turned on, the first gating unit 81 is turned off, and the signal of the second level terminal VB is transmitted to the output terminal of the drive circuit. Using the signal of the first level terminal VA or the second level terminal VB as the output signal of the drive circuit ensures that the output of the drive signal is not affected by the fluctuations of the transistors in the first inverter 20 and the second inverter 30, thus making the overall output of the drive circuit more stable. Assuming that when the first node P is high, the first gating unit 81 is turned on, and the signal of the first level terminal VA is output from the output terminal as a drive signal or drive hold signal provided to the drive electrode. When the signal of the first node P is a low-level signal, the signal of the second node NP is a high-level signal, the second gating unit 82 is turned on, and the signal of the second level terminal VB is transmitted to the output terminal of the driving circuit. Optionally, the signal of the second level terminal VB is a DC signal, such as a 0-level signal. In this stage, the driving electrode corresponding to the driving circuit does not need to provide the driving signal to the droplet to drive it forward. Therefore, outputting a low-level signal is beneficial to reducing the overall power consumption of the driving circuit.

[0101] Figure 8 The diagram shown is a schematic of a drive circuit including the gating module 80. Please refer to it. Figure 8 In an optional embodiment of the present invention, the first gating unit 81 includes a sixth transistor T6, and the second gating unit 82 includes a seventh transistor T7. The transistors included in the first gating unit 81, the second gating unit 82, the data writing module 10, the first inverter 20, and the second inverter 30 are of the same type.

[0102] Specifically, this embodiment shows that the first gating unit 81 and the second gating unit 82 each include transistors, and the types of transistors are the same as those of the transistors included in the data writing module 10, the first inverter 20 and the second inverter 30. In this way, the driving circuit provided in this embodiment of the invention can be formed using transistors of the same structure, without the need to form different transistor structures. Therefore, it is beneficial to reduce the process complexity of manufacturing the driving circuit and improve production efficiency.

[0103] Continue to refer to Figure 8In an optional embodiment of the present invention, one of the first level terminal VA and the other of the second level terminal VB transmits an AC signal, while the other transmits a DC signal; the voltage value corresponding to the AC signal is between the voltage values ​​of the first power supply terminal D1 and the second power supply terminal D2. Optionally, the voltage of the DC signal can be 0V. When a gating module 80 is introduced into the driving circuit, the first level terminal VA and the second level terminal VB alternately output signals to the output terminal of the driving circuit. When the signals of the first level terminal VA and the second level terminal VB are respectively an AC signal and a 0V DC signal, the output signal can be switched between an AC signal and a 0V DC signal. When the driving circuit is applied to a microfluidic driving device, AC driving of droplets can be realized, reducing the hysteresis effect caused by charge accumulation during the driving process.

[0104] It should be noted that, Figure 8 This embodiment is illustrated using the example that all transistors in each driving transistor are N-type transistors. In some other embodiments of the present invention, when a gating module 80 is introduced into the driving circuit, each transistor may also be a P-type transistor. For example, please refer to... Figure 9 , Figure 9 The diagram shown is another circuit schematic when the drive circuit includes the gating module 80. When the transistors in the drive circuit are as follows... Figure 9 When the P-type transistor is shown, except for the different conduction levels, it is similar to... Figure 8 The operation of the driving circuit shown is similar, and will not be described in detail here.

[0105] Based on the same inventive concept, the present invention also provides a microfluidic driving device. Figure 10 The diagram shown is a schematic diagram of a microfluidic driving device provided in an embodiment of the present invention. The microfluidic driving device includes a substrate 00, a driving layer 01 and a microfluidic structure layer 02, with the driving layer 01 located between the substrate 00 and the microfluidic structure layer 02.

[0106] The driving layer 01 includes a driving circuit, multiple driving electrodes 90, and a common electrode 011 disposed opposite to the driving electrodes 90. The output terminal of the driving circuit is electrically connected to the driving electrodes 90. The microfluidic structure layer 02 includes at least one first channel 021, which corresponds to the multiple driving electrodes 90. The driving circuit is the driving circuit mentioned in the above embodiment. Optionally, a droplet 022 is disposed in the first channel 021.

[0107] When the driving circuit mentioned in the above embodiments of the present invention provides a driving signal to the driving electrode 90 in the microfluidic driving device, since no storage capacitor is required in the driving circuit, and no charging process for the storage capacitor is required, the driving signal can be quickly written to the driving electrode 90, thereby improving the driving efficiency of the droplets. Moreover, the latching circuit composed of the first inverter and the second inverter can also achieve long-term holding of the driving signal, which is beneficial to further improve the driving efficiency of the droplets and meet the driving requirements of large-scale driving electrode arrays in microfluidic driving devices.

[0108] Figure 11 The image shown is a top view of the area where the drive circuit is located in the microfluidic drive device provided in an embodiment of the present invention. Figure 12 As shown Figure 11 A cross-sectional view of a microfluidic drive device along the AA' direction is shown. In this embodiment, the drive circuit does not include a gating module. Figure 13 The image shown is another top view of the area where the drive circuit is located in the microfluidic drive device provided in this embodiment of the invention. Figure 14 As shown Figure 13 A cross-sectional view of a microfluidic drive device along the BB' direction is shown in this embodiment. The drive circuit shown includes a gating module 80.

[0109] Please refer to Figure 11 and Figure 12 ,as well as Figure 13 and Figure 14 In an optional embodiment of the present invention, the driving layer includes a first metal layer M1, an active layer Y, and a second metal layer M2 disposed on one side of the substrate 00. The first metal layer M1 and the active layer Y are isolated by an insulating layer. The first metal layer M1 is located between the active layer Y and the substrate 00. The second metal layer M2 is located on the side of the active layer Y away from the substrate 00. In the driving circuit, the gate of the transistor is located on the first metal layer M1, and the first electrode and the second electrode are located on the second metal layer M2. The active layer Y includes an oxide layer or an amorphous silicon layer.

[0110] When the active layer Y is an oxide layer, all transistors in the driving circuit are oxide transistors; when the active layer Y is an amorphous silicon layer, all transistors in the driving circuit are low-temperature polycrystalline silicon transistors. Using oxide transistors or low-temperature polycrystalline silicon transistors to construct the driving circuit of a microfluidic driving device results in a relatively simple structure. During the fabrication of the first metal layer M1, the gates of each transistor in the driving circuit can be formed in the same process; the active layers Y of each transistor can also be fabricated in the same process; during the fabrication of the second metal layer M2, the sources and drains of each transistor can be formed in the same process, thereby simplifying the overall fabrication process of the microfluidic driving device and improving its production efficiency.

[0111] When the active layer Y is an oxide layer, an etching barrier layer may also be included between the active layer Y and the second metal layer M2, for example, please refer to [reference needed]. Figure 15 The etching barrier layer Z can prevent the oxide layer from being etched during the etching of the second metal layer M2, thus protecting the oxide layer. Figure 15 As shown Figure 11 Another AA' cross-sectional view of the microfluidic drive device.

[0112] Based on the same inventive concept, the present invention also provides a driving method for a microfluidic driving device. Figure 16 The diagram shown is a flowchart of a driving method for a microfluidic driving device provided in an embodiment of the present invention. Please refer to it. Figure 16 and Figure 5 The driving method is used to drive the microfluidic driving device in the above embodiments, and the driving method includes:

[0113] S1. Introduce a droplet into the first channel 021;

[0114] S2. In the first stage t1, a first control signal is provided to the driving circuit connected to the driving electrode 90 at the location of the droplet, controlling the data writing module 10 to turn on, the data signal line Data inputs the first signal, and controls the microfluidic circuit to transmit the driving signal to the driving electrode 90.

[0115] S3. In the second stage t2, a second control signal is provided to the drive circuit to turn off the control data writing module 10. The first inverter 20 and the second inverter 30 control the drive circuit to transmit the drive holding signal to the drive electrode 90 by controlling the signals of the first node P and the second node NP.

[0116] Figure 17 The image shown is related to Figure 5 Please refer to the timing diagram corresponding to the driving circuit in the image. Figure 5 and Figure 17 In the first stage t1, a first control signal is provided to the driving circuit corresponding to the driving electrode 90 at the droplet's location, turning on the data writing module 10. This first control signal can be considered as a signal provided to the control terminal of the data writing module 10. The first signal input to the data signal line Data is transmitted to the first node P. When the output terminal of the second inverter 30 serves as the output terminal of the driving circuit, the aforementioned first signal will be output as the output signal of the driving circuit and output to the driving electrode. A driving voltage is formed in the region where the driving electrode is located, driving the droplet forward. In this way, the driving signal to the driving electrode is written quickly, which is beneficial for achieving effective driving of the droplet.

[0117] In the second stage t2, a second control signal is provided to the driving circuit connected to the driving electrode 90 at the droplet location, causing the data writing module 10 to turn off. If the output of the second inverter 30 is used as the output of the driving circuit, the latching effect of the first inverter 20 and the second inverter 30 can maintain the signal of the first node P, thereby enabling the driving circuit to output a driving hold signal to the driving electrode 90, which is continuously provided to the driving electrode. In this way, the driving signal can be maintained using the first inverter 20 and the second inverter 30, achieving continuous driving of the droplet.

[0118] Continue to combine Figure 5 and Figure 17 In an optional embodiment of the present invention, the driving method further includes:

[0119] In the third stage t3, a first control signal is provided to the drive circuit to turn on the control data writing module 10, the data signal line Data inputs the second signal, and the control drive circuit transmits the third signal to the drive electrode 90. The voltage value corresponding to the third signal is less than the voltage values ​​of the drive signal and the drive holding signal.

[0120] Through the driving of the droplet in the first stage t1 and the second stage t2, the droplet has moved to the edge position of the corresponding nth driving electrode 90. At this time, the nth driving electrode 90 no longer needs to provide a driving signal to the droplet, and the driving signal is instead provided by the (n+1)th driving electrode 90. Therefore, in the third stage t3, when the data writing module 10 is turned on, the second signal can be input through the data signal line Data, so that the driving circuit transmits the third signal to the nth driving electrode 90. When the output terminal of the second inverter 30 is used as the output terminal of the driving circuit, the second signal in the third stage t3 is the third signal transmitted to the nth driving electrode 90. The voltage value of the third signal is less than the voltage values ​​of the driving signal and the driving hold signal, so it does not need to drive the nth driving electrode. The (n+1)th driving electrode 90 can start to play a driving role, thereby realizing continuous driving of the droplet.

[0121] Continue to refer to Figure 5 and Figure 17 In an optional embodiment of the present invention, in the driving circuit, the data writing module 10 includes a first transistor T1, the first inverter 20 includes a second transistor T2 and a third transistor T3, and the second inverter 30 includes a fourth transistor T4 and a fifth transistor T5.

[0122] In the first stage t1, the first transistor T1 is turned on, and the voltage value of the drive signal is Vdata1;

[0123] In the second stage t2, the first transistor T1 is turned off, and the signal output by the first node P is the drive-hold signal; the fourth transistor T4 is turned on, and the voltage value of the drive-hold signal is VDD-Vth, where Vdata1 = VDD-Vth, VDD is the voltage value of the first power supply terminal D1, and Vth is the threshold voltage of the fourth transistor T4; or, the fourth transistor T4 is turned on, and the voltage value of the drive-hold signal is VEE-Vth, where Vdata1 = VEE-Vth, VEE is the voltage value of the first power supply terminal D1, and Vth is the threshold voltage of the fourth transistor T4.

[0124] by Figure 5 and Figure 17 Taking the illustrated embodiment as an example, each transistor is an N-type transistor. In the first stage t1, a high-level signal is provided to the gate of the first transistor T1, and the first transistor T1 is turned on. Assuming that the signal of the data signal line Data is a high-level drive signal and the voltage value is Vdata1, the drive signal will be output to the drive electrode 90.

[0125] In the second stage t2, a low-level signal is provided to the gate of the first transistor T1, and the first transistor T1 is turned off; the signal of the first node P remains at a high level, the third transistor T3 is turned on, and the low-level signal of the second power supply terminal D2 is transmitted to the second node NP, causing the fifth transistor T5 to be turned off and the fourth transistor T4 to be turned on. At this time, the voltage value of the drive holding signal output by the output terminal of the drive circuit is VDD-Vth, where Vth is the threshold voltage of the fourth transistor T4.

[0126] In this embodiment, the value of the driving signal Vdata1 output by the driving circuit in the first stage t1 is set to be equal to the value of the driving hold signal VDD-Vth output in the second stage t2. This ensures that the voltage values ​​supplied to the driving electrode 90 in the first stage t1 and the second stage t2 are consistent. In the second stage t2, the driving signal is well held, which is beneficial for achieving effective and continuous driving of the droplet.

[0127] Figure 18 The image shown is related to Figure 6 Please refer to the timing diagram corresponding to the driving circuit in the diagram. Figure 6 and Figure 18All transistors are P-type transistors. In the first stage t1, a low-level signal is provided to the gate of the first transistor T1, turning it on. Assuming the data signal line Data is a low-level drive signal with a voltage value of Vdata1, this drive signal is output to the drive electrode. In the second stage t2, a high-level signal is provided to the gate of the first transistor T1, turning it off. The signal at the first node P remains low, turning on the third transistor T3. The high-level signal at the second power supply terminal D2 is transmitted to the fifth transistor T5, turning it off and turning on the fourth transistor T4. At this time, the voltage value of the drive hold signal output by the drive circuit is VEE-Vth, where Vth is the threshold voltage of the fourth transistor T4. In this embodiment, the value of the drive signal Vdata1 output by the drive circuit in the first stage t1 is equal to the value of the drive hold signal VED-Vth output in the second stage t2, so that the voltage values ​​provided to the drive electrode 90 in the first stage t1 and the second stage t2 are consistent. In the second stage t2, the drive signal is well maintained, which is also beneficial for achieving effective and continuous driving of the droplet.

[0128] In an optional embodiment of the present invention, in the third stage t3, the first transistor T1 is turned on, and the second signal of the data signal line Data is used as the third signal.

[0129] In the third stage (t3), continue to refer to... Figure 5 and Figure 17 A high-level signal is provided to the first transistor T1, turning it on. At this time, the second signal on the data signal line Data is a low-level signal, which serves as the third signal to drive the driving electrode. In the third stage t3, the droplet is about to leave the driving electrode, so there is no need to provide a signal to the driving electrode to propel it forward; it can be driven by the next driving electrode.

[0130] Figure 19 As shown Figure 8 Please refer to the timing diagram corresponding to the driver circuit. Figure 19 In an optional embodiment of the present invention, in the driving circuit, the data writing module 10 includes a first transistor T1, the first inverter 20 includes a second transistor T2 and a third transistor T3, and the second inverter 30 includes a fourth transistor T4 and a fifth transistor T5; the microfluidic circuit also includes a gating module 80, which includes a sixth transistor T6 and a seventh transistor T7, the first terminal of the sixth transistor T6 is connected to a first level terminal VA, and the second terminal of the seventh transistor T7 is connected to a second level terminal VB;

[0131] In the first stage t1, the first transistor T1 is turned on, the signal of the first node P controls the sixth transistor T6 to be turned on, and the signal of the first level terminal VA is used as the driving signal.

[0132] In the second stage t2, the first transistor T1 is turned off, the signal of the first node P is maintained, the control of the sixth transistor T6 is kept on, and the signal of the first level terminal VA is used as the drive holding signal.

[0133] Specifically, this embodiment illustrates a driving method when the driving circuit includes a gating module 80. This embodiment uses N-type transistors as an example for explanation. In the first stage t1, the first transistor T1 is turned on, and the high-level signal of the data signal line Data is transmitted to the first node P, controlling the sixth transistor T6 to turn on and the seventh transistor T7 to turn off. At this time, the signal at the first level terminal VA serves as the driving signal; optionally, the signal at the first level terminal VA is an AC signal.

[0134] In the second stage t2, the first transistor T1 is turned off, the signal at the first node P remains at a high level, the sixth transistor T6 remains on, and the AC signal at the first level terminal VA still serves as the drive-hold signal. Thus, the drive signal and drive-hold signal output by the drive circuit in both the first stage t1 and the second stage t2 are consistent AC signals, which is beneficial for achieving continuous and stable AC drive of the liquid crystal and reducing the hysteresis effect caused by charge accumulation during the drive process.

[0135] Continue to combine Figure 8 and Figure 19 In an optional embodiment of the present invention, in the third stage t3, the first transistor T1 is turned on, the second signal of the data signal line Data is transmitted to the first node P, the second transistor T2 is turned on, the signal of the first power supply terminal D1 is transmitted to the second node NP, the seventh transistor T7 is turned on, and the signal of the second level terminal VB is used as the third signal.

[0136] Specifically, in the third stage t3, the second signal of the data signal line Data is a low-level signal. When the low-level signal is transmitted to the first node P, the third transistor T3 is turned off and the second transistor T2 is turned on. The high-level signal of the first voltage terminal is transmitted to the second node NP, causing the seventh transistor T7 to turn on. The signal of the second voltage terminal VB serves as the third signal. Optionally, the signal of the second voltage terminal VB is a DC signal, for example, the voltage value is 0. There is no need to provide the driving electrode 90 with a voltage that can drive the droplet forward, which helps to reduce the overall power consumption.

[0137] Based on the same inventive concept, this invention also provides another driving circuit. Figure 20 The diagram shown is a schematic representation of another driving circuit provided in an embodiment of the present invention. Please refer to it. Figure 20 The driving circuit includes a data writing module 10, a first inverter 20, a second inverter 30, and a third inverter 40.

[0138] The first end of the data writing module 10 is connected to the data signal line Data, the second end is connected to the input end of the first inverter 20, and the control end is connected to the control signal line Gate.

[0139] The first terminal of the first inverter 20 is connected to the first power supply terminal D1, the second terminal is connected to the second power supply terminal D2, and the output terminal is connected to the third node P'.

[0140] The first terminal of the second inverter 30 is connected to the first power supply terminal D1, the second terminal is connected to the second power supply terminal D2, the input terminal is connected to the third node P', and the output terminal is connected to the fourth node NP'.

[0141] The input terminal of the third inverter 40 is connected to the fourth node NP', the output terminal is connected to the third node P', the first terminal is connected to the first power supply terminal D1, and the second terminal is connected to the second power supply terminal D2.

[0142] The third node P' serves as the output terminal of the driving circuit and is electrically connected to the driving electrode; alternatively, the third node P' serves as the control terminal, controlling the output signal of the driving circuit.

[0143] Specifically, continue to refer to Figure 20 The driving circuit provided in this embodiment introduces three inverters: a first inverter 20, a second inverter 30, and a third inverter 40. The output of the first inverter 20, the input of the second inverter 30, and the output of the third inverter 40 are all connected to the third node P'. The output of the second inverter 30 and the input of the third inverter 40 are also connected to the third node P'. When the third node P' outputs a low level, the fourth node NP' outputs a high level; when the third node P' outputs a high level, the fourth node NP' outputs a low level. The signals of the third node P' and the fourth node NP' are latched and stored. It should be noted that the data writing module 10, the first inverter 20, the second inverter 30, and the third inverter 40 mentioned in this embodiment do not contain capacitors.

[0144] When the third node P' is used as the output of the driving circuit, after the data writing module 10 is turned on, the signal of the data signal line Data can control the first inverter 20 to transmit the signal of the first power supply terminal D1 to the third node P'. This facilitates the rapid writing of the driving signal, eliminating the need for a storage capacitor and the charging process. After the data writing module 10 is turned off, the signal of the third node P' is fed back to the input of the second inverter 30, achieving signal feedback locking, which helps to maintain the driving signal for a long time. In addition, in this embodiment, the fourth node NP' is not connected to the data signal line Data, so the signal of the fourth node NP' and the signal of the data signal line Data are less likely to interfere with each other, which helps to improve the stability of the signal output by the driving circuit.

[0145] Continue to refer to Figure 20 The data writing module 10 includes a first transistor T1, the first inverter 20 includes a second transistor T2 and a third transistor T3, the second inverter 30 includes a fourth transistor T4 and a fifth transistor T5, and the third inverter 40 includes an eighth transistor T8 and a ninth transistor T9. Two transistors in the first inverter 20 are connected in series between the first power supply terminal D1 and the second power supply terminal D2. Similarly, two transistors in the second inverter 30 and the third inverter 40 are also connected in series between the first power supply terminal D1 and the second power supply terminal D2. The second terminal of the third transistor T3, the gate of the fifth transistor T5, and the second terminal of the ninth transistor T9 are all connected to the third node P'. The second terminal of the fifth transistor T5 and the gate of the ninth transistor T9 are connected to the fourth node NP'. The specific operation of the driving circuit will be described in detail in subsequent driving method embodiments. It should be noted that the first terminal of a transistor mentioned in this invention generally refers to the terminal where the transistor receives signals, and the second terminal of a transistor generally refers to the terminal where the transistor outputs signals.

[0146] Figure 21 The diagram shown is a structural schematic of another driving circuit provided in an embodiment of the present invention, including a gating module 80. In an optional embodiment of the present invention, the driving circuit further includes a gating module 80, which includes a first gating unit 81 and a second gating unit 82. The control terminal of the first gating unit 81 is connected to a third node P', and the control terminal of the second gating unit 82 is connected to a fourth node NP'. The first terminal of the first gating unit 81 is connected to a first level terminal VA, and the second terminal is connected to the output terminal OUT of the driving circuit. The first terminal of the second gating unit 82 is connected to a second level terminal VB, and the second terminal is connected to the output terminal OUT of the driving circuit.

[0147] Specifically, when a gating module 80 is introduced into the driving circuit, the output of the gating module 80 can be controlled by the signals of the third node P' and the fourth node NP'. The signal output by the gating module 80 is then provided as a driving signal to the driving electrode 90. This approach also eliminates the need to introduce a storage capacitor into the driving circuit, which is beneficial for improving the driving efficiency of the driving electrode 90 and for enabling the driving of a large-scale array of driving electrodes 90.

[0148] Optionally, the first gating unit 81 includes a tenth transistor T10, and the second gating unit 82 includes an eleventh transistor T11. The gate of the tenth transistor T10 is connected to the third node P', its first terminal is connected to the first level terminal VA, and its second terminal is connected to the output terminal of the driving circuit. The gate of the eleventh transistor T11 is connected to the fourth node NP', its first terminal is connected to the second power supply terminal D2, and its second terminal is connected to the output terminal of the driving circuit. When the signal from the third node P' controls the tenth transistor T10 to turn on, the signal from the first level terminal VA is transmitted to the output terminal of the driving circuit as the output signal of the driving circuit. When the signal from the fourth node NP' controls the eleventh transistor T11 to turn on, the signal from the second power supply terminal D2 is transmitted to the output terminal of the driving circuit as the output signal of the driving circuit. The specific operating timing of the driving circuit including the gating module 80 will be described in detail in subsequent embodiments.

[0149] In an optional embodiment of the present invention, the data writing module 10, the first inverter 20, the second inverter 30 and the third inverter 40 all include transistors, and each transistor is of the same type. For example, each transistor can be an N-type transistor or a P-type transistor. In this way, the driving circuit provided in the embodiment of the present invention can be formed using transistors of the same structure, without the need to form different transistor structures. This helps to reduce the process complexity of manufacturing the driving circuit and improve production efficiency.

[0150] It should be noted that, Figure 20 and Figure 21 In the illustrated embodiment, the driving transistor in the driving circuit is only an example of an N-type transistor. In some other embodiments of the present invention, the driving transistor may also be uniformly represented as a P-type transistor, and the present invention does not limit this.

[0151] Based on the same inventive concept, this invention also provides another microfluidic actuation device, the structural diagram of which can be referred to. Figure 10 It includes a substrate 00, a driving layer 01 and a microfluidic structure layer 02, with the driving layer 01 located between the substrate 00 and the microfluidic structure layer 02;

[0152] The driving layer 01 includes a driving circuit, multiple driving electrodes 90, and a common electrode 011 disposed opposite to the driving electrodes 90. The output terminal of the driving circuit is electrically connected to the driving electrodes 90. The microfluidic structure layer includes at least one first channel 021, which corresponds to the multiple driving electrodes 90. The driving circuit is... Figures 20 to 21 The microfluidic drive circuit of the embodiment shown.

[0153] When the driving circuit mentioned in the above embodiments of the present invention provides a driving signal to the driving electrode 90 in the microfluidic driving device, since no storage capacitor is required in the driving circuit, and no charging process for the storage capacitor is required, the driving signal can be quickly written to the driving electrode 90, improving the driving efficiency of the droplets. Furthermore, the latching circuit composed of the first inverter 20, the second inverter 30, and the third inverter 40 can also maintain the driving signal for a long time, which is beneficial to further improve the driving efficiency of the droplets and meet the driving requirements of large-scale arrays of driving electrodes 90 in the microfluidic driving device. Moreover, in this embodiment, the fourth node NP' is not connected to the data signal line Data, so the signal of the fourth node NP' and the signal of the data signal line Data are less likely to interfere with each other, which is beneficial to improving the stability of the signal output by the driving circuit.

[0154] Based on the same inventive concept, the present invention also provides a driving method for a microfluidic driving device. Figure 22 The diagram shown is another flowchart of the driving method for the microfluidic driving device provided in an embodiment of the present invention. Figure 23 As shown Figure 20 A timing diagram corresponding to the driving circuit in the microfluidic driving device is provided. This diagram shows a driving circuit with three inverters, where the output of the third inverter serves as the output of the driving circuit. This driving method is used to drive the microfluidic driving device shown in the diagram. The driving method includes:

[0155] S11, introduce droplets into the first channel 021;

[0156] S12. In the first stage t1, a first control signal is provided to the microfluidic driving circuit connected to the driving electrode 90 at the location of the droplet, and the control data writing module 10 is turned on. The first signal of the data signal line Data is used as the driving signal and transmitted to the driving electrode 90. The voltage value of the driving signal is Vdata1.

[0157] S13. In the second stage t2, a second control signal is provided to the microfluidic drive circuit, the control data writing module 10 is turned off, and the signal output by the third node P' is a drive-hold signal provided by the third inverter 40 to the drive electrode 90. The voltage value of the drive-hold signal is VDD-Vth, where Vdata1 = VDD-Vth, VDD is the voltage value of the first power supply terminal D1, and Vth is the threshold voltage of the transistor in the third inverter 40; or, the voltage value of the drive-hold signal is VEE-Vth, where Vdata1 = VEE-Vth, VEE is the voltage value of the first power supply terminal D1, and Vth is the threshold voltage of the transistor in the third inverter 40.

[0158] Please refer to Figure 10 , Figure 20 and Figure 23 This embodiment uses N-type transistors as an example. The output of the third inverter 40, i.e., the third node P', serves as the output of the driving circuit. In the first stage t1, the data writing module 10 is turned on, and the first signal of the data signal line Data is transmitted to the third node P' as the driving signal, which is then provided to the driving electrode 90. No storage capacitor is needed, achieving fast writing of the driving signal. The voltage value of the driving signal is Vdata1. In the second stage t2, the data writing module 10 is turned off. Due to the latching effect of the three inverters, the high-level signal of the third node P' is fed back to the gate of the fifth transistor T5 in the second inverter 30, turning on the fifth transistor T5. The low-level signal of the second power supply terminal D2 is transmitted to the fourth node NP', the seventh transistor T7 is turned off, and the sixth transistor T6 is turned on. The signal of the first power supply terminal D1 is transmitted to the third node P' through the sixth transistor T6 in the third inverter 40. At this time, the signal value transmitted to the third node P' is VDD-Vth. In this embodiment, VDD-Vth = Vdata1 is defined so that the signals provided to the driving electrode 90 in the first stage t1 and the second stage t2 are consistent, and the driving electrode 90 can continuously and effectively drive the droplet, thus achieving effective maintenance of the driving signal.

[0159] when Figure 20 When the transistor in the circuit is a P-type transistor, the voltage value of the drive-hold signal can be controlled to be VEE-Vth, where Vdata1 = VEE-Vth, VEE is the voltage value of the first power supply terminal D1, and Vth is the threshold voltage of the transistor in the third inverter 40. This also helps to ensure the consistency of the signals provided to the drive electrode in the first stage t1 and the second stage t2, which is beneficial for achieving continuous and effective drive of the droplet.

[0160] Based on the same inventive concept, this invention also provides another driving method for a microfluidic driving device. Figure 24The diagram shown is a flowchart of another driving method for the microfluidic driving device provided in an embodiment of the present invention, used to drive such... Figure 21 The microfluidic drive device shown is described in conjunction with... Figure 21 The microfluidic driving circuit in the microfluidic driving device also includes a gating module 80, which includes a first gating unit 81 and a second gating unit 82. The control terminal of the first gating unit 81 is connected to the third node P', and the control terminal of the second gating unit 82 is connected to the fourth node NP'. The first terminal of the first gating unit 81 is connected to the first level terminal VA, and the second terminal is connected to the output terminal of the driving circuit. The first terminal of the second gating unit 82 is connected to the second level terminal VB, and the second terminal is connected to the output terminal of the driving circuit. Figure 25 As shown Figure 24 A timing diagram of a driving circuit.

[0161] Please combine Figure 21 , Figure 24 and Figure 25 The driving methods include:

[0162] S21, introduce droplets into the first channel 021;

[0163] S22. In the first stage t1, a first control signal is provided to the microfluidic driving circuit connected to the driving electrode 90 at the location of the droplet, and the control data writing module 10 is turned on; the signal of the third node P' controls the first gating unit 81 to be turned on and the second gating unit 82 to be turned off, and the signal of the first level terminal VA is used as the driving signal and transmitted to the driving electrode 90.

[0164] S23. In the second stage t2, the data writing module 10 is cut off, the signal of the third node P' is maintained, the first gating unit 81 is turned on, the second gating unit 82 is turned off, and the signal of the first level terminal VA is used as the drive holding signal and transmitted to the drive electrode 90.

[0165] The driving method provided in this embodiment corresponds to Figure 21 The driving circuit shown includes three inverters and a gating module 80. The first gating unit 81 and the second gating unit 82 in the gating module 80 are controlled by signals from the third node P' and the fourth node NP', respectively. In the first stage t1, when the data writing module 10 is turned on, the data signal line Data is transmitted to the third node P', controlling the first gating unit 81 to turn on. The signal at the first level terminal VA is transmitted to the output of the driving circuit through the first gating unit 81. This eliminates the need for a storage capacitor, enabling rapid writing of the driving signal.

[0166] In the second stage t2, the data writing module 10 is cut off, the signal of the third node P' is maintained, the first gating unit 81 continues to be turned on, and the signal of the first level terminal VA serves as the drive holding signal. Thus, in both the first stage t1 and the second stage t2, the signal output from the first level terminal VA serves as the signal provided to the drive electrode 90, which is beneficial for achieving continuous and effective driving of the droplet. Optionally, the signal of the first level terminal VA can be an AC signal, which can realize AC driving of the droplet and reduce the hysteresis effect caused by charge accumulation during the driving process.

[0167] Optionally, in the third stage t3, the data writing module 10 is turned on, the high-level signal of the data signal line Data controls the third transistor T3 to turn on, the low-level signal of the second power supply terminal D2 is transmitted to the third node P', the fifth transistor T5 is turned off, the fourth transistor T4 is turned on, the high-level signal of the first power supply terminal is transmitted to the fourth node NP', the ninth transistor T9 is turned on, the low-level signal of the second power supply terminal D2 is transmitted to the third node P', the tenth transistor T10 is turned off, the eleventh transistor T11 is turned on, and the DC signal of the second level terminal VB is transmitted to the output terminal OUT of the drive circuit. This achieves AC drive of the droplet.

[0168] As can be seen from the above embodiments, the driving circuit, microfluidic driving device, and driving method provided by the present invention achieve at least the following beneficial effects:

[0169] The driving circuit provided in this embodiment of the invention incorporates a data writing module and two inverters. The two inverters form a latching circuit. When the data writing module is on, it writes data to the output of the second inverter. The output of the second inverter serves as the output of the driving circuit, and the signal can be directly provided to the driving electrode to be driven through the output of the second inverter. This eliminates the need for a storage capacitor and the charging process, enabling rapid signal writing. When the data writing module is off, the signal from the output of the second inverter is fed back to the input of the first inverter, achieving signal feedback locking and facilitating long-term signal retention. Therefore, the driving circuit provided in this embodiment of the invention achieves both rapid signal writing and long-term signal retention, which is beneficial for driving large-scale driving electrode arrays. When this driving circuit is applied to a microfluidic driving device, it helps improve the driving efficiency of droplets.

[0170] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A drive circuit characterized by comprising: Includes a data writing module, a first inverter, and a second inverter; The output of the data writing module is connected to the first node; The first terminal of the first inverter is connected to the first power supply terminal, the second terminal is connected to the second power supply terminal, the input terminal is connected to the first node, and the output terminal is connected to the second node. The first terminal of the second inverter is connected to the first power supply terminal, the second terminal is connected to the second power supply terminal, the input terminal is connected to the second node, and the output terminal is connected to the input terminal of the first inverter. The data writing module, the first inverter, and the second inverter all include transistors, and all the transistors are of the same type. It also includes a gating module, which includes a first gating unit and a second gating unit. The control terminal of the first gating unit is connected to the first node, and the control terminal of the second gating unit is connected to the second node. The first terminal of the first gating unit is connected to a first level terminal, and the second terminal is connected to the output terminal of the driving circuit. The first terminal of the second gating unit is connected to a second level terminal, and the second terminal is connected to the output terminal of the driving circuit. Of the first power supply terminal and the second power supply terminal, one transmits an AC signal and the other transmits a DC signal; the voltage value corresponding to the AC signal is between the voltage values ​​of the first power supply terminal and the second power supply terminal. The driving circuit is used to provide a driving signal to the driving electrode in the microfluidic driving device, including: in a first stage, the driving circuit transmits a driving signal to the driving electrode in the microfluidic driving device; in a second stage, the driving circuit transmits a driving hold signal to the driving electrode in the microfluidic driving device; the driving signal is equal to the driving hold signal; in a third stage, the driving circuit transmits a third signal to the driving electrode in the microfluidic driving device, the voltage value corresponding to the third signal being less than the driving signal.

2. The drive circuit according to claim 1, characterized in that, The output terminal of the second inverter serves as the output terminal of the driving circuit and is electrically connected to the driving electrode; alternatively, the signals of the first node and the second node serve as control signals to control the output of the signal at the output terminal of the driving circuit.

3. The driving circuit according to claim 1, characterized in that, The data writing module includes a first transistor, the gate of which is connected to a control signal line, the first electrode of which is connected to a data signal line, and the second electrode of which is connected to the first node.

4. The driving circuit according to claim 1, characterized in that, The first inverter includes a second transistor and a third transistor. The gate and first terminal of the second transistor are both connected to the first power supply terminal, and the second terminal is connected to the second node. The gate of the third transistor is connected to the first node, the first terminal is connected to the second power supply terminal, and the second terminal is connected to the second node.

5. The driving circuit according to claim 4, characterized in that, The aspect ratio of the second transistor is A2, and the aspect ratio of the third transistor is A3, wherein, , where k1≥10.

6. The driving circuit according to claim 1, characterized in that, The second inverter includes a fourth transistor and a fifth transistor. The gate and first terminal of the fourth transistor are both connected to the first power supply terminal, and the second terminal is connected to the first node. The gate of the fifth transistor is connected to the second node, the first terminal is connected to the second power supply terminal, and the second terminal is connected to the first node.

7. The driving circuit according to claim 6, characterized in that, The aspect ratio of the fourth transistor is A4, and the aspect ratio of the fifth transistor is A5, wherein... , where k3≥10.

8. The driving circuit according to claim 1, characterized in that, All transistors are N-type transistors, with the first power supply terminal being a positive power supply terminal and the second power supply terminal being a negative power supply terminal.

9. The driving circuit according to claim 1, characterized in that, All transistors are P-type transistors, with the first power supply terminal being the negative power supply terminal and the second power supply terminal being the positive power supply terminal.

10. The driving circuit according to claim 1, characterized in that, The first gating unit includes a sixth transistor, and the second gating unit includes a seventh transistor. The transistors contained in the first gating unit, the second gating unit, the data writing module, the first inverter, and the second inverter are of the same type.

11. A microfluidic drive device, characterized in that, It includes a substrate, a driving layer, and a microfluidic structure layer, wherein the driving layer is located between the substrate and the microfluidic structure layer; The driving layer includes a driving circuit, a plurality of driving electrodes, and a common electrode disposed opposite to the driving electrodes, wherein the output terminal of the driving circuit is electrically connected to the driving electrodes; the microfluidic structure layer includes at least one first channel, the first channel corresponding to the plurality of driving electrodes; wherein the driving circuit is the driving circuit according to any one of claims 1 to 10.

12. The microfluidic drive device according to claim 11, characterized in that, The driving layer includes a first metal layer, an active layer, and a second metal layer M2 disposed on one side of the substrate. The first metal layer and the active layer are isolated by an insulating layer. The first metal layer is located between the active layer and the substrate. The second metal layer M2 is located on the side of the active layer away from the substrate. The gate of the transistor is located in the first metal layer, and the first electrode and the second electrode are located in the second metal layer M2; the active layer includes an oxide layer or an amorphous silicon layer.

13. A driving method for a microfluidic driving device, characterized in that, The driving method for driving the microfluidic driving device according to claim 11 or 12 includes: A droplet is introduced into the first channel; In the first stage, a first control signal is provided to the driving circuit connected to the driving electrode at the location of the droplet to control the data writing module to turn on, the data signal line inputs the first signal, and the microfluidic circuit is controlled to transmit the driving signal to the driving electrode; In the second stage, a second control signal is provided to the driving circuit to control the data writing module to turn off. The first inverter and the second inverter control the driving circuit to transmit the drive holding signal to the driving electrode by controlling the signals of the first node and the second node.

14. The driving method according to claim 13, characterized in that, The driving method further includes: In the third stage, a first control signal is provided to the driving circuit to control the data writing module to turn on, and a second signal is input to the data signal line to control the driving circuit to transmit the third signal to the driving electrode.

15. The driving method according to claim 14, characterized in that, In the driving circuit, the data writing module includes a first transistor, the first inverter includes a second transistor and a third transistor, and the second inverter includes a fourth transistor and a fifth transistor. In the first stage, the first transistor is turned on, and the voltage value of the drive signal is Vdata1; In the second stage, the first transistor is turned off, and the signal output by the first node is the drive-hold signal; the fourth transistor is turned on, and the voltage value of the drive-hold signal is VDD-Vth, where Vdata1=VDD-Vth, VDD is the voltage value of the first power supply terminal, and Vth is the threshold voltage of the fourth transistor; or, the fourth transistor is turned on, and the voltage value of the drive-hold signal is VEE-Vth, where Vdata1=VEE-Vth, VEE is the voltage value of the first power supply terminal, and Vth is the threshold voltage of the fourth transistor.

16. The driving method according to claim 15, characterized in that, In the third stage, the first transistor is turned on, and the second signal of the data signal line serves as the third signal.

17. The driving method according to claim 14, characterized in that, In the microfluidic driving circuit, the data writing module includes a first transistor, the first inverter includes a second transistor and a third transistor, and the second inverter includes a fourth transistor and a fifth transistor; the microfluidic circuit also includes a gating module, which includes a sixth transistor and a seventh transistor, the first terminal of the sixth transistor is connected to a first level terminal, and the first terminal of the seventh transistor is connected to a second level terminal; In the first stage, the first transistor is turned on, the signal of the first node controls the sixth transistor to be turned on, and the signal at the first level terminal serves as the driving signal. In the second stage, the first transistor is turned off, the signal of the first node is maintained, the sixth transistor is kept on, and the signal at the first level terminal serves as the drive hold signal.

18. The driving method according to claim 17, characterized in that, In the third stage, the first transistor is turned on, the second signal of the data signal line is transmitted to the first node, the second transistor is turned on, the signal of the first power supply terminal is transmitted to the second node, controlling the seventh transistor to be turned on, and the signal of the second level terminal serves as the third signal.

19. A driving circuit, characterized in that, It includes a data writing module, a first inverter, a second inverter, and a third inverter; The first end of the data writing module is connected to the data signal line, the second end is connected to the input end of the first inverter, and the control end is connected to the control signal line. The first terminal of the first inverter is connected to the first power supply terminal, the second terminal is connected to the second power supply terminal, and the output terminal is connected to the third node. The first end of the second inverter is connected to the first power supply terminal, the second end is connected to the second power supply terminal, the input terminal is connected to the third node, and the output terminal is connected to the fourth node. The input terminal of the third inverter is connected to the fourth node, the output terminal is connected to the third node, the first terminal is connected to the first power supply terminal, and the second terminal is connected to the second power supply terminal. The third node serves as the output terminal of the driving circuit and is electrically connected to the driving electrode; or, the third node serves as a control terminal to control the output signal of the driving circuit. The data writing module, the first inverter, the second inverter, and the third inverter all include transistors, and all the transistors are of the same type. It also includes a gating module, which includes a first gating unit and a second gating unit. The control terminal of the first gating unit is connected to the third node, and the control terminal of the second gating unit is connected to the fourth node. The first terminal of the first gating unit is connected to a first level terminal, and the second terminal is connected to the output terminal of the driving circuit. The first terminal of the second gating unit is connected to a second level terminal, and the second terminal is connected to the output terminal of the driving circuit. Of the first power supply terminal and the second power supply terminal, one transmits an AC signal and the other transmits a DC signal; the voltage value corresponding to the AC signal is between the voltage values ​​of the first power supply terminal and the second power supply terminal. The driving circuit is used to provide a driving signal to the driving electrode in the microfluidic driving device, including: in a first stage, the driving circuit transmits a driving signal to the driving electrode in the microfluidic driving device; in a second stage, the driving circuit transmits a driving hold signal to the driving electrode in the microfluidic driving device; the driving signal is equal to the driving hold signal; in a third stage, the driving circuit transmits a third signal to the driving electrode in the microfluidic driving device, the voltage value corresponding to the third signal being less than the driving signal.

20. A microfluidic drive device, characterized in that, It includes a substrate, a driving layer, and a microfluidic structure layer, wherein the driving layer is located between the substrate and the microfluidic structure layer; The driving layer includes a driving circuit, a plurality of driving electrodes, and a common electrode disposed opposite to the driving electrodes, wherein the output terminal of the driving circuit is electrically connected to the driving electrodes; the microfluidic structure layer includes at least one first channel, the first channel corresponding to the plurality of driving electrodes; wherein the driving circuit is the microfluidic driving circuit as described in claim 19.

21. A driving method for a microfluidic driving device, characterized in that, The driving method for driving the microfluidic driving device of claim 20 includes: A droplet is introduced into the first channel; In the first stage, a first control signal is provided to the microfluidic driving circuit connected to the driving electrode at the location of the droplet to control the data writing module to be turned on. The first signal of the data signal line is used as the driving signal and transmitted to the driving electrode. The voltage value of the driving signal is Vdata1. In the second stage, a second control signal is provided to the microfluidic driving circuit to control the data writing module to turn off. The signal output by the third node is the drive hold signal provided by the third inverter to the driving electrode. The voltage value of the drive hold signal is VDD-Vth, where Vdata1=VDD-Vth, VDD is the voltage value of the first power supply terminal, and Vth is the threshold voltage of the transistor in the third inverter; or, the voltage value of the drive hold signal is VEE-Vth, where Vdata1=VEE-Vth, VEE is the voltage value of the first power supply terminal, and Vth is the threshold voltage of the transistor in the third inverter.

22. A driving method for a microfluidic driving device, characterized in that, For driving the microfluidic driving device of claim 20, the microfluidic driving circuit in the microfluidic driving device further includes a gating module, the gating module includes a first gating unit and a second gating unit, the control terminal of the first gating unit is connected to the third node, the control terminal of the second gating unit is connected to the fourth node, the first terminal of the first gating unit is connected to a first level terminal, and the second terminal is connected to the output terminal of the driving circuit. The first end of the second gating unit is connected to the second level terminal, and the second end is connected to the output terminal of the driving circuit; The driving method includes: A droplet is introduced into the first channel; In the first stage, a first control signal is provided to the microfluidic driving circuit connected to the driving electrode at the location of the droplet to control the data writing module to turn on; the signal of the third node controls the first gating unit to turn on and the second gating unit to turn off, and the signal at the first level terminal is used as the driving signal and transmitted to the driving electrode; In the second stage, the data writing module is turned off, the signal of the third node is held, the first gating unit is turned on, the second gating unit is turned off, and the signal at the first level terminal is transmitted to the driving electrode as the driving hold signal.

Images