A queue-based control word output feedback control method

Abstract

The application discloses a queue-based control word output feedback control method, relates to the technical field of multi-core processor task output management, and comprises the following steps: firstly, sequentially writing ordered control words output by a task scheduling unit into an Exit queue, determining the number of in-queue control words, secondly, sequentially outputting the control words in the Exit queue, recording the number of out-of-queue control words, recording and writing the control words into an auxiliary queue if the output fails, when the number of in-queue control words in the Exit queue is equal to the number of out-of-queue control words, performing the next step, sequentially outputting control words in a Subexit queue and a Waitexit queue, marking the loop output control words, writing the control words into an Interrupt queue if the number of marks reaches a set threshold, otherwise, continuously outputting the control words, finally, performing data protection, task revocation or remapping operation according to error feedback types, and completing the control word output work; the method makes the task output more orderly, controllable and efficient through a specific control word output mechanism, and further improves the system working efficiency.

Description

Technical Field

[0001] This invention relates to the technical field of multi-core processor task output management, and specifically to a queue-based control word output feedback control method. Background Technology

[0002] With the development of integrated circuit technology, multi-core parallel processing has become increasingly widespread. Heterogeneous multi-core processors integrate multiple cores with different architectures on a single chip, allowing them to allocate tasks to suitable cores based on task characteristics. For a multi-core system serving multiple external devices, a key issue is how to fully utilize processor resources with varying performance to achieve automatic resource adjustment and load balancing when faced with multiple device transmission requests. In multi-core systems, employing a reasonable scheduling algorithm to output ordered operation control words, mobilizing multiple data transmission control units to work in parallel, and ensuring efficient control word output and a robust error feedback mechanism are crucial. Current technologies typically output the results from the task scheduling unit directly to the destination unit, with the interrupt unit handling errors. However, the time required from interrupt generation to interrupt handling is significant, and sequential control word output requires a protection mechanism to prevent deadlock. Therefore, in multi-core systems, a control word output unit with an error feedback mechanism is of paramount importance. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art, adopt a reasonable scheduling algorithm to output ordered operation control words, mobilize multiple data transmission control units to work in parallel, improve the output efficiency of data transmission control words, improve the error response mechanism of data transmission tasks, and improve the overall performance of multi-core processor systems.

[0004] The technical solution of this invention is: to utilize a queue-based approach to control a set of ordered control words output by the task scheduling unit, and to possess a complete error feedback mechanism to ensure efficient and orderly output of control words, thereby improving overall system performance. The queue-based control word output feedback control method includes:

[0005] S1: The output control unit receives ordered control words, writes the control words to be transmitted into the Exit queue, and determines the number of words to be enqueued.

[0006] S2: The output control unit outputs control words sequentially according to the Exit queue order. If the output fails, it is recorded and the control word is written to the auxiliary queue.

[0007] S3: Auxiliary queue outputs control word. If the output fails, a count is written to the end of the queue. When the number of failed outputs of the control word reaches a preset value, it is written to the Interrupt queue.

[0008] S4: The error feedback unit includes S2M feedback processing mechanism, M2S feedback processing mechanism and M2M feedback processing mechanism, and performs error feedback processing according to the error type of the interrupt queue data transmission task.

[0009] Furthermore, in S1, when the control word output unit is idle, a control word acquisition request is sent to the task scheduling unit.

[0010] Furthermore, in S2, when the number of items dequeued from the Exit queue equals the number of items enqueued, S3 is executed.

[0011] Furthermore, the auxiliary queues in S2 include the Subexit queue and the Waitexit queue;

[0012] The output control unit outputs to the designated data transmission control unit according to the ID information carried by the control word, following the Exit queue order. A Success signal indicates successful transmission, while a Busy signal extends the counter flag of the control word and writes it to the Subexit queue. An Error signal indicates a storage problem with the control word, so it is written to the Wait queue. An Error signal indicates a DMA transfer error with the control word, so it is directly written to the Interrupt queue.

[0013] Furthermore, when the Subexit queue is not empty, the Exit queue and the Subexit queue alternately output control words. If the control word output by the Exit queue is busy, it continues to be written to the tail of the Subexit queue.

[0014] Furthermore, the output of the Subexit queue is executed first, followed by the output of the Waitexit queue. The specific steps are as follows:

[0015] S3.1: The Subexit queue outputs the control word in a loop. If the output fails, it is counted and written to the end of the queue. A preset loop threshold is set. When the number of failed outputs of the control word reaches the preset threshold, it is written to the Interrupt queue.

[0016] S3.2: The WaitTick queue outputs the control word in a loop. If the output fails, it is counted and written to the end of the queue. A preset loop threshold is set. When the number of failed outputs of the control word reaches the preset threshold, it is written to the Interrupt queue.

[0017] Furthermore, in S4, data transmission tasks are divided into three types based on direction: tasks S2M from external devices to on-chip cores, tasks M2S from on-chip cores to external devices, and tasks M2M between on-chip cores. For tasks from external devices to on-chip cores, the external device sends a continuous data stream to the designated on-chip storage space. For tasks from on-chip cores to external devices, the storage descriptor is used for sliced ​​transmission. For tasks between on-chip cores, both the source and terminal storage are represented in descriptor form. In the error feedback unit, the feedback processing mechanism handles data transmission tasks matching their direction and processes them according to the control word transmission error type. The processing method is as follows:

[0018] S2M feedback handling mechanism: Handles data transfer tasks (S2M) sent from external devices to on-chip cores, determines the error feedback type of task transfer failure when writing to the Interrupt queue, and if the error feedback is caused by Busy, it adopts a remapping mechanism to match other idle processing cores, changes the destination ID parameter in the storage descriptor, and executes the data transfer task. If the error feedback is caused by Error, it increases the original priority and re-adds the task to the task scheduling unit to wait for subsequent transmission. Among them, if the error feedback is caused by DMA transfer error, the data is lost, the data transfer task is canceled, the acquired destination storage descriptor is released, and the data is recorded and reported to the system.

[0019] M2S Feedback Processing Mechanism: Processes data transmission tasks (M2S) sent from the on-chip core to external devices, determines the type of error feedback when writing to the Interrupt queue. If the error feedback is caused by Busy, the execution priority of the control word is increased and it is re-added to the task scheduling unit. If the error feedback is caused by Error, the storage descriptor is not reclaimed, and the remaining source data to be transmitted is re-initiated by the data transmission control unit to complete the slice transmission.

[0020] M2M feedback handling mechanism: Handles data transfer tasks (M2M) between on-chip cores, determines the error feedback type when writing to the Interrupt queue, if the error feedback is caused by Busy, adopts the remapping mechanism to select other idle cores for processing, if there is no suitable core, increases the original priority and re-adds it to the task scheduling unit to wait for subsequent transmission, if the error feedback is caused by Error, releases the prefetched destination memory descriptor and re-initiates the transmission transaction.

[0021] Furthermore, after processing the control words in this group in S4, S1 is executed.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] (1) The orderly control word is output based on the queue. The Exit queue, the auxiliary queue and the Interrupt queue are used to process the control word and complete the transmission task. Multiple data transmission control units are mobilized to work in parallel, so that all tasks are output in a more orderly, controllable and efficient manner, which improves the system efficiency.

[0024] (2) When the Subexit queue in the auxiliary queue is not empty, the Exit queue and the Subexit queue output control words in an interleaved manner. The interleaved output method ensures that the control words with higher priority are output in advance, while the control words newly written to the Subexit queue are placed at the end of the queue, making the execution more orderly.

[0025] (3) When the auxiliary queue is working, the Subexit queue output work is executed first, and the Waitet queue output work is executed later. The waiting time is relatively long to ensure that enough space is released, thereby increasing the probability of successful control word output.

[0026] (4) Optimize the error feedback handling mechanism, classify and process different error feedback types, shorten data processing time, and improve the overall performance of multi-core processor systems;

[0027] (5) The on-chip storage space is subdivided using storage descriptors to better understand the usage of on-chip storage, which has the effect of data protection, efficient management of on-chip storage space, and works in conjunction with the control word output unit to improve data transmission efficiency. Attached Figure Description

[0028] Figure 1 This is a schematic flowchart of the queue-based control word output feedback control method according to an embodiment of the present invention;

[0029] Figure 2 This is a control word output control structure diagram according to an embodiment of the present invention;

[0030] Figure 3 This is a diagram showing the operational changes of the queue control word according to an embodiment of the present invention;

[0031] Figure 4 This is a flowchart of the control word output unit according to an embodiment of the present invention. Detailed Implementation

[0032] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0033] In the following description, many specific details are set forth in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0034] This embodiment provides a queue-based control word output feedback control method, the steps of which are as follows: Figure 1 As shown, the control word output control structure is as follows: Figure 2 As shown, the method includes:

[0035] S1: When the control word output unit is idle, it initiates a control word acquisition request to the task scheduling unit, receives the ordered control word sequence output by the task scheduling unit, writes the control words to be transmitted into the Exit queue, and determines the number of control words to be enqueued in this group.

[0036] S2: The output control unit outputs sequentially according to the Exit queue order, and outputs to the designated data transmission control unit according to the ID information carried in the control word. The output controller receives feedback signals. A Success signal indicates successful control word output. If a Busy signal is received, the counter flag of the control word is extended, and then it is written to the Subexit queue. If an Error signal is received, the control word output fails due to a storage problem and is written to the Wait queue; if it is due to a DMA transfer error, it is directly written to the Interrupt queue. When the Subexit queue is not empty, the Exit queue and the Subexit queue interleave the output of control words. During interleaving, the control word with the higher priority is output first. If a control word output from the Exit queue is busy, it continues to be written to the end of the Subexit queue. When the number of dequeues from the Exit queue equals the number of enqueues, S3 is executed.

[0037] S3: First, output the Subexit queue, then execute the Waitexit queue output. Specifically:

[0038] S3.1: The Subexit queue operates by first executing the control word output in the Subexit queue, cyclically outputting the control word. If the output fails, a count is written to the end of the queue. A preset loop threshold is set; when the number of failed control word outputs reaches the threshold, the value is written to the Interrupt queue. After the Subexit queue is processed, step S3.2 is executed.

[0039] S3.2: WaitTick queue operation, executing WaitTick queue control word output, cyclically outputting the control word. A preset loop threshold is set; when the number of failed WaitTick queue control word outputs reaches the preset threshold, the word is written to the Interrupt queue.

[0040] S4: In the error feedback unit, the feedback processing mechanism handles the data transmission task that matches its direction and processes different error feedback types of control words in the Interrupt queue. After completing the processing of this group of control words, S1 is executed. The specific processing method is as follows:

[0041] The S2M feedback processing mechanism determines the type of error feedback when writing to the Interrupt queue. If the error feedback is caused by Busy, a remapping mechanism is used to match other idle processing cores, change the destination ID parameter in the storage descriptor, and execute the data transfer task. If the error feedback is caused by Error, the original priority is increased and the task is re-added to the task scheduling unit to wait for subsequent transmission. In cases where the error feedback is caused by DMA transmission error and data is lost, the data transfer task is canceled, the acquired destination storage descriptor is released, and the error is recorded and reported to the system.

[0042] The M2S feedback processing mechanism determines the type of error feedback when writing to the Interrupt queue. If the error feedback is caused by Busy, the execution priority of the control word is increased and it is re-added to the task scheduling unit. If the error feedback is caused by Error, the storage descriptor is not reclaimed, and the remaining source data to be transmitted is re-initiated by the data transmission control unit to complete the slice transmission.

[0043] The M2M feedback handling mechanism determines the type of error feedback when writing to the Interrupt queue. If the error feedback is caused by Busy, a remapping mechanism is used to select another idle core for processing. If there is no suitable core, the original priority is increased and the core is re-added to the task scheduling unit to wait for subsequent transmission. If the error feedback is caused by Error, the pre-fetched destination storage descriptor is released and the transmission transaction is re-initiated.

[0044] Example:

[0045] In a system environment with eight DSP processor cores and four peripherals, each of the four peripherals has an independent data transmission control unit, with destination execution terminals EDTC0, EDTC1, EDTC2, and EDTC3 respectively. The eight cores share an internal data transmission control unit, with destination execution terminal IDTC0. The system receives eight data transmission task control words output by the task scheduling unit and executes data exchange tasks according to these control words. The workflow of the control word output unit is as follows: Figure 4 As shown, the specific steps are as follows:

[0046] S1: The control word output unit receives a set of ordered control word sequences from the task scheduling unit, writes the control words to be transmitted into the Exit queue, and determines that the number of control words to be enqueued in this group is 8.

[0047] S2: The eight control words to be transmitted in the Exit queue are output sequentially. Control word Task0 outputs normally, and the EDTC0 data transmission control unit is active. Therefore, control word Task1 fails to output, the control word counter is expanded, and it is marked and written to the Subexit queue. Task2 continues to be output; due to insufficient destination storage, an Error is reported, and it is marked and written to the Wait queue. Task3 continues to be output; since EDTC2 is in data transmission mode, a Busy error is reported, and the control word counter is expanded and written to the Subexit queue. Tasks 4, 5, 6, and 7 continue to be output, and are written to the designated transmit queues according to the error feedback signals. The number of dequeues from the Exit queue equals the number of enqueues, i.e., S3 is executed. It should be noted that the control words in the queue are collectively referred to as transmit control words. The changes in the queue control words during processing are as follows... Figure 3 As shown.

[0048] S3: Following S2, the Subexit queue currently stores the control words for Task1, Task3, and Task7; the Waitet queue stores the control words for Task2, Task4, Task5, and Task6. The auxiliary queues operate by first executing the output from the Subexit queue, then the output from the Waitet queue. Specifically:

[0049] S3.1: The Subexit queue operates by first executing the control word output in the Subexit queue, looping through the output. If an output fails, a count is written to the end of the queue. A preset loop threshold M is set; when the number of failed outputs of the control word reaches the threshold M, it is written to the Interrupt queue. If Task1 successfully outputs after N loops, and Task3 and Task7 fail to output after M loops, they are written to the Interrupt queue. After the Subexit queue is processed, S3.2 is executed.

[0050] S3.2: Waitexit queue operation, executing Waitexit queue control word output. The loop threshold is set to 3 times, and the control words for Task2, Task4, Task5, and Task6 are output sequentially in a loop. If the output of the control word Task2 is successful during the loop, but a DMA error occurs during data transmission in Task4, Task5, and Task6, feedback is written to the Interrupt queue. Once the Waitexit queue is idle, S4 is executed.

[0051] S4: In the error feedback unit, the feedback handling mechanism matches different handling responses based on the control word error type in the Interrupt queue. The Interrupt queue includes Task 3, Task 4, Task 5, Task 6, and Task 7. To demonstrate the completeness of the error feedback handling mechanism, these five tasks are handled differently, specifically:

[0052] Task 3 uses S2M for data transfer, meaning the external device writes data to on-chip memory as a data stream. The feedback is due to output failure caused by the target processing core's Busy behavior, and multiple attempts to output were ineffective. Therefore, a suitable processing core is selected to replace the computation and complete the remapping process. The selected target core meets the following conditions:

[0053] 1. The processing cores have the same computational functions;

[0054] 2. The core is currently idle; there are no queued tasks at the moment.

[0055] 3. The target core has sufficient cache space, and cores with larger cache spaces are selected first to ensure load balancing.

[0056] If no suitable target core is available to complete the task, the task's original priority is increased, and it is re-added to the task scheduling unit.

[0057] Task 4 uses S2M for data transfer, meaning the external device writes data to on-chip memory as a data stream. The error is due to data loss caused by an internal DMA transfer error. Because the external device inputs data as a stream without data protection mechanisms, errors during transmission result in irrecoverable data loss. Therefore, this type of error will be undone, reported to the system, and handled by the system interrupt routine.

[0058] Task 5 uses M2S for data transfer, meaning data is transferred from on-chip storage to an external device. The error in this task was caused by an error during DMA data transfer, leading to a transfer interruption. Because of the presence of a descriptor control module, on-chip data is managed in the form of storage descriptors; that is, the original data space is not released until the data transfer is complete, thus providing a data protection mechanism. Therefore, Task 5 will have the data transfer control unit re-establish the connection with the peripheral device to complete the slice transfer.

[0059] Task 6 uses an M2M data transfer type, meaning that on-chip cores complete the mutual mapping of memory regions. The error type for this task is an error occurring during DMA data transfer. Because inter-core communication supports link transfers, the link relationship changes as the task executes. Therefore, the transfer transaction needs to be re-initiated, releasing the allocated memory descriptors, reacquiring memory space, and then executing the transfer.

[0060] Task 7 uses M2M for data transfer. The error type is due to the target core being in a Busy state and occupied for an extended period. Therefore, a suitable processing core is selected to replace the computation and complete the remapping process. The selected target core meets the following conditions:

[0061] 1. The processing cores have the same computational functions;

[0062] 2. The core is currently idle; there are no queued tasks at the moment.

[0063] 3. The target core has sufficient cache space, and cores with larger cache spaces are selected first to ensure load balancing.

[0064] If no suitable target core is available to complete the task, the task's original priority is increased, and it is re-added to the task scheduling unit.

[0065] The processing procedure for the eight input data transmission control words is shown in the table below.

[0066] Table 1 Data Transmission Control Word Processing Procedure

[0067]

[0068]

[0069] The steps in this invention can be adjusted, combined, or deleted according to actual needs.

[0070] Although the invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of the invention. The scope of protection of the invention is defined by the appended claims and may include various modifications, alterations, and equivalents made to the invention without departing from the scope and spirit of the invention.

Claims

1. A queue-based control word output feedback control method, characterized in that, The queue-based control word output feedback control method includes: S1: The output control unit receives ordered control words, writes the control words to be transmitted into the Exit queue, and determines the number of words to be enqueued. S2: The output control unit outputs control words sequentially according to the Exit queue order. If the output fails, it is recorded and the control word is written to the auxiliary queue. The auxiliary queue includes the Subexit queue and the Waitexit queue; The output control unit outputs to the designated data transmission control unit according to the ID information carried by the control word in the order of the Exit queue. The feedback of Success indicates that the transmission is successful. The feedback of Busy signal will extend the count flag of the control word and write it into the Subexit queue. The feedback of Error signal and the control word has a storage problem will write it into the Wait queue. The feedback of Error signal and the control word has a DMA transmission error will write it directly into the Interrupt queue. S3: Auxiliary queue outputs control word. If the output fails, a count is written to the end of the queue. When the number of failed outputs of the control word reaches a preset value, it is written to the Interrupt queue. First, execute the output of the Subexit queue, then execute the output of the Waitexit queue. The specific steps are as follows: S3.1: The Subexit queue outputs the control word in a loop. If the output fails, it is counted and written to the end of the queue. A preset loop threshold is set. When the number of failed outputs of the control word reaches the preset threshold, it is written to the Interrupt queue. S3.2: The WaitTick queue outputs the control word in a loop. If the output fails, it is counted and written to the end of the queue. A preset loop threshold is set. When the number of failed outputs of the control word reaches the preset threshold, it is written to the Interrupt queue. S4: The error feedback unit includes an S2M feedback processing mechanism, an M2S feedback processing mechanism, and an M2M feedback processing mechanism, which performs error feedback processing based on the error type of the data transmission task in the Interrupt queue. The data transmission tasks are divided into three types according to their direction: S2M (sending data from an external device to an on-chip core), M2S (sending data from an on-chip core to an external device), and M2M (sending data between on-chip cores). In the latter, the external device sends a continuous data stream to the on-chip storage space, while the on-chip core sends data to the external device by slicing the data from the storage descriptor. In the inter-chip core task transmission, both the source and terminal storage are presented in the form of descriptors. In the error feedback unit, the feedback processing mechanism handles the data transmission task that matches its direction and processes it according to the control word transmission error type.

2. The queue-based control word output feedback control method according to claim 1, characterized in that, In step S1, when the control word output unit is idle, it sends a control word acquisition request to the task scheduling unit.

3. The queue-based control word output feedback control method according to claim 1, characterized in that, In step S2, step S3 is executed when the number of items dequeued from the Exit queue equals the number of items enqueued.

4. The queue-based control word output feedback control method according to claim 1, characterized in that, When the Subexit queue is not empty, the Exit queue and the Subexit queue alternately output control words. If the control word output by the Exit queue is busy, it continues to be written to the tail of the Subexit queue.

5. The queue-based control word output feedback control method according to claim 1, characterized in that, In step S4, the processing method is as follows: S2M feedback handling mechanism: Handles data transfer tasks (S2M) sent from external devices to on-chip cores, determines the error feedback type of task transfer failure when writing to the Interrupt queue, and if the error feedback is caused by Busy, it adopts a remapping mechanism to match other idle processing cores, changes the destination ID parameter in the storage descriptor, and executes the data transfer task. If the error feedback is caused by Error, it increases the original priority and re-adds the task to the task scheduling unit to wait for subsequent transmission. Among them, if the error feedback is caused by DMA transfer error, the data is lost, the data transfer task is canceled, the acquired destination storage descriptor is released, and the data is recorded and reported to the system. M2S Feedback Processing Mechanism: Processes data transmission tasks (M2S) sent from the on-chip core to external devices, determines the error feedback type of the task transmission failure when writing to the Interrupt queue, increases the execution priority of the control word if the error feedback is caused by Busy, and re-adds it to the task scheduling unit if the error feedback is caused by Error, does not reclaim the storage descriptor, and the remaining source data to be transmitted is re-initiated by the data transmission control unit to complete the slice transmission. M2M feedback handling mechanism: Handles data transfer tasks (M2M) between on-chip cores, determines the error feedback type when writing to the Interrupt queue, if the error feedback is caused by Busy, adopts the remapping mechanism to select other idle cores for processing, if there is no suitable core, increases the original priority and re-adds it to the task scheduling unit to wait for subsequent transmission, if the error feedback is caused by Error, releases the prefetched destination memory descriptor and re-initiates the transmission transaction.

6. The queue-based control word output feedback control method according to claim 1, characterized in that, In step S4, S1 is executed after the processing of the control word group is completed.

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