A delay-locked loop and memory

Abstract

The embodiment of the present disclosure provides a delay-locked loop and a memory, the delay-locked loop comprising: a preprocessing module configured to receive an initial clock signal, preprocess the initial clock signal, output a first clock signal and a second clock signal; a first adjustable delay line configured to receive the first clock signal, adjust and transmit the first clock signal, and output a first target clock signal; a second adjustable delay line configured to receive the second clock signal, adjust and transmit the second clock signal, and output a second synchronization clock signal; and a first adjustment module configured to adjust the phase of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal. In this way, the first adjustment module can correct the phase difference between the first synchronization clock signal and the second target clock signal, and improve the phase deviation between the target clock signals.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more particularly to a delay phase-locked loop and a memory. Background Technology

[0002] In Dynamic Random Access Memory (DRAM), a Delay-Locked Loop (DLL) needs to synchronize and lock four-phase clock signals (i.e., four clock signals with phases differing by 90 degrees) to obtain a set of target clock signals with a phase difference of 90 degrees, in order to sample the data signal DQ. However, due to mismatches or performance deviations in the components of the DLL, the phase difference between the final target clock signals may be offset, reducing the data sampling effect. Summary of the Invention

[0003] This disclosure provides a delay phase-locked loop and a memory that can reduce the phase deviation of the target clock signal output by the delay phase-locked loop.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a delayed phase-locked loop, the delayed phase-locked loop comprising:

[0006] The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal.

[0007] The first adjustable delay line is configured to receive the first clock signal, adjust and transmit the first clock signal, and output the first target clock signal.

[0008] The second adjustable delay line is configured to receive the second clock signal, adjust and transmit the second clock signal, and output the second synchronous clock signal.

[0009] The first adjustment module is configured to receive the first target clock signal and the second synchronous clock signal, perform delay adjustment on the second synchronous clock signal based on the first target clock signal, and output the second target clock signal.

[0010] The phase difference between the first target clock signal and the second target clock signal is a preset value.

[0011] In some embodiments, the preprocessing module includes: a receiving module configured to receive the initial clock signal and output a clock signal to be processed; wherein the clock period of the clock signal to be processed is the same as the clock period of the initial clock signal; and a phase-splitting module configured to receive the clock signal to be processed, perform frequency division and phase-splitting processing on the clock signal to be processed, and output the first clock signal and the second clock signal; wherein the clock periods of the first clock signal and the second clock signal are the same, and the clock period of the first clock signal is twice the clock period of the initial clock signal.

[0012] In some embodiments, the first adjustment module includes: a first control module configured to receive the first target clock signal and the second synchronization clock signal, and output a first control code based on the phase difference between the first target clock signal and the second synchronization clock signal; a first delay chain including a plurality of first delay units configured to receive the first control code and the second synchronization clock signal; and based on the first control code, to perform delay adjustment on the second synchronization clock signal using the plurality of first delay units, and output the second target clock signal.

[0013] In some embodiments, the first control module includes: a first pulse processing module configured to receive the first target clock signal and the second synchronization clock signal, and output a first pulse signal and a second pulse signal; wherein the first pulse signal and the second pulse signal each include one pulse, and the pulse width of the first pulse signal indicates the phase difference between the first target clock signal and the second synchronization clock signal, and the pulse width of the second pulse signal indicates the phase difference between the inverted signals of the second synchronization clock signal and the first target clock signal; a first time-to-digital conversion module configured to receive the first pulse signal and the second pulse signal; convert the first pulse signal to output a first conversion code, and convert the second pulse signal to output a second conversion code; wherein the first conversion code is used to characterize the width of the first pulse signal, and the second conversion code is used to characterize the width of the second pulse signal; and a first logic module configured to receive the first conversion code and the second conversion code, perform a subtraction operation on the second conversion code and the first conversion code, and output the first control code.

[0014] In some embodiments, the first pulse processing module includes: a first pulse module configured to receive a first target clock signal and a second synchronization clock signal, perform an XOR operation on the first target clock signal and the second synchronization clock signal to obtain a first detection signal, perform pulse truncation and widening processing on the first detection signal to obtain a first intermediate signal, perform an AND operation on the first intermediate signal and the first detection signal, and output the first pulse signal; wherein the first detection signal includes multiple pulses, and the pulse width of the first detection signal indicates the phase difference between the first target clock signal and the second synchronization clock signal, the first intermediate signal includes one pulse, and the pulse width of the first intermediate signal is greater than the pulse width of the first detection signal. Width; the second pulse module is configured to receive the inverted signal of the first target clock signal and the second synchronous clock signal, perform XOR processing on the inverted signal of the first target clock signal and the second synchronous clock signal to obtain a second detection signal, perform pulse truncation and widening processing on the second detection signal to obtain a second intermediate signal, perform AND processing on the second intermediate signal and the second detection signal, and output the second pulse signal; wherein, the second detection signal includes multiple pulses, and the pulse width of the second detection signal indicates the phase difference between the inverted signal of the first target clock signal and the second synchronous clock signal, and the second intermediate signal includes one pulse, the pulse width of the second intermediate signal being greater than the pulse width of the second detection signal.

[0015] In some embodiments, the first time conversion module includes: a first conversion module configured to receive a first pulse signal, sample and delay the first pulse signal to obtain a plurality of first sampling clock signals, sample the first pulse signal using the plurality of first sampling clock signals, and output the first conversion code; and a second conversion module configured to receive a second pulse signal, sample and delay the second pulse signal to obtain a plurality of second sampling clock signals, sample the second pulse signal using the plurality of second sampling clock signals, and output the second conversion code.

[0016] In some embodiments, the preprocessing module is further configured to preprocess the initial clock signal and output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; the delay-locked loop further includes: a third adjustable delay line configured to receive the third clock signal, adjust and transmit the third clock signal, and output a third target clock signal; wherein the phase difference between the first target clock signal and the third target clock signal is 180 degrees; a fourth adjustable delay line configured to receive the fourth clock signal, adjust and transmit the fourth clock signal, and output a fourth synchronous clock signal; a second adjustment module configured to receive the third target clock signal and the fourth synchronous clock signal, adjust the delay of the fourth synchronous clock signal based on the third target clock signal, and output a fourth target clock signal; wherein the adjacent phase difference between the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal is 90 degrees.

[0017] In some embodiments, the phase-splitting module is further configured to perform frequency division and phase-splitting processing on the clock signal to be processed, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; wherein the clock periods of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are the same, and the clock period of the first clock signal is twice the clock period of the initial clock signal.

[0018] In some embodiments, the second adjustment module includes: a second control module configured to receive the third target clock signal and the fourth synchronization clock signal, and output a second control code based on the phase difference between the third target clock signal and the fourth synchronization clock signal; and a second delay chain including a plurality of second delay units configured to receive the second control code and the fourth synchronization clock signal, and adjust the delay of the fourth synchronization clock signal using the plurality of second delay units based on the second control code, and output the fourth target clock signal.

[0019] In some embodiments, the second control module includes: a second pulse processing module configured to receive the third target clock signal and the fourth synchronization clock signal, and output a third pulse signal and a fourth pulse signal; wherein each of the third pulse signal and the fourth pulse signal includes one pulse, and the pulse width of the third pulse signal indicates the phase difference between the third target clock signal and the fourth synchronization clock signal, and the pulse width of the fourth pulse signal indicates the phase difference between the inverted signals of the fourth synchronization clock signal and the third target clock signal; a second time-to-digital conversion module configured to receive the third pulse signal and the third pulse signal; convert the third pulse signal to output a third conversion code, and convert the fourth pulse signal to output a fourth conversion code; wherein the third conversion code is used to characterize the width of the third pulse signal, and the fourth conversion code is used to characterize the width of the fourth pulse signal; and a second logic module configured to receive the third conversion code and the fourth conversion code, perform a subtraction operation on the fourth conversion code and the third conversion code, and output the second control code.

[0020] In some embodiments, the second pulse processing module includes: a third pulse module configured to receive the third target clock signal and the fourth synchronization clock signal, perform XOR processing on the third target clock signal and the fourth synchronization clock signal to obtain a third detection signal, perform pulse truncation and widening processing on the third detection signal to obtain a third intermediate signal, perform AND processing on the third intermediate signal and the third detection signal, and output the third pulse signal; wherein the third detection signal includes multiple pulses, and the pulse width of the third detection signal indicates the phase difference between the third target clock signal and the fourth synchronization clock signal, the third intermediate signal includes one pulse, and the pulse width of the third intermediate signal is greater than the pulse width of the third detection signal. The fourth pulse module is configured to receive the inverted signal of the third target clock signal and the fourth synchronous clock signal, perform XOR processing on the inverted signal of the third target clock signal and the fourth synchronous clock signal to obtain a fourth detection signal, perform pulse truncation and widening processing on the fourth detection signal to obtain a fourth intermediate signal, perform AND processing on the fourth intermediate signal and the fourth detection signal, and output the fourth pulse signal; wherein, the fourth detection signal includes multiple pulses, and the pulse width of the fourth detection signal indicates the phase difference between the inverted signal of the third target clock signal and the fourth synchronous clock signal, the fourth intermediate signal includes one pulse, and the pulse width of the fourth intermediate signal is greater than the pulse width of the fourth detection signal.

[0021] In some embodiments, the second time conversion module includes: a third conversion module configured to receive a third pulse signal, sample and delay the third pulse signal to obtain a plurality of third sampling clock signals, sample the third pulse signal using the plurality of third sampling clock signals, and output the third conversion code; and a fourth conversion module configured to receive a fourth pulse signal, sample and delay the fourth pulse signal to obtain a plurality of fourth sampling clock signals, sample the fourth pulse signal using the plurality of fourth sampling clock signals, and output the fourth conversion code.

[0022] In some embodiments, the first pulse module includes: a first flip-flop, a second flip-flop, a first NOT gate, a fourth delay unit, a first AND gate, a first XOR gate, and a second AND gate; the second pulse module, the third pulse module, and the fourth pulse module have the same structure as the first pulse module; wherein, in the first pulse module, the first input terminal of the first XOR gate receives the first target clock signal, the second input terminal of the first XOR gate receives the second synchronization clock signal, and the output terminal of the first XOR gate is used to output the first detection signal; the input terminal of the first flip-flop receives a first power supply signal, and the clock terminal of the first flip-flop is connected to the output terminal of the first XOR gate; the first NOT gate... The input terminal of the gate is connected to the output terminal of the first XOR gate; the input terminal of the second flip-flop receives the ground signal; the output terminal of the second flip-flop is connected to the output terminal of the first NOT gate; the input terminal of the fourth delay unit is connected to the output terminal of the second flip-flop; the first input terminal of the first AND gate is connected to the output terminal of the first flip-flop; the second input terminal of the first AND gate is connected to the output terminal of the fourth delay unit; the output terminal of the first AND gate is used to output the first intermediate signal; the first input terminal of the second AND gate is connected to the output terminal of the first AND gate; the second input terminal of the second AND gate is connected to the output terminal of the first XOR gate; the output terminal of the second AND gate is used to output the first pulse signal.

[0023] In some embodiments, the first conversion code, the second conversion code, the third conversion code, and the fourth conversion code each include multiple sub-signals; the first conversion module includes a third flip-flop, a third delay chain, and multiple fourth flip-flops, and the second conversion module, the third conversion module, and the fourth conversion module all have the same structure as the first conversion module; wherein, in the first conversion module, the input terminal of the third flip-flop receives a second power supply signal, the clock terminal of the third flip-flop receives the first pulse signal, and the output terminal of the third flip-flop is connected to the input terminal of the third delay chain; the input terminals of all the fourth flip-flops are used to receive the first pulse signal; the third delay chain includes multiple third delay units arranged in series, the clock terminal of one fourth flip-flop is correspondingly connected to the output terminal of one third delay unit, and the output terminal of one fourth flip-flop outputs one sub-signal of the first conversion code.

[0024] In some embodiments, the first delay chain includes a plurality of first delay units arranged in series, and the second delay chain includes a plurality of second delay units; the first delay units in the first delay chain, the second delay units in the second delay chain, and the third delay units in the third delay chain are identical.

[0025] In some embodiments, the i-th sub-signal of the first control code is used to control the i-th first delay unit to be in an on or off state, and the i-th sub-signal of the second control code is used to control the i-th second delay unit to be in an on or off state; the first delay chain is specifically configured to use the first delay unit in the on state to delay the second synchronization clock signal and output the second target clock signal; the second delay chain is specifically configured to use the second delay unit in the on state to delay the fourth synchronization clock signal and output the fourth target clock signal.

[0026] In some embodiments, the first 'a' bits of the first control code are in a first state, and the last (Aa) bits of the first control code are in a second state; the first 'b' bits of the second control code are in a first state, and the last (Bb) bits of the second control code are in a second state; A, B, a, and b are all positive integers, and a is less than or equal to A, where A refers to the total number of bits of the sub-signals in the first control code, and b is less than or equal to B, where B refers to the total number of bits of the sub-signals in the second control code; the first delay chain is specifically configured to use the first to the 'a'th first delay units to delay the second synchronization clock signal, and to determine the output signal of the 'a'th first delay unit as the second target clock signal; the second delay chain is specifically configured to use the first to the 'b'th second delay units to delay the fourth synchronization clock signal, and to determine the output signal of the 'b'th second delay unit as the fourth target clock signal.

[0027] In some embodiments, the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are used for data sampling processing after passing through corresponding signal transmission paths; the delay phase-locked loop further includes: a feedback module configured to receive the first clock signal and output an analog clock signal, wherein the analog clock signal is used to simulate the waveform of the first target clock signal after passing through the signal transmission path; a detection module configured to receive the first clock signal and the analog clock signal, perform phase detection on the first clock signal and the analog clock signal, and obtain a phase detection signal; a parameter adjustment module configured to receive the phase detection signal and output a delay line control signal based on the phase detection signal; a first adjustable delay line specifically configured to receive the delay line control signal, adjust and transmit the first clock signal based on the delay line control signal, and output the first target clock signal; a second adjustable delay line specifically configured to receive the delay line control signal, adjust and transmit the second clock signal based on the delay line control signal, and output the second synchronization clock signal.

[0028] In some embodiments, the feedback module includes: a fifth adjustable delay line configured to receive the first clock signal and the delay line control signal, adjust and transmit the first clock signal based on the delay line control signal, and output a replicated clock signal; wherein the fifth adjustable delay line has the same structure as the first adjustable delay line, and the replicated clock signal is used to simulate the waveform of the first target clock signal; and a replicated delay module configured to receive the replicated clock signal, perform delay processing on the replicated clock signal, and output an analog clock signal; wherein the replicated delay module is used to simulate the delay of the signal transmission path.

[0029] In a second aspect, embodiments of this disclosure provide a memory that includes at least the delay phase-locked loop described in the first aspect.

[0030] This disclosure provides a delay-locked loop (DLL) and a memory. The DLL includes: a preprocessing module configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal; a first adjustable delay line configured to receive the first clock signal, adjust and transmit the first clock signal, and output a first target clock signal; a second adjustable delay line configured to receive a second clock signal, adjust and transmit the second clock signal, and output a second synchronous clock signal; and a first adjustment module configured to adjust the delay of the second synchronous clock signal based on the first target clock signal and output a second target clock signal. The phase difference between the first target clock signal and the second target clock signal is a preset value. Thus, the first adjustment module can correct the phase difference between the first synchronous clock signal and the second target clock signal, improving the phase deviation between the target clock signals. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a delay phase-locked loop;

[0032] Figure 2 A signal timing diagram Figure 1 ;

[0033] Figure 3 A signal timing diagram Figure 2 ;

[0034] Figure 4 A schematic diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 1 ;

[0035] Figure 5 A schematic diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 2 ;

[0036] Figure 6 A signal timing diagram provided for an embodiment of this disclosure Figure 1 ;

[0037] Figure 7 A schematic diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 3 ;

[0038] Figure 8 A signal timing diagram provided for an embodiment of this disclosure Figure 2 ;

[0039] Figure 9A partial structural diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 1 ;

[0040] Figure 10 A partial structural diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 2 ;

[0041] Figure 11 A signal timing diagram provided for an embodiment of this disclosure Figure 3 ;

[0042] Figure 12 This is a schematic diagram of a clock synchronization circuit provided in an embodiment of the present disclosure;

[0043] Figure 13 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] Dynamic Random Access Memory (DRAM)

[0046] Synchronous Dynamic Random Access Memory (SDRAM)

[0047] Double Data Rate SDRAM (DDR)

[0048] Low-power DDR (LPDDR)

[0049] The nth generation DDR standard (DDRn Specification, DDRn), such as DDR3, DDR4, DDR5, DDR6.

[0050] The nth generation LPDDR standard (LPDDRn Specification, LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6.

[0051] Currently, memory is increasingly moving towards higher speeds. Taking DDR5 as an example, due to its increased speed and process limitations, the high-speed clock signal at the interface needs to be converted to a low-speed clock signal internally. For instance, the delay-locked loop (DLL) in the memory needs to dynamically adjust the clock signal delay and perform delay matching through a large number of inverter chains. At high speeds, these inverter chains may cause a significant accumulation of jitter, ultimately leading to signal loss. Therefore, at the high speeds of DDR5, to ensure signal quality, the initial clock signal CLK from the outside is internally divided / phased to obtain a four-phase clock signal. The four-phase clock signals are then fed into the DLL for phase synchronization and locking. Finally, the data selection module (Mux) uses the adjusted four-phase clock signals to sample and select the output of the data signal DQ to obtain the target data signal.

[0052] See Figure 1 This shows a schematic diagram of a delay phase-locked loop. (See also...) Figure 2 It illustrates a signal timing diagram. Figure 1 .like Figure 1 and Figure 2As shown, the initial clock signal CLK enters the delay-locked loop (PLL) through the receiving module, and is then processed by the phase-splitting module into four-phase clock signals (clk0, clk90, clk180, and clk270), with the frequency of the four-phase clock signals reduced to half that of the initial clock signal CLK. Next, the four-phase clock signals are adjusted in terms of delay and duty cycle using four adjustable delay lines. Thus, after phase locking in the PLL, four-phase target clock signals (DLL0, DLL90, DLL180, and DLL270) are obtained. These target clock signals DLL0, DLL90, DLL180, and DLL270 are transmitted to the data selection module via corresponding signal transmission paths. The data selection module converts the four-phase target clock signals DLL0, DLL90, DLL180, and DLL270 into a data sampling clock signal DQS. Subsequently, the data signal DQ is sampled using the data sampling clock signal DQS to obtain the target data signal. In addition, the delay-locked loop also includes a fifth adjustable delay line, a replication delay module, a detection module, and a parameter tuning module. The fifth adjustable delay line and the replication delay module form a loop. The fifth adjustable delay line receives the clock signal clk0, and the replication delay module outputs an analog clock signal. The analog clock signal is used to simulate the waveform of the target clock signal DLL0 when it is transmitted to the data selection module. The detection module detects the phase difference between the analog clock signal and the clock signal clk0. The parameter tuning module outputs a delay line control signal based on the detection result of the detection module. The delay line control signal is used to control the operating parameters of all adjustable delay lines. In this way, the delay-locked loop has a closed-loop feedback mechanism to ensure that the final processed target clock signals DLL0 / DLL90 / DLL180 / DLL270 meet the requirements.

[0053] As described above, the initial clock signal CLK is divided into four paths entering the delay-locked loop (DLL). To ensure that the rising and falling edges of the initial clock signal CLK are not lost, the DLL needs to prepare four main adjustable delay lines to perform phase synchronization and locking processing on the four-phase clock signals before finally transmitting them to the data selection module (Mux). However, due to the mismatch between the four adjustable delay lines, and the inherent errors in the four-phase clock signals (clk0, clk90, clk180, and clk270) output by the conversion module, there is also a phase deviation between the target clock signals DLL0 / DLL90 / DLL180 / DLL270. (See also...) Figure 3 It illustrates a signal timing diagram. Figure 2 .like Figure 3As shown, the phase differences (represented by T1, T2, T3 and T4) between the target clock signals DLL0DLL90 / DLL180 / DLL270 that are finally sent to the data selection module are not the same. At this time, the lengths of the pulse periods (represented by t1 and t2) in the data sampling clock signal DQS are not the same, that is, the effective window of the data sampling clock signal is small, which limits the improvement of memory performance.

[0054] Based on this, the present disclosure provides a delay phase-locked loop (PLL) to improve the phase deviation between the clock signals output by the PLL, thereby further improving the performance of the memory.

[0055] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0056] In one embodiment of this disclosure, see Figure 4 It shows a schematic diagram of the structure of a delay phase-locked loop 10 provided in an embodiment of this disclosure. Figure 1 .like Figure 4 As shown, the delay phase-locked loop 10 includes:

[0057] Preprocessing module 11 is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal.

[0058] The first adjustable delay line 12 is configured to receive the first clock signal, adjust and transmit the first clock signal, and output the first target clock signal.

[0059] The second adjustable delay line 13 is configured to receive the second clock signal, adjust and transmit the second clock signal, and output the second synchronous clock signal.

[0060] The first adjustment module 14 is configured to receive a first target clock signal and a second synchronous clock signal, adjust the delay of the second synchronous clock signal based on the first target clock signal, and output a second target clock signal, wherein the phase difference between the first target clock signal and the second target clock signal is a preset value.

[0061] It should be noted that the delay-locked loop 10 of this disclosure embodiment can be applied to, but is not limited to, memory, such as DRAM, SDRAM, etc. Furthermore, in other analog / digital circuits, the delay-locked loop 10 provided in this disclosure embodiment can be used to generate a set of clock signals with different phases.

[0062] In the delay-locked loop 10, a first target clock signal and a second synchronous clock signal are obtained through a first adjustable delay line 12 and a second adjustable delay line 13, respectively. Then, a first adjustment module 14 is used to adjust the delay of the second synchronous clock signal to obtain the second target clock signal, ensuring that the phase difference between the first target clock signal and the second target clock signal is a preset value. In this way, by introducing the first adjustment module 14, the phase difference between the first synchronous clock signal and the second target clock signal can be corrected, improving the phase deviation caused by delay line mismatch or preprocessing.

[0063] It should be noted that the preset values ​​can be set according to the actual application scenario, such as 180 degrees or 90 degrees. Furthermore, the phase difference limits in this disclosure embodiment allow for a certain error; that is, the phase difference between the first target clock signal and the second target clock signal is the preset value within the allowable error range. Unless otherwise specified, the subsequent limitations regarding phase difference and clock period can be understood accordingly.

[0064] The embodiments disclosed herein will be described with a preset value of 90 degrees. At this time, the first target clock signal can be represented as DLL0, and the second target clock signal can be represented as DLL90. Other cases can be understood by referring to the following.

[0065] In some embodiments, see Figure 5 It shows a schematic diagram of the structure of a delay phase-locked loop 10 provided in an embodiment of this disclosure. Figure 2 .like Figure 5 As shown, the preprocessing module 11 includes:

[0066] The receiving module 111 is configured to receive the initial clock signal CLK and output a clock signal to be processed; wherein the clock period of the clock signal to be processed is the same as the clock period of the initial clock signal CLK.

[0067] Phase splitting module 112 is configured to receive a clock signal to be processed, perform frequency division and phase splitting processing on the clock signal to be processed, and output a first clock signal clk0 and a second clock signal clk90; wherein the clock periods of the first clock signal clk0 and the second clock signal clk90 are the same, and the clock period of the first clock signal clk0 is twice the clock period of the initial clock signal CLK.

[0068] It should be noted that, ideally, the phase difference between the first clock signal clk0 and the second clock signal clk90 is 90 degrees. However, due to deviations in actual process parameters and mismatch issues, the operating parameters of the phase splitting module 112 may be deviated, resulting in the phase difference between the first clock signal clk0 and the second clock signal clk90 not being 90 degrees and exceeding the allowable error range. This is also part of the reason why the first adjustment module 14 needs to be introduced.

[0069] In some embodiments, please refer to Figure 4 and Figure 5 The first adjustment module 14 includes:

[0070] The first control module 141 is configured to receive a first target clock signal DLL0 and a second synchronization clock signal DL90, and output a first control code DLLCode1 based on the phase difference between the first target clock signal DLL0 and the second synchronization clock signal DL90.<N:0> ;

[0071] The first delay chain 142 includes multiple first delay units and is configured to receive the first control code DLLCode1.<N:0> Second synchronization clock signal DL90; based on first control code DLLCode1<N:0> The delay of the second synchronous clock signal DL90 is adjusted by using multiple first delay units, and the second target clock signal DLL90 is output.

[0072] It should be noted that the first control code is DLLCode1.<N:0> It is obtained by converting the phase deviation between the second synchronization clock signal DL90 and the ideal situation (i.e., the first target clock signal DLL0 delayed by 90 degrees). Furthermore, the first delay chain 142 can be based on the first control code DLLCode1.<N:0> The phase of the second synchronous clock signal DL90 is adjusted forward or backward to obtain the second target clock signal DLL90, so as to ensure that the phase difference between the first target clock signal DLL0 and the second target clock signal DLL90 is 90 degrees.

[0073] In some embodiments, such as Figure 5 As shown, the first control module 141 includes:

[0074] The first pulse processing module 21 is configured to receive a first target clock signal DLL0 and a second synchronous clock signal DL90, and output a first pulse signal IN0 and a second pulse signal IN1; wherein the first pulse signal IN0 and the second pulse signal IN1 each include one pulse, and the pulse width of the first pulse signal IN0 indicates the phase difference between the first target clock signal DLL0 and the second synchronous clock signal DL90, and the pulse width of the second pulse signal IN1 indicates the phase difference between the second synchronous clock signal DL90 and the inverted signal of the first target clock signal;

[0075] The first time-to-digital converter module 22 is configured to receive a first pulse signal IN0 and a second pulse signal IN1; convert the first pulse signal IN0; and output a first conversion code TDCCode0.<N:0> It also converts the second pulse signal IN1 and outputs the second conversion code TDCCode1.<N:0> Among them, the first conversion code is TDCCode0.<N:0> Used to characterize the width of the first pulse signal IN0, the second conversion code TDCCode1<N:0> Used to characterize the width of the second pulse signal IN1;

[0076] The first logic module 23 is configured to receive the first conversion code TDCCode0.<N:0> Second conversion code TDCCode1<N:0> For the second conversion code TDCCode1<N:0> And the first conversion code TDCCode0<N:0> Perform subtraction and output the first control code DLLCode1.<N:0> .

[0077] Thus, if the pulse width of the first pulse signal IN0 is greater than the pulse width of the second pulse signal IN1, it indicates that the second synchronization clock signal DL90 is too lagging; if the pulse width of the first pulse signal IN0 is less than the pulse width of the second pulse signal IN1, it indicates that the second synchronization clock signal DL90 is too advanced. Simultaneously, the first conversion code TDCCode0...<N:0> The value corresponds to the pulse width of the first pulse signal IN0, and the second conversion code TDCCode1<N:0> The value of is corresponding to the pulse width of the second pulse signal IN1, therefore the second conversion code TDCCode1 is...<N:0> Subtract the first conversion code TDCCode0<N:0> Able to obtain the first control code DLLCode1<N:0> .

[0078] Specifically, depending on the definitions of the parameters in the circuit and the different signal connection relationships, the first conversion code TDCCode0 may also be used.<N:0> Subtract the second conversion code TDCCode1<N:0> Obtain the first control code DLLCode1<N:0> The specific mechanism needs to be determined based on the actual circuit.

[0079] In some embodiments, see Figure 6 It illustrates a signal timing diagram provided in an embodiment of this disclosure. Figure 1 Please refer to this. Figure 5 and Figure 6 The first pulse processing module 21 includes:

[0080] The first pulse module 211 is configured to receive a first target clock signal DLL0 and a second synchronization clock signal DL90, perform an XOR operation on the first target clock signal DLL0 and the second synchronization clock signal DL90 to obtain a first detection signal D0, perform pulse truncation and widening operation on the first detection signal D0 to obtain a first intermediate signal S0, perform an AND operation on the first intermediate signal S0 and the first detection signal D0, and output a first pulse signal IN0; wherein, the first detection signal D0 includes multiple pulses, and the pulse width of the first detection signal D0 indicates the phase difference between the first target clock signal DLL0 and the second synchronization clock signal DL90, and the first intermediate signal S0 includes one pulse, and the pulse width of the first intermediate signal S0 is greater than the pulse width of the first detection signal D0;

[0081] The second pulse module 212 is configured to receive the inverted signal of the first target clock signal and the second synchronous clock signal DL90, perform XOR processing on the inverted signal of the first target clock signal and the second synchronous clock signal DL90 to obtain a second detection signal D1, perform pulse truncation and widening processing on the second detection signal D1 to obtain a second intermediate signal S1, and perform AND processing on the second intermediate signal S1 and the second detection signal D1 to output a second pulse signal IN1; wherein, the second detection signal D1 includes multiple pulses, and the pulse width of the second detection signal D1 indicates the phase difference between the inverted signal of the first target clock signal and the second synchronous clock signal DL90, and the second intermediate signal S1 includes one pulse, the pulse width of the second intermediate signal S1 being greater than the pulse width of the second detection signal D1.

[0082] Here, the pulse of the first intermediate signal S0 at least covers a complete pulse of the first detection signal D0, and the pulse of the second intermediate signal S1 at least covers a complete pulse of the second detection signal D1. Figure 6 In the diagram, "△" represents the amount of widening during the widening process.

[0083] It should be noted that the structure of the first pulse module 211 and the second pulse module 212 can be composed of a variety of electrical components. A specific example will be provided later in this disclosure.

[0084] In some embodiments, please refer to Figure 5 and Figure 6 The first-time conversion module 22 includes:

[0085] The first conversion module 221 is configured to receive a first pulse signal IN0, sample and delay the first pulse signal IN0 to obtain multiple first sampling clock signals, sample the first pulse signal IN0 using the multiple first sampling clock signals, and output a first conversion code TDCCode0.<N:0> ;

[0086] The second conversion module 222 is configured to receive the second pulse signal IN1, sample and delay the second pulse signal IN1 to obtain multiple second sampling clock signals, sample the second pulse signal IN1 using the multiple second sampling clock signals, and output the second conversion code TDCCode1.<N:0> .

[0087] It should be noted that the structures of the first conversion module 221 and the second conversion module 222 are similar, and they can be composed of a variety of electrical components. A specific example will be provided later in this disclosure.

[0088] In some embodiments, see Figure 7 It shows a schematic diagram of the structure of a delay phase-locked loop 10 provided in an embodiment of this disclosure. Figure 3 .like Figure 7 As shown, the output signal of the delay phase-locked loop 10 may also include a third target clock signal DLL180 and a fourth target clock signal DLL270. That is, the delay phase-locked loop 10 outputs a first target clock signal DLL0, a second target clock signal DLL90, a third target clock signal DLL180, and a fourth target clock signal DLL270, and the phase difference between adjacent target clock signals is 90 degrees.

[0089] At this time, the preprocessing module 11 is also configured to preprocess the initial clock signal CLK and output the first clock signal clk0, the second clock signal clk90, the third clock signal clk180, and the fourth clock signal clk270. Correspondingly, the delay phase-locked loop 10 also includes:

[0090] The third adjustable delay line 15 is configured to receive the third clock signal clk180, adjust and transmit the third clock signal clk180, and output the third target clock signal DLL180; wherein the phase difference between the first target clock signal DLL0 and the third target clock signal DLL180 is 180 degrees.

[0091] The fourth adjustable delay line 16 is configured to receive the fourth clock signal clk270, adjust and transmit the fourth clock signal clk270, and output the fourth synchronous clock signal DL270.

[0092] The second adjustment module 17 is configured to receive the third target clock signal DLL180 and the fourth synchronous clock signal DL270, adjust the delay of the fourth synchronous clock signal DL270 based on the third target clock signal DLL180, and output the fourth target clock signal DLL270.

[0093] It should be noted that, due to the circuit principle of the delay phase-locked loop 10, the mismatch between the first target clock signal DLL0 output from the first adjustable delay line 12 and the third target clock signal DLL180 output from the third adjustable delay line 15 is relatively small, as explained in the previous section. Figure 3 In other words, the phase difference between the first target clock signal DLL0 and the third target clock signal DLL180 can be considered to be stable at 180 degrees, meaning that the first target clock signal DLL0 and the third target clock signal DLL180 are inverse signals. However, the phase of the fourth synchronous clock signal DL270 directly output by the fourth adjustable delay line 16 may be offset due to mismatch or other reasons. Therefore, the second adjustment module 17 is introduced to adjust the delay of the fourth synchronous clock signal DL270, which can make the phase difference between the third target clock signal DLL180 and the fourth target clock signal DLL270 90 degrees, thus improving the phase deviation caused by delay line mismatch or preprocessing.

[0094] It should also be noted that, such as Figure 7 As shown, the phase-splitting module 112 is further configured to perform frequency division and phase division processing on the clock signal to be processed, and output a first clock signal clk0, a second clock signal clk90, a third clock signal clk180 and a fourth clock signal clk270; wherein, the clock periods of the first clock signal clk0, the second clock signal clk90, the third clock signal clk180 and the fourth clock signal clk270 are the same, and the clock period of the first clock signal clk0 is twice the clock period of the initial clock signal CLK.

[0095] It should be understood that the composition of the second adjustment module 17 is similar to that of the first adjustment module 14, as detailed below.

[0096] In some embodiments, such as Figure 7 As shown, the second adjustment module 17 includes:

[0097] The second control module 171 is configured to receive the third target clock signal DLL180 and the fourth synchronization clock signal DL270, and output the second control code DLLCode2 based on the phase difference between the third target clock signal DLL180 and the fourth synchronization clock signal DL270.<N:0> ;

[0098] The second delay chain 172 includes multiple second delay units and is configured to receive the second control code DLLCode2.<N:0> And the fourth synchronization clock signal DL270, based on the second control code DLLCode2<N:0> The fourth synchronous clock signal DL270 is delayed by using multiple second delay units, and the fourth target clock signal DLL270 is output.

[0099] It should be noted that the second control code DLLCode2<N:0> It is obtained by converting the phase deviation between the fourth synchronization clock signal DL270 and the ideal situation (i.e., the third target clock signal DLL180 delayed by 90 degrees). Furthermore, the second delay chain 172 can be based on the second control code DLLCode2.<N:0> The phase of the fourth synchronous clock signal DL270 is adjusted forward or backward to obtain the fourth target clock signal DLL270, so as to ensure that the phase difference between the third target clock signal DLL180 and the fourth target clock signal DLL270 is 90 degrees.

[0100] In some embodiments, see Figure 8 It illustrates a signal timing diagram provided in an embodiment of this disclosure. Figure 2 Please refer to this. Figure 7 and Figure 8 The second control module 171 includes:

[0101] The second pulse processing module 24 is configured to receive the third target clock signal DLL180 and the fourth synchronization clock signal DL270, and output the third pulse signal IN2 and the fourth pulse signal IN3; wherein the third pulse signal IN2 and the fourth pulse signal IN3 each include one pulse, and the pulse width of the third pulse signal IN2 indicates the phase difference between the third target clock signal DLL180 and the fourth synchronization clock signal DL270, and the pulse width of the fourth pulse signal IN3 indicates the phase difference between the fourth synchronization clock signal DL270 and the inverted signal of the third target clock signal;

[0102] The second time-to-digital converter module 25 is configured to receive the third pulse signal IN2 and convert the third pulse signal IN2, and output the third conversion code TDCCode2.<N:0> It also converts the fourth pulse signal IN3 and outputs the fourth conversion code TDCCode3.<N:0> Among them, the third conversion code is TDCCode2.<N:0> The fourth conversion code, TDCCode3, is used to characterize the width of the third pulse signal IN2.<N:0> Used to characterize the width of the fourth pulse signal IN3;

[0103] The second logic module 26 is configured to receive the third conversion code TDCCode2.<N:0> and the fourth conversion code TDCCode3<N:0> For the fourth conversion code TDCCode3<N:0> and the third conversion code TDCCode2<N:0> Perform the subtraction operation and output the second control code DLLCode2.<N:0> .

[0104] Thus, if the pulse width of the third pulse signal IN2 is greater than the pulse width of the fourth pulse signal IN3, it indicates that the fourth synchronization clock signal DL270 is too lagging; if the pulse width of the third pulse signal IN2 is less than the pulse width of the fourth pulse signal IN3, it indicates that the fourth synchronization clock signal DL270 is too advanced. Simultaneously, the third conversion code TDCCode2...<N:0> The value corresponds to the pulse width of the third pulse signal IN2, and the fourth conversion code is TDCCode3.<N:0> The value of TDCCode3 corresponds to the pulse width of the fourth pulse signal IN3.<N:0> Subtract the third conversion code TDCCode2<N:0> Able to obtain the second control code DLLCode2<N:0> .

[0105] In some embodiments, such as Figure 7 As shown, the second pulse processing module 24 includes:

[0106] The third pulse module 213 is configured to receive the third target clock signal DLL180 and the fourth synchronization clock signal DL270, perform XOR processing on the third target clock signal DLL180 and the fourth synchronization clock signal DL270 to obtain the third detection signal D2, perform pulse truncation and widening processing on the third detection signal D2 to obtain the third intermediate signal S2, and perform AND processing on the third intermediate signal S2 and the third detection signal D2 to output the third pulse signal IN2; wherein, the third detection signal D2 includes multiple pulses, and the pulse width of the third detection signal D2 indicates the phase difference between the third target clock signal DLL180 and the fourth synchronization clock signal DL270, and the third intermediate signal S2 includes one pulse, and the pulse width of the third intermediate signal S2 is greater than the pulse width of the third detection signal D2;

[0107] The fourth pulse module 214 is configured to receive the inverted signal of the third target clock signal and the fourth synchronization clock signal DL270, perform XOR processing on the inverted signal of the third target clock signal and the fourth synchronization clock signal DL270 to obtain the fourth detection signal D3, perform pulse truncation and widening processing on the fourth detection signal D3 to obtain the fourth intermediate signal S3, and perform AND processing on the fourth intermediate signal S3 and the fourth detection signal D3 to output the fourth pulse signal IN3; wherein, the fourth detection signal D3 includes multiple pulses, and the pulse width of the fourth detection signal D3 indicates the phase difference between the inverted signal of the third target clock signal and the fourth synchronization clock signal DL270, and the fourth intermediate signal S3 includes one pulse, the pulse width of the fourth intermediate signal S3 being greater than the pulse width of the fourth detection signal D3.

[0108] Here, the pulse of the third intermediate signal S2 covers at least one complete pulse of the third detection signal D2, and the pulse of the fourth intermediate signal S3 covers at least one complete pulse of the fourth detection signal D3. Meanwhile, the third pulse module 213 and the fourth pulse module 214 can be composed of various electrical components, and a specific example will be provided later in this disclosure.

[0109] In some embodiments, such as Figure 7 As shown, the second time conversion module 25 includes:

[0110] The third conversion module 223 is configured to receive the third pulse signal IN2, sample and delay the third pulse signal IN2 to obtain multiple third sampling clock signals, use the multiple third sampling clock signals to sample the third pulse signal IN2, and output the third conversion code TDCCode2.<N:0> ;

[0111] The fourth conversion module 224 is configured to receive the fourth pulse signal IN3, sample and delay the fourth pulse signal IN3 to obtain multiple fourth sampling clock signals, use the multiple fourth sampling clock signals to sample the fourth pulse signal IN3, and output the fourth conversion code TDCCode3.<N:0> .

[0112] It should be noted that the third conversion module and the fourth conversion module have similar structures and can be composed of a combination of various electrical components. A specific example will be provided later in this disclosure.

[0113] As can be seen from the above, for the delay phase-locked loop 10, since the first adjustment module is used to make additional adjustments to the second synchronous clock signal DL90 output by the second adjustable delay line, and the second adjustment module is used to make delay adjustments to the fourth synchronous clock signal DL270 output by the fourth adjustable delay line, the phase difference of the final four-phase clock signal can be guaranteed to be the preset value, thereby improving the phase deviation caused by delay line mismatch or preprocessing and improving the data sampling effect.

[0114] As mentioned above, the first pulse module 211 to the fourth pulse module 214 have the same structure, and the first conversion module 221 to the fourth conversion module 224 have the same structure. The following uses the first pulse module 211 and the first conversion module 221 as examples to provide feasible circuit element compositions.

[0115] In some embodiments, see Figure 9 It shows a partial structural diagram of a delay phase-locked loop 10 provided in an embodiment of this disclosure. Figure 1 .like Figure 9 As shown, the first pulse module 211 ( Figure 9The first pulse module 211 (comprising two parts, 211a and 211b) includes: a first flip-flop 301, a second flip-flop 302, a first NOT gate 303, a fourth delay unit 304, a first AND gate 305, a first XOR gate 306, and a second AND gate 307. In the first pulse module 211, the first input of the first XOR gate 306 receives the first target clock signal DLL0, the second input of the first XOR gate 306 receives the second synchronization clock signal DL90, and the output of the first XOR gate 306 is used to output the first detection signal D0. The input of the first flip-flop 301 receives the first power supply signal VDD, and the clock terminal of the first flip-flop 301 is connected to the output of the first XOR gate 306. The input of the first NOT gate 303 is connected to the first XOR gate 306. The output terminal of the first AND gate 305 is connected to the output terminal of the first AND gate 301, the input terminal of the second AND gate 305 is connected to the output terminal of the first AND gate 301, the second input terminal of the first AND gate 305 is connected to the output terminal of the fourth AND gate 304, and the output terminal of the first AND gate 305 is used to output the first intermediate signal S0; the first input terminal of the second AND gate 307 is connected to the output terminal of the first AND gate 305, the second input terminal of the second AND gate 307 is connected to the output terminal of the first XOR gate 306, and the output terminal of the second AND gate 307 is used to output the first pulse signal IN0.

[0116] It should be noted that, as mentioned above Figure 8 As shown, the first detection signal D0 includes multiple pulses, and the pulse width of each pulse indicates the phase difference between the first target clock signal DLL0 and the second synchronization clock signal DL90. The first intermediate signal S0 includes only one pulse signal, and the pulse width of the first intermediate signal S0 is (the pulse width of the first detection signal D0 + the delay value Δ of the fourth delay unit 304). The pulse of the first intermediate signal S0 covers, and only covers, one pulse of the first detection signal D0. Thus, performing a bitwise AND operation between the first intermediate signal S0 and the first detection signal D0 retains exactly one pulse of the first detection signal D0, thereby obtaining a first pulse signal IN0 that indicates the phase difference between the first target clock signal DLL0 and the second synchronization clock signal DL90.

[0117] To avoid confusion, Figure 9 The devices in the first pulse module 211 are numbered, as shown in the dashed box. The devices in the second to fourth pulse modules are not numbered. Please understand this accordingly.

[0118] Second pulse module 212 ( Figure 9In the first XOR gate (which includes two parts, 212a and 212b), the first input of the first XOR gate is the second synchronous clock signal DL90, the second input of the first XOR gate is the third target clock signal DLL180 (equivalent to the inverted signal of the first target clock signal), the output of the first XOR gate is used to output the second detection signal D1, the output of the first AND gate is used to output the second intermediate signal S1, the output of the second AND gate is used to output the first pulse signal IN0, and the connection relationship of the remaining devices is the same as that of the first pulse module 211.

[0119] In the third pulse module 213 ( Figure 9 In the first XOR gate (which includes two parts, 213a and 213b), the first input of the first XOR gate is the third target clock signal DLL180, the second input of the first XOR gate is the fourth synchronization clock signal DL270, the output of the first XOR gate is used to output the third detection signal D2, the output of the first AND gate is used to output the third intermediate signal S2, the output of the second AND gate is used to output the third pulse signal IN2, and the connection relationship of the remaining devices is the same as that of the first pulse module 211.

[0120] In the fourth pulse module 214 ( Figure 9 In the first XOR gate (which includes two parts, 214a and 214b), the first input of the first XOR gate is the fourth synchronous clock signal DL270, the second input of the first XOR gate is the first target clock signal DLL0 (equivalent to the inverted signal of the third target clock signal), the output of the first XOR gate is used to output the fourth detection signal D3, the output of the first AND gate is used to output the fourth intermediate signal S3, the output of the second AND gate is used to output the fourth pulse signal IN3, and the connection relationship of the remaining devices is the same as that of the first pulse module 211.

[0121] Thus, as Figure 8 and Figure 9 As shown, the first pulse signal IN0, the second pulse signal IN1, the third pulse signal IN2, and the fourth pulse signal IN3 are obtained through the first pulse module 211 to the fourth pulse module 214, thereby obtaining the offset of the second synchronous clock signal DL90 and the fourth synchronous clock signal DL270.

[0122] In some embodiments, the first conversion code TDCCode0<N:0> Second conversion code TDCCode1<N:0> Third conversion code TDCCode2<N:0> Fourth conversion code TDCCode3<N:0> Each of them includes multiple sub-signals. The first conversion code is TDCCode0.<N:0> For example, it includes TDCcode0: <0> TDCcode0: <1> ...TDCcode0 <n>These are sub-signals.

[0123] See Figure 10 It shows a partial structural diagram of a delay phase-locked loop 10 provided in an embodiment of this disclosure. Figure 2 .like Figure 10 As shown, the first conversion module 221 includes a third flip-flop 308, a third delay chain 309, and multiple fourth flip-flops 310. The input of the third flip-flop 308 receives the second power supply signal VDD, the clock input of the third flip-flop 308 receives the first pulse signal IN0, and the output of the third flip-flop 308 is connected to the input of the third delay chain 309. All the inputs of the fourth flip-flops 310 are used to receive the first pulse signal IN0. The third delay chain 309 includes multiple third delay units arranged in series. The clock input of one fourth flip-flop 310 is correspondingly connected to the output of one third delay unit, and the output of one fourth flip-flop 310 outputs the first conversion code TDCCode0.<N:0> One of the sub-signals.

[0124] It should be noted that, for ease of explanation, the output signal of the third flip-flop 308 is denoted as signal Clk_start_0, see [link to documentation]. Figure 11 It illustrates a signal timing diagram provided in an embodiment of this disclosure. Figure 3 .like Figure 11 As shown, at the rising edge of the first pulse signal IN0, the signal Clk_start_0 changes from a low level to a high level. During the process of passing through multiple third delay units, the signal Clk_start_0 sequentially obtains signals Clk_start0 (used as the clock signal for the first fourth flip-flop 310), Clk_start1 (used as the clock signal for the second fourth flip-flop 310), ..., Clk_startN (used as the clock signal for the last fourth flip-flop 310). The first pulse signal IN0 is sampled using signal Clk_start0 to obtain the TDC0 code. <0> TDCcode0 is obtained by sampling the first pulse signal IN0 using the signal Clk_start1. <1> ...TDCcode0 is obtained by sampling the first pulse signal IN0 using the signal Clk_startN. <n>Thus, the first conversion code TDCCode0 is obtained.<N:0> .

[0125] akin, Figure 10 Only the devices in the first conversion module 221 are numbered; the devices in the second to fourth conversion modules are not numbered. Please understand this accordingly.

[0126] Specifically, in the second conversion module 222, the clock terminal of the third flip-flop and the input terminals of all the fourth flip-flops are used to receive the second pulse signal IN1, and the output terminal of one fourth flip-flop outputs the second conversion code TDCCode1.<N:0> The third sub-signal. In the third conversion module 223, the clock terminal of the third flip-flop and the input terminals of all the fourth flip-flops are used to receive the third pulse signal IN2, and the output terminal of one of the fourth flip-flops outputs the third conversion code TDCCode2.<N:0> One sub-signal. In the fourth conversion module 224, the clock terminal of the third flip-flop and the input terminals of all fourth flip-flops are used to receive the fourth pulse signal IN3, and the output terminal of one fourth flip-flop outputs the fourth conversion code TDCCode3.<N:0> One of the sub-signals.

[0127] In this way, the phase difference between the first target clock signal DLL0 and the second synchronization clock signal DL90 is converted to obtain the first conversion code TDCCode0.<N:0> The phase difference between the inverted signals of the second synchronization clock signal DL90 and the first target clock signal DLL0 is converted to obtain the second conversion code TDCCode1.<N:0> The phase difference between the third target clock signal DLL180 and the fourth synchronization clock signal DL270 is converted to obtain the third conversion code TDCCode2.<N:0> The phase difference between the fourth synchronization clock signal DL270 and the inverted signal of the third target clock signal is converted to obtain the fourth conversion code TDCCode3.<N:0> .

[0128] It should be noted that the structures of the first delay chain 142, the second delay chain 172, and the third delay chain 309 are identical. That is, the first delay chain 142 includes multiple first delay units arranged in series, and the second delay chain 172 includes multiple second delay units; the first delay units in the first delay chain 142, the second delay units in the second delay chain 172, and the third delay units in the third delay chain 309 are identical.

[0129] In some embodiments, for the first delay chain 142 and the second delay chain 172, the first control code DLLCode1<N:0> The i-th sub-signal is used to control the i-th first delay unit to be in an on or off state, and the second control code DLLCode2<N:0> The i-th sub-signal is used to control whether the i-th second delay unit is in the on or off state;

[0130] The first delay chain 142 is specifically configured to use the first delay unit in the enabled state to delay the second synchronous clock signal DL90 and output the second target clock signal DLL90.

[0131] The second delay chain 172 is specifically configured to delay the fourth synchronous clock signal DL270 by using the second delay unit in the enabled state, and output the fourth target clock signal DLL270.

[0132] In this way, the delay value of the delay chain can be adjusted by reducing or increasing the number of delayed units, and the output target clock signal can be processed earlier or later.

[0133] Alternatively, in some other embodiments, the first control code DLLCode1<N:0> The first a-position sub-signal is in the first state, and the first control code is DLLCode1.<N:0> The last (Aa) bit signal is the second state; the second control code DLLCode2<N:0> The first b-bit sub-signal is in the first state, and the second control code is DLLCode2.<N:0> The last (Bb) sub-signals represent the second state; A, B, a, and b are all positive integers, with a less than or equal to A, where A refers to the total number of bits in the sub-signals of the first control code, and b less than or equal to B, where B refers to the total number of bits in the sub-signals of the second control code. Here, A = B = N + 1.

[0134] The first delay chain 142 is specifically configured to use the first to the ath first delay units to delay the second synchronous clock signal DL90, and to determine the output signal of the ath first delay unit as the second target clock signal DLL90;

[0135] The second delay chain 172 is specifically configured to use the first to the bth second delay units to delay the fourth synchronous clock signal DL270, and to determine the output signal of the bth second delay unit as the fourth target clock signal DLL270.

[0136] Taking the first delay chain 142 as an example, assuming the first control code DLLCode1<N:0> =110000, at this time the output of the second first delay unit outputs the second target clock signal DLL90, that is, the second target clock signal DLL90 will not pass through the last 4 second delay units; assuming DLLCode1<N:0> =111100, at this time the output terminal of the fourth second delay unit outputs the second target clock signal DLL90, that is, the second target clock signal DLL90 will not pass through the last two second delay units.

[0137] Thus, since the delay phase-locked loop 10 introduces the first adjustment module 14 and the second adjustment module 17, it can improve the phase deviation caused by delay line mismatch or preprocessing.

[0138] In some embodiments, such as Figure 9 As shown, the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180, and the fourth target clock signal DLL270 are used for data sampling processing after passing through their respective signal transmission paths. Specifically, after passing through their respective signal transmission paths, the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180, and the fourth target clock signal DLL270 reach the data selection module (Mux). The data selection module uses the four-phase target clock signals to sample and select the output of the data signal DQ to obtain the target data signal. Here, a certain number of buffers can be set on each signal transmission path to increase the driving capability of the signal, and the number of buffers on all four signal transmission paths is the same.

[0139] like Figure 9 As shown, the delay phase-locked loop 10 also includes:

[0140] The feedback module (including the fifth adjustable delay line 411 and the replication delay module 412) is configured to receive the first clock signal clk0 and output an analog clock signal, and the analog clock signal is used to simulate the waveform of the first target clock signal DLL0 after passing through the signal transmission path.

[0141] The detection module 42 is configured to receive the first clock signal clk0 and the analog clock signal, perform phase detection on the first clock signal clk0 and the analog clock signal, and obtain a phase detection signal.

[0142] The parameter tuning module 43 is configured to receive the phase detection signal and output the delay line control signal based on the phase detection signal;

[0143] The first adjustable delay line 12 is specifically configured to receive a delay line control signal, adjust and transmit the first clock signal clk0 based on the delay line control signal, and output the first target clock signal DLL0.

[0144] The second adjustable delay line 13 is specifically configured to receive the delay line control signal, adjust and transmit the second clock signal clk90 based on the delay line control signal, and output the second synchronous clock signal DL0.

[0145] Similarly, the third adjustable delay line 15 is specifically configured to receive a delay line control signal, adjust and transmit the third clock signal clk180 based on the delay line control signal, and output the third target clock signal DLL180; the fourth adjustable delay line 16 is specifically configured to receive a delay line control signal, adjust and transmit the fourth clock signal clk270 based on the delay line control signal, and output the fourth synchronous clock signal DL270.

[0146] It should be noted that the waveform of the first target clock signal DLL0 upon reaching the data selection module must be consistent with the waveform of the first clock signal clk0. Therefore, a feedback adjustment mechanism is required. Specifically, after passing through the feedback module 151, the first clock signal clk0 generates an analog clock signal. Since the analog clock signal can simulate the waveform of the first target clock signal DLL0 upon reaching the data selection module, the delay line control signal is adjusted based on the difference between the analog clock signal and the first clock signal clk0 to adjust the operating parameters of the first adjustable delay line.

[0147] Furthermore, the waveform of the analog clock signal is not exactly the same as the waveform of the first target clock signal DLL0 after passing through the signal transmission path. In actual working scenarios, after the memory enters a stable operating state, the analog clock signal can be frequency divided to reduce the update frequency of the delay line adjustment signal, avoid signal jitter caused by signal glitches, and reduce power consumption.

[0148] In one specific embodiment, such as Figure 9 As shown, the feedback module includes:

[0149] The fifth adjustable delay line 411 is configured to receive the first clock signal clk0 and the delay line control signal, adjust and transmit the first clock signal clk0 based on the delay line control signal, and output a copied clock signal; wherein, the fifth adjustable delay line has the same structure as the first adjustable delay line, and the copied clock signal is used to simulate the waveform of the first target clock signal DLL0;

[0150] The replication delay module 412 is configured to receive the replication clock signal, perform delay processing on the replication clock signal, and output an analog clock signal; wherein, the replication delay module is used to simulate the delay of the signal transmission path.

[0151] In this way, the fifth adjustable delay line 411 is used to replicate the processing of the first adjustable delay line, and the replication delay module 412 is used at least to replicate the delay when the first target clock signal DLL0 is transmitted through the signal transmission path, thereby forming a closed loop of feedback adjustment.

[0152] In summary, for delay-locked loops (PLLs), to reduce signal deviations caused by layout mismatch, process errors, and voltage / temperature (PVT) factors, the rising edge information of the first, second, third, and fourth target clock signals is first logically processed to form first pulse signals IN0 to fourth pulse signals IN3. These first to fourth pulse signals IN0 and IN3 are then input to four independent time-to-digital converter modules (i.e., the first to fourth conversion modules) to obtain the corresponding first conversion code TDCcode0.<N:0> ~Fourth conversion code TDCcode3<N:0> Then, the second conversion code TDCcode1<N:0> Subtract the first conversion code TDCcode0<N:0> To obtain the first control code DLLCode1<N:0> The fourth conversion code TDCcode3<N:0> Subtract the third conversion code TDCcode2<N:0> To obtain the second control code DLLCode2<N:0> Finally, using the first control code DLLCode1<N:0> The delay of the second synchronization clock signal is adjusted using the second control code DLLCode2.<N:0> The fourth synchronous clock signal is delayed and adjusted to obtain a four-phase target clock signal with a smaller phase deviation, thereby improving the data sampling effect.

[0153] In another embodiment of this disclosure, see Figure 12 This illustrates a schematic diagram of a clock synchronization circuit 50 provided in an embodiment of the present disclosure. Figure 12 As shown, the clock synchronization circuit 50 includes the aforementioned delay phase-locked loop 10 and data selection module 51, and a signal transmission path is provided between the delay phase-locked loop 10 and the data selection module 51; wherein,

[0154] The delay phase-locked loop 10 is configured to receive an initial clock signal and output a first target clock signal DLL0, a second target clock signal DLL90, a third target clock signal DLL180, and a fourth target clock signal DLL270; wherein the phases of the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180, and the fourth target clock signal DLL270 are successively 90 degrees apart.

[0155] The data selection module 51 is configured to receive the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180, and the fourth target clock signal DLL270 respectively via the corresponding signal transmission paths, and to sample and select the data signal DQ using the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180, and the fourth target clock signal DLL270 to obtain the target data signal.

[0156] In particular, such as Figure 12 As shown, for all signal transmission paths, the same number of buffers are set for each signal transmission path to achieve signal delay and drive enhancement. Figure 8 The example shown uses two buffers for each signal transmission path, but in actual applications, there may be more or fewer.

[0157] It should be noted that the structure of the delay phase-locked loop 10 is described above. It has a first adjustment module on the output side of the second adjustable delay line and a second adjustment module on the output side of the fourth adjustable delay line. The first adjustment module is used to adjust the delay of the signal output by the second adjustable delay line, and the second adjustment module is used to adjust the delay of the signal output by the fourth adjustable delay line. Therefore, it can ensure that the phase difference of the final four-phase clock signal is the preset value, improve the phase deviation caused by delay line mismatch or preprocessing, and improve the data sampling effect.

[0158] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 13 This illustrates a schematic diagram of the composition structure of a memory 60 provided in an embodiment of this disclosure. For example... Figure 13 As shown, the memory 60 includes at least the aforementioned delay phase-locked loop 10.

[0159] In some embodiments, the memory conforms to at least one of the following specifications: DDR3, DDR4, DDR5, DDR6, LPDDR3, LPDDR4, LPDDR5, LPDDR6.

[0160] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.< / n> < / n>

Claims

1. A delay phase-locked loop, characterized in that, The delay phase-locked loop includes: The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first adjustable delay line is configured to receive the first clock signal, adjust and transmit the first clock signal, and output the first target clock signal. The second adjustable delay line is configured to receive the second clock signal, adjust and transmit the second clock signal, and output the second synchronous clock signal. The first adjustment module is configured to receive the first target clock signal and the second synchronous clock signal, perform delay adjustment on the second synchronous clock signal based on the first target clock signal, and output the second target clock signal. The phase difference between the first target clock signal and the second target clock signal is a preset value.

2. The delay phase-locked loop according to claim 1, characterized in that, The preprocessing module includes: The receiving module is configured to receive the initial clock signal and output a clock signal to be processed; wherein the clock period of the clock signal to be processed is the same as the clock period of the initial clock signal. The phase-splitting module is configured to receive the clock signal to be processed, perform frequency division and phase-splitting processing on the clock signal to be processed, and output the first clock signal and the second clock signal. Wherein, the first clock signal and the second clock signal have the same clock period, and the clock period of the first clock signal is twice the clock period of the initial clock signal.

3. The delay phase-locked loop according to claim 2, characterized in that, The first adjustment module includes: The first control module is configured to receive the first target clock signal and the second synchronization clock signal, and output a first control code based on the phase difference between the first target clock signal and the second synchronization clock signal. The first delay chain includes multiple first delay units configured to receive the first control code and the second synchronization clock signal; based on the first control code, the multiple first delay units are used to adjust the delay of the second synchronization clock signal to output the second target clock signal.

4. The delay phase-locked loop according to claim 3, characterized in that, The first control module includes: The first pulse processing module is configured to receive the first target clock signal and the second synchronization clock signal, and output a first pulse signal and a second pulse signal; wherein the first pulse signal and the second pulse signal each include one pulse, and the pulse width of the first pulse signal indicates the phase difference between the first target clock signal and the second synchronization clock signal, and the pulse width of the second pulse signal indicates the phase difference between the inverted signals of the second synchronization clock signal and the first target clock signal; A first-time digital conversion module is configured to receive a first pulse signal and a second pulse signal; convert the first pulse signal and output a first conversion code; and convert the second pulse signal and output a second conversion code; wherein the first conversion code is used to characterize the width of the first pulse signal, and the second conversion code is used to characterize the width of the second pulse signal. The first logic module is configured to receive the first conversion code and the second conversion code, perform a subtraction operation on the second conversion code and the first conversion code, and output the first control code.

5. The delay phase-locked loop according to claim 4, characterized in that, The first pulse processing module includes: The first pulse module is configured to receive the first target clock signal and the second synchronization clock signal, perform an XOR operation on the first target clock signal and the second synchronization clock signal to obtain a first detection signal, perform pulse truncation and widening operation on the first detection signal to obtain a first intermediate signal, perform an AND operation on the first intermediate signal and the first detection signal, and output the first pulse signal; wherein, the first detection signal includes multiple pulses, and the pulse width of the first detection signal indicates the phase difference between the first target clock signal and the second synchronization clock signal, and the first intermediate signal includes one pulse, the pulse width of the first intermediate signal being greater than the pulse width of the first detection signal; The second pulse module is configured to receive the inverted signal of the first target clock signal and the second synchronous clock signal, perform XOR processing on the inverted signal of the first target clock signal and the second synchronous clock signal to obtain a second detection signal, perform pulse truncation and widening processing on the second detection signal to obtain a second intermediate signal, perform AND processing on the second intermediate signal and the second detection signal, and output the second pulse signal; wherein, the second detection signal includes multiple pulses, and the pulse width of the second detection signal indicates the phase difference between the inverted signal of the first target clock signal and the second synchronous clock signal, and the second intermediate signal includes one pulse, the pulse width of the second intermediate signal being greater than the pulse width of the second detection signal.

6. The delay phase-locked loop according to claim 5, characterized in that, The first time conversion module includes: The first conversion module is configured to receive a first pulse signal, perform sampling and delay processing on the first pulse signal to obtain multiple first sampling clock signals, perform sampling processing on the first pulse signal using the multiple first sampling clock signals, and output the first conversion code. The second conversion module is configured to receive a second pulse signal, perform sampling and delay processing on the second pulse signal to obtain multiple second sampling clock signals, perform sampling processing on the second pulse signal using the multiple second sampling clock signals, and output the second conversion code.

7. The delay phase-locked loop according to claim 6, characterized in that, The preprocessing module is further configured to preprocess the initial clock signal and output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The delay phase-locked loop also includes: The third adjustable delay line is configured to receive the third clock signal, adjust and transmit the third clock signal, and output a third target clock signal; wherein the phase difference between the first target clock signal and the third target clock signal is 180 degrees. The fourth adjustable delay line is configured to receive the fourth clock signal, adjust and transmit the fourth clock signal, and output the fourth synchronous clock signal; The second adjustment module is configured to receive the third target clock signal and the fourth synchronous clock signal, perform delay adjustment on the fourth synchronous clock signal based on the third target clock signal, and output the fourth target clock signal. The adjacent phase difference between the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal is 90 degrees.

8. The delay phase-locked loop according to claim 7, characterized in that, The phase-splitting module is further configured to perform frequency division and phase-splitting processing on the clock signal to be processed, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same clock period, and the clock period of the first clock signal is twice the clock period of the initial clock signal.

9. The delay phase-locked loop according to claim 8, characterized in that, The second adjustment module includes: The second control module is configured to receive the third target clock signal and the fourth synchronization clock signal, and output a second control code based on the phase difference between the third target clock signal and the fourth synchronization clock signal; The second delay chain includes multiple second delay units, configured to receive the second control code and the fourth synchronization clock signal, and based on the second control code, use the multiple second delay units to perform delay adjustment on the fourth synchronization clock signal to output the fourth target clock signal.

10. The delay phase-locked loop according to claim 9, characterized in that, The second control module includes: The second pulse processing module is configured to receive the third target clock signal and the fourth synchronization clock signal, and output a third pulse signal and a fourth pulse signal; wherein the third pulse signal and the fourth pulse signal each include one pulse, and the pulse width of the third pulse signal indicates the phase difference between the third target clock signal and the fourth synchronization clock signal, and the pulse width of the fourth pulse signal indicates the phase difference between the inverted signals of the fourth synchronization clock signal and the third target clock signal; The second time-to-digital conversion module is configured to receive the third pulse signal and the third pulse signal; convert the third pulse signal and output a third conversion code; and convert the fourth pulse signal and output a fourth conversion code; wherein the third conversion code is used to characterize the width of the third pulse signal, and the fourth conversion code is used to characterize the width of the fourth pulse signal. The second logic module is configured to receive the third conversion code and the fourth conversion code, perform a subtraction operation on the fourth conversion code and the third conversion code, and output the second control code.

11. The delay phase-locked loop according to claim 10, characterized in that, The second pulse processing module includes: The third pulse module is configured to receive the third target clock signal and the fourth synchronization clock signal, perform an XOR operation on the third target clock signal and the fourth synchronization clock signal to obtain a third detection signal, perform pulse truncation and widening processing on the third detection signal to obtain a third intermediate signal, perform an AND operation on the third intermediate signal and the third detection signal, and output the third pulse signal; wherein, the third detection signal includes multiple pulses, and the pulse width of the third detection signal indicates the phase difference between the third target clock signal and the fourth synchronization clock signal, and the third intermediate signal includes one pulse, and the pulse width of the third intermediate signal is greater than the pulse width of the third detection signal; The fourth pulse module is configured to receive the inverted signal of the third target clock signal and the fourth synchronization clock signal, perform XOR processing on the inverted signal of the third target clock signal and the fourth synchronization clock signal to obtain a fourth detection signal, perform pulse truncation and widening processing on the fourth detection signal to obtain a fourth intermediate signal, perform AND processing on the fourth intermediate signal and the fourth detection signal, and output the fourth pulse signal; wherein, the fourth detection signal includes multiple pulses, and the pulse width of the fourth detection signal indicates the phase difference between the inverted signal of the third target clock signal and the fourth synchronization clock signal, and the fourth intermediate signal includes one pulse, and the pulse width of the fourth intermediate signal is greater than the pulse width of the fourth detection signal.

12. The delay phase-locked loop according to claim 11, characterized in that, The second time conversion module includes: The third conversion module is configured to receive a third pulse signal, sample and delay the third pulse signal to obtain multiple third sampling clock signals, use the multiple third sampling clock signals to sample the third pulse signal, and output the third conversion code. The fourth conversion module is configured to receive a fourth pulse signal, sample and delay the fourth pulse signal to obtain multiple fourth sampling clock signals, use the multiple fourth sampling clock signals to sample the fourth pulse signal, and output the fourth conversion code.

13. The delay phase-locked loop according to claim 11, characterized in that, The first pulse module includes: a first flip-flop, a second flip-flop, a first NOT gate, a fourth delay unit, a first AND gate, a first XOR gate, and a second AND gate; the second pulse module, the third pulse module, and the fourth pulse module have the same structure as the first pulse module. In the first pulse module, the first input of the first XOR gate receives the first target clock signal, the second input of the first XOR gate receives the second synchronization clock signal, and the output of the first XOR gate is used to output the first detection signal; the input of the first flip-flop receives the first power supply signal, and the clock terminal of the first flip-flop is connected to the output of the first XOR gate; the input of the first NOT gate is connected to the output of the first XOR gate, the input of the second flip-flop receives the ground signal, and the output of the second flip-flop is connected to the output of the first NOT gate; the input of the fourth delay unit is connected to the output of the second flip-flop, the first input of the first AND gate is connected to the output of the first flip-flop, the second input of the first AND gate is connected to the output of the fourth delay unit, and the output of the first AND gate is used to output the first intermediate signal; the first input of the second AND gate is connected to the output of the first AND gate, the second input of the second AND gate is connected to the output of the first XOR gate, and the output of the second AND gate is used to output the first pulse signal.

14. The delay phase-locked loop according to claim 12, characterized in that, The first conversion code, the second conversion code, the third conversion code, and the fourth conversion code each include multiple sub-signals; The first conversion module includes a third flip-flop, a third delay chain, and multiple fourth flip-flops, and the second conversion module, the third conversion module, and the fourth conversion module all have the same structure as the first conversion module; wherein, In the first conversion module, the input terminal of the third flip-flop receives the second power supply signal, the clock terminal of the third flip-flop receives the first pulse signal, and the output terminal of the third flip-flop is connected to the input terminal of the third delay chain; the input terminals of all fourth flip-flops are used to receive the first pulse signal; the third delay chain includes multiple third delay units arranged in series, the clock terminal of one fourth flip-flop is correspondingly connected to the output terminal of one third delay unit, and the output terminal of one fourth flip-flop outputs one bit of the first conversion code sub-signal.

15. The delay phase-locked loop according to claim 14, characterized in that, The first delay chain includes a plurality of first delay units arranged in series, and the second delay chain includes a plurality of second delay units; The first delay unit in the first delay chain, the second delay unit in the second delay chain, and the third delay unit in the third delay chain are identical.

16. The delay phase-locked loop according to claim 15, characterized in that, The i-th sub-signal of the first control code is used to control the i-th first delay unit to be in an on or off state, and the i-th sub-signal of the second control code is used to control the i-th second delay unit to be in an on or off state; The first delay chain is specifically configured to use the first delay unit in the enabled state to delay the second synchronization clock signal and output the second target clock signal; The second delay chain is specifically configured to delay the fourth synchronization clock signal using the second delay unit in the enabled state, and output the fourth target clock signal.

17. The delay phase-locked loop according to claim 16, characterized in that, The first 'a' sub-signals of the first control code are in the first state, and the last (Aa) sub-signals of the first control code are in the second state; the first 'b' sub-signals of the second control code are in the first state, and the last (Bb) sub-signals of the second control code are in the second state; A, B, a, and b are all positive integers, and a is less than or equal to A, where A refers to the total number of bits in the sub-signals of the first control code, and b is less than or equal to B, where B refers to the total number of bits in the sub-signals of the second control code; The first delay chain is specifically configured to use the first to the ath first delay units to delay the second synchronization clock signal, and to determine the output signal of the ath first delay unit as the second target clock signal; The second delay chain is specifically configured to use the first to the bth second delay units to delay the fourth synchronous clock signal, and to determine the output signal of the bth second delay unit as the fourth target clock signal.

18. The delay phase-locked loop according to any one of claims 7-17, characterized in that, The first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are used for data sampling processing after passing through their respective signal transmission paths; The delay phase-locked loop also includes: The feedback module is configured to receive the first clock signal and output an analog clock signal, wherein the analog clock signal is used to simulate the waveform of the first target clock signal after passing through the signal transmission path; The detection module is configured to receive the first clock signal and the analog clock signal, perform phase detection on the first clock signal and the analog clock signal, and obtain a phase detection signal; The parameter tuning module is configured to receive the phase detection signal and output a delay line control signal based on the phase detection signal; The first adjustable delay line is specifically configured to receive the delay line control signal, adjust and transmit the first clock signal based on the delay line control signal, and output the first target clock signal; The second adjustable delay line is specifically configured to receive the delay line control signal, adjust and transmit the second clock signal based on the delay line control signal, and output the second synchronous clock signal.

19. The delay phase-locked loop according to claim 18, characterized in that, The feedback module includes: The fifth adjustable delay line is configured to receive the first clock signal and the delay line control signal, adjust and transmit the first clock signal based on the delay line control signal, and output a replicated clock signal; wherein, the fifth adjustable delay line has the same structure as the first adjustable delay line, and the replicated clock signal is used to simulate the waveform of the first target clock signal; The replication delay module is configured to receive the replication clock signal, perform delay processing on the replication clock signal, and output an analog clock signal; wherein, the replication delay module is used to simulate the delay of the signal transmission path.

20. A memory, characterized in that, The memory includes a delay phase-locked loop as described in any one of claims 1-19.

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