Super junction device and manufacturing method thereof

Abstract

The invention provides a super junction device and a manufacturing method thereof. The super junction device comprises a gallium oxide substrate; the N-type epitaxial layer is positioned on the surface of the gallium oxide substrate, and a high-resistance layer is formed in the surface of one side, far away from the gallium oxide substrate, of the N-type epitaxial layer; the multi-stage grooves are located in the N-type epitaxial layer, each multi-stage groove comprises N sub-grooves arranged in the first direction, the sizes of the N sub-grooves in the second direction are not completely the same, N is not smaller than 3, the first direction is perpendicular to the plane where the gallium oxide substrate is located and points to the gallium oxide substrate, the second direction is perpendicular to the plane where the gallium oxide substrate is located, and the third direction is perpendicular to the plane where the gallium oxide substrate is located. The second direction is perpendicular to the first direction; the first P-type oxide layer covers the surface of the multi-stage groove, and the surface of the multi-stage groove comprises the bottom of the multi-stage groove and the side wall of the multi-stage groove. The super junction device is high in voltage resistance and low in process difficulty.

Description

Technical Field

[0001] The present application relates to the technical field of power devices, and in particular to a super junction device and a method for manufacturing the same. Background Art

[0002] In recent years, the application scope of power devices has become more and more extensive, from mobile phones and fast charging of new energy vehicles to photovoltaic power generation and high-voltage power grid transmission, gradually penetrating into all aspects of life, bringing great convenience to our daily life. Therefore, power devices will play an important role in the future to improve people's quality of life. However, the voltage resistance performance of existing power devices needs to be improved. Summary of the invention

[0003] In view of this, the present application provides a super junction device and a method for manufacturing the same, the scheme is as follows:

[0004] A super junction device, comprising:

[0005] Gallium oxide substrate;

[0006] An N-type epitaxial layer located on the surface of the gallium oxide substrate, wherein a high resistance layer is formed in a surface of the N-type epitaxial layer away from the gallium oxide substrate;

[0007] A plurality of multi-level trenches located in the N-type epitaxial layer, the multi-level trenches comprising N sub-grooves arranged along a first direction, and the sizes of the N sub-grooves in a second direction are not completely the same, wherein N is not less than 3, the first direction is perpendicular to the plane where the gallium oxide substrate is located and points to the gallium oxide substrate, and the second direction is perpendicular to the first direction;

[0008] A first P-type oxide layer covers the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewall of the multi-level trench.

[0009] Optionally, the N-type epitaxial layer includes a plurality of N-type epitaxial units, a portion of the N-type epitaxial layer located between adjacent multi-level trenches is an N-type epitaxial unit, and a first P-type oxide layer on a sidewall of at least one sub-trench in the multi-level trench and an N-type epitaxial unit at a corresponding position thereof satisfy a charge balance condition, and the charge balance condition is Among them, W NiO Characterizes the width of the first P-type oxide layer on the sidewall of a sub-trench in a multi-level trench, N NiO Characterizes the concentration of the first P-type oxide layer on the sidewall of the sub-trench, Characterizes the width of the epitaxial unit at the corresponding position of this sub-trench, Characterizes the concentration of the epitaxial unit at the corresponding position of this sub-trench.

[0010] Optionally, dimensions of the N sub-grooves in the second direction gradually decrease along the first direction.

[0011] Optionally, in the first direction, sizes of the N sub-grooves in the second direction vary uniformly along the first direction.

[0012] Optionally, the multi-level trenches penetrate the N-type epitaxial layer or the multi-level trenches do not penetrate the N-type epitaxial layer.

[0013] Optionally, in the first direction, the shape of the top view of the multi-level groove is a strip, a circle, a rectangle or a hexagon.

[0014] Optionally, the super junction device includes a cell region, a transition region and a terminal region, the terminal region is located at the periphery of the cell region, and the transition region is located between the cell region and the terminal region.

[0015] Optionally, it also includes: a second P-type oxide layer covering the surface of a portion of the first P-type oxide layer located in the terminal region of the super junction device.

[0016] Optionally, the second P-type oxide layer also extends to cover a portion of the surface of the transition region.

[0017] Optionally, the plurality of multi-level grooves include a first multi-level groove located in the cell region and a second multi-level groove located in the terminal region, and a first P-type oxide layer and a second P-type oxide layer located on the surface of the second multi-level groove expose at least a portion of the bottom of the second multi-level groove.

[0018] A method for manufacturing a super junction device, comprising:

[0019] Growing an N-type epitaxial layer on a gallium oxide substrate, and forming a high resistance layer in a surface of the N-type epitaxial layer away from the gallium oxide substrate;

[0020] A plurality of multi-level trenches are formed in the N-type epitaxial layer, wherein the multi-level trenches include N sub-grooves arranged along a first direction, and the sizes of the N sub-grooves in a second direction are not completely the same, wherein N is not less than 3, the first direction is perpendicular to the plane where the gallium oxide substrate is located and points to the gallium oxide substrate, and the second direction is perpendicular to the first direction;

[0021] A first P-type oxide layer covering the surface of the multi-level groove is formed on the surface of the multi-level groove, wherein the surface of the multi-level groove includes the bottom of the multi-level groove and the sidewall of the multi-level groove.

[0022] Optionally, the super junction device includes a cell region, a transition region and a terminal region, the terminal region is located outside the cell region, and the transition region is located between the cell region and the terminal region. The method also includes: forming a second P-type oxide layer on the surface of the portion of the first P-type oxide layer located in the terminal region of the super junction device.

[0023] Optionally, the second P-type oxide layer also extends to cover a portion of the surface of the transition region.

[0024] Optionally, the plurality of multi-level grooves include a first multi-level groove located in the cell region and a second multi-level groove located in the terminal region, and the method further includes: removing at least a portion of the first P-type oxide layer and the second P-type oxide layer located at the bottom of the second multi-level groove.

[0025] Optionally, the first P-type oxide layer is a NiO layer, and forming the first P-type oxide layer covering the multi-level groove surface on the multi-level groove surface includes: first filling metal nickel into the multi-level groove, and then oxidizing the metal nickel in the multi-level groove in an oxygen atmosphere to form the first P-type oxide layer covering the multi-level groove surface on the multi-level groove surface.

[0026] In the super junction device provided in the embodiment of the present application, the gallium oxide substrate is an N-type gallium oxide substrate, and the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, thereby improving the voltage resistance performance of the super junction device.

[0027] In the super junction device provided in the embodiment of the present application, the N-type epitaxial layer 20 has a plurality of multi-level grooves, the multi-level grooves include N sub-grooves arranged along a first direction X, and the sizes of the N sub-grooves in a second direction Y are not completely the same, wherein N is not less than 3, so that when the thickness and concentration of the first P-type oxide layer located on the surface of the multi-level grooves change, the probability that at least part of the multi-level grooves and the N-type epitaxial layer meet the charge balance condition can be increased through a plurality of sub-grooves of unequal sizes, thereby reducing the probability that the reverse breakdown voltage of the super junction device will be greatly reduced due to a slight change in the thickness and concentration of the first P-type oxide layer, thereby improving the reverse breakdown voltage of the super junction device.

[0028] In addition, in the super junction device provided in the embodiment of the present application, since the thickness and concentration of the first P-type oxide layer vary slightly, a plurality of sub-grooves of different sizes can be used so that at least part of the multi-level grooves and the N-type epitaxial layer meet the charge balance condition. Therefore, during the manufacturing process of the super junction device, the process control requirements for the concentration of the first P-type oxide layer when it is formed are relatively low, thereby improving the doping concentration window of the first P-type oxide layer and reducing the process difficulty of the super junction device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0030] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0031] Figure 1 A schematic diagram of the structure of a single-stage trench gallium oxide superjunction diode formed by sputtering a P-type NiO layer;

[0032] Figure 2 A schematic diagram of the structure of a super junction device provided by one embodiment of the present application;

[0033] Figure 3 A schematic diagram of the structure of a super junction device provided by another embodiment of the present application;

[0034] Figure 4 A schematic diagram of a top view of a multi-level trench in a super junction device provided by an embodiment of the present application;

[0035] Figure 5 A schematic diagram of a top view of a multi-level trench in a super junction device provided by another embodiment of the present application;

[0036] Figure 6 A schematic diagram of a top view of a multi-level trench in a super junction device provided in yet another embodiment of the present application;

[0037] Figure 7 A schematic diagram of a top view of a multi-level trench in a super junction device provided by another embodiment of the present application;

[0038] Figure 8 Schematic diagram of the voltage withstand capability of super junction devices;

[0039] Figure 9-Figure 26 A schematic diagram of some structures involved in the manufacturing process of a method for manufacturing a super junction device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0041] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0042] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0043] As described in the background technology section, the voltage resistance performance of existing power devices needs to be improved.

[0044] It should be noted that in the application of power devices, the Baliga's figure-of-merit BFOM is an indicator used to indicate the applicability of semiconductor materials in power electronics, which is expressed as: BFOM = εμE3, ε is the dielectric constant, μ is the mobility, E is the breakdown field strength of the semiconductor, and the BFOM value is roughly positively correlated with the sixth power of the bandgap width Eg. Therefore, a larger bandgap width means that wide-bandgap semiconductors have lower power loss and higher conversion efficiency in the application of power devices, thereby achieving more excellent and ideal power electronics applications.

[0045] Among wide bandgap semiconductor materials, Ga2O3 has a bandgap width of 4.8eV, an ideal breakdown electric field strength of 8MV / cm and a BFOM value of up to 3400, which is about 4 times that of GaN and 10 times that of SiC. It is an ideal material for making high-voltage devices.

[0046] However, there is no report on the successful realization of p-type doping in Ga2O3. This makes it impossible to form a homogeneous P-type doped region to construct a superjunction device through epitaxial backfill or ion implantation like Si and SiC to alleviate the contradiction between low conduction loss and high withstand voltage of the device.

[0047] Specifically, the reasons why Ga2O3 cannot form a homogeneous P-type doped region through epitaxial backfill or ion implantation like Si and SiC include: it is difficult to find acceptor impurities with small activation energy; theoretical calculations show that the maximum dispersion of the valence band of Ga2O3 is small and the effective mass is very large, resulting in almost a local distribution of small μ for free holes; theoretical predictions have been made specifically for Ga2O3 that due to local lattice distortion, the local self-capture energy of free holes in the volume is very large, which leads to the formation of small poles, which undoubtedly prohibits the conduction of effective holes.

[0048] In view of this, researchers began to invest in heterogeneous PN junctions. The P-type materials currently studied in heterogeneous PN junctions include NiO, Cu2O, SnO, etc. Among them, NiO has become the mainstream choice with its large bandgap width of 3.6-4.0eV and controllable P-type doping. In 2020, Lu et al. reported a heterojunction constructed of NiO film and β-Ga2O3 prepared by sputtering, realizing the first β-Ga2O3 bipolar device with a kilovolt breakdown voltage. Subsequently, many researchers have made significant progress in improving the performance of NiO / β-Ga2O3 heterogeneous pn junctions. In addition, the NiO / β-Ga2O3 heterojunction structure has also been widely used in other device structures, such as junction barrier Schottky diodes (JBS), junction field effect transistors (JFETs), and edge termination (ET) structures.

[0049] It should be noted that ordinary power devices can directly sputter NiO on the surface of β-Ga2O3 to form a heterojunction, which is similar to thin film deposition, and the direction of its PN junction is vertical; while superjunction devices need to form a PN junction in the horizontal direction. In order to overcome the difficulty in manufacturing superjunction devices caused by the lack of effective P-type doping in gallium oxide, the inventors have found that grooves can be dug in the gallium oxide epitaxial layer and NiO film can be sputtered in the grooves to form a charge balance area, thereby forming a larger breakdown voltage and lower on-resistance. Figure 1 As shown, Figure 1 The schematic diagram of the structure of a single-stage trench gallium oxide super junction diode formed by sputtering a P-type NiO layer 01 is shown.

[0050] but, Figure 1The structure shown has a problem of relatively high difficulty in manufacturing process. This is because during the manufacturing process, on the one hand, the P-type NiO layer 01 needs to be uniformly sputtered on the side wall of the groove 02 to form a good coverage, and at the same time, the concentration of the P-type nickel oxide layer 01 needs to be accurately controlled so that it can just exhaust the n-type Ga2O3 on both sides. Both processes are difficult to achieve in relatively deep grooves. A slight change in the thickness and concentration of the P-type NiO layer on the side wall of the groove will greatly reduce the reverse breakdown voltage of the power device. On the other hand, the terminal area of ​​the power device also needs to adopt a high-efficiency junction terminal structure to match the superjunction structure of the cell area, thereby achieving the withstand voltage of the entire device. During the specific production, it is necessary to etch a relatively wide groove in the terminal area, and then remove the NiO layer on the other side and bottom of the groove to maintain the charge balance with the cell area. However, this method will make the metal on the NiO layer (i.e., the anode) particularly difficult to make. The Schottky metal (i.e., the anode) needs to cover no more than the side wall of the NiO layer in the terminal area, and at the same time, it needs to be electrically connected to the NiO layer in the terminal area. The thickness of the sidewall NiO layer is often in the range of 100nm-300nm, which places extremely high requirements on the metal covering process and is not suitable for mass production feasibility.

[0051] In view of this, an embodiment of the present application provides a super junction device and a method for manufacturing the same, so as to improve the voltage resistance performance of the super junction device and reduce the process difficulty of the super junction device.

[0052] Specifically, Figure 2 As shown, the super junction device provided in the embodiment of the present application includes:

[0053] Gallium oxide substrate 10;

[0054] An N-type epitaxial layer 20 located on the surface of the gallium oxide substrate 10, wherein a high resistance layer 21 is formed on the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10;

[0055] A plurality of multi-level trenches in the N-type epitaxial layer 20, wherein the multi-level trenches include N sub-trenches arranged along a first direction X, and the sizes of the N sub-trenches in a second direction Y are not completely the same, wherein N is not less than 3, the first direction X is perpendicular to the plane where the gallium oxide substrate 10 is located, and points to the gallium oxide substrate 10, and the second direction Y is perpendicular to the first direction X;

[0056] A first P-type oxide layer 30 covers the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewall of the multi-level trench.

[0057] Optionally, in one embodiment of the present application, the gallium oxide substrate is an N-type gallium oxide substrate, the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, and the high resistance layer is an N-type gallium oxide high resistance layer, but the present application does not limit this and it depends on the specific circumstances.

[0058] In the super junction device provided in the embodiment of the present application, the gallium oxide substrate is an N-type gallium oxide substrate, and the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, thereby improving the voltage resistance performance of the super junction device.

[0059] It should be noted that, in this embodiment, the N-type epitaxial layer includes a plurality of N-type epitaxial units, the portion of the N-type epitaxial layer located between adjacent multi-level trenches is an N-type epitaxial unit, and the first P-type oxide layer at at least one sub-trench in the multi-level trench and the N-type epitaxial unit at its corresponding position satisfy a charge balance condition, and the charge balance condition is Among them, W NiO Characterizes the width (thickness) of the first P-type oxide layer on the sidewall of a sub-trench in a multi-level trench, N NiO Characterizes the concentration of the first P-type oxide layer on the sidewall of the sub-trench, Characterizes the width of the epitaxial unit at the corresponding position of this sub-trench, Characterizes the concentration of the epitaxial unit at the corresponding position of this sub-trench.

[0060] For example, the multi-level grooves include the i-th multi-level grooves and the i+1-th multi-level grooves, the portion of the N-type epitaxial layer located between the i-th multi-level grooves and the i+1-th multi-level grooves is the i-th epitaxial unit, the product of the thickness and concentration of the first P-type oxide layer at the j-th sub-groove in the i-th multi-level groove and the first P-type oxide layer at the j-th sub-groove in the i+1-th multi-level groove is equal to the product of the width and concentration of the portion of the i-th epitaxial unit corresponding to the j-th sub-groove position, wherein i and j are both integers not less than 1.

[0061] It should be noted that when the first P-type oxide layer at a sub-trench in the multi-level trench and the N-type epitaxial unit at its corresponding position meet the charge balance condition, the current conduction area at other sub-trench in the multi-level trench will become larger, and the overall on-resistance of the super junction device will become smaller, thereby making the super junction device have a smaller on-resistance.

[0062] In the super junction device provided in the embodiment of the present application, the N-type epitaxial layer 20 has a plurality of multi-level grooves, the multi-level grooves include N sub-grooves arranged along a first direction X, and the sizes of the N sub-grooves in a second direction Y are not completely the same, wherein N is not less than 3, so that when the thickness and concentration of the first P-type oxide layer located on the surface of the multi-level grooves change, the probability that at least part of the multi-level grooves and the N-type epitaxial layer meet the charge balance condition can be increased through a plurality of sub-grooves of unequal sizes, thereby reducing the probability that the reverse breakdown voltage of the super junction device will be greatly reduced due to a slight change in the thickness and concentration of the first P-type oxide layer, thereby improving the reverse breakdown voltage of the super junction device.

[0063] In addition, in the super junction device provided in the embodiment of the present application, since the thickness and concentration of the first P-type oxide layer vary slightly, a plurality of sub-grooves of different sizes can be used so that at least part of the multi-level grooves and the N-type epitaxial layer meet the charge balance condition. Therefore, during the manufacturing process of the super junction device, the process control requirements for the concentration of the first P-type oxide layer when it is formed are relatively low, thereby improving the doping concentration window of the first P-type oxide layer and reducing the process difficulty of the super junction device.

[0064] Optionally, in one embodiment of the present application, the dimensions of the N sub-grooves in the second direction gradually decrease along the first direction so as to reduce the process difficulty of the multi-level grooves while ensuring that the dimensions of the N sub-grooves in the second direction are not exactly the same, but the present application does not limit this and it depends on the specific circumstances.

[0065] In addition, in this embodiment, the sizes of the N sub-grooves in the second direction gradually decrease along the first direction, and a step surface can be formed at the boundary region of the adjacent sub-grooves in the first direction, such as Figure 2 As shown in the dotted box in the figure, the uniformity of the formation of the portion of the first P-type oxide layer located on the side walls of each sub-groove can be improved, and the first P-type oxide layer can be uniformly formed on the surface of the multi-level groove, so as to reduce the process difficulty while ensuring the uniformity of the portion of the first P-type oxide layer located on the side walls of each sub-groove.

[0066] Specifically, in one embodiment of the present application, the N sub-grooves satisfy at least one of a first condition and a second condition in the second direction, wherein the first condition includes that the maximum value of the size of the N sub-grooves in the second direction is not greater than 5 microns, and the minimum value is not less than 500 nanometers, but the present application does not limit the specific numerical values ​​of the maximum and minimum values ​​of the size of the N sub-grooves in the second direction, which depends on the process capability; the second condition includes that the maximum value of the size of the N sub-grooves in the second direction does not exceed the target size + 1 micron, and the minimum value is not less than the target size - 1 micron, wherein the target size is determined according to the charge balance condition.

[0067] Optionally, in one embodiment of the present application, in the first direction, the sizes of the N sub-grooves in the second direction vary uniformly along the first direction, but the present application does not limit this, and it depends on the specific situation. Specifically, in the first direction, the size difference between adjacent sub-grooves in the same multi-level groove in the second direction can be 0.2 microns, but the present application does not limit this, and it depends on the specific situation.

[0068] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 As shown, the multi-level trenches do not penetrate the N-type epitaxial layer 20 to increase the reverse breakdown voltage of the super junction device; in another embodiment of the present application, as Figure 3 As shown, the multi-level trenches penetrate the N-type epitaxial layer 20 to reduce the overall resistance of the super junction device and reduce the power of the super junction device. The present application does not limit this and it depends on the specific situation.

[0069] It should be noted that when the multi-level trenches penetrate the N-type epitaxial layer, the overall resistance of the super junction device is smaller, the power is smaller, and correspondingly, the reverse breakdown voltage is also smaller; when the multi-level trenches do not penetrate the N-type epitaxial layer, the overall resistance of the super junction device is larger, the power is larger, and correspondingly, the reverse breakdown voltage is also larger.

[0070] Based on any of the above embodiments, in one embodiment of the present application, the first P-type oxide layer is a NiO layer, a Cu2O layer or a SnO layer, and the present application does not limit this, depending on the specific circumstances.

[0071] It should be noted that, in this embodiment, the super junction device includes a cell region and a terminal region. The cell region is a functional region of the super junction device, and the terminal region is located at the periphery of the cell region and is used to disperse the electric field, alleviate the sharp corner discharge of the cell region, alleviate the discharge concentration phenomenon of the cell region, and increase the reverse breakdown voltage of the super junction device.

[0072] Optionally, in one embodiment of the present application, the super junction device also includes a transition zone located between the cell region and the terminal region, that is, the super junction device includes a cell region, a transition zone and a terminal region, the terminal region is located at the periphery of the cell region, and the transition zone is located between the cell region and the terminal region to increase the distance between the cell region and the terminal region, thereby reducing the process difficulty of the super junction device on the basis of ensuring that the subsequently formed second electrode layer can make the cell region and the terminal region electrically connected, and the second electrode layer will not cover the part of the side wall of the multi-level groove of the first P-type oxide layer located in the terminal region.

[0073] Since the transition region is provided between the cell region and the terminal region, the charge balance condition formed by the first P-type oxide layer will be destroyed to a certain extent. Therefore, in one embodiment of the present application, Figure 2 and Figure 3 As shown, the super junction device further includes: a second P-type oxide layer 40 covering the surface of the portion of the first P-type oxide layer 30 located in the terminal region of the super junction device. It should be noted that, in this embodiment, the second P-type oxide layer at at least one sub-groove in the multi-level groove and the N-type epitaxial unit at its corresponding position also meet the charge balance condition, and the charge distribution of the cell region in the super junction device is adjusted to alleviate the reduction of the reverse breakdown voltage caused by the charge imbalance in the cell region.

[0074] Optionally, in one embodiment of the present application, the second P-type oxide layer also extends to cover a portion of the surface of the transition zone, thereby ensuring that the subsequently formed second electrode layer can electrically connect the cell region and the terminal region, and the second electrode layer will not cover the portion of the first P-type oxide layer located on the side walls of the multi-level grooves in the terminal region, so that the second P-type oxide layer can be formed on a portion of the surface of the transition zone, thereby reducing the process difficulty of forming the portion of the second P-type oxide layer located in the terminal region, but the present application does not limit this and it depends on the specific circumstances.

[0075] Specifically, in one embodiment of the present application, the second P-type oxide layer may be a NiO layer, a Cu2O layer or a SnO layer; it should be noted that the materials of the first P-type oxide layer and the second P-type oxide layer may be the same or different, and the present application does not limit this, depending on the specific circumstances.

[0076] It should be noted that, in this embodiment, the multi-level grooves are only located in the cell region and the terminal region, and the transition region is not provided with multi-level grooves. Optionally, based on any of the above embodiments, in an embodiment of the present application, the multiple multi-level grooves include a first multi-level groove located in the cell region and a second multi-level groove located in the terminal region, and the first P-type oxide layer and the second P-type oxide layer located on the surface of the second multi-level groove expose at least a part of the bottom of the second multi-level groove, so that the terminal region of the super junction device has a better charge balance state, so that the terminal region has a higher withstand voltage.

[0077] Optionally, in one embodiment of the present application, the side wall of the second multi-level groove away from the cell area is covered with the second P-type oxide layer to increase the switching speed of the super junction device when used as a power switch and reduce switching losses, but the present application is not limited to this. In other embodiments of the present application, the side wall of the second multi-level groove away from the cell area may not be covered with the second P-type oxide layer, depending on the specific circumstances.

[0078] Based on any of the above embodiments, in one embodiment of the present application, in the first direction, the top view of the multi-level groove is in the shape of a strip (eg Figure 4 As shown), round (as Figure 5 As shown), rectangle (as Figure 6 ) or hexagonal (as shown Figure 7 As shown), or other shapes, the present application does not limit this, depending on the specific circumstances. It should be noted that in the first direction, when the shape of the top view of the multi-level groove is a hexagon, in a plane parallel to the gallium oxide substrate, the top views of the multi-level grooves in adjacent rows are arranged in an interlaced manner to increase the reverse breakdown voltage of the super junction device, but the present application does not limit this, depending on the specific circumstances.

[0079] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 and Figure 3 As shown, the super junction device further includes: a first electrode layer located on a side of the gallium oxide substrate away from the N-type epitaxial layer. Optionally, the first electrode layer is a cathode layer.

[0080] Specifically, in one embodiment of the present application, the first electrode layer includes a stacked Ti metal layer and an Au metal layer, and the Ti metal layer is located between the Au metal layer and the gallium oxide substrate. Specifically, in one embodiment of the present application, the thickness of the Ti metal layer ranges from 20nm to 200nm, and the thickness of the Au metal layer ranges from 80nm to 1000nm, for example: the thickness of the Ti metal layer is 20nm, the thickness of the Au metal layer is 80nm, or the thickness of the Ti metal layer is 200nm, and the thickness of the Au metal layer is 1000nm. The present application does not limit this, and it depends on the specific situation.

[0081] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 and Figure 3 As shown, the super junction device further includes: a second electrode layer electrically connected to a portion of the N-type epitaxial layer located in the cell region, the second electrode layer covers the cell region, and optionally, the second electrode layer is an anode layer.

[0082] On the basis of the above embodiments, in one embodiment of the present application, if the super junction device also includes a transition zone, the second electrode layer may further extend toward the transition zone to cover a portion of the surface of the transition zone to reduce the process difficulty of forming the second electrode layer, but the present application does not limit this, as long as the second electrode layer does not cover the terminal area.

[0083] Specifically, in one embodiment of the present application, the second electrode layer includes a stacked Ni metal layer and an Au metal layer, and the Ni metal layer is located between the Au metal layer and the N-type epitaxial layer. Specifically, in one embodiment of the present application, the thickness of the Ni metal layer ranges from 20nm to 200nm, and the thickness of the Au metal layer ranges from 80nm to 1000nm, for example: the thickness of the Ni metal layer is 20nm, and the thickness of the Au metal layer is 80nm, or, the thickness of the Ni metal layer is 200nm, and the thickness of the Au metal layer is 1000nm. The present application does not limit this, and it depends on the specific situation.

[0084] Optionally, in one embodiment of the present application, continue as Figure 2 and Figure 3 As shown, the super junction device further includes: a passivation layer 60, which covers the terminal region of the super junction device and exposes at least a portion of the second electrode layer 50, so as to facilitate electrical connection of the second electrode layer 50 with the outside.

[0085] Specifically, in one embodiment of the present application, the passivation layer is a silicon oxide layer, formed by a deposition process, and has a thickness of about 1 μm, but the present application does not limit this, and it depends on the specific circumstances.

[0086] like Figure 8 As shown, Figure 8 It is a schematic diagram of the withstand voltage capability of super junction devices, where curve B is Figure 1 Schematic diagram of the withstand voltage capability of the super junction device shown in FIG. 1 ; wherein the area enclosed by the curve B, the vertical dotted line and the coordinate axis represents Figure 1 The curve A is a schematic diagram of the withstand voltage capability of the super junction device provided in the embodiment of the present application. The area enclosed by the curve A, the vertical dotted line and the coordinate axis represents the withstand voltage capability of the super junction device provided in the embodiment of the present application. Figure 8 It can be seen that the voltage resistance and Figure 1 The voltage withstand capability of the superjunction devices shown is not much different. Figure 1 The super junction device shown in the figure has a greatly reduced process difficulty of the super junction device provided in the embodiment of the present application. Therefore, the super junction device provided in the embodiment of the present application has a high withstand voltage performance and a low process difficulty.

[0087] In addition, the method for manufacturing a super junction device provided in the embodiment of the present application can be applied to manufacturing the super junction device provided in any of the above embodiments. Specifically, the method for manufacturing a super junction device provided in the embodiment of the present application includes:

[0088] S1: growing an N-type epitaxial layer on a gallium oxide substrate, and forming a high resistance layer on a surface of the N-type epitaxial layer away from the gallium oxide substrate. Optionally, the gallium oxide substrate is an N-type gallium oxide substrate, the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, and the high resistance layer is an N-type gallium oxide high resistance layer.

[0089] Specifically, in one embodiment of the present application, growing an N-type epitaxial layer on a gallium nitride substrate, and forming a high resistance layer on a surface of the N-type epitaxial layer away from the gallium oxide substrate comprises:

[0090] like Fig. 9 As shown, an N-type epitaxial layer 20 is grown on a gallium oxide substrate 10 by using a HVPE epitaxial growth method;

[0091] like Fig.10 As shown, a preset element is implanted into a first thickness in the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10, and annealing is performed to activate the preset element, so as to form a high resistance layer 21 in the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10.

[0092] It should be noted that HVPE (Hydride Vapor Phase Epitaxy) is a new technology for preparing nitride materials. Its specific process is to use hydrogen to deposit nitride crystals on a substrate at high temperature. In other embodiments of the present application, other methods can also be used to generate an N-type epitaxial layer on the oxide substrate. The present application does not limit this and it depends on the specific situation.

[0093] It should also be noted that, in this embodiment, the formation of the high resistance layer can reduce the electric field intensity on the surface of the N-type epitaxial layer to reduce leakage.

[0094] Specifically, in one embodiment of the present application, the preset element may be nitrogen, magnesium, or beryllium. The present application does not limit this, and the specific situation depends on the specific situation. Taking the preset element as nitrogen as an example, the value range of the first thickness is 0.5μm to 1μm, and the doping concentration of nitrogen in the first thickness of the N-type epitaxial layer is 2e16cm -3 ~2e18cm -3 , but this application does not limit this and it depends on the specific circumstances.

[0095] Optionally, in one embodiment of the present application, the thickness of the N-type epitaxial layer is in the range of 5 μm to 10 μm, and the doping concentration of the N-type epitaxial layer is in the range of 5E15 cm -3 ~2E16cm -3 , but this application does not limit this and it depends on the specific circumstances.

[0096] Continuing to take the preset element as nitrogen as an example, on the basis of the above embodiment, in one embodiment of the present application, the preset element is implanted into a first thickness within the surface of the N-type epitaxial layer away from the gallium oxide substrate, and annealed, and activation of the preset element includes: implanting the preset element into a first thickness within the surface of the N-type epitaxial layer away from the gallium oxide substrate, and then annealing at 1100° C. for 30 minutes to complete activation of the preset element.

[0097] Optionally, in one embodiment of the present application, after the preset element is implanted into the first thickness of the N-type epitaxial layer away from the surface of the gallium oxide substrate, it is placed in an activation furnace at 1100° C. and annealed for 30 minutes to complete the activation of the preset element, but the present application is not limited to this and it depends on the specific situation.

[0098] Optionally, in one embodiment of the present application, after forming an N-type epitaxial layer on the surface of the gallium oxide substrate and before forming a high resistance layer on the surface of the N-type epitaxial layer away from the gallium oxide substrate, the manufacturing method further includes:

[0099] S11: forming a first electrode layer on a side of the gallium oxide substrate 10 away from the N-type epitaxial layer 20, such as Fig.11 and Fig.12 As shown, in this embodiment, the first electrode layer 11 is first formed on the side of the gallium oxide substrate 10 away from the N-type epitaxial layer 20, and then a high resistance layer 21 is formed on the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10. Optionally, the first electrode layer 21 is a cathode layer.

[0100] Specifically, in one embodiment of the present application, forming a first electrode layer on a side of the gallium oxide substrate away from the N-type epitaxial layer includes:

[0101] Depositing a first electrode layer on a side of the gallium oxide substrate away from the N-type epitaxial layer;

[0102] The first electrode layer is annealed in a nitrogen atmosphere at 450° C. to 500° C. to form an ohmic contact with the gallium oxide substrate.

[0103] Optionally, in one embodiment of the present application, the first electrode layer includes a stacked Ti metal layer and an Au metal layer, and the Ti metal layer is located between the Au metal layer and the gallium oxide substrate. Specifically, in one embodiment of the present application, the thickness of the Ti metal layer ranges from 20nm to 200nm, and the thickness of the Au metal layer ranges from 80nm to 1000nm, for example: the thickness of the Ti metal layer is 20nm, the thickness of the Au metal layer is 80nm, or the thickness of the Ti metal layer is 200nm, and the thickness of the Au metal layer is 1000nm. The present application does not limit this, and it depends on the specific situation.

[0104] S2: Fig.13 As shown, a plurality of multi-level trenches 22 are formed in the N-type epitaxial layer 20, and the multi-level trenches 22 include N sub-grooves arranged along a first direction X, and the sizes of the N sub-grooves in a second direction Y are not completely the same, wherein N is not less than 3, the first direction X is perpendicular to the plane where the gallium oxide substrate 10 is located, and points to the gallium oxide substrate 10, and the second direction Y is perpendicular to the first direction X.

[0105] Optionally, in one embodiment of the present application, continue as Fig.13 As shown, the dimensions of the N sub-grooves in the second direction gradually decrease along the first direction, so as to reduce the process difficulty of the multi-level grooves while ensuring that the dimensions of the N sub-grooves in the second direction are not exactly the same, but the present application does not limit this and it depends on the specific circumstances.

[0106] Specifically, in one embodiment of the present application, continue as follows Fig.13As shown, the multi-level grooves do not penetrate the N-type epitaxial layer to increase the reverse breakdown voltage of the super junction device; in another embodiment of the present application, the multi-level grooves penetrate the N-type epitaxial layer to reduce the overall resistance of the super junction device and reduce the power of the super junction device. The present application does not limit this and it depends on the specific circumstances.

[0107] Based on any of the above embodiments, in one embodiment of the present application, in the first direction, the top view of the multi-level groove is in the shape of a strip (eg Figure 4 As shown), round (as Figure 5 As shown), rectangle (as Figure 6 ) or hexagonal (as shown Figure 7 As shown), or other shapes, the present application does not limit this, depending on the specific circumstances. It should be noted that in the first direction, when the shape of the top view of the multi-level groove is a hexagon, in a plane parallel to the gallium oxide substrate, the top views of the multi-level grooves in adjacent rows are arranged in an interlaced manner to increase the reverse breakdown voltage of the super junction device, but the present application does not limit this, depending on the specific circumstances.

[0108] S3: forming a first P-type oxide layer covering the surface of the multi-level groove on the surface of the multi-level groove, wherein the surface of the multi-level groove includes the bottom of the multi-level groove and the sidewall of the multi-level groove.

[0109] It should be noted that, in this embodiment, the N-type epitaxial layer includes a plurality of N-type epitaxial units, and the portion of the N-type epitaxial layer located between adjacent multi-level trenches is an N-type epitaxial unit. Fig.13 The dashed box portion 23 in the multi-level trench 22, the first P-type oxide layer on the sidewall of at least one sub-trench in the multi-level trench 22 and the N-type epitaxial unit 23 at the corresponding position meet the charge balance condition, and the charge balance condition is Among them, W NiO Characterizes the width of the first P-type oxide layer on the sidewall of a sub-trench in a multi-level trench, N NiO Characterizes the concentration of the first P-type oxide layer on the side of the sub-trench, Characterizes the width of the epitaxial unit at the corresponding position of this sub-trench, Characterizes the concentration of the epitaxial unit at the corresponding position of this sub-trench. Wherein, the width is the dimension along the second direction Y.

[0110] For example, the multi-level grooves include the i-th multi-level groove and the i+1-th multi-level groove, the portion of the N-type epitaxial layer located between the i-th multi-level groove and the i+1-th multi-level groove is the i-th epitaxial unit, the product of the thickness and concentration of the first P-type oxide layer at the j-th sub-groove in the i-th multi-level groove and the j-th sub-groove in the i+1-th multi-level groove is equal to the product of the width and concentration of the portion of the i-th epitaxial unit corresponding to the j-th sub-groove position, wherein i and j are both integers not less than 1.

[0111] Specifically, in one embodiment of the present application, the N sub-grooves satisfy at least one of a first condition and a second condition in the second direction, wherein the first condition includes that the maximum value of the size of the N sub-grooves in the second direction is not greater than 5 microns, and the minimum value is not less than 500 nanometers, but the present application does not limit the specific numerical values ​​of the maximum and minimum values ​​of the size of the N sub-grooves in the second direction, which depends on the process capability; the second condition includes that the maximum value of the size of the N sub-grooves in the second direction does not exceed the target size + 1 micron, and the minimum value is not less than the target size - 1 micron, wherein the target size is determined according to the charge balance condition.

[0112] Optionally, in one embodiment of the present application, in the first direction, the sizes of the N sub-grooves in the second direction vary uniformly along the first direction, but the present application does not limit this, and it depends on the specific circumstances. Specifically, in the first direction, the size variation of adjacent sub-grooves in the same multi-level groove in the second direction may be 0.2 microns, but the present application does not limit this, and it depends on the specific circumstances.

[0113] Based on any of the above embodiments, in one embodiment of the present application, the first P-type oxide layer is a NiO layer, a Cu2O layer or a SnO layer, and the present application does not limit this, depending on the specific circumstances.

[0114] Specifically, in one embodiment of the present application, forming a first P-type oxide layer covering the surface of the multi-level groove on the surface of the multi-level groove includes:

[0115] like Fig.14 As shown, a first P-type oxide layer 30 is formed to cover the surface of the multi-level trench 22 and the surface of the N-type epitaxial layer 20 on a side away from the gallium oxide substrate 10;

[0116] like Fig.15As shown, a first photoresist layer 31 is formed on the side of the first P-type oxide layer 30 away from the surface of the multi-level groove 22, the first photoresist layer 31 covers the first P-type oxide layer 30 and completely fills the multi-level groove 22, and the first P-type oxide layer 30 includes a first portion located on the surface of the multi-level groove 22 and a second portion located on the surface of the N-type epitaxial layer 20;

[0117] Continue as Fig.15 As shown, the first photoresist layer 31 is partially removed (such as planarized), the portion of the first photoresist layer 31 located on the surface of the second portion is removed, and the portion of the first photoresist layer 31 located on the surface of the first portion is retained;

[0118] like Fig.16 As shown, the second portion is removed, that is, the portion of the first P-type oxide layer 30 located on the surface of the N-type epitaxial layer 20 is removed;

[0119] like Fig.17 As shown, the remaining portion of the first photoresist layer is removed, and only the portion of the first P-type oxide layer 30 located at the bottom of the multi-level trench 22 and the sidewall of the multi-level trench 22 is retained.

[0120] Optionally, based on the above embodiment, in one embodiment of the present application, forming a first P-type oxide layer covering the surface of the multi-level grooves and the surface of the N-type epitaxial layer away from the gallium oxide substrate comprises: forming the first P-type oxide layer covering the surface of the multi-level grooves and the surface of the N-type epitaxial layer away from the gallium oxide substrate by a thin film sputtering process, wherein the surface of the multi-level grooves includes the bottom of the multi-level grooves and the sidewalls of the multi-level grooves. It should be noted that the thin film sputtering process is a physical vapor deposition (PVD) technology, which is mainly used to prepare various functional thin films. Specifically, the thin film sputtering process sputters atoms or molecules on the surface of the target material and deposits them on the substrate material by momentum transfer, thereby forming a desired thin film.

[0121] In another embodiment of the present application, the first P-type oxide layer is a NiO layer, and forming the first P-type oxide layer covering the surface of the multi-level grooves and the surface of the N-type epitaxial layer away from the gallium oxide substrate includes: first filling the multi-level grooves with metallic nickel, and then oxidizing the metallic nickel in the multi-level grooves in an oxygen atmosphere to form the first P-type oxide layer on the surface of the multi-level grooves covering the surface of the multi-level grooves and the surface of the N-type epitaxial layer away from the gallium oxide substrate.

[0122] In the method for manufacturing a super junction device provided in an embodiment of the present application, the gallium oxide substrate is an N-type gallium oxide substrate, and the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, thereby improving the voltage resistance performance of the super junction device.

[0123] Moreover, in the method for manufacturing a super junction device provided in an embodiment of the present application, the N-type epitaxial layer 20 has a plurality of multi-level grooves, and the multi-level grooves include N sub-grooves arranged along a first direction X, and the sizes of the N sub-grooves in a second direction Y are not completely the same, wherein the N is not less than 3, so that when the thickness and concentration of the first P-type oxide layer located on the surface of the multi-level grooves change, the probability that at least part of the multi-level grooves and the N-type epitaxial layer meet the charge balance condition can be increased through a plurality of sub-grooves of unequal sizes, thereby reducing the probability that the reverse breakdown voltage of the super junction device will be greatly reduced due to a slight change in the thickness and concentration of the first P-type oxide layer, thereby improving the reverse breakdown voltage of the super junction device.

[0124] In addition, in the method for manufacturing a super junction device provided in an embodiment of the present application, since the thickness and concentration of the first P-type oxide layer vary slightly, a plurality of sub-grooves of unequal sizes can be used so that at least part of the multi-level grooves and the N-type epitaxial layer satisfy the charge balance condition. Therefore, during the manufacturing process of the super junction device, the process control requirements for the concentration of the first P-type oxide layer when it is formed are relatively low, thereby increasing the doping concentration window of the first P-type oxide layer and reducing the process difficulty of the super junction device.

[0125] In addition, in the manufacturing method of the super junction device provided in the embodiment of the present application, the dimensions of the N sub-grooves in the second direction gradually decrease along the first direction, and a step surface can be formed in the boundary area of ​​the adjacent sub-grooves in the first direction, thereby improving the uniformity of the formation of the first P-type oxide layer located on the side walls of each sub-groove, and further allowing the first P-type oxide layer to be uniformly formed on the surface of the multi-level groove, so as to reduce the process difficulty on the basis of ensuring the uniformity of the first P-type oxide layer located on the side walls of each sub-groove.

[0126] It should be noted that, in this embodiment, the super junction device includes a cell region and a terminal region. The cell region is a functional region of the super junction device, and the terminal region is located at the periphery of the cell region and is used to disperse the electric field, alleviate the sharp corner discharge of the cell region, alleviate the discharge concentration phenomenon of the cell region, and increase the reverse breakdown voltage of the super junction device.

[0127] Optionally, in one embodiment of the present application, the super junction device also includes a transition zone located between the cell region and the terminal region, that is, the super junction device includes a cell region, a transition zone and a terminal region, the terminal region is located at the periphery of the cell region, and the transition zone is located between the cell region and the terminal region to increase the distance between the cell region and the terminal region, thereby reducing the process difficulty of the super junction device on the basis of ensuring that the subsequently formed second electrode layer can make the cell region and the terminal region electrically connected, and the second electrode layer will not cover the part of the side wall of the multi-level groove of the first P-type oxide layer located in the terminal region.

[0128] Since the transition region is provided between the cell region and the terminal region, the charge balance condition formed by the first P-type oxide layer will be destroyed to a certain extent, therefore, in one embodiment of the present application, the manufacturing method further includes:

[0129] S4: forming a second P-type oxide layer on the surface of the portion of the first P-type oxide layer located in the terminal region of the super junction device. It should be noted that, in this embodiment, the second P-type oxide layer at at least one sub-groove in the multi-level groove and the N-type epitaxial unit at its corresponding position also meet the charge balance condition, and the charge distribution of the cell region in the super junction device is adjusted to alleviate the reduction of the reverse breakdown voltage caused by the charge imbalance in the cell region.

[0130] Optionally, in one embodiment of the present application, the second P-type oxide layer also extends to cover a portion of the surface of the transition zone, thereby ensuring that the subsequently formed second electrode layer can electrically connect the cell area and the terminal area, and the second electrode layer will not cover the side walls of the multi-level grooves located in the terminal area, so that the second P-type oxide layer can be formed on a portion of the surface of the transition zone, thereby reducing the process difficulty of forming the portion of the second P-type oxide layer located in the terminal area, but the present application does not limit this and it depends on the specific circumstances.

[0131] Specifically, in one embodiment of the present application, the second P-type oxide layer may be a NiO layer, a Cu2O layer or a SnO layer; it should be noted that the materials of the first P-type oxide layer and the second P-type oxide layer may be the same or different, and the present application does not limit this, depending on the specific circumstances.

[0132] The super junction device provided in the embodiment of the present application is described below by taking the super junction device including a transition region as an example.

[0133] Specifically, in one embodiment of the present application, forming a second P-type oxide layer on a surface of a portion of the first P-type oxide layer located in a terminal region of the super junction device includes:

[0134] like Fig.18 As shown, a second photoresist layer 32 is formed on the surface of the N-type epitaxial layer 20 and the surface of the first P-type oxide layer 30, and the second photoresist layer 32 completely fills the multi-level trenches;

[0135] Continue as Fig.18 As shown, the second photoresist layer 32 is partially removed (eg, planarized) to expose at least a portion of the surface of the transition region of the super junction device and the terminal region;

[0136] like Fig.19 As shown, a second P-type oxide layer 40 is formed on the surface of the second photoresist layer 32 and on the surface of the super junction device in an area not covered by the second photoresist layer 32. Optionally, the second P-type oxide layer 40 is formed by a thin film sputtering process;

[0137] like Fig. 20 As shown, the second photoresist layer 32 and a portion of the second P-type oxide layer 40 located on the surface thereof are removed.

[0138] It should be noted that, in this embodiment, the multi-level grooves are only located in the cell region and the terminal region, and the transition region is not provided with multi-level grooves.

[0139] Optionally, based on any of the above embodiments, in an embodiment of the present application, the plurality of multi-level grooves include a first multi-level groove located in the cell region and a second multi-level groove located in the terminal region, and the method further includes: removing at least a portion of the bottom of the second multi-level groove so that the terminal region of the super junction device has a better charge balance state, so that the terminal region has a higher withstand voltage.

[0140] Optionally, in one embodiment of the present application, the side wall of the second multi-level groove away from the cell area is covered with the second P-type oxide layer to increase the switching speed of the super junction device when used as a power switch and reduce switching losses, but the present application is not limited to this. In other embodiments of the present application, the side wall of the second multi-level groove away from the cell area may not be covered with the second P-type oxide layer, depending on the specific circumstances.

[0141] Specifically, in one embodiment of the present application, removing at least a portion of the bottom of the second multi-level groove includes:

[0142] like Fig.21 As shown, a third photoresist layer 41 covering the super junction device is formed, and the third photoresist layer 41 covers the cell region, the transition region and the terminal region;

[0143] Continue as Fig.21As shown, the third photoresist layer 41 is partially removed to expose the bottom of the multi-level groove located in the terminal area, that is, to expose the bottom of the second multi-level groove;

[0144] like Fig. 22 As shown, the first P-type oxide layer and the second P-type oxide layer are removed from the bottom of the second multi-level trench;

[0145] like Fig.23 As shown, the third photoresist layer 41 is removed.

[0146] Specifically, in one embodiment of the present application, the second P-type oxide layer may be a NiO layer, a Cu2O layer or a SnO layer, which is not limited in the present application and depends on the specific circumstances. Optionally, in one embodiment of the present application, the second P-type oxide layer may be the same material as the first P-type oxide layer, such as the first P-type oxide layer is a NiO layer and the second P-type oxide layer is also a NiO layer, which is not limited in the present application and the first P-type oxide layer and the second P-type oxide layer may also be different materials, which depends on the specific circumstances.

[0147] On the basis of any of the above embodiments, in one embodiment of the present application, the method further includes: forming a second electrode layer electrically connected to the portion of the N-type epitaxial layer located in the cell region, the second electrode layer covers the cell region, and the second electrode layer is an anode layer. Optionally, if the super junction device also includes a transition region, the second electrode layer may also extend toward the transition region to cover a portion of the surface of the transition region to reduce the process difficulty of forming the second electrode layer, but the present application does not limit this, as long as the second electrode layer does not cover the terminal region.

[0148] Specifically, in one embodiment of the present application, forming a second electrode layer electrically connected to a portion of the N-type epitaxial layer located in the cell region includes:

[0149] like Fig.24 As shown, a fourth photoresist layer 42 is formed in the plurality of multi-level grooves, and the fourth photoresist layer 42 is planarized to form a fourth photoresist layer 42 filling the plurality of multi-level grooves;

[0150] like Fig.25 As shown, a second electrode layer 50 is formed on the surface of the super junction device, and the second electrode layer 50 is patterned so that the second electrode layer 50 at least completely covers the cell area and exposes the terminal area. Optionally, the second electrode layer 50 also extends to the transition area to cover a portion of the transition area.

[0151] Optionally, in one embodiment of the present application, the second electrode layer includes a stacked Ni metal layer and an Au metal layer, and the Ni metal layer is located between the Au metal layer and the N-type epitaxial layer. Specifically, in one embodiment of the present application, the thickness of the Ni metal layer ranges from 20nm to 200nm, and the thickness of the Au metal layer ranges from 80nm to 1000nm, for example: the thickness of the Ni metal layer is 20nm, and the thickness of the Au metal layer is 80nm, or the thickness of the Ni metal layer is 200nm, and the thickness of the Au metal layer is 1000nm. The present application does not limit this, and it depends on the specific situation.

[0152] Based on any of the above embodiments, in one embodiment of the present application, after the second electrode layer is formed, the method further includes: Fig.26 As shown, a passivation layer 60 is formed, and the passivation layer 60 covers the terminal region of the super junction device and exposes at least a portion of the second electrode layer 50 to facilitate electrical connection of the second electrode layer 50 with the outside.

[0153] Taking the super junction device including a transition region as an example, specifically, in one embodiment of the present application, a passivation layer is formed, the passivation layer covers the terminal region of the super junction device, and at least exposes a portion of the second electrode layer, including:

[0154] forming a passivation layer, wherein the passivation layer covers the terminal region, the transition region and the cell region of the super junction device;

[0155] The passivation layer is opened with holes so that the passivation layer exposes at least a partial area of ​​the second electrode layer, so that the second electrode layer is electrically connected to the outside.

[0156] Optionally, in an embodiment of the present application, the passivation layer is a silicon oxide layer, formed by a deposition process, and has a thickness of about 1 μm, but the present application does not limit this, and it depends on the specific circumstances.

[0157] In summary, in the method for manufacturing a super junction device provided in an embodiment of the present application, the N-type epitaxial layer 20 has a plurality of multi-level grooves, and the multi-level grooves include N sub-grooves arranged along a first direction X, and the sizes of the N sub-grooves in a second direction Y are not completely the same, wherein the N is not less than 3, so that when the thickness and concentration of the first P-type oxide layer located on the surface of the multi-level grooves change, the probability that at least part of the multi-level grooves and the N-type epitaxial layer meet the charge balance condition can be increased through a plurality of sub-grooves of unequal sizes, thereby reducing the probability that the reverse breakdown voltage of the super junction device will be greatly reduced due to a slight change in the thickness and concentration of the first P-type oxide layer, thereby improving the reverse breakdown voltage of the super junction device.

[0158] In addition, in the method for manufacturing a super junction device provided in the embodiment of the present application, since the thickness and concentration of the first P-type oxide layer vary slightly, a plurality of sub-grooves of unequal sizes can be used so that at least part of the multi-level grooves and the N-type epitaxial layer satisfy the charge balance condition. Therefore, during the manufacturing process of the super junction device, the process control requirements for the concentration of the first P-type oxide layer when it is formed are relatively low, the doping concentration window of the first P-type oxide layer is increased, and the process difficulty of the super junction device is reduced, so that the super junction device manufactured by the method for manufacturing a super junction device provided in the embodiment of the present application has higher voltage resistance and lower process difficulty.

[0159] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0160] It should be noted that in the description of this application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. for ease of understanding and description.

[0161] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0162] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A super junction device, It is characterized in that include: Gallium oxide substrate; An N-type epitaxial layer located on the surface of the gallium oxide substrate, wherein a high resistance layer is formed in a surface of the N-type epitaxial layer away from the gallium oxide substrate; A plurality of multi-level trenches located in the N-type epitaxial layer, the multi-level trenches comprising N sub-grooves arranged along a first direction, and the sizes of the N sub-grooves in a second direction are not completely the same, wherein N is not less than 3, the first direction is perpendicular to the plane where the gallium oxide substrate is located and points to the gallium oxide substrate, and the second direction is perpendicular to the first direction; A first P-type oxide layer covers the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewall of the multi-level trench.

2. The super junction device according to claim 1, It is characterized in that The N-type epitaxial layer includes a plurality of N-type epitaxial units, the portion of the N-type epitaxial layer located between adjacent multi-level trenches is an N-type epitaxial unit, the first P-type oxide layer on the sidewall of at least one sub-trench in the multi-level trench and the N-type epitaxial unit at its corresponding position satisfy a charge balance condition, and the charge balance condition is Among them, W NiO Characterizes the width of the first P-type oxide layer on the sidewall of a sub-trench in a multi-level trench, N NiO Characterizes the concentration of the first P-type oxide layer on the sidewall of the sub-trench, Characterizes the width of the epitaxial unit at the corresponding position of this sub-trench, Characterizes the concentration of the epitaxial unit at the corresponding position of this sub-trench.

3. The super junction device according to claim 1, It is characterized in that Dimensions of the N sub-grooves in the second direction gradually decrease along the first direction.

4. The super junction device according to claim 3, It is characterized in that In the first direction, sizes of the N sub-grooves in the second direction vary uniformly along the first direction.

5. The super junction device according to claim 1, It is characterized in that The multi-level trenches penetrate the N-type epitaxial layer or the multi-level trenches do not penetrate the N-type epitaxial layer.

6. The super junction device according to claim 1, It is characterized in that In the first direction, the shape of the multi-level groove in a top view is a strip, a circle, a rectangle or a hexagon.

7. The super junction device according to claim 1, It is characterized in that The super junction device comprises a cell region, a transition region and a terminal region, wherein the terminal region is located at the periphery of the cell region, and the transition region is located between the cell region and the terminal region.

8. The super device according to claim 7, It is characterized in that Also includes: A second P-type oxide layer covers a surface of a portion of the first P-type oxide layer located in a terminal region of the super junction device.

9. The super junction device according to claim 8, It is characterized in that The second P-type oxide layer also extends to cover a portion of the surface of the transition region.

10. The super junction device according to claim 8, It is characterized in that The plurality of multi-level trenches include a first multi-level trench located in the cell region and a second multi-level trench located in the terminal region, and a first P-type oxide layer and a second P-type oxide layer located on the surface of the second multi-level trench expose at least a portion of the bottom of the second multi-level trench.

11. A method for manufacturing a super junction device, It is characterized in that include: Growing an N-type epitaxial layer on a gallium oxide substrate, and forming a high resistance layer in a surface of the N-type epitaxial layer away from the gallium oxide substrate; A plurality of multi-level trenches are formed in the N-type epitaxial layer, wherein the multi-level trenches include N sub-grooves arranged along a first direction, and the sizes of the N sub-grooves in a second direction are not completely the same, wherein N is not less than 3, the first direction is perpendicular to the plane where the gallium oxide substrate is located and points to the gallium oxide substrate, and the second direction is perpendicular to the first direction; A first P-type oxide layer covering the surface of the multi-level trench is formed on the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewall of the multi-level trench.

12. The super junction device according to claim 11, It is characterized in that The super junction device includes a cell region, a transition region and a terminal region, wherein the terminal region is located outside the cell region, and the transition region is located between the cell region and the terminal region. The method also includes: forming a second P-type oxide layer on the surface of the portion of the first P-type oxide layer located in the terminal region of the super junction device.

13. The super junction device according to claim 12, It is characterized in that The second P-type oxide layer also extends to cover a portion of the surface of the transition region.

14. The super junction device according to claim 12 or 13, It is characterized in that The plurality of multi-level trenches include a first multi-level trench located in the cell region and a second multi-level trench located in the terminal region. The method further includes: removing at least a portion of the first P-type oxide layer and the second P-type oxide layer located at the bottom of the second multi-level trench.

15. The super junction device according to claim 11, It is characterized in that The first P-type oxide layer is a NiO layer, and forming the first P-type oxide layer covering the multi-level groove surface on the multi-level groove surface includes: first filling metal nickel into the multi-level groove, and then oxidizing the metal nickel in the multi-level groove in an oxygen atmosphere to form the first P-type oxide layer covering the multi-level groove surface on the multi-level groove surface.

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