Time synchronization method and system for wireless deterministic network

Abstract

The invention provides a time synchronization method and system for a wireless deterministic network, and relates to the technical field of communication. The method comprises the following steps: designing a handshake protocol based on a Linux kernel, and generating a message with an identifier; the message is identified and a timestamp is inserted when the message is sent to pass through the MAC layer, and the message is identified and the timestamp is captured when the message is received to pass through the MAC layer; performing synchronization error compensation calculation according to the acquired timestamp information, wherein synchronization error compensation comprises phase error compensation and frequency error compensation; designing a compensation filter, and inputting the calculated compensation data into the compensation filter for screening; and inputting the screened compensation data into a clock system for compensation to finish synchronization. According to the method, the influence of asymmetric transmission delay and wireless transmission abnormal compensation data on the time synchronization precision in a wireless time synchronization mechanism can be effectively inhibited, so that the time synchronization precision and reliability are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a time synchronization method and system for a wireless deterministic network. Background Art

[0002] With the expansion of modern industrial scale and the demand for intelligence, traditional industrial fieldbuses are gradually being replaced by real-time Ethernet based on the IEEE 802.3 standard. Real-time Ethernet technologies such as Profinet, EtherCAT, SERCOS III, time-sensitive networks (TSN), and time-triggered Ethernet (TTE) can provide deterministic transmission because data transmission in these networks is almost based on precise time, which ensures that time-critical services have no resource competition. The time synchronization technology of Profinet IRTd is based on the improvement of the IEEE 1588 precision time protocol. EtherCAT utilizes a unique distributed time synchronization mechanism. Powerlink adopts a timestamp-based synchronization mechanism. SERCOS III adopts a coherent frame time synchronization mechanism based on coherent frames. In addition, TSN improves PTP to general PTP (gPTP) in IEEE 802.1AS. TTE specifies time synchronization methods in AS6802 to ensure the reliability and security of the network. However, these precise time synchronization technologies are all based on wired networks and are not suitable for wireless networks.

[0003] Since wired networks have many limitations in industrial field wiring and equipment diagnosis, many industrial factories are transforming wired network information transmission and exchange into wireless networks. The first step is to establish accurate wireless time synchronization. Currently, there are convenient wireless time synchronization implementation solutions, such as GPS and NTP. Among them, GPS can achieve nanosecond synchronization accuracy, but it is affected by the surrounding environment and terrain, and the implementation and maintenance costs are high, so it is not suitable for industrial production. NTP is widely used in Ethernet time synchronization, but its synchronization accuracy is milliseconds, which cannot meet the needs of industrial production. The mechanism of IEEE1588 precision time protocol has the characteristics of simplicity, reliability, high accuracy and flexible deployment. There are IEEE 1588 protocol and software timestamps used in IEEE 802.11 wireless LAN synchronization system, but under different network loads, the transmission asymmetric delay generated is large, which has a greater impact on synchronization accuracy. Some of these time synchronization methods have special requirements for the experimental environment or poor compatibility with general protocols.

[0004] Chinese invention patent CN116939801A discloses a wearable device wireless time synchronization method based on physical layer cross-technology communication. The method uses a wireless radio frequency coordinator to send and receive synchronization messages to correct the local clock. However, the asymmetric transmission delay of the protocol stack is not considered, and the synchronization accuracy is insufficient.

[0005] A wireless time synchronization method is disclosed in Chinese invention patent CN117336848A, which calibrates the clock by interpolation calculation, two-way time measurement and clock difference calculation in the time comparison process. This method does not filter outliers in the compensation data in the time synchronization protocol implementation, and the time synchronization stability is insufficient.

[0006] The time synchronization method for industrial wireless deterministic networks needs to take into account several characteristics such as hardware cost, flexible deployment, and high reliability. The mechanism of the IEEE 1588 precise time synchronization protocol has the above characteristics, but as a wired network protocol, it needs further integration and adaptation when applied to wireless networks. In the integration and adaptation process, the key difficulties of wireless time synchronization are: first, the time stamp insertion position. The traditional integration method is to set the time stamp insertion position at the application layer of the wireless protocol stack. However, under different network loads, the asymmetric transmission delay caused by the protocol stack will reduce the time compensation measurement accuracy and the time synchronization accuracy is poor; second, the application layer needs to design an adaptive software protocol stack to apply hardware timestamps; third, in the time frequency compensation part, the hardware clock frequency is difficult to adjust; fourth, the reliability and certainty of wireless network data transmission are worse than those of wired networks. During the time synchronization process, the generation of abnormal values ​​will greatly affect the stability of time synchronization. Therefore, it is necessary to develop a high-reliability time synchronization architecture based on the integration of wireless networks and IEEE 1588 basic mechanisms to ensure the accuracy and stability of wireless time synchronization. Summary of the invention

[0007] In view of the above problems, the purpose of the present invention is to provide a time synchronization method and system for a wireless deterministic network. On the basis of not affecting the function of the wireless protocol stack and the time delay measurement mechanism, the timestamp insertion and time synchronization related modules are built in the MAC layer of the wireless network, which effectively reduces the uncertain time delay caused by the measurement message when passing through the protocol stack and improves the time synchronization accuracy; the high-speed parallel time compensation filtering module of the MAC layer is used to improve the stability of time synchronization.

[0008] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0009] In one aspect, a time synchronization method for a wireless deterministic network is provided, the method comprising the following steps:

[0010] S1. Design a handshake protocol based on the Linux kernel to generate messages with identifiers;

[0011] S2, the message is identified and a timestamp is inserted when it is sent through the MAC layer, and the message is identified and a timestamp is captured when it is received through the MAC layer;

[0012] S3. Perform synchronization error compensation calculation according to the acquired timestamp information, wherein the synchronization error compensation includes phase error compensation and frequency error compensation;

[0013] S4, designing a compensation filter, and inputting the calculated compensation data into the compensation filter for screening;

[0014] S5. Input the screened compensation data into the clock system for compensation to complete synchronization.

[0015] Optionally, the clock system is a hardware clock system, including a mixed mode clock manager, a reset signal, a phase compensation interface, a frequency compensation interface, and an output terminal;

[0016] The hybrid mode clock manager IP core is used to obtain a clock with a frequency of 125 MHz to drive the clock system; the reset signal is used to reset and restart the clock system; the phase compensation interface and the frequency compensation interface are connected to the compensation filter to correct the clock system; the time information output by the output end is used as a timestamp, and the time synchronization accuracy of the master clock and the slave clock is checked through the second pulse PPS.

[0017] Optionally, the insertion / capture position of the timestamp is set between the MAC layer data sending / receiving queue and the OFDM module.

[0018] Optionally, the format of the message is designed based on a wireless frame, the header includes a source MAC address, a destination MAC address and related information, and a plurality of special data fields are defined in a payload portion of the wireless frame, including an identifier field and a time information field;

[0019] The identifier field is set to 2 bytes, which is used to distinguish three types of synchronization messages: pcap_send_pkt_b, pcap_send_pkt_c and pcap_seend_pkt_d; the time information field is set to 32 bytes, which includes the time record and compensation data of each synchronization cycle.

[0020] Optionally, the phase error compensation specifically includes:

[0021] The master clock sends a pcap_send_pkt_b message to the slave clock and records the sending time T1. The slave clock receives the message and records the receiving time T2.

[0022] The slave clock starts the reverse transmission delay calculation by sending a pcap_send_pkt_c message to the master clock and records the sending time T3. The master clock records the receiving time T4 of the pcap_send_pkt_c message.

[0023] The master clock sends a pcap_send_pkt_d message carrying a timestamp of T4;

[0024] Collect four timestamps T1-T4 to calculate the offset time between the master clock and the slave clock; assuming that the network transmission path is symmetrical, the link delay formula is as follows:

[0025] (1)

[0026] The slave clock calculates the offset time using the following formula:

[0027] (2)

[0028] (3)

[0029] Among them, T master is the master clock time, T slave is the slave clock time, T offset It is the offset time between the master clock and the slave clock.

[0030] Optionally, the frequency error compensation specifically includes:

[0031] When the slave clock receives a pcap_send_pkt_b message, it records a timestamp. After receiving pcap_send_pkt_b messages twice, it corrects the clock frequency of the slave clock by comparing the following two types of timestamp intervals: the timestamp interval received from the slave clock and the timestamp interval sent from the master clock.

[0032] After multiple exchanges of pcap_send_pkt_b messages, the formula for the master-slave frequency ratio is as follows:

[0033] (4)

[0034] Wherein, T1(1) is the sending time of the pcap_send_pkt_b message sent by the master clock to the slave clock in the first interaction, and T1(n) is the sending time of the pcap_send_pkt_b message sent by the master clock to the slave clock in the nth interaction; T2(1) is the receiving time when the slave clock receives and records the message in the first interaction, and T2(n) is the receiving time when the slave clock receives and records the message in the nth interaction; n≥2;

[0035] The minimum clock period of both the master clock and the slave clock is 8ns, so the frequency error compensation means that the clock system increases by 1ns after each total frequency compensation clock period has passed;

[0036] The frequency error compensation formula is as follows:

[0037] (5)

[0038] (6)

[0039] (7)

[0040] (8)

[0041] (9)

[0042] T offset is the phase error compensation data calculated in formula (3); F offset Represents the frequency parameter that needs to be compensated in the current clock state; F offset_clk It indicates the final frequency error compensation data obtained by superimposing the previously calculated frequency error compensation data and the newly calculated frequency error compensation data.

[0043] Optionally, the compensation filter includes a compensation data register and a comparator;

[0044] The compensation data register is used to record the previous compensation data and the current compensation data, and the comparator is used to check whether the current compensation data is out of range. The comparison rule is: if the absolute difference between the current compensation data and the previous compensation data is equal to or less than the comparison threshold, the current compensation data is used to update the time offset between the master and slave clocks; otherwise, the current compensation data is set to "0" and wait for the next measurement to avoid abnormal data affecting the time synchronization process.

[0045] On the other hand, a time synchronization system for a wireless deterministic network is provided, for implementing any of the above methods, the system comprising: an ARM-based handshake protocol design module, an FPGA-based clock system, a timestamp identification and capture module, a synchronization error compensation calculation module, a compensation data filtering module, and a compensation module;

[0046] Among them, the handshake protocol design module is used to design a handshake protocol based on the Linux kernel and generate a message with an identifier; the timestamp identification and capture module is used to identify and insert the timestamp when the message is sent through the MAC layer, and to identify and capture the timestamp when the message is received through the MAC layer; the synchronization error compensation calculation module is used to perform synchronization error compensation calculation based on the acquired timestamp information, and the synchronization error compensation includes phase error compensation and frequency error compensation; the compensation data filtering module is used to design a compensation filter, and the calculated compensation data is input into the compensation filter for screening; the compensation module is used to input the screened compensation data into the clock system for compensation to complete synchronization.

[0047] In another aspect, an electronic device is provided, the electronic device comprising:

[0048] processor;

[0049] A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are loaded and executed by the processor, the steps of the above-mentioned time synchronization method are implemented.

[0050] On the other hand, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores program code, and the program code can be called by a processor to execute the steps of the above-mentioned time synchronization method.

[0051] The beneficial effects brought about by the technical solution provided by the present invention include at least:

[0052] (1) A time synchronization architecture is built at the MAC layer of the hardware part for time synchronization. The location for inserting and capturing timestamps is set between the MAC layer data transceiver queue and OFDM to minimize the asymmetric delay of the protocol stack.

[0053] (2) A handshake protocol is designed to complete the transmission of time information. The frame format defined in the protocol contains a variety of time information, which improves the flexibility and scalability of the protocol stack.

[0054] (3) In order to solve the problem of difficulty in adjusting the hardware time and frequency compensation, a frequency compensation calculation method was designed. New frequency compensation data can be obtained through the timestamp information, phase compensation information, and the previous frequency compensation information. After each time the frequency compensation data has passed, 1ns is added or subtracted to complete the compensation, thus avoiding the increasing time error of the clock system after phase synchronization.

[0055] (4) A compensation data filtering module is designed after the synchronization error compensation calculation module to suppress abnormal compensation data from entering the local clock, thereby improving the stability of time synchronization and ultimately improving the synchronization accuracy and reliability of the entire time synchronization system.

[0056] A time synchronization method and system for a wireless deterministic network constructed by the present invention can effectively suppress the influence of asymmetric transmission delay in the wireless time synchronization mechanism and abnormal compensation data of wireless transmission on the time synchronization accuracy, thereby improving the accuracy and reliability of time synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0058] Figure 1 is a flow chart of a time synchronization method for a wireless deterministic network provided by an embodiment of the present invention;

[0059] Figure 2 is a schematic diagram of the architecture of a time synchronization method for a wireless deterministic network provided by an embodiment of the present invention;

[0060] Figure 3 is a schematic diagram of a high-reliability clock system provided by an embodiment of the present invention;

[0061] Figure 4 It is a schematic diagram of the synchronization message format provided by an embodiment of the present invention;

[0062] Figure 5 is a schematic diagram of phase error compensation provided by an embodiment of the present invention;

[0063] Figure 6 is a schematic diagram of frequency error compensation provided by an embodiment of the present invention;

[0064] Figure 7 is a schematic diagram of a compensation data filter provided by an embodiment of the present invention;

[0065] Figure 8 It is a schematic diagram of a WiFi time synchronization experimental platform provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0068] The embodiment of the present invention provides a time synchronization method for a wireless deterministic network, which can be implemented by an electronic device, which can be a terminal or a server. Figure 1 As shown, the processing flow of the method may include the following steps:

[0069] S1. Design a handshake protocol based on the Linux kernel to generate messages with identifiers;

[0070] S2, the message is identified and a timestamp is inserted when it is sent through the MAC layer, and the message is identified and a timestamp is captured when it is received through the MAC layer;

[0071] S3. Perform synchronization error compensation calculation according to the acquired timestamp information, wherein the synchronization error compensation includes phase error compensation and frequency error compensation;

[0072] S4, designing a compensation filter, and inputting the calculated compensation data into the compensation filter for screening;

[0073] S5. Input the screened compensation data into the clock system for compensation to complete synchronization.

[0074] Figure 2 Schematic diagram of the architecture of the time synchronization method described in the embodiment of the present invention. The radio frequency front end (RFFE) is a universal module for signal reception and transmission. The present invention does not modify this module, so it will not be further introduced. Figure 2(a) shows the software part, which includes the main part of the Linux application. In order to implement the IEEE 1588 basic mechanism of wireless network, the present invention designs a custom handshake protocol based on the Linux kernel. In linuxptp, software or hardware timestamps are configured for outgoing and incoming data packets. In the embodiment of the present invention, only the hardware timestamp in the MAC layer is enabled. A handshake protocol with an identifier is established to provide a channel for timestamp interaction. In the custom handshake protocol, three identification codes are created to enable the device to identify the frame type and give a response. These main functions pcap_send_pkt_b, pcap_send_pkt_c and pcap_seend_pkt_d are three different types of synchronization messages, and pthread_create and pcap-loop_pkt are used to create listening threads and loops to obtain synchronization fields in messages. Other Linux components in the wireless protocol stack remain unchanged, such as the wireless driver.

[0075] Figure 2 (b) shows the hardware part, which represents the newly designed module in the FPGA. The MAC layer of the wireless protocol stack and all newly designed time synchronization related modules are implemented on the FPGA. In the embodiment of the present invention, a highly reliable hardware clock system is designed to provide a nanosecond clock instead of a software clock. At the MAC layer output interface of the wireless protocol stack, once the message is identified as containing a special identifier field in the custom handshake protocol, a timestamp is inserted between the send queue and the OFDM processing module at the end of the message. Similarly, at the input interface, once the message is identified as containing a special identifier field in the custom handshake protocol, the timestamp is extracted and recorded, and the timestamp is parsed using the special identifier to obtain the time-related information required for synchronization. After all time records are collected, the timestamp information is immediately transmitted to the synchronization error compensation calculation module, and the phase error compensation and frequency error compensation are calculated respectively. The accuracy of the phase compensation can reach 1ns, and the accuracy of the frequency compensation can reach -192dB.

[0076] Then, due to the possible abnormal data, the compensation information may be inaccurate and may have unexpected effects on the clock system. In order to ensure the reliability and stability of time synchronization, a compensation filter is designed to filter out erroneous compensation data. Finally, the filtered compensation data enters the clock system, compensates the clock, and completes the synchronization.

[0077] Furthermore, if Figure 3 As shown, the clock system is a hardware clock system, including a mixed mode clock manager, a reset signal, a phase compensation interface, a frequency compensation interface, and an output end.

[0078] The hybrid mode clock manager IP core is used to obtain a clock with a frequency of 125 MHz to drive the clock system. The reset signal is used to reset and restart the clock system, and its input is the lock signal of the hybrid mode clock manager IP. When the 125Mhz clock is stable, the signal is pulled up. Therefore, the minimum scale of the clock system is 8ns. The phase compensation interface and the frequency compensation interface are connected to the compensation filter for correcting the clock system. The time information output by the output end is used as a timestamp: a 48-bit second clock and a 32-bit nanosecond clock. Finally, the time synchronization accuracy of the master clock and the slave clock is checked by the second pulse PPS, and the pulse width is configured to 80ns.

[0079] In the embodiment of the present invention, the insertion / capture position of the timestamp is set between the MAC layer data sending / receiving queue and the OFDM module, which can minimize the asymmetric delay of the protocol stack.

[0080] Furthermore, if Figure 4 As shown, the format of the message is designed based on the wireless frame, and the header includes the source MAC address, the destination MAC address and other related information. In order to record the time information used for synchronization, multiple special data fields are defined in the payload part of the wireless frame, including an identifier field and a time information field.

[0081] The identifier field is set to 2 bytes to distinguish three types of synchronization messages: pcap_send_pkt_b, pcap_send_pkt_c and pcap_seend_pkt_d. The special identification value of pcap_send_pkt_b is 0x86bb, the special identification value of pcap_send_pkt_c is 0x86cc, and the special identification value of pcap_seend_pkt_d is 0x869d. The signaling exchange process will be discussed later.

[0082] The time information field is set to 32 bytes, containing the time record and compensation data for each synchronization cycle. Therefore, the hardware compensation data can be transmitted to the Linux application layer and broadcast to other local network synchronization devices, which provides a reference for subsequent research on time synchronization in the LAN. Only the T4 and timestamp segments are enabled in the master clock, while the T4 segment is only disabled in the slave clock. In order to follow the data verification method used in the wireless protocol stack, the last data segment is a verification data segment to ensure data reliability.

[0083] Furthermore, clock compensation is divided into phase compensation and frequency compensation. The principles of phase synchronization methods are generally similar. The master and slave clocks record timestamps by exchanging time synchronization messages and calculate round-trip delays by measuring message interaction time. Assuming that the network transmission path is symmetrical, the slave clock can self-correct through the time difference to achieve synchronization with the master clock. Figure 5 As shown, the phase error compensation specifically includes:

[0084] The master clock (master node clock) sends a pcap_send_pkt_b message to the slave clock (slave node clock) and records the sending time T1. The slave clock receives the message and records the receiving time T2.

[0085] The slave clock starts the reverse transmission delay calculation by sending a pcap_send_pkt_c message to the master clock and records the sending time T3. The master clock records the receiving time T4 of the pcap_send_pkt_c message.

[0086] The master clock sends a pcap_send_pkt_d message carrying a timestamp of T4.

[0087] Since the design of the present invention adopts a single-step mode, the pcap_send_pkt_b message transmission time T1 is carried by itself, so the timestamp recorded in the embodiment of the present invention is closer to the physical layer. The four timestamps T1-T4 are collected to calculate the offset time between the master clock and the slave clock.

[0088] Assuming that the network transmission path is symmetrical, the link delay formula is as follows:

[0089] (1)

[0090] The slave clock calculates the offset time using the following formula:

[0091] (2)

[0092] (3)

[0093] Among them, T master is the master clock time, T slave is the slave clock time, T offset It is the offset time between the master clock and the slave clock.

[0094] The above calculation method is based on the situation that the clock frequencies between the master clock and the slave clock are the same. If they have different frequencies, the calculated offset will be offset after a long period of operation, so a frequency compensation method is needed. Not all synchronization messages need to participate in frequency compensation. When the slave clock receives a pcap_send_pkt_b message, it records a receiving timestamp. After receiving the pcap_send_pkt_b message twice, the clock frequency of the slave clock is corrected by comparing the following two types of timestamp intervals: the timestamp interval received from the slave clock and the timestamp interval sent from the master clock.

[0095] like Figure 6 As shown in the figure, after multiple exchanges of pcap_send_pkt_b messages, the formula for the master-slave frequency ratio is as follows:

[0096] (4)

[0097] Wherein, T1(1) is the sending time of the pcap_send_pkt_b message sent by the master clock to the slave clock in the first interaction, and T1(n) is the sending time of the pcap_send_pkt_b message sent by the master clock to the slave clock in the nth interaction; T2(1) is the receiving time when the slave clock receives and records the message in the first interaction, and T2(n) is the receiving time when the slave clock receives and records the message in the nth interaction; n≥2.

[0098] In the design of the present invention, it is considered that FPGA is not suitable for directly using division operations to control the clock frequency, and the minimum clock cycles of the master clock and the slave clock are both 8ns. Therefore, the frequency error compensation means that the clock system increases by 1ns after each total frequency compensation clock cycle has passed.

[0099] The frequency error compensation formula is as follows:

[0100] (5)

[0101] (6)

[0102] (7)

[0103] (8)

[0104] (9)

[0105] T offset is the phase error compensation data calculated in formula (3); F offset Represents the frequency parameter that needs to be compensated in the current clock state; F offset_clkIt indicates the final frequency error compensation data obtained by superimposing the previously calculated frequency error compensation data and the newly calculated frequency error compensation data.

[0106] Furthermore, it is necessary to screen the calculated compensation data. Several filtering algorithms such as Kalman filter can effectively reduce the random noise generated by clock deviation and frequency drift in the calculation and measurement process, but they are easily interfered by abnormal data, which seriously affects the filtering accuracy. Therefore, in the embodiment of the present invention, a compensation filter is designed to reduce the influence of abnormal data.

[0107] like Figure 7 As shown, the compensation filter includes a compensation data register and a comparator. The compensation data register is used to record the previous compensation data and the current compensation data, and the comparator is used to check whether the current compensation data is out of range, in order to ensure that abnormal values ​​do not affect the local clock. The comparison rule is: if the absolute difference between the current compensation data and the previous compensation data is equal to or less than the comparison threshold, the current compensation data is used to update the time offset between the master and slave clocks, otherwise, the current compensation data is set to "0" and wait for the next measurement to avoid abnormal data affecting the time synchronization process.

[0108] In the experimental verification part, an experimental platform is first established to evaluate the performance of the proposed wireless time synchronization method. Then the performance of the single-hop Wi-Fi synchronization designed under different network loads is analyzed, which are generated by mobile phones and personal computers (PCs) connected to the same AP.

[0109] The test bench for experimental research is as follows Figure 8As shown. The two wireless devices of the master and slave nodes are ZedBoard development kits with AD-FMCOMMS3. They are two openwifi software defined radio (SDR) boards without wireless time synchronization protocol. AD-FMComms3 is the FMC board of AD9361, which is a highly integrated RF agile transceiver. Based on the open source WiFi project, a full set of time synchronization modules are added to the MAC layer of the FPGA program part, and the hardware description file is compiled. Then the hardware description file is loaded into the two boards. After restarting the board, the hardware description file is successfully loaded. One of the two boards is configured as AP mode and the other is configured as client mode. The AP is connected to the client (slave node) and the mobile phone (iperf3 client) through WiFi, and the AP is connected to the PC (iperf3 server) through a wired network. The ARM part of the two wireless boards runs a custom handshake protocol. The master node periodically sends synchronization messages to the slave node. The slave node responds to the master node according to the handshake protocol. The MAC layer of the slave node collects the time information when the message is exchanged, calculates the phase\frequency error between itself and the master node, and compensates for it. The Iperf3 server and client apply network load to the AP to verify the stability of time synchronization and test the accuracy and reliability of the design.

[0110] All experiments were conducted in the laboratory, using oscilloscopes, logic analyzers, and analysis software to analyze the clock error logs and PPS signals of the master and slave local clocks. Through the analysis, the accuracy of time synchronization was measured. First, the comparison threshold of the compensation filter was determined through multiple short-term experiments. According to the requirements of synchronization accuracy, the approximate experimental range of the comparison threshold was about 1us. Then, the local optimal compensation threshold was used for subsequent long-term experiments. It should be noted that all experimental evaluations used results collected during the stable stage of time synchronization. Synchronization occurred twice per second between the master and slave devices, and the experiment lasted for one hour.

[0111] Correspondingly, an embodiment of the present invention also provides a time synchronization system for a wireless deterministic network, the system comprising: an ARM-based handshake protocol design module, an FPGA-based clock system, a timestamp identification and capture module, a synchronization error compensation calculation module, a compensation data filtering module and a compensation module.

[0112] Among them, the handshake protocol design module is used to design a handshake protocol based on the Linux kernel and generate a message with an identifier; the timestamp identification and capture module is used to identify and insert the timestamp when the message is sent through the MAC layer, and to identify and capture the timestamp when the message is received through the MAC layer; the synchronization error compensation calculation module is used to perform synchronization error compensation calculation based on the acquired timestamp information, and the synchronization error compensation includes phase error compensation and frequency error compensation; the compensation data filtering module is used to design a compensation filter, and the calculated compensation data is input into the compensation filter for screening; the compensation module is used to input the screened compensation data into the clock system for compensation to complete synchronization.

[0113] The system of this embodiment can be used to execute Figure 1 The technical solution of the method embodiment shown has similar implementation principles and technical effects, which will not be repeated here.

[0114] In summary, in the embodiment of the present invention, a method and system for time synchronization of wireless deterministic networks are proposed to solve the problem of insufficient time synchronization accuracy and stability of wireless deterministic networks, and a time synchronization architecture of wireless deterministic networks is designed and implemented, including the software part of the application layer and the hardware part of the MAC layer. The time synchronization mechanism proposed in the present invention runs on a development board containing ARM and FPGA components. In order to establish a time synchronization process similar to the PTP mechanism, a handshake protocol with a custom frame format is designed on the basis of the wireless frame; in addition, a hardware time synchronization related module is designed in the wireless MAC layer to identify special time synchronization messages so that the accurate hardware timestamp is closer to the PHY layer; in order to process time-related information with hardware, the hardware clock is frequency compensated, and a frequency compensation clock calculation method is designed for compensation; in order to make the time compensation value more stable, a compensation filter is designed to reduce abnormal values ​​that affect the time synchronization accuracy, thereby improving the accuracy and stability of time synchronization.

[0115] Therefore, compared with the prior art, the present invention has the following advantages:

[0116] (1) Wireless protocol stack hardware timestamp mechanism: To address the asymmetric transmission delay problem of time synchronization messages caused by protocol stack transmission delay, the timestamp insertion position is set between the MAC layer data transceiver queue and the OFDM module, which effectively reduces the asymmetric delay caused by the timestamp passing through the protocol stack, ensures the symmetry of the transmission path of time synchronization messages for time information exchange between synchronization devices, and improves the accuracy of time synchronization error measurement.

[0117] (2) Wireless synchronization frame handshake mechanism: To address the incompatibility between the hardware clock system and the protocol stack application layer, a handshake protocol with a custom frame format is designed at the application layer of the wireless network protocol stack, which improves the flexibility and scalability of the hardware clock system.

[0118] (3) Frequency compensation clock calculation method: In order to solve the problem of difficulty in adjusting the frequency compensation of the hardware clock system, a frequency compensation clock calculation method is designed. The frequency compensation is completed by increasing or decreasing the time of the frequency compensation clock by 1ns each time, thus avoiding the increasing time error of the clock system after phase synchronization.

[0119] (4) Time compensation filtering mechanism: In view of the uncertainty of wireless networks and the possible outlier problems in time synchronization error compensation data, a time error compensation filtering mechanism is designed. The absolute difference between the newly calculated compensation data and the last compensation data is continuously compared with the threshold as a parameter to adjust the credibility of the compensation data. Based on the credibility, it is determined whether the compensation data is allowed to correct the local clock, thereby improving the stability of time synchronization.

[0120] In an exemplary embodiment, the present invention further provides an electronic device, the electronic device comprising:

[0121] processor;

[0122] A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are loaded and executed by the processor, the steps of the above-mentioned time synchronization method are implemented.

[0123] In an exemplary embodiment, the present invention further provides a computer-readable storage medium, wherein at least one instruction is stored in the computer-readable storage medium, and the at least one instruction is loaded and executed by a processor to implement the steps of the time synchronization method as described above. For example, the computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0124] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0125] References in the specification to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it should be within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0126] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0127] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0128] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0129] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0130] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0131] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0132] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0133] The present invention covers any substitution, modification, equivalent method and scheme made on the essence and scope of the present invention. In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without the description of these details. In addition, in order to avoid unnecessary confusion about the essence of the present invention, well-known methods, processes, procedures, components and circuits are not described in detail.

[0134] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A time synchronization method for a wireless deterministic network, characterized in that: The following steps are involved: S1. Design a handshake protocol based on the Linux kernel to generate messages with identifiers; S2, the message is identified and a timestamp is inserted when it is sent through the MAC layer, and the message is identified and a timestamp is captured when it is received through the MAC layer; S3. Perform synchronization error compensation calculation according to the acquired timestamp information, wherein the synchronization error compensation includes phase error compensation and frequency error compensation; S4, designing a compensation filter, and inputting the calculated compensation data into the compensation filter for screening; S5. Input the screened compensation data into the clock system for compensation to complete synchronization.

2. The time synchronization method according to claim 1, characterized in that: The clock system is a hardware clock system, including a mixed mode clock manager, a reset signal, a phase compensation interface, a frequency compensation interface, and an output terminal; The mixed mode clock manager IP core is used to obtain a clock with a frequency of 125 MHz to drive the clock system; the reset signal is used to reset and restart the clock system; The phase compensation interface and the frequency compensation interface are connected to the compensation filter for correcting the clock system; the time information outputted from the output end is used as a timestamp, and the time synchronization accuracy of the master clock and the slave clock is checked through the second pulse PPS.

3. The time synchronization method according to claim 1, characterized in that: The insertion / capture position of the timestamp is set between the MAC layer data sending / receiving queue and the OFDM module.

4. The time synchronization method according to claim 1, characterized in that: The format of the message is designed based on a wireless frame, the header includes a source MAC address, a destination MAC address and related information, and a plurality of special data fields are defined in the payload part of the wireless frame, including an identifier field and a time information field; The identifier field is set to 2 bytes, which is used to distinguish three types of synchronization messages: pcap_send_pkt_b, pcap_send_pkt_c and pcap_seend_pkt_d; the time information field is set to 32 bytes, which includes the time record and compensation data of each synchronization cycle.

5. The time synchronization method according to claim 1, characterized in that: The phase error compensation specifically includes: The master clock sends a pcap_send_pkt_b message to the slave clock and records the sending time T1. The slave clock receives the message and records the receiving time T2. The slave clock starts the reverse transmission delay calculation by sending a pcap_send_pkt_c message to the master clock and records the sending time T3. The master clock records the receiving time T4 of the pcap_send_pkt_c message. The master clock sends a pcap_send_pkt_d message carrying a timestamp of T4; Collect four timestamps T1-T4 to calculate the offset time between the master clock and the slave clock; assuming that the network transmission path is symmetrical, the link delay formula is as follows: (1) The slave clock calculates the offset time using the following formula: (2) (3) Among them, T master is the master clock time, T slave is the slave clock time, T offset It is the offset time between the master clock and the slave clock.

6. The time synchronization method according to claim 5, characterized in that: The frequency error compensation specifically includes: When the slave clock receives a pcap_send_pkt_b message, it records a timestamp. After receiving pcap_send_pkt_b messages twice, it corrects the clock frequency of the slave clock by comparing the following two types of timestamp intervals: the timestamp interval received from the slave clock and the timestamp interval sent from the master clock. After multiple exchanges of pcap_send_pkt_b messages, the formula for the master-slave frequency ratio is as follows: (4) Wherein, T1(1) is the sending time of the pcap_send_pkt_b message sent by the master clock to the slave clock in the first interaction, and T1(n) is the sending time of the pcap_send_pkt_b message sent by the master clock to the slave clock in the nth interaction; T2(1) is the receiving time when the slave clock receives and records the message in the first interaction, and T2(n) is the receiving time when the slave clock receives and records the message in the nth interaction; n≥2; The minimum clock period of both the master clock and the slave clock is 8ns, so the frequency error compensation means that the clock system increases by 1ns after each total frequency compensation clock period has passed; The frequency error compensation formula is as follows: (5) (6) (7) (8) (9) T offset is the phase error compensation data calculated in formula (3); F offset Represents the frequency parameter that needs to be compensated in the current clock state; F offset_clk It indicates the final frequency error compensation data obtained by superimposing the previously calculated frequency error compensation data and the newly calculated frequency error compensation data.

7. The time synchronization method according to claim 1, characterized in that: The compensation filter includes a compensation data register and a comparator; The compensation data register is used to record the previous compensation data and the current compensation data, and the comparator is used to check whether the current compensation data is out of range. The comparison rule is: if the absolute difference between the current compensation data and the previous compensation data is equal to or less than the comparison threshold, the current compensation data is used to update the time offset between the master and slave clocks; otherwise, the current compensation data is set to "0" and wait for the next measurement to avoid abnormal data affecting the time synchronization process.

8. A time synchronization system for a wireless deterministic network, the system being used to implement the method according to any one of claims 1 to 7, characterized in that: The system includes: an ARM-based handshake protocol design module, an FPGA-based clock system, a timestamp recognition and capture module, a synchronization error compensation calculation module, a compensation data filtering module and a compensation module; Among them, the handshake protocol design module is used to design a handshake protocol based on the Linux kernel and generate a message with an identifier; the timestamp identification and capture module is used to identify and insert the timestamp when the message is sent through the MAC layer, and to identify and capture the timestamp when the message is received through the MAC layer; the synchronization error compensation calculation module is used to perform synchronization error compensation calculation based on the acquired timestamp information, and the synchronization error compensation includes phase error compensation and frequency error compensation; the compensation data filtering module is used to design a compensation filter, and the calculated compensation data is input into the compensation filter for screening; the compensation module is used to input the screened compensation data into the clock system for compensation to complete synchronization.

9. An electronic device, characterized in that: The electronic device comprises: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are loaded and executed by the processor, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, which can be called by a processor to execute the method according to any one of claims 1 to 7.

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