Storage device and operating method of storage device

Abstract

The invention relates to a storage device and an operation method of the storage device. The storage device may read a plurality of data units from a host memory buffer before entering a low power mode, disengage a communication link with a host after reading the plurality of data units, perform a background operation based on at least one data unit of the plurality of data units, and enter the low power mode after performing the background operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0089482, filed on Jul. 11, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a storage device that enters a low power mode after performing a background operation and an operating method of the storage device. Background Art

[0004] The storage device is a device that stores data according to a request from an external device such as a computer, a mobile terminal (eg, a smartphone or a tablet), or the like.

[0005] The storage device may include a memory for storing data and a controller for controlling the memory. The memory may be a volatile memory or a non-volatile memory. The controller may receive a command from an external device (i.e., a host) and perform or control an operation to read, write, or erase data in the memory included in the storage device according to the received command.

[0006] On the other hand, the storage device can access data stored in a host memory buffer in the host. The storage device can read the data stored in the host memory buffer and perform internal operations based on the read data. Summary of the invention

[0007] Embodiments of the present disclosure may provide a storage device capable of minimizing power consumed in performing background operations when a host enters a low power mode, and an operating method of the storage device.

[0008] In one aspect, an embodiment of the present disclosure may provide a storage device, comprising: a memory configured to store data; and a controller configured to receive a request to enter a low power mode from a host, read multiple data units from a host memory buffer before entering the low power mode, release a communication link with the host after reading the multiple data units, perform a background operation based on at least one of the multiple data units, and the storage device enters the low power mode after performing the background operation.

[0009] On the other hand, an embodiment of the present disclosure may provide an operating method of a storage device, the operating method comprising: before entering a low power mode, reading multiple data units from a host memory buffer; releasing a communication link with the host; performing a background operation based on at least one data unit among the multiple data units; and entering a low power mode after performing the background operation.

[0010] On the other hand, an embodiment of the present disclosure may provide a storage device, comprising: a memory configured to store data; and a controller configured to determine whether a condition for the storage device to enter a low power mode is met, transmit a signal indicating that the storage device enters a low power mode to a host when the condition is met, read a plurality of data units from a host memory buffer included in the host, release a communication link with the host after reading the plurality of data units, perform a background operation based on at least one of the plurality of data units, and the storage device enters the low power mode after performing the background operation.

[0011] According to an embodiment of the present disclosure, when a host enters a low power mode, power consumed in performing background operations can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic configuration diagram of a storage device according to an embodiment of the present disclosure.

[0013] Figure 2 It is schematically shown Figure 1 Block diagram of the memory.

[0014] Figure 3 The schematic structure of a system according to an embodiment of the present disclosure is shown.

[0015] Figure 4 A flowchart showing an operation of a storage device entering a low power mode according to an embodiment of the present disclosure is shown.

[0016] Figure 5 An example of multiple data units according to an embodiment of the present disclosure is shown.

[0017] Figure 6 An example is shown in which a storage device according to an embodiment of the present disclosure stores a plurality of data units.

[0018] Figure 7 Another example in which a storage device according to an embodiment of the present disclosure stores a plurality of data units is shown.

[0019] Figure 8 An operation of releasing a communication link between a storage device and a host according to an embodiment of the present disclosure is shown.

[0020] Fig. 9 An example in which a storage device according to an embodiment of the present disclosure performs a background operation is shown.

[0021] Fig.10 Another example of a storage device performing a background operation according to an embodiment of the present disclosure is shown.

[0022] Figure 11 to Figure 12The operation of the storage device after waking up from a low power mode according to an embodiment of the present disclosure is shown.

[0023] Fig.13 An operating method of a storage device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In this specification, references to "an embodiment", "another embodiment", etc. are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments.

[0025] Hereinafter, various embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. However, the present invention can be implemented in different forms and variations, and should not be construed as being limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the present disclosure will be complete and comprehensive, and the present invention will be fully conveyed to those skilled in the art to which the present invention belongs. In the present disclosure, the same reference numerals represent the same parts in the various drawings and embodiments of the present invention.

[0026] Method described herein, process and / or operation can be performed by code or instruction to be performed by computer, processor, controller or other signal processing device.Computer, processor, controller or other signal processing device can be those described herein or the element except the element described herein.Because the algorithm of the basis of formation method (or the operation of computer, processor, controller or other signal processing device) is described in detail, the code or instruction for implementing the operation of method embodiment can convert computer, processor, controller or other signal processing device into the special processor for performing the method herein.

[0027] When implemented at least partially in software, controllers, processors, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, and other signal generation and signal processing components may include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing device.

[0028] Figure 1 is a schematic configuration diagram of a storage device 100 according to an embodiment of the present disclosure.

[0029] Reference Figure 1 , the storage device 100 may include a memory 110 that stores data and a controller 120 that controls the memory 110 .

[0030] The memory 110 includes a plurality of memory blocks, and operates under the control of the controller 120. The operation of the memory 110 may include, for example, a read operation, a program operation (also referred to as a write operation), and an erase operation.

[0031] The memory 110 may include a memory cell array including a plurality of memory cells (also referred to as “cells”) storing data.

[0032] For example, the memory 110 may be implemented as various types of memory such as DDR SDRAM (double data rate synchronous dynamic random access memory), LPDDR4 (fourth generation low power double data rate) SDRAM, GDDR (graphic double data rate) SDRAM, LPDDR (low power DDR), RDRAM (Rambus dynamic random access memory), NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin transfer torque random access memory (STT-RAM).

[0033] The memory 110 may be implemented in a three-dimensional array structure. The embodiments of the present disclosure may be applied to a charge trap flash memory (CTF) in which a charge storage layer is configured by a dielectric layer and a flash memory in which a charge storage layer is configured by a conductive floating gate.

[0034] The memory 110 may receive a command and an address from the controller 120 and may access a region selected by the address in the memory cell array. The memory 110 may perform an operation indicated by the command on the region selected by the address.

[0035] The memory 110 may perform a programming operation, a reading operation, or an erasing operation. For example, when performing a programming operation, the memory 110 may program data to an area selected by an address. When performing a reading operation, the memory 110 may read data from an area selected by an address. In an erasing operation, the memory 110 may erase data stored in an area selected by an address.

[0036] The controller 120 may control a write (program) operation, a read operation, an erase operation, and a background operation of the memory 110. For example, the background operation may include at least one of a garbage collection (GC) operation, a wear leveling (WL) operation, a read reclaim (RR) operation, a bad block management (BBM) operation, and the like.

[0037] The controller 120 may control the operation of the memory 110 according to a request from an external device (eg, a host) located outside the storage device 100. However, the controller 120 may control the operation of the memory 110 even without a request from the host.

[0038] As non-limiting examples, the host may be a computer, an ultra mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID (radio frequency identification) device, and a mobile device capable of driving under human control or autonomous driving (e.g., a vehicle, a robot, or a drone), etc. Alternatively, the host may be a virtual reality (VR) device providing a 2D or 3D virtual reality image or an augmented reality (AR) device providing an augmented reality image. The host may be any of various electronic devices that require a storage device 100 capable of storing data.

[0039] The host may include at least one operating system (OS). The operating system may generally manage and control functions and operations of the host, and may control interoperability between the host and the storage device 100. The operating system may be classified into a general operating system and a mobile operating system according to the mobility of the host.

[0040] The controller 120 and the host may be separate devices from each other, or the controller 120 and the host may be integrated into one device. Hereinafter, for convenience of explanation, the controller 120 and the host are described as separate devices from each other.

[0041] Reference Figure 1 , the controller 120 may include a memory interface 122 , a control circuit 123 , and a host interface 121 .

[0042] The host interface 121 may provide an interface for communicating with the host. For example, the host interface 121 provides an interface using one of the following communication standards or protocols: USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI (Peripheral Component Interconnect) protocol, PCI-E (PCI-Express) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, IDE (Integrated Drive Electronics) protocol, and a dedicated protocol.

[0043] When receiving a request from the host, the control circuit 123 may receive the request through the host interface 121 and may perform an operation of processing the received command.

[0044] The memory interface 122 may be coupled with the memory 110 to provide an interface for communicating with the memory 110. That is, the memory interface 122 may provide an interface between the memory 110 and the controller 120 under the control of the control circuit 123.

[0045] The control circuit 123 may perform overall control operations of the controller 120 to control the operation of the memory 110. To this end, the control circuit 123 may include a processor 124 and a working memory 125, and may further include an error detection and correction circuit (ECC circuit) 126, for example.

[0046] The processor 124 may control the overall operation of the controller 120 and may perform logical operations. The processor 124 may communicate with the host through the host interface 121 and may communicate with the memory 110 through the memory interface 122.

[0047] The processor 124 may perform logic operations required to perform the functions of the flash translation layer (FTL). The processor 124 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the flash translation layer (FTL). The flash translation layer (FTL) may receive the logical block address (LBA) and convert the logical block address (LBA) into a physical block address (PBA) by using a mapping table.

[0048] Based on the mapping unit, the flash translation layer can adopt multiple address mapping methods. Representative address mapping methods include page mapping method, block mapping method and hybrid mapping method.

[0049] The processor 124 may randomize the data received from the host. For example, the processor 124 may randomize the data received from the host by using a set randomization seed. The randomized data may be provided to the memory 110 and may be programmed into the memory cell array of the memory 110.

[0050] In a read operation, the processor 124 may derandomize the data received from the memory 110. For example, the processor 124 may derandomize the data received from the memory 110 by using a derandomization seed. The derandomized data may be output to the host.

[0051] The processor 124 may execute firmware to control the operation of the controller 120. That is, in order to control the overall operation of the controller 120 and perform logical operations, the processor 124 may execute (drive) firmware loaded into the working memory 125 during startup. Hereinafter, the operation of the storage device 100 according to an embodiment of the present disclosure will be described as the processor 124 executing firmware that defines the corresponding operation.

[0052] The firmware is a program executed in the storage device 100 to drive the storage device 100, and may include various functional layers. For example, the firmware may include binary data respectively defining codes for executing the functional layers.

[0053] For example, the firmware may include at least one of a flash translation layer (FTL) that performs a conversion function between a logical address requested by the host to the storage device 100 and a physical address of the memory 110, a host interface layer (HIL) for analyzing a request from the host and transmitting a command corresponding to the request to the flash translation layer (FTL), and a flash interface layer (FIL) that transmits a command indicated by the flash translation layer (FTL) to the memory 110.

[0054] Such firmware may be loaded into the working memory 125 from, for example, the memory 110 or a separate nonvolatile memory (e.g., ROM or NOR flash memory) located outside the memory 110. When performing a boot operation after power-on, the processor 124 may first load all or part of the firmware into the working memory 125.

[0055] The processor 124 may execute the logic operation defined in the firmware loaded in the working memory 125 to control the overall operation of the controller 120. The processor 124 may store the result of executing the logic operation defined in the firmware in the working memory 125. The processor 124 may control the controller 120 according to the result of executing the logic operation defined in the firmware so that the controller 120 generates a command or a signal. When a portion of the firmware defining the logic operation to be executed is stored in the memory 110 but is not loaded in the working memory 125, the processor 124 may create an event (e.g., an interrupt) for loading the corresponding portion of the firmware from the memory 110 to the working memory 125.

[0056] The processor 124 may load metadata for driving firmware from the memory 110. The metadata, which is data for managing the memory 110, may include management information on user data stored in the memory 110, for example.

[0057] The firmware may be updated when the storage device 100 is manufactured or while the storage device 100 is running. The controller 120 may download new firmware from the outside of the storage device 100 and update the existing firmware to the new firmware.

[0058] In order to drive the controller 120, the working memory 125 can store firmware, program code, commands and data. The working memory 125 can be a volatile memory, which includes, for example, at least one of SRAM (static RAM), DRAM (dynamic RAM) and SDRAM (synchronous DRAM). On the other hand, in addition to the working memory 125, the controller 120 can also use a separate volatile memory (e.g., SRAM, DRAM) located outside the controller 120.

[0059] The error detection and correction circuit 126 may detect one or more error bits in the target data using an error correction code and correct the detected error bits. The target data may be, for example, data stored in the working memory 125 or data read from the memory 110.

[0060] The error detection and correction circuit 126 can decode the data by using an error correction code. The error detection and correction circuit 126 can be implemented using various code decoders. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

[0061] For example, when each read data is composed of a plurality of sectors, the error detection and correction circuit 126 can detect an error bit in each read data in units of sectors. A sector can refer to a data unit smaller than a page which is a read unit of a flash memory. The sectors constituting each read data can be matched with each other using addresses.

[0062] The error detection and correction circuit 126 may calculate a bit error rate (BER) based on a sector unit, and may determine whether the error is correctable. For example, when the bit error rate (BER) is higher than a reference value, the error detection and correction circuit 126 may determine that the corresponding sector is uncorrectable or failed. On the other hand, when the bit error rate (BER) is lower than a reference value, the error detection and correction circuit 126 may determine that the corresponding sector is correctable or passed.

[0063] The error detection and correction circuit 126 may sequentially perform error detection and correction operations on all read data. In the case where a sector included in the read data is correctable, the error detection and correction circuit 126 may omit the error detection and correction operations of the corresponding sector of the next read data. If the error detection and correction operations on all read data are completed in this manner, the error detection and correction circuit 126 may detect uncorrectable sectors in the last read data. There may be one or more sectors that are determined to be uncorrectable. The error detection and correction circuit 126 may transmit information (e.g., address information) about the sectors determined to be uncorrectable to the processor 124.

[0064] The bus 127 may provide a channel between the components 121, 122, 124, 125, and 126 of the controller 120. The bus 127 may include, for example, a control bus for transmitting various control signals, commands, etc., and a data bus for transmitting various data, etc.

[0065] Some of the above components 121, 122, 124, 125, and 126 of the controller 120 may be omitted, or some of the above components 121, 122, 124, 125, and 126 of the controller 120 may be integrated into one component. In addition to the above components 121, 122, 124, 125, and 126 of the controller 120, one or more other components may be added.

[0066] In the following, reference will be made to Figure 2 The memory 110 is described in more detail.

[0067] Figure 2 It is schematically shown Figure 1 A block diagram of the memory 110 is shown in FIG.

[0068] Reference Figure 2 , the memory 110 may include a memory cell array 210 , an address decoder 220 , a read and write circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0069] The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz, where z is a natural number of 2 or more.

[0070] In the plurality of memory blocks BLK1 to BLKz, a plurality of word lines WL and a plurality of bit lines BL may be provided, and a plurality of memory cells (MC) may be arranged.

[0071] The plurality of memory blocks BLK1 to BLKz may be coupled to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1 to BLKz may be coupled to the read and write circuit 230 through a plurality of bit lines BL.

[0072] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. For example, the plurality of memory cells may be nonvolatile memory cells and may be configured by nonvolatile memory cells having a vertical channel structure.

[0073] The memory cell array 210 may be configured by a memory cell array of a two-dimensional structure, or may also be configured by a memory cell array of a three-dimensional structure.

[0074] Each of the plurality of memory cells included in the memory cell array 210 may store at least 1 bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-layer cell (SLC) capable of storing 1 bit of data. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-layer cell (MLC) capable of storing 2 bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-layer cell (TLC) capable of storing 3 bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-layer cell (QLC) capable of storing 4 bits of data. In another example, the memory cell array 210 may include a plurality of memory cells, each of which may store 5 or more bits of data.

[0075] The number of data bits stored in each of the plurality of memory cells may be dynamically determined. For example, a single-layer cell storing 1 bit of data may be changed to a triple-layer cell storing 3 bits of data.

[0076] Reference Figure 2 , the address decoder 220 , the read and write circuit 230 , the control logic 240 , and the voltage generating circuit 250 may operate as peripheral circuits for driving the memory cell array 210 .

[0077] The address decoder 220 may be coupled to the memory cell array 210 through a plurality of word lines WL.

[0078] The address decoder 220 may operate under the control of the control logic 240 .

[0079] The address decoder 220 may receive an address through an input / output buffer in the memory 110. The address decoder 220 may decode a block address in the received address. The address decoder 220 may select at least one memory block according to the decoded block address.

[0080] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0081] During a read operation, the address decoder 220 may apply a read voltage Vread to a selected word line WL in a selected memory block, and may apply a pass voltage Vpass to the remaining unselected word lines WL.

[0082] During a program verification operation, the address decoder 220 may apply a verification voltage generated by the voltage generation circuit 250 to a selected word line WL in a selected memory block, and may apply a pass voltage Vpass to remaining unselected word lines WL.

[0083] The address decoder 220 may decode the column address in the received address and may send the decoded column address to the read and write circuit 230 .

[0084] The read operation and the program operation of the memory 110 may be performed in units of pages. An address received when requesting a read operation or a program operation may include at least one of a block address, a row address, and a column address.

[0085] The address decoder 220 may select a memory block and a word line according to the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read and write circuit 230.

[0086] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0087] The read and write circuit 230 may include a plurality of page buffers PB. The read and write circuit 230 may operate as a read circuit in a read operation of the memory cell array 210, and may operate as a write circuit in a write operation of the memory cell array 210.

[0088] The above-mentioned read and write circuit 230 may also be referred to as a page buffer circuit or a data register circuit including a plurality of page buffers PB. The read and write circuit 230 may include a data buffer responsible for a data processing function, and may further include a cache buffer responsible for a cache function.

[0089] A plurality of page buffers PB may be coupled to the memory cell array 210 through a plurality of bit lines BL. The plurality of page buffers PB may continuously supply a sensing current to the bit lines BL coupled to the memory cells to sense a threshold voltage (Vth) of the memory cells during a read operation and a program verification operation, and may latch sensing data by sensing a change in a current amount according to a program state of a corresponding memory cell using a sensing node.

[0090] The read and write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0091] During a read operation, the read and write circuit 230 temporarily stores read data by sensing data of a memory cell and then outputs the data DATA to an input / output buffer of the memory 110. In an embodiment, the read and write circuit 230 may further include a column selection circuit in addition to the page buffer PB or the page register.

[0092] The control logic 240 may be coupled with the address decoder 220, the read and write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory 110.

[0093] The control logic 240 may control the overall operation of the memory 110 under the control of the control signal CTRL. The control logic 240 may output a control signal for adjusting a precharge potential level of a sensing node of a plurality of page buffers PB.

[0094] The control logic 240 may control the read and write circuit 230 to perform a read operation of the memory cell array 210. The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used during a read operation in response to a voltage generation circuit control signal output from the control logic 240.

[0095] Each memory block of the above-described memory 110 may be configured by a plurality of pages corresponding to a plurality of word lines WL and a plurality of cell strings corresponding to a plurality of bit lines BL.

[0096] In the memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged to cross each other. For example, each of the plurality of word lines WL may be arranged in a row direction, and each of the plurality of bit lines BL may be arranged in a column direction. In another example, each of the plurality of word lines WL may be arranged in a column direction, and each of the plurality of bit lines BL may be arranged in a row direction.

[0097] The memory cell may be coupled to one of a plurality of word lines WL and one of a plurality of bit lines BL. A transistor may be provided in each memory cell.

[0098] For example, the transistor provided in each memory cell (MC) may include a drain, a source, and a gate. The drain (or source) of the transistor may be connected to the corresponding bit line BL directly or via another transistor. The source (or drain) of the transistor may be connected to the source line (which may be ground) directly or via another transistor. The gate of the transistor may include a floating gate surrounded by a dielectric and a control gate to which a gate voltage is applied from a word line WL.

[0099] In each memory block, a first selection line (also called a source selection line or a drain selection line) may be additionally disposed on the outside of a first outermost word line among the two outermost word lines that is closer to the read and write circuit 230, and a second selection line (also called a drain selection line or a source selection line) may be additionally disposed on the outside of a second outermost word line among the two outermost word lines.

[0100] At least one dummy word line may be additionally disposed between the first outermost word line and the first selection line. At least one dummy word line may also be additionally disposed between the second outermost word line and the second selection line.

[0101] The read operation and program operation (write operation) of the above-mentioned memory block may be performed in units of pages, and the erase operation may be performed in units of memory blocks.

[0102] Figure 3 Schematic structure of a system 10 according to an embodiment of the present disclosure is shown.

[0103] Reference Figure 3 , the system 10 may include a host 300 and a storage device 100 .

[0104] The host 300 may be connected to the storage device 100. The storage device 100 may be one of a plurality of devices connected to the host 300.

[0105] The host 300 may include a host memory buffer HMB. The host memory buffer HMB may be provided in a host memory (not shown) included in the host 300. For example, the host memory (not shown) may be a volatile memory (eg, SRAM, DRAM) included in the host 300.

[0106] The host memory buffer HMB may be located inside the host 300 , but may be used only by the memory device 100 .

[0107] The host 300 may transmit information related to the host memory buffer HMB to the memory device 100 so that the memory device 100 may access the host memory buffer HMB.

[0108] The host memory buffer HMB may store a plurality of data units DU. The storage device 100 may use the plurality of data units DU. For example, the plurality of data units DU may be part of user data stored in the storage device 100, or may be metadata of the user data.

[0109] The storage device 100 may include a memory 110 and a controller 120 .

[0110] The memory 110 may store data. The memory 110 may include a plurality of memory blocks for storing data.

[0111] The controller 120 may perform background operations (eg, garbage collection, wear leveling, read reclamation, trimming). Regardless of a request from the host 300, the controller 120 may perform background operations according to preset conditions.

[0112] The controller 120 may read a plurality of data units DU stored in the host memory buffer HMB from the host memory buffer HMB to perform a background operation.

[0113] The storage device 100 may enter a low power mode. When the storage device 100 enters a low power mode, the storage device 100 may operate to consume less power than in a normal mode. For example, the storage device 100 may deactivate some operations that are activated in a normal mode in the low power mode to reduce power consumption. Further, the term "deactivate" may also be referred to as "sleep", "idle", "standby", etc.

[0114] When certain conditions are met, the memory device 100 may enter a low power mode.

[0115] For example, the storage device 100 may enter the low power mode according to the request of the host 300. The host 300 may transmit the request to enter the low power mode to the storage device 100, and the controller 120 of the storage device 100 may receive the request and cause the storage device 100 to enter the low power mode.

[0116] As another example, when the conditions for entering the low power mode are met (e.g., no request is received from the host 300 within a predetermined period of time), the storage device 100 may automatically enter the low power mode. In this case, the controller 120 of the storage device 100 may transmit a signal to the host 300 indicating that the storage device 100 enters the low power mode.

[0117] When the storage device 100 is in the low power mode, power from the host 300 may be cut off and the host 300 may be inaccessible. At this time, the storage device 100 may not be able to access the host memory buffer HMB.

[0118] When the storage device 100 enters the low power mode, the controller 120 may enter the low power mode after executing a background operation that needs to be executed before entering the low power mode. For example, when it is determined that the storage device 100 is not ready to enter the low power mode before entering the low power mode, the storage device 100 may execute the background operation that has not been executed during the run time and then enter the low power mode.

[0119] The following will be Figure 4 Detailed description is given in .

[0120] Figure 4 A flowchart showing an operation of the storage device 100 entering a low power mode according to an embodiment of the present disclosure is shown.

[0121] Reference Figure 4 , before entering the low power mode, the controller 120 of the storage device 100 may read a plurality of data units DU stored in the host memory buffer HMB from the host memory buffer HMB of the host 300 ( S410 ).

[0122] After reading the plurality of data units DU, the controller 120 may release the communication link with the host 300 (S420). At this time, the controller 120 cannot access the host memory buffer HMB. After the communication link is released, the host 300 may deactivate some functions of the host 300 by entering a low power mode.

[0123] Then, the controller 120 may perform background operations based on one or more data units read from the host memory buffer HMB (S430). Since the communication link with the host 300 is released and the host memory buffer HMB cannot be accessed, the controller 120 may perform background operations using the data units read from the host memory buffer HMB.

[0124] After performing the background operation, the controller 120 may cause the storage device 100 to enter a low power mode ( S440 ).

[0125] The low power mode may be one of a plurality of candidate low power modes that enables the memory device 100 to consume power equal to or greater than a threshold power consumption. The power consumption amounts of the candidate low power modes may be different from each other.

[0126] For example, the low power mode may be a sleep mode. In the sleep mode, the storage device 100 cannot perform operations requested by the host 300, but can only perform background operations.

[0127] For example, the low power mode may be a deep sleep mode in which the memory device 100 may shut down components of the memory device 100 except for components required to maintain the data stored in the memory device 100 in order to save the data stored in the memory device 100 using minimum power.

[0128] The amount of power consumed by the memory device 100 may vary according to the mode of the memory device 100. For example, the amount of power consumed by the memory device 100 may decrease in the order of a mode for performing a write operation, a mode for performing a read operation, a sleep mode, and a deep sleep mode.

[0129] When entering a low power mode capable of consuming power equal to or greater than a threshold power consumption, the controller 120 may perform background operations, and after entering another low power mode, the controller 120 does not perform background operations.

[0130] Figure 5 An example of a plurality of data units DU according to an embodiment of the present disclosure is shown.

[0131] Reference Figure 5 , each of the plurality of data units DU may be mapping data indicating a mapping relationship between the logical address area LA and the physical address area PA.

[0132] In this case, the sizes of the logical address area LA and the physical address area PA indicated by the mapping data may be a multiple of the page size (eg, 4 KB).

[0133] The mapping data may include a plurality of sub-mapping data units, each of which may indicate a mapping relationship between a logical address region having a specified size and a physical address region.

[0134] The storage device 100 may load the mapping data using the host memory buffer HMB of the host 300. Due to resource limitations of the storage device 100, the storage device 100 may not ensure that there is enough space inside the storage device 100 to load necessary mapping data.

[0135] At this time, the storage device 100 may overcome the resource limitation of the storage device 100 by loading the mapping data into the host memory buffer HMB.

[0136] Figure 6 An example is shown in which the storage device 100 stores a plurality of data units DU according to an embodiment of the present disclosure.

[0137] Reference Figure 6 , the controller 120 of the storage device 100 may store a plurality of data units DU read from the host memory buffer HMB in the buffer BUF.

[0138] The controller 120 may quickly access the read plurality of data units DU by using the buffer BUF, and may access the plurality of data units DU even after the communication link with the host 300 is disconnected.

[0139] For example, the buffer BUF may be provided in the working memory 120 in the controller 120. As another example, the buffer BUF may be provided in a separate volatile memory.

[0140] Furthermore, the controller 120 may delete data previously stored in the buffer BUF before storing the read plurality of data units DU in the buffer BUF.

[0141] Figure 7 Another example in which a storage device according to an embodiment of the present disclosure stores a plurality of data units is shown.

[0142] Reference Figure 7 , the controller 120 of the storage device 100 may first store (dump) a plurality of data units DU read from the host memory buffer HMB in the memory 110, and the controller 120 may load all or part of the plurality of data units DU stored in the memory 110 into the buffer BUF.

[0143] Due to resource limitations of the controller 120, the size of the allocatable buffer BUF may be smaller than the total size of the multiple data units DU. In this case, all the multiple data units DU cannot be stored in the buffer BUF at the same time.

[0144] Therefore, the controller 120 may first store a plurality of data units DU in the memory 110 and then load a portion of them into the buffer BUF. The controller 120 may perform a background operation based on the data units loaded into the buffer BUF.

[0145] Figure 8 An operation of the storage device 100 releasing the communication link with the host 300 according to an embodiment of the present disclosure is shown.

[0146] Reference Figure 8 , the controller 120 of the storage device 100 may release the communication link with the host 300 before performing the background operation after reading the plurality of data units DU from the host memory buffer HMB.

[0147] For example, a communication link with the host 300 may be established based on a Compute eXpress Link (CXL) interface.

[0148] By releasing the communication link with the host 300 before the controller 120 performs the background operation, the host 300 can enter the low power mode by itself before the controller 120 completes the background operation. This is because the controller 120 does not access the host memory buffer HMB of the host 300 when performing the background operation.

[0149] Therefore, the host 300 can enter the low power mode faster and minimize power consumption.

[0150] Hereinafter, an embodiment in which the controller 120 performs a background operation will be described.

[0151] For example, the background operation may be a garbage collection (GC) operation or a trimming operation.

[0152] When performing the garbage collection operation, valid data stored in a specific area (eg, a sacrificed memory block) of the memory 110 may be migrated to another area. After the valid data is migrated to another area, a free space in the memory 110 may be secured by deleting the specific area.

[0153] When performing a trim operation, the data corresponding to a specific logical address may be invalid. In this way, the deletion of invalid data can be performed efficiently.

[0154] First, in Fig. 9 In the example of the background operation being a garbage collection operation, Fig.10 In the description, a case where the background operation is a trimming operation is taken as an example.

[0155] Fig. 9An example in which the storage device 100 performs a background operation according to an embodiment of the present disclosure is shown.

[0156] exist Fig. 9 In the background operation, the garbage collection operation is performed. When performing the garbage collection operation, the controller 120 of the storage device 100 can migrate data stored in a specific area of ​​the memory 110 to another area. The controller 120 can identify the location of the specific area through a physical address area corresponding to the specific area included in the memory 110.

[0157] exist Fig. 9 In this case, the controller 120 may migrate data corresponding to the logical address area LA1 from the physical address area PA1 to the physical address area PA1'. In this case, the data previously stored in the physical address area PA1 becomes invalid, and the data newly stored in the physical address area PA1' becomes valid.

[0158] At this time, among the data units DU stored in the buffer BUF, the data unit corresponding to the logical address area LA1 can be updated. Fig. 9 In the embodiment, the value of the physical address area included in the data unit corresponding to the logical address area LA1 can be updated from PA1 to PA1'.

[0159] Similarly, the controller 120 may migrate data corresponding to the logical address area LA2 from the physical address area PA2 to the physical address area PA2' In this case, the data previously stored in the physical address area PA2 becomes invalid, and the data newly stored in the physical address area PA2' becomes valid.

[0160] At this time, among the data units DU stored in the buffer BUF, the data unit corresponding to the logical address area LA2 may be updated. Fig. 9 In the embodiment, the value of the physical address area included in the data unit corresponding to the logical address area LA2 can be updated from PA2 to PA2'.

[0161] On the other hand, Fig. 9 Therefore, among the data units DU stored in the buffer BUF, the data unit corresponding to the logical address area LA3 is not updated.

[0162] On the other hand, the controller 120 may manage which data unit is updated among the data units DU stored in the buffer BUF through various data structures.

[0163] For example, the controller 120 may set a bitmap corresponding to the data unit DU stored in the buffer BUF, and may change the value of a bit corresponding to the updated data unit among data bits included in the bitmap.

[0164] As another example, the controller 120 may generate an update data unit list among the data units DU stored in the buffer BUF.

[0165] Fig.10 Another example of the storage device 100 performing a background operation according to an embodiment of the present disclosure is shown.

[0166] exist Fig.10 In the embodiment, the background operation is a trim operation. When the trim operation is performed based on the data unit, the controller 120 of the storage device 100 may invalidate the data corresponding to the logical address area indicated by the data unit. In this case, the mapping relationship between the logical address area and the physical address area included in the data unit may be released, and for this purpose, the valid physical address area may be deleted.

[0167] exist Fig.10 In this case, the controller 120 may release the mapping relationship between the logical address area LA1 and the physical address area PA1. In this case, the data in the physical address area PA1 stored in the memory 110 becomes invalid.

[0168] At this time, among the data units DU stored in the buffer BUF, the data unit corresponding to the logical address area LA1 may be updated. Fig.10 In the example, the value of the physical address included in the data unit corresponding to the logical address area LA1 can be deleted.

[0169] Similarly, the controller 120 may release the mapping relationship between the logical address area LA2 and the physical address area PA2. In this case, the data stored in the physical address area PA2 of the memory 110 becomes invalid.

[0170] At this time, among the data units DU stored in the buffer BUF, the data unit corresponding to the logical address area LA2 may be updated. Fig.10 In the example, the value of the physical address included in the data unit corresponding to the logical address area LA2 can be deleted.

[0171] exist Fig.10 In the embodiment, the controller 120 may not release the mapping relationship between the logical address area LA3 and the physical address area PA3. In this case, the data stored in the physical address area PA3 of the memory 110 becomes valid. Among the data units DU stored in the buffer BUF, the data unit corresponding to the logical address area LA3 is not updated.

[0172] Hereinabove, the operation when the memory device 100 enters the low power mode has been described.

[0173] Hereinafter, an operation after the memory device 100 wakes up from the low power mode will be described.

[0174] Figure 11 to Figure 12 The operation of the storage device 100 after waking up from the low power mode according to an embodiment of the present disclosure is shown.

[0175] exist Fig.11 In the embodiment, after the storage device 100 wakes up from the low power mode, the controller 120 of the storage device 100 may reset the communication link with the host 300. In this case, the controller 120 may access the host memory buffer HMB again.

[0176] At this time, the controller 120 may update the target data unit TGT_DU among the plurality of data units DU read from the host memory buffer HMB before entering the low power mode, to the host memory buffer HMB.

[0177] The target data unit TGT_DU may be a data unit read from the target area TGT_AREA of the host memory buffer HMB. In addition, the target data unit TGT_DU may be a data unit updated when a background operation is performed before entering the low power mode.

[0178] exist Fig.12 In the low power mode, the controller 120 may rewrite the target data unit TGT_DU into the target area TGT_AREA. That is, the controller 120 may write the updated target data unit TGT_DU again to the location where the target data unit TGF_DU was previously stored before entering the low power mode.

[0179] Fig.13 An operating method of the storage device 100 according to an embodiment of the present disclosure is shown.

[0180] Reference Fig.13 , the operating method of the storage device 100 may include: before entering the low power mode, reading a plurality of data units DU stored in the host memory buffer HMB from the host memory buffer HMB of the host 300 ( S1310 ).

[0181] As described above, the storage device 100 may enter the low power mode according to the request of the host 300, or may enter the low power mode by itself when the conditions for entering the low power mode are met.

[0182] Each of the plurality of data units DU may be mapping data indicating a mapping relationship between a logical address region and a physical address region.

[0183] The operating method of the storage device 100 may include releasing a communication link with the host 300 ( S1320 ).

[0184] The operation method of the storage device 100 may include performing a background operation based on at least one of the data units DU read from the host memory buffer HMB (S1330). The storage device 100 may release a communication link with the host 300 before performing the background operation.

[0185] The operating method of the storage device 100 may include entering a low power mode after performing a background operation ( S1340 ).

[0186] The operating method of the storage device 100 may further include resetting the communication link with the host 300 after waking up from the low power mode, and updating the target data unit TGT_DU among the data units DU read from the host memory buffer HMB into the host memory buffer HMB. The target data unit TGT_DU may be a data unit read from the target area TGT_AREA of the host memory buffer HMB and updated when performing a background operation.

[0187] Updating the target data unit TGT_DU in the host memory buffer HMB may rewrite the target data unit TGT_DU into the target area TGT_AREA.

[0188] Although the embodiments of the present disclosure are described for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only as descriptive rather than limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure should be interpreted in conjunction with the attached claims, and all equivalent schemes falling within the scope of the attached claims are encompassed. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A storage device, comprising: Memory, which stores data; as well as A controller, the controller: receiving a request from a host to enter a low power mode; prior to entering the low power mode, reading a plurality of data units from a host memory buffer; releasing the communication link with the host after reading the plurality of data units; performing a background operation based on at least one data unit of the plurality of data units; and After performing the background operation, the storage device enters the low power mode.

2. The storage device according to claim 1, in, The low power mode includes a candidate low power mode capable of consuming power equal to or greater than a threshold power consumption among a plurality of candidate low power modes.

3. The storage device according to claim 2, in, The low power mode includes a sleep mode in which only the background operation can be performed, or a deep sleep mode in which minimum power is used to retain data.

4. The storage device according to claim 1, in, Each of the plurality of data units includes mapping data indicating a mapping relationship between a logical address region and a physical address region.

5. The storage device according to claim 1, in, The controller stores the plurality of data units in the memory or in a buffer included in the controller.

6. The storage device according to claim 5, in, The controller further deletes data previously stored in the buffer before storing the plurality of data units in the buffer.

7. The storage device according to claim 1, in, The controller releases the communication link with the host before performing the background operation.

8. The storage device according to claim 7, in, The communication link is established based on a computing fast link interface, namely, a CXL interface.

9. The storage device according to claim 1, in, The background operation includes a garbage collection operation or a trimming operation.

10. The storage device according to claim 1, The controller further: After waking up from the low power mode, resetting the communication link with the host; and updating a target data unit among the plurality of data units into the host memory buffer, in, The target data unit is a data unit that is read from a target area of ​​the host memory buffer and updated when the background operation is performed.

11. The storage device according to claim 10, in, When the target data unit is updated, the target data unit is rewritten into the target area.

12. A method for operating a storage device, comprising: Prior to entering a low power mode, reading a plurality of data units from a host memory buffer; Release the communication link with the host; performing a background operation based on at least one data unit of the plurality of data units; as well as The low power mode is entered after performing the background operation.

13. The operating method according to claim 12, in, Each of the plurality of data units includes mapping data indicating a mapping relationship between a logical address region and a physical address region.

14. The operating method according to claim 12, in, The communication link is released before performing the background operation.

15. The operating method according to claim 12, further comprising: After waking up from the low power mode, resetting a communication link with the host; and updating a target data unit among the plurality of data units into the host memory buffer; The target data unit is a data unit that is read from a target area of ​​the host memory buffer and updated when the background operation is performed.

16. The operating method according to claim 15, in, Updating the target data unit includes rewriting the target data unit into the target area.

17. The operating method according to claim 12, further comprising: Prior to reading the plurality of data units, a request to enter the low power mode is received from the host.

18. The operating method according to claim 12, further comprising: determining whether a condition for the storage device to enter the low power mode is satisfied; as well as When the condition is met, a signal instructing the storage device to enter the low power mode is transmitted to the host.

19. A storage device, comprising: Memory, which stores data; as well as A controller, the controller: determining whether a condition for the storage device to enter a low power mode is satisfied; When the condition is met, transmitting a signal to a host instructing the storage device to enter the low power mode; reading a plurality of data units from a host memory buffer included in the host; releasing the communication link with the host after reading the plurality of data units; performing a background operation based on at least one data unit of the plurality of data units; and After performing the background operation, the storage device enters the low power mode.

20. The storage device according to claim 19, in, The controller determines that the condition is satisfied when no request is received from the host within a set period of time.

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