Efficient serial bus communication method

Abstract

The invention discloses an efficient serial bus communication method, and relates to the field of communication, and the efficient serial bus communication method comprises the following steps: 1, all nodes to send data compete, the node with the highest priority is competed through the respective bus priority sequence, the node with the highest priority obtains the bus control right, and the node with the highest priority obtains the bus control right; compared with the prior art, the method has the beneficial effects that each bus node is allowed to initiate active communication at the same time on the bus through a logic mechanism, the bus is scrambled through respective priorities, the nodes with high priorities can continuously send all data in a lossless manner, and the nodes with failed scrambling automatically exit and initiate when the bus is idle; compared with the traditional master-slave communication, the communication efficiency of the serial bus is higher; according to the method, the availability is improved by using the algorithm, frame loss communication errors possibly occur within 1000V without using an anti-interference filtering algorithm, and 4000V zero frame loss is realized by using the anti-interference filtering algorithm.

Description

Technical Field

[0001] The invention relates to the field of communication, and in particular to an efficient serial bus communication method. Background Art

[0002] Traditional multi-machine master-slave communication generally adopts polling, such as serial port UART, 485, etc. The host requires each node to send in sequence. For example, if 1 host has 64 slave nodes, the host needs to send 64 times and the slaves need to reply 64 times, accumulating 128 times, plus 128 safe communication intervals.

[0003] If the traditional master-slave communication has nodes with high timeliness, for example, a switch 1 can only wait for 5 sending cycles before sending once, time slice rotation is required. Assume that node 0 is the host, node 1 is a high real-time node, and the other nodes are 2 to 64; the sending order is: 0,1,0,2,0,3,0,4,0,5,0,1,0,6,0,7,0,8,0,9,0,1,0,10,0,11....0,64.

[0004] Therefore, when there are nodes with high time-efficiency in traditional master-slave communication, high-priority nodes must be allowed to jump the queue once in several sending cycles, which reduces bus utilization. When more high-priority nodes appear, bus utilization further decreases, which needs to be improved. Summary of the invention

[0005] The object of the present invention is to provide an efficient serial bus communication method to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] An efficient serial bus communication method comprises the following steps:

[0008] Step 1: All nodes that want to send data compete to select the node with the highest priority through their respective bus priority sequences. The node with the highest priority obtains bus control and sends a communication sequence.

[0009] Step 2: After the data of the node with the highest priority is sent, the bus is pulled high to the idle level;

[0010] Step 3: The idle time of the bus to the idle level reaches T id Or more than T id , repeat steps 1 and 2 in sequence until no node needs to send data.

[0011] As a further solution of the present invention: Step 1 specifically comprises the following steps:

[0012] Step 11, all nodes that want to send data are aligned when the edge of the start signal TS is generated, and the alignment error is a basic period Δt;

[0013] Step 12, after the start signal TS ends, all nodes that want to send data start bus grabbing, and all node controllers that want to send data send priority sequences bit by bit at the same time;

[0014] Step 13, determine the node corresponding to the priority sequence with the highest priority through logic;

[0015] Step 14: The node with the highest priority obtains bus control and sends a communication sequence.

[0016] As a further solution of the present invention: in step 13, the data bus is designed to be an AND logic structure, and all nodes that want to send data send 1 and 0 to the bus at the same time under the AND logic structure, and the bus AND logic operation result level is 0 level; the node that sends 1 reads the bus level and its own sending level is inconsistent, and the node that sends 1 automatically exits the bus competition and waits for idleness to appear; at this time, all nodes that send 0 will carry out the next round of competition and start sending the second bit of the priority sequence. Similarly, they will exit if there is inconsistency between sending and reading, until only the last node is left and is identified as the node with the highest priority at the moment; or after sending all priority sequences, the node with the highest priority has a completely consistent bus sending sequence and a bus reading sequence, and is identified as the node with the highest priority at the moment.

[0017] As a further solution of the present invention: the communication sequence includes an alignment signal, a contention sequence, a broadcast command, a special command, a number of bytes, data, a check byte, and encryption.

[0018] As a further solution of the present invention: the data segment adopts the RZ coding system, that is, the return-to-zero coding system, and the data bits all contain 0 and 1 levels, so as to prevent the data segment from having a continuous high level or a continuous low level.

[0019] As a further solution of the present invention: the bus priority sequence adopts a non-return-to-zero code system to improve the reliability of contention and reduce the speed and accuracy of sampling the basic period Δt.

[0020] As a further solution of the present invention: the idle time of the bus between data transmissions of different nodes is greater than the time for competing for the node with the highest priority.

[0021] As a further solution of the present invention: the efficient serial bus communication method also includes an anti-interference filtering algorithm, and the anti-interference filtering algorithm includes the following steps:

[0022] Step S4, IO level reading algorithm: adopt the continuous level reading method, if a certain level is collected more than twice in the continuous sampling interval, it is judged that the level is valid;

[0023] Step S5, module synchronization check when sending: when each module sends a level, the synchronization will determine whether the sending level and the receiving level are consistent at the receiving end. If they are inconsistent, it will be sent in error and the next round of competition will be restarted;

[0024] Step S6, using the pilot level to synchronize valid messages: before sending the priority sequence and data message, a pilot level will be added to synchronize the following data bits;

[0025] Step S7, data verification: at the end of data transmission, the last byte is not less than one as the data verification byte, and the algorithm is the characteristic operation value of all previous data, including cumulative sum, XOR, CRC, to ensure the correctness of data transmission;

[0026] Step S8, independent bus high level receiving reset: the receiving port always makes a high level reset judgment, and if a judgment greater than the specified duration occurs, the receiving state is reset;

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention allows each bus node to initiate active communication on the bus at the same time through a logical mechanism, and to compete for the bus through their respective priorities. High-priority nodes can continue to send all data without loss, and nodes that fail to compete automatically exit and wait until the bus is idle before initiating again. Compared with traditional master-slave communication, the serial bus communication efficiency is higher; the present invention uses an algorithm to improve availability. If the anti-interference filtering algorithm is not used, frame loss communication errors may occur within 1000V in the EFT machine test. By using the anti-interference filtering algorithm, zero frame loss in the EFT machine test of 4000V is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is the structure diagram of the protocol frame.

[0029] Figure 2 This is the timing diagram of the contention segment.

[0030] Figure 3 This is the timing diagram of the data segment.

[0031] Figure 4 This is a structural diagram for sending data.

[0032] Figure 5 Schematic diagram of the implementation of the anti-interference filtering algorithm.

[0033] Figure 6 This is a schematic diagram of the IO level reading algorithm in the anti-interference filtering algorithm to confirm the true value. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0035] See also Figure 1 , an efficient serial bus communication method, comprising the following steps:

[0036] Step 1: All nodes that want to send data compete to select the node with the highest priority through their respective bus priority sequences. The node with the highest priority obtains bus control and sends a communication sequence.

[0037] Step 2: After the data of the node with the highest priority is sent, the bus is pulled high to the idle level;

[0038] Step 3: The idle time of the bus to the idle level reaches T id Or more than T id , repeat steps 1 and 2 in sequence until no node needs to send data.

[0039] In this embodiment: Step 1 specifically includes the following steps:

[0040] Step 11, all nodes that want to send data are aligned when the edge of the start signal TS is generated, and the alignment error is a basic period Δt;

[0041] Step 12, after the start signal TS ends, all nodes that want to send data start bus grabbing, and all node controllers that want to send data send priority sequences bit by bit at the same time;

[0042] Step 13, determine the node corresponding to the priority sequence with the highest priority through logic;

[0043] Step 14: The node with the highest priority obtains bus control and sends a communication sequence.

[0044] In this embodiment: In step 13, the data bus is designed to be an AND logic structure, and all nodes that want to send data send 1 and 0 to the bus at the same time under the AND logic structure, and the bus AND logic operation result level is 0 level; the node that sends 1 reads the bus level and its own sending level is inconsistent, and the node that sends 1 automatically exits the bus competition and waits for idleness to appear; at this time, all nodes that send 0 will carry out the next round of competition and start sending the second bit of the priority sequence. Similarly, they will exit if there is inconsistency between sending and reading, until only the last node is left and is identified as the node with the highest priority at the moment; or after sending all priority sequences, the node with the highest priority has a completely consistent bus sending sequence and a bus reading sequence, and is identified as the node with the highest priority at the moment.

[0045] In this embodiment: the communication sequence includes an alignment signal, a competition sequence, a broadcast command, a special command, a byte number, data, a check byte, and encryption.

[0046] In this embodiment: the data segment adopts the RZ coding system, that is, the return-to-zero coding system, and the data bits all contain 0 and 1 levels to prevent the data segment from having a continuous high level or a continuous low level.

[0047] In this embodiment: the bus priority sequence adopts a non-return-to-zero code system to improve the reliability of contention and reduce the speed and accuracy of sampling the basic period Δt.

[0048] In this embodiment, the idle time of the bus between data transmissions of different nodes is greater than the time it takes to compete for the node with the highest priority. The priority sequence may maintain the same level for a long time, so it is necessary to ensure that the idle time is greater than the time it takes to compete for the node with the highest priority.

[0049] In this embodiment: the efficient serial bus communication method further includes an anti-interference filtering algorithm, and the anti-interference filtering algorithm includes the following steps:

[0050] Step S4, IO level reading algorithm: adopt the continuous level reading method, if a certain level is collected more than twice in the continuous sampling interval, it is judged that the level is valid;

[0051] Step S5, module synchronization check when sending: when each module sends a level, the synchronization will determine whether the sending level and the receiving level are consistent at the receiving end. If they are inconsistent, it will be sent in error and the next round of competition will be restarted;

[0052] Step S6, using the pilot level to synchronize valid messages: before sending the priority sequence and data message, a pilot level will be added to synchronize the following data bits;

[0053] Step S7, data verification: at the end of data transmission, the last byte of not less than one is a data verification byte, and the algorithm is the characteristic operation value of all the previous data, and commonly used methods include cumulative sum, XOR, CRC, etc., to ensure the correctness of data transmission; the cumulative sum, XOR, and CRC are just examples for illustration, and the characteristic operation value is not limited in actual use;

[0054] Step S8, independent bus high-level receiving reset: the receiving port always performs a high-level reset judgment. If a judgment is made that the duration is greater than the specified duration, the receiving state is reset.

[0055] See also Figure 5 The present invention uses an algorithm to improve availability. If the anti-interference filtering algorithm is not used, frame loss communication errors may occur within 1000V when the EFT machine is tested. By using the anti-interference filtering algorithm, zero frame loss is achieved in the EFT machine test of 4000V, reducing the problems of insufficient timeliness and decreased communication performance caused by frame loss, and improving the application scenarios of the bus and products that can adapt to highly complex interference.

[0056] See also Figure 6 , corresponding to the content in step S4, if a certain level is collected more than twice in the continuous sampling interval, it is judged that the level is valid.

[0057] In a specific embodiment:

[0058] 1. Bus level control method:

[0059] #1. Each node uses two timers with the same frequency to control input IO and output IO respectively;

[0060] #2. Under normal bus conditions, an external pull-up resistor is connected to clamp the bus at a high level, and the data bus is designed as an AND logic structure. Any node can pull down the bus level by outputting IO.

[0061] #3. Output IO uses open-drain output. When there is a sending request task, it sends the protocol frame pulse to the bus.

[0062] #4. Input IO, mainly has two functions:

[0063] A. Receive bus data according to the protocol frame structure;

[0064] B. When this machine has a sending task, it is responsible for detecting whether the output level is consistent with the input level. It not only plays a competitive role in the competition section, but also serves as a sending level self-check to ensure the correctness of the sent data.

[0065] #5. The guide level of each segment is mainly used to keep the sampling level aligned when sending the contention byte and data segment;

[0066] #6. Bus idle judgment condition: In the non-receiving state (the receiving program has not received the guide level, and the receiving program starts), the high level duration is greater than 7 basic cycles Δt (2 consecutive basic cycles Δt ensure that the guide level is not being received, and the other 4 basic cycles Δt are the maximum period of the tail level sent in the previous cycle).

[0067] 2. The protocol frame structure is as follows Figure 1 As shown, based on the master-slave-free structure, each node can send and receive freely according to the protocol frame structure.

[0068] 3. The competition segment timing diagram is as follows Figure 2 As shown, at this stage, by sending each node ID byte, the bus level is read at the input IO port to determine whether it is consistent with this node: if not consistent, the sending is interrupted; if consistent, the sending continues to complete the priority judgment.

[0069] 4. The data segment timing diagram is shown in Figure 3. At this stage, the system communication protocol data is sent to the bus. At the same time, the sending level and data are read and self-checked at the input IO port. If there is an error, the resending program is executed.

[0070] 5. Please refer to Figure 4 The checksum of the data segment is the sum of 0-N bytes, and the last eight bits are taken as the tail check byte.

[0071] 6. The bus reception adopts multi-level cache, and the received data is placed in the cache to ensure the reception status of the bus data at all times.

[0072] 7. When each node receives data, it uses a long high level reset. When the bus sends an error due to interference or other reasons, the receiving program can be reset to receive the next round of data again.

[0073] Let's take a refrigerator as an example to explain.

[0074]

[0075] The switch is a node operated by the user. When the door is opened, the refrigerator light needs to respond immediately. In this case, all switches are at high priority. For example, when switch 2 is actuated, when the bus has sent the current data, it can immediately or earlier obtain control during the snatch, broadcast the data to the bus, and light 2 can receive the data and turn on the light. At this moment, the mainboard also receives the switch 2 data and can record the number of switch actions for system control. In this case, it can be seen that data does not necessarily need a clear destination, but rather indicates its identity. Each node uses data on demand without the need for coordination by a host. In this example, if the mainboard issues a command "all sensors submit data", for example, 6 sensors in the system will automatically compete for but send various data in order, with an interval of bus idle time T id The queueing is completed in order and the efficiency is very high.

[0076] In traditional serial UART\485 and other master-slave communication, polling is generally adopted. The host requires each node to send in turn. For example, if 1 host has 64 slave nodes, the host needs to send 64 times, and the slaves need to reply 64 times, accumulating 128 times, plus 128 safety communication intervals. If there are nodes with high priority in the traditional master-slave communication, the bus utilization rate will decrease and the speed will be slower.

[0077] If the present invention takes 1+64 nodes as an example, only one command is needed, and 64 nodes are queued and sent closely in sequence, which is basically 65 times + 65*T id， The speed is increased by more than 1 times.

[0078] The present invention allows each bus node to initiate active communication on the bus at the same time through a logic mechanism, and compete for the bus through their respective priorities. High-priority nodes can continue to send all data without loss, and nodes that fail to compete automatically exit and wait until the bus is idle before initiating again. Compared with traditional master-slave communication, its serial bus communication efficiency is higher.

[0079] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered as exemplary and non-restrictive in all respects.

[0080] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An efficient serial bus communication method, characterized in that: The high-efficiency serial bus communication method comprises the following steps: Step 1: All nodes that want to send data compete to select the node with the highest priority through their respective bus priority sequences. The node with the highest priority obtains bus control and sends a communication sequence. Step 2: After the data of the node with the highest priority is sent, the bus is pulled high to the idle level; Step 3: The idle time of the bus to the idle level reaches T id Or more than T id , repeat steps 1 and 2 in sequence until no node needs to send data.

2. The high-efficiency serial bus communication method according to claim 1, characterized in that: Step 1 specifically includes the following steps: Step 11, all nodes that want to send data are aligned when the edge of the start signal TS is generated, and the alignment error is a basic period Δt; Step 12, after the start signal TS ends, all nodes that want to send data start bus grabbing, and all node controllers that want to send data send priority sequences bit by bit at the same time; Step 13, determine the node corresponding to the priority sequence with the highest priority through logic; Step 14: The node with the highest priority obtains bus control and sends a communication sequence.

3. The high-efficiency serial bus communication method according to claim 2, characterized in that: In step 13, the data bus is designed as an AND logic structure, and all nodes that want to send data send 1 and 0 to the bus at the same time under the AND logic structure, and the level of the bus AND logic operation result is 0 level; The node that sends 1 reads a bus level that is inconsistent with the level it sends. The node that sends 1 automatically exits the bus competition and waits for the idle state to appear. At this time, all nodes that sent 0 will enter the next round of competition and start sending the second bit of the priority sequence. If they encounter inconsistency between sending and reading, they will exit until only the last node is identified as the node with the highest current priority; or after sending all priority sequences, the node with the highest priority has consistent bus sending sequence and bus reading sequence, and is identified as the node with the highest current priority.

4. The high-efficiency serial bus communication method according to claim 1, characterized in that: The communication sequence includes alignment signal, competition sequence, broadcast command, special command, byte number, data, check byte, and encryption.

5. The high-efficiency serial bus communication method according to any one of claims 1 to 4, characterized in that: The data segment adopts the RZ coding system, that is, the return-to-zero coding system. The data bits contain 0 and 1 levels to prevent the data segment from having a continuous high level or a continuous low level.

6. The high-efficiency serial bus communication method according to any one of claims 1 to 4, characterized in that: The bus priority sequence adopts a non-return-to-zero code system to improve the reliability of contention and reduce the speed and accuracy of sampling the basic period Δt.

7. The high-efficiency serial bus communication method according to claim 1, characterized in that: The idle time of the bus between data transmissions of different nodes is greater than the time it takes to compete for the node with the highest priority.

8. The high-efficiency serial bus communication method according to claim 1, characterized in that: The efficient serial bus communication method further includes an anti-interference filtering algorithm, which includes the following steps: Step S4, IO level reading algorithm: adopt the continuous level reading method, if a certain level is collected more than twice in the continuous sampling interval, it is judged that the level is valid; Step S5, module synchronization check when sending: when each module sends a level, the synchronization will determine whether the sending level and the receiving level are consistent at the receiving end. If they are inconsistent, it will be sent in error and the next round of competition will be restarted; Step S6, using the pilot level to synchronize valid messages: before sending the priority sequence and data message, a pilot level will be added to synchronize the following data bits; Step S7, data verification: at the end of data transmission, the last byte is not less than one as the data verification byte, and the algorithm is the characteristic operation value of all previous data, including cumulative sum, XOR, CRC, to ensure the correctness of data transmission; Step S8, independent bus high-level receiving reset: the receiving port always performs a high-level reset judgment. If a judgment is made that the duration is greater than the specified duration, the receiving state is reset.

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