FPGA (Field Programmable Gate Array) test method and device

Abstract

The invention provides an FPGA (Field Programmable Gate Array) test method, which comprises the following steps that: a plurality of to-be-tested FPGA chips are in a serial test network, and a configuration chip obtains data streams of the plurality of to-be-tested FPGA chips from flash and inputs the data streams into the serial test network; when any to-be-tested FPGA chip in the serial test network is successfully configured, a pulse signal is generated, and test data transmission interfaces between the adjacent to-be-tested FPGA chips are controlled to be communicated for data stream transmission; a configuration control signal interface between the adjacent FPGA chips to be tested is controlled to be communicated, and the configuration control signal interface is used for returning a pulse signal; when any FPGA chip to be tested is configured successfully, a pulse signal is generated and transmitted back to the configuration chip, and the configuration chip retransmits the data stream to the next FPGA chip to be tested; and if the configuration of any FPGA chip to be tested fails, the configuration chip determines the position where the chip with the problem is configured and feeds back the position to the upper computer. The invention further provides an FPGA testing device.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA testing, and in particular relates to an FPGA testing method and device. Background Art

[0002] With the continuous development of chip manufacturing technology, the scale of field programmable gate arrays (FPGA) continues to expand, and the internal resources continue to be enriched, which requires more overhead for testing. Each chip needs to use different test stimuli to test the internal resources, logic circuits, DSP, etc. of FPGA. For batch testing, the complexity and overhead of FPGA are greatly increased.

[0003] Generally, the device for FPGA testing is a host computer, which communicates with multiple configuration chips through a bus. After receiving the code stream information from the host computer, the corresponding configuration chip configures the FPGA chip below. After the configuration is completed, it reports the configuration result. The host computer receives the result and processes the chip according to the result. In this test environment, as the number of chips increases, the number of configuration chips required also increases, the hardware overhead will be relatively large, and the host computer needs to interact with each configuration chip below, which makes the software level very cumbersome and complicated. In this case, a convenient, simple, and low-cost test solution and device is needed. When the number of chips to be tested increases, only the connection needs to be added to achieve the test goal, without the need for additional configuration chips. The increase in test chips will not cause the host computer protocol to need to be updated, and there is no need to rely on the FPGA's own hardware to implement it. Summary of the invention

[0004] The present invention provides an FPGA testing method and device, which can configure and test multiple FPGA chips only through one configuration chip. When an FPGA chip is added to the test system, there is no need to update the host computer protocol, and it does not rely on the FPGA's own hardware implementation.

[0005] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0006] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides an FPGA testing method, wherein multiple FPGA chips to be tested are in a serial test network, and the first FPGA chip to be tested communicates with a configuration chip; the configuration chip obtains the data stream of multiple FPGA chips to be tested from the flash and inputs it into the serial test network; if any FPGA chip to be tested in the serial test network is successfully configured, a pulse signal is generated to control the test data transmission interface between adjacent FPGA chips to be tested to be connected for data stream transmission; and the configuration control signal interface between adjacent FPGA chips to be tested is controlled to be connected for pulse signal feedback; if any FPGA chip to be tested is successfully configured, a pulse signal is generated to be transmitted back to the configuration chip, and after receiving the pulse signal, the configuration chip resends the data stream to the next FPGA chip to be tested; if any FPGA chip to be tested fails to be configured, the configuration chip determines the position of the chip with configuration problems and feeds back to the host computer.

[0007] If the configuration chip sends the configuration data stream to the FPGA chip to be tested for a preset time and does not receive a returned pulse signal, the configuration of the FPGA chip to be tested fails.

[0008] If any FPGA chip to be tested fails to be configured, replace the chip and continue configuration from the replaced chip.

[0009] When the configuration chip detects a pulse signal that is consistent with the number of FPGA chips to be tested, all FPGA chips to be tested are configured.

[0010] The test start signal of the end FPGA chip to be tested remains set to 1. After the configuration of all FPGA chips to be tested is completed, the end FPGA chip to be tested starts testing. After the test of any FPGA chip to be tested is completed, it sends a test completion signal, and controls the test results to be transmitted to the previous FPGA chip to be tested through the test result transmission interface until it is transmitted to the configuration chip. After the test of the FPGA chip to be tested is completed, the test completion signal is sent to the previous FPGA chip to be tested, and the test start signal of the previous FPGA chip to be tested is pulled high, and the previous FPGA chip to be tested starts testing.

[0011] When the test start signal of the FPGA chip to be tested is low, the test result transmission interfaces between adjacent FPGAs to be tested are connected.

[0012] The test results of the FPGA chip that has completed the test are directly transmitted to the configuration chip via the test result transmission interface.

[0013] After the configuration chip receives the test completion signal, a test is completed, and the configuration chip feeds back the test result to the host computer, and the host computer replaces the test chip data stream in the flash and starts the next round of chip testing.

[0014] The configuration chip determines whether there is an FPGA chip to be tested that has no feedback result based on the received test result.

[0015] Another technical solution of the present invention provides an FPGA testing device, comprising a host computer, a configuration chip and multiple FPGA chips to be tested; the host computer communicates with the configuration chip to receive test information sent back by the configuration chip and to update the data stream in the flash of the configuration chip; the flash in the configuration chip stores the data stream used for testing the FPGA chip to be tested; the multiple FPGA chips to be tested are connected by connecting the configuration control signal interface, the test data transmission interface, the test control signal interface and the test result transmission interface on each FPGA chip to be tested, so that the multiple FPGA chips to be tested form a serial test network.

[0016] The configuration control signal interface includes configuration control signal input and output interfaces set on each FPGA chip to be tested, which are used to return the pulse signal generated after the configuration of the FPGA chip to be tested is completed; the test data transmission interface includes test data input and output interfaces set on each FPGA chip to be tested. Under the control of the pulse signal generated after the configuration of the FPGA chip to be tested is successful, the test input and output interfaces between adjacent FPGA chips to be tested are connected to realize the transmission of data streams one by one; the test control signal interface includes test control signal input and output interfaces connected on each FPGA chip to be tested. After any FPGA chip to be tested completes the test, the generated test completion signal is transmitted to the next FPGA chip to be tested through the connected test control signal input and output interfaces, and the test start signal of the next FPGA chip to be tested is pulled high; the test result transmission interface includes test result input and output interfaces set on each FPGA chip to be tested. When the test start signal of any FPGA chip to be tested is low, the test result input and output interfaces are connected. When the test start signal of any FPGA chip to be tested is pulled high, the test result of the current FPGA chip to be tested begins to be transmitted to the adjacent FPGA chip to be tested through the test result output interface.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. When implementing batch FPGA chip testing, the present invention can realize the configuration and testing of batch chips through only one configuration chip. At the same time, adding FPGA chips to be tested in the system only requires adding connections, without changing the hardware or updating the host computer protocol.

[0018] 2. The test system of the present invention is simple, requiring only a host computer and a configuration chip, and the rest are chips to be tested, without requiring additional overhead.

[0019] 3. The test method of the present invention has strong scalability, and the bit width of the transmitted data can be determined according to user needs. At the same time, the user can also use the interface of the present invention to modify the format and type of the transmitted data according to needs.

[0020] 4. The configuration chip of the present invention can detect the location of the chip that failed to be configured and the location of the chip that failed to be tested. The configuration chip sends the collected location information of the chip that failed to be configured and the location information of the chip that failed to be tested to the host computer, and the host computer takes corresponding measures.

[0021] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a schematic diagram of the FPGA testing device of the present invention.

[0024] Figure 2 This is a flow chart of the FPGA testing method of the present invention. DETAILED DESCRIPTION

[0025] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0026] Example 1 Embodiment 1 provides an FPGA testing method, in which multiple FPGA chips to be tested are in a serial test network, and the first FPGA chip to be tested communicates with a configuration chip; the configuration chip obtains the data stream of multiple FPGA chips to be tested from the flash and inputs it into the serial test network; any FPGA chip to be tested in the serial test network is successfully configured, and a pulse signal is generated to control the test data transmission interface between adjacent FPGA chips to be tested to be connected for data stream transmission; and the configuration control signal interface between adjacent FPGA chips to be tested is controlled to be connected for pulse signal feedback; any FPGA chip to be tested is successfully configured, and a pulse signal is generated to be transmitted back to the configuration chip, and after receiving the pulse signal, the configuration chip resends the data stream to the next FPGA chip to be tested; if any FPGA chip to be tested fails to be configured, the configuration chip determines the location of the chip with configuration problems and feeds back to the host computer.

[0027] The following is combined with Figure 1 And attached Figure 2 The FPGA testing method of the present invention is explained in detail, see Figure 1 as well as Figure 2 The FPGA testing method of the present invention tests multiple FPGA chips to be tested through a configuration chip, wherein interfaces between the multiple FPGA chips are interconnected to form a serial test network, and the first FPGA chip communicates with the configuration chip.

[0028] Among them, each FPGA chip to be tested has multiple interfaces for signal and data transmission, which at least need to include an interface for test data transmission, a configuration control signal interface for FPGA configuration, a test control signal interface for controlling the start of the test, and a test result transmission interface for test result transmission. The present invention only defines the most basic interface. Of course, the test can set other signal groups as needed, and configure interfaces for these signal groups accordingly. For example, the signal group corresponding to the test stimulus is not defined in Example 1 of the present invention. This is because the test in Example 1 only requires clock stimulus, and the clock is provided by the test circuit and does not depend on the test chip. For adding other test stimuli, the corresponding signal group can be added accordingly and the control test stimulus signal interface can be configured.

[0029] by Figure 1For example, each FPGA chip of the present invention is provided with interfaces cfg_finish_m and cfg_finish_s for transmitting pulse signals generated when the FPGA chip is successfully configured, wherein the interface cfg_finish_m is used to send pulse signals, and the interface cfg_finish_s is used to receive pulse signals. When the FPGA chip to be tested is configured successfully, the interface cfg_finish_m outputs a pulse signal, and the interfaces cfg_finish_m and cfg_finish_s between different FPGA chips to be tested are connected, and the pulse signals are transmitted to the configuration chips one by one through the channel formed between the interface cfg_finish_s and the interface cfg_finish_m.

[0030] The interface cfg_port_m[m:0] (m is the total bit width of the data flow for configuring the FPGA chip, and the data flow can have control signal clock and data) and the interface cfg_port_s[m:0] are used to test data transmission. The interface cfg_port_m[m:0] and the interface cfg_port_s[m:0] between different FPGA chips to be tested are connected after the FPGA chip to be tested sends a pulse signal. After the pulse signal generated after the chip configuration is successful reaches the configuration chip, the configuration chip will send the test data flow again through the data transmission channel formed by the interface cfg_port_m[m:0] and the interface cfg_port_s[m:0] to the FPGA chip to be configured.

[0031] The test_start interface is used to control the start of the test, and the test_finish interface sends a test completion signal after the test is completed. When the test start signal is set to 1, the FPGA chip to be tested starts testing, and sends a test completion signal after the test is completed. The signal is transmitted to the test_start interface through the test_finish interface, and the test start signal of the next FPGA chip to be tested is pulled high. When the test completion signals are transmitted to the configuration chips one by one, a test is completed.

[0032] The test result output interface test_result_m[n:0] for transmitting the test result and the test result receiving interface test_result_s[n:0] for receiving the test result (n represents the bit width of the returned data). The interface test_result_m[n:0] and the interface test_result_s[n:0] are connected when the test start signal is 0. At this time, the test result can be directly transmitted to the configuration chip through the data return channel formed between the interface test_result_m[n:0] and the interface test_result_s[n:0] between different FPGA chips to be tested. When the test start signal is 1, the current FPGA chip to be tested will output the test result of the current FPGA chip through the interface test_result_m[n:0].

[0033] The specific process of the present invention is as follows: the host computer communicates with the configuration chip, and the flash in the configuration chip stores a data stream file for testing the FPGA chip to be tested. After the test starts, after the host computer configures the configuration chip (if the configuration chip supports flash loading data stream, two data streams are placed in the flash, the first is the data stream file of the configuration chip, and the second is the data stream file of the FPGA chip to be tested), the configuration chip takes the data stream of the chip to be tested from the flash, and converts the data stream into the configuration interface timing that meets the requirements (selected according to the interface timing supported by the chip to be tested), and the converted data stream is input to the interface cfg_port_s[m:0] of the FPGA chip to be tested 0 of the serial test network. After the FPGA chip to be tested 0 is configured successfully, a pulse signal is generated, and at the same time, the cfg_finish_s of the FPGA chip to be tested 0 is connected to the cfg_finish_m of the FPGA chip to be tested 1, and the cfg_port_m[m:0] of the FPGA chip to be tested 0 is connected to the cfg_port_s[m:0] of the FPGA chip to be tested 1. The generated pulse signal is transmitted back to the configuration chip through the cfg_finish_m of the FPGA chip to be tested 0. At this time, the configuration chip knows that the FPGA chip to be tested 0 is configured successfully, and sends it to The data stream of chip 0 to be configured is sent again. At this time, the data stream sent again is sent to FPGA chip 1 to be tested through the test data transmission channel between FPGA chip 0 to be tested and FPGA chip 1 to be tested (that is, the test data transmission channel formed between interface cfg_port_m[m:0] of FPGA chip 0 to be tested and interface cfg_port_s[m:0] of FPGA chip 1 to be tested), and FPGA chip 1 to be tested is configured again. When FPGA chip 1 to be tested is successfully configured, FPGA chip 1 to be tested generates a pulse signal, which is transmitted back to the configuration chip through the configuration control signal transmission channel between FPGA chip 0 to be tested and FPGA chip 1 to be tested (that is, the control signal transmission channel formed between interface cfg_finish_s of FPGA chip 0 to be tested and interface cfg_finish_m of FPGA chip 1 to be tested). At the same time, the pulse signal generated after FPGA chip 1 to be tested is successfully configured will control the test data transmission channel and configuration control signal transmission channel between FPGA chip 1 to be tested and FPGA chip 2 to be tested, and then continue the configuration of the next control chip.

[0034] In Example 1, during the process of configuring the FPGA chip to be tested, when the generated pulse signal is transmitted back to the configuration chip, it indicates that the FPGA chip to be tested is successfully configured. If the configuration chip sends a data stream for more than the set time without generating a pulse signal, it indicates that the configuration of a certain chip has failed. Since the multiple FPGA chips to be tested in Example 1 are configured one by one, pulse signals are generated one by one and returned to the configuration chip one by one, the returned pulse signal serial number can be queried to determine which FPGA chip to be tested has failed to be configured.

[0035] After all the FPGA chips to be tested are configured in Example 1 through the above-mentioned configuration method, the chips to be configured can be tested one by one (since the test data has been transmitted to the FPGA chip to be tested during configuration, only one test is required).

[0036] In order to facilitate the monitoring of the progress of system testing, Example 1 sets the test start signal (test_start) of the last FPGA chip N to be tested to 1. As long as all the FPGA chips to be tested are configured, the FPGA chip N to be tested starts testing. When the test of FPGA chip N to be tested is completed, the test completion signal of FPGA chip N to be tested will be pulled high, and the test completion signal will be transmitted through the interface test_finish on FPGA chip N to be tested to the interface test_start of FPGA chip N-1 to be tested, thereby pulling up the test start signal of FPGA chip N-1 to be tested. At this time, FPGA chip N-1 to be tested starts testing. When the test start signal on any FPGA chip to be tested is 0, the test result output interface test_result_m on the FPGA chip to be tested is connected to the test result receiving interface test_result_s on the adjacent FPGA chip to be tested, that is, when the test start signal of all FPGA chips to be tested is 0 (except for the last FPGA chip to be tested which is always set to 1, the rest of the initial values ​​are 0), the test result output interface of the adjacent FPGA chips to be tested is connected to the test result input interface, forming a test result transmission channel, and the test result of any FPGA chip to be tested can be transmitted to the configuration chip through the test result transmission channel. When the test start signal on any FPGA chip to be tested is pulled high to 1, the FPGA chip to be tested starts to be tested, and the test result of the FPGA chip to be tested is output through the interface test_result_m. Through this method, it can be ensured that the test system starts testing from the last FPGA chip to be tested, one by one from the back to the front, and outputs the test results one by one, and the test results can be directly output to the configuration chip. Therefore, the configuration chip can determine the location of the FPGA chip to be tested that has not returned test results in the test system according to the order of the returned test results (if there is no return within the timeout, it can be determined that the test of a certain FPGA chip to be tested has failed), and feed back the test failure results to the host computer, which can process them as needed.

[0037] In Example 1, since the test completion signal is transmitted one by one, when the configuration chip receives the test completion signal, it indicates that all test chips have completed the test, and one stimulus test is completed. The host computer will re-replace the test chip data stream in the flash and repeat the above test process.

[0038] The test method in Example 1 only needs one configuration chip to implement the test of multiple FPGA chips to be tested. Compared with the prior art, it is not necessary to set up multiple configuration chips, which reduces the cost of the device. In addition, the test method has strong scalability, and the transmission data bit width can be determined by the user. At the same time, the present invention stipulates a simple data transmission signal, and the user can add additional control signal groups as needed. In addition, the configuration chip of the present invention can monitor the position of the FPGA chip to be tested that fails to configure and test in real time, and the test results are sent to the host computer for the host computer to make decisions.

[0039] Example 2 Embodiment 2 provides an FPGA testing device, comprising a host computer, a configuration chip, and multiple FPGA chips to be tested; the host computer communicates with the configuration chip to receive test information sent back by the configuration chip and to update the data stream in the flash of the configuration chip; the flash in the configuration chip stores a data stream for testing the FPGA chip to be tested; the multiple FPGA chips to be tested are connected by connecting the configuration control signal interface, the test data transmission interface, the test control signal interface, and the test result transmission interface on each FPGA chip to be tested, so that the multiple FPGA chips to be tested form a serial test network.

[0040] The following is combined with Figure 1 A detailed description of an FPGA test device in this embodiment 2 is provided in Figure 2 The test device includes a configuration chip and a host computer that communicates with the configuration chip. The configuration chip has a flash that stores a data stream for testing the FPGA chip to be tested. Multiple chips to be tested are connected to each other through signal lines to form a serial test network. The first test chip of the serial test network is connected to the configuration chip through a signal line. The interface includes a configuration control signal interface, a test data transmission interface, a test control signal interface, and a test result transmission interface. The specific configuration control signal interface includes a configuration control signal input interface cfg_finish_s and a configuration control signal output interface cfg_finish_m set on each FPGA chip to be tested, which are used to return the pulse signal generated after the configuration of the FPGA chip to be tested is completed; The test data transmission interface includes a test data output interface cfg_port_m[m:0] and a test data input interface cfg_port_s[m:0] set on each FPGA chip to be tested. Under the control of the pulse signal generated after the FPGA chip to be tested is successfully configured, the test input and output interfaces between adjacent FPGA chips to be tested are connected to realize the transmission of data streams one by one. The test control signal interface includes a test control signal input interface (test_start interface) and a test control signal output interface (test_finish interface) connected on each FPGA chip to be tested. After any FPGA chip to be tested completes the test, the generated test completion signal is transmitted to the next FPGA chip to be tested via the connected test control signal input and output interfaces, and the test start signal of the next FPGA chip to be tested is pulled high; The test result transmission interface includes a test result output interface test_result_m[n:0] and a test result input interface test_result_n[n:0] set on each FPGA chip to be tested. When the test start signal of any FPGA chip to be tested is low, the test result input and output interfaces are connected. When the test start signal of any FPGA chip to be tested is pulled high, the output result of the FPGA chip to be tested begins to be transmitted to the adjacent FPGA chip to be tested through the test result output interface.

[0041] The configuration chip is an FPGA chip, and the FPGA chip is used as the configuration chip to facilitate connection with the interface of the FPGA chip to be tested.

[0042] The above is a detailed introduction to an FPGA testing method and device provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A FPGA testing method, characterized in that: Multiple FPGA chips to be tested are in a serial test network, and the first FPGA chip to be tested communicates with a configuration chip; The configuration chip obtains the data streams of multiple FPGA chips to be tested from the flash and inputs them into the serial test network; If any FPGA chip to be tested in the serial test network is configured successfully, a pulse signal is generated to control the connection of the test data transmission interface between adjacent FPGA chips to be tested for data stream transmission; And controlling the configuration control signal interface between adjacent FPGA chips to be tested to be connected for the return of pulse signals; If any FPGA chip to be tested is configured successfully, a pulse signal is generated and transmitted back to the configuration chip. After receiving the pulse signal, the configuration chip resends the data stream to the next FPGA chip to be tested. If any FPGA chip to be tested fails to be configured, the configuration chip determines the location of the chip with the configuration problem and feeds back to the host computer.

2. The FPGA testing method according to claim 1, characterized in that: If the configuration chip sends the configuration data stream to the FPGA chip to be tested for a preset time and does not receive a returned pulse signal, the configuration of the FPGA chip to be tested fails.

3. The FPGA testing method according to claim 1, characterized in that: If any FPGA chip to be tested fails to be configured, replace the chip and continue configuration from the replaced chip.

4. The FPGA testing method according to claim 1, characterized in that: When the configuration chip detects a pulse signal that is consistent with the number of FPGA chips to be tested, all FPGA chips to be tested are configured.

5. The FPGA testing method according to claim 1, characterized in that: The test start signal of the terminal FPGA chip to be tested is kept at 1, and after all the FPGA chips to be tested are configured, the terminal FPGA chip to be tested starts testing; After the test of any FPGA chip to be tested is completed, a test completion signal is sent out, and the test result is controlled to be transmitted to the previous FPGA chip to be tested via the test result transmission interface until it is transmitted to the configuration chip; After the FPGA chip to be tested completes the test, the test completion signal is sent to the previous FPGA chip to be tested, and the test start signal of the previous FPGA chip to be tested is pulled high, and the previous FPGA chip to be tested starts the test.

6. The FPGA testing method according to claim 5, characterized in that: When the test start signal of the FPGA chip to be tested is low, the test result transmission interfaces between adjacent FPGAs to be tested are connected.

7. The FPGA testing method according to claim 6, characterized in that: The test results of the FPGA chip that has completed the test are directly transmitted to the configuration chip via the test result transmission interface.

8. The FPGA testing method according to claim 5, characterized in that: After the configuration chip receives the test completion signal, a test is completed, and the configuration chip feeds back the test result to the host computer, and the host computer replaces the test chip data stream in the flash and starts the next round of chip testing.

9. The FPGA testing method according to claim 7, characterized in that: The configuration chip determines whether there is an FPGA chip to be tested that has no feedback result based on the received test result.

10. An FPGA testing device, characterized in that: Including host computer, configuration chip and multiple FPGA chips to be tested; The host computer communicates with the configuration chip to receive the test information sent back by the configuration chip and update the data stream in the flash of the configuration chip; The flash memory in the configuration chip stores a data stream for testing the FPGA chip to be tested; The multiple FPGA chips to be tested are connected to each other by connecting the configuration control signal interface, the test data transmission interface, the test control signal interface and the test result transmission interface on each FPGA chip to be tested, so that the multiple FPGA chips to be tested form a serial test network.

11. The FPGA testing device according to claim 10, characterized in that: The configuration control signal interface includes a configuration control signal input and output interface set on each FPGA chip to be tested, which is used to return the pulse signal generated after the configuration of the FPGA chip to be tested is completed; The test data transmission interface includes a test data input and output interface set on each FPGA chip to be tested. Under the control of a pulse signal generated after the FPGA chip to be tested is successfully configured, the test input and output interfaces between adjacent FPGA chips to be tested are connected to realize data stream transmission one by one; The test control signal interface includes a test control signal input and output interface connected on each FPGA chip to be tested. After any FPGA chip to be tested completes the test, the generated test completion signal is transmitted to the next FPGA chip to be tested via the connected test control signal input and output interface, and the test start signal of the next FPGA chip to be tested is pulled high; The test result transmission interface includes test result input and output interfaces set on each FPGA chip to be tested. When the test start signal of any FPGA chip to be tested is low, the test result input and output interfaces are connected. When the test start signal of any FPGA chip to be tested is pulled high, the test result of the current FPGA chip to be tested begins to be transmitted to the adjacent FPGA chip to be tested through the test result output interface.

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