Packaging structure of semiconductor device and semiconductor device

Abstract

The invention provides a packaging structure of a semiconductor device and the semiconductor device. The packaging structure comprises a substrate; the power module comprises a plurality of power sub-modules, each power sub-module comprises a positive electrode layer, a negative electrode layer, a decoupling structure, an upper bridge arm structure and a lower bridge arm structure, the positive electrode layer is located on one side of the negative electrode layer, the decoupling structure is electrically connected with the positive electrode layer and the negative electrode layer, the upper bridge arm structure is located on the positive electrode layer, and the lower bridge arm structure is located on the negative electrode layer. The lower bridge arm structure is located on one side of the cathode layer deviating from the anode layer; the positive bus is electrically connected with the positive layer, the negative bus is electrically connected with the negative layer, and the decoupling structure is electrically connected with the positive bus and the negative bus in parallel. When the upper bridge arm structure is switched on and off in a high-frequency state, high-frequency current can be generated, the current and a semiconductor chip nearby the decoupling structure with low impedance can form a very short loop, the area of the current loop is greatly reduced, and equivalent parasitic inductance in the high-frequency loop is reduced.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a packaging structure of a semiconductor device and a semiconductor device. Background Art

[0002] With the rise and continuous development of new energy power generation, electric vehicles and other industries, the demand for power semiconductor devices is increasing. Wide bandgap semiconductor materials represented by silicon carbide (SiC) are leading the development of power semiconductor devices towards higher voltage, higher frequency and greater power with their superior performance.

[0003] However, the packaging structure of SiC power devices still uses traditional Si power devices. In practical applications, traditional packaging will introduce a large number of parasitic parameters. The higher operating frequency of high-voltage SiC power devices will produce large voltage and current spikes on parasitic inductance and capacitance, threatening the safe and stable operation of power devices. In addition, in high-current applications, multiple chips need to be used in parallel to increase the current capacity. The difference in parasitic parameters will lead to uneven distribution of dynamic and static currents in parallel branches, reducing the reliability of the module. Therefore, in order to give full play to the advantages of SiC MOSFET power devices in high-voltage and high-power application scenarios, it is necessary to optimize the existing packaging structure and reduce the parasitic parameters introduced by the packaging. Summary of the invention

[0004] The main purpose of the present application is to provide a semiconductor device packaging structure and a semiconductor device, so as to at least solve the problem of high internal parasitic parameters and low reliability of the semiconductor device packaging structure in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a packaging structure of a semiconductor device is provided, comprising: a substrate; a plurality of drive modules and a power module, wherein the drive modules and the power modules are located on the substrate, the power module is located between adjacent drive modules, the power module comprises a plurality of power sub-modules, each of the power sub-modules comprises: a positive electrode layer, a negative electrode layer, a decoupling structure, an upper bridge arm structure and a lower bridge arm structure, the positive electrode layer is located on one side of the negative electrode layer, the decoupling structure is electrically connected to the positive electrode layer and the negative electrode layer respectively, the upper bridge arm structure is located on the positive electrode layer, and the lower bridge arm structure is located on the side of the negative electrode layer away from the positive electrode layer; a positive bus bar and a negative bus bar, wherein the positive bus bar is electrically connected to the positive electrode layer, the negative bus bar is electrically connected to the negative electrode layer, and the decoupling structure is electrically connected to the positive bus bar and the negative bus bar in parallel.

[0006] Optionally, each of the power submodules comprises: an upper structure and a lower structure, wherein: the upper structure comprises: an upper conductive layer and an upper heat dissipation layer, the upper conductive layer is located on the side of the upper heat dissipation layer away from the substrate, and the positive electrode layer and the negative electrode layer are part of the upper conductive layer; the lower structure comprises: a lower conductive layer, a lower heat dissipation layer and an intermediate layer, the intermediate layer is located between the upper heat dissipation layer and the lower heat dissipation layer, and the lower conductive layer is located between the lower heat dissipation layer and the substrate.

[0007] Optionally, the upper conductive layer includes an AC layer, the AC layer is located on a side of the negative electrode layer away from the positive electrode layer, and the AC layer is electrically connected to the drain of the lower bridge arm structure.

[0008] Optionally, the packaging structure also includes: a positive busbar and a negative busbar, wherein: the positive busbar is located on the positive electrode layer of the power sub-module, and the positive busbar is electrically connected to the drain of the upper bridge arm structure and the positive electrode of the external power supply, respectively; the negative busbar is located on the negative electrode layer of the power sub-module, and the negative busbar is electrically connected to the source of the lower bridge arm structure and the negative electrode of the external power supply, respectively, and the extension direction of the positive busbar is parallel to that of the negative busbar.

[0009] Optionally, the packaging structure further includes: a first connection layer and a second connection layer, wherein: the first connection layer is electrically connected to the source of the upper bridge arm and the second connection layer respectively, and the second connection layer is electrically connected to the AC layer.

[0010] Optionally, the packaging structure further includes a load busbar, which is located on the AC layer of the power submodule and is electrically connected to the AC layer and an external load, respectively.

[0011] Optionally, the packaging structure also includes: a PCB board, a gate lead terminal, a source lead terminal and a bonding wire, wherein: the PCB board is located on the side of the driving module away from the substrate; the gate lead terminal is electrically connected to the gate of the upper bridge arm structure or the lower bridge arm structure; the source lead terminal is electrically connected to the source of the upper bridge arm structure or the lower bridge arm structure; the bonding wires are respectively connected to the upper bridge arm structure and the upper conductive layer, or the bonding wires are respectively connected to the upper bridge arm structure and the PCB board.

[0012] Optionally, the decoupling structure includes two decoupling capacitors, and the decoupling capacitors are symmetrically distributed on the power sub-module.

[0013] Optionally, each of the power sub-modules includes a lower bridge arm structure, which is located on the AC layer of the power sub-module. The upper bridge arm structure and the lower bridge arm structure each include two semiconductor chips, and the upper bridge arm structure, the lower bridge arm structure and the decoupling capacitor are symmetrically distributed on the power sub-module.

[0014] According to another aspect of the present application, a semiconductor device is provided, including a packaging structure of the semiconductor device.

[0015] By applying the technical solution of the present application, a plurality of driving modules and power modules are provided in the packaging structure of the semiconductor device, and a plurality of power sub-modules are provided in the power sub-module, and a decoupling structure is provided in the power sub-module, and the decoupling structure is electrically connected to the positive electrode layer and the negative electrode layer respectively, and is electrically connected in parallel to the above-mentioned positive electrode bus and the above-mentioned negative electrode bus, and an upper bridge arm structure (including two parallel semiconductor chips) is also provided on the positive electrode layer, and when the upper bridge arm structure is switched in a high-frequency state, a high-frequency current is generated, and the current forms a loop with the semiconductor chip near the decoupling structure with low impedance, compared with the current flow path from the positive electrode bus through the upper bridge arm structure (with a current flow path inside), the positive electrode layer (with a circuit structure), the upper bridge arm structure of the negative electrode layer, the negative electrode bus and then to the positive electrode bus in the prior art, the present application forms a very short loop, greatly reducing the current loop area, and reducing the equivalent parasitic inductance in the high-frequency loop. The problem of high internal parasitic parameters and low reliability of the packaging structure of semiconductor devices in the prior art is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic top view of a semiconductor device packaging structure provided according to an embodiment of the present application is shown;

[0018] Figure 2 Shows Figure 1 A schematic diagram of the side view structure at the A-A' angle;

[0019] Figure 3 Shows Figure 1 A schematic diagram of the side view structure at the B-B' angle of view;

[0020] Figure 4 A schematic diagram of an internal power circuit of a semiconductor device packaging structure provided according to an embodiment of the present application is shown;

[0021] Figure 5A schematic top view of a packaging structure of a semiconductor device in the prior art is shown.

[0022] The above drawings include the following reference numerals:

[0023] 10. Substrate; 20. Drive module; 30. Power module; 31. Power submodule; 32. Positive electrode layer; 33. Negative electrode layer; 34. Decoupling structure; 35. Upper bridge arm structure; 361. Semiconductor chip; 362. Semiconductor chip; 363. Semiconductor chip; 364. Semiconductor chip; 37. Decoupling capacitor; 38. AC layer; 39. Lower bridge arm structure; 40. Positive busbar; 50. Negative busbar; 60. First connection layer; 70. Second connection layer; 80. Load busbar; 90. PCB board; 100. Gate lead terminal; 110. Source lead terminal; 120. Bonding wire; 130. Semiconductor device of prior art. DETAILED DESCRIPTION

[0024] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] As introduced in the background technology, in high current applications, multiple chips need to be used in parallel to increase the current capacity. The difference in parasitic parameters will lead to uneven distribution of dynamic and static currents in the parallel branches, reducing the reliability of the module. Therefore, in order to give full play to the advantages of SiC MOSFET power devices in high voltage and high power application scenarios, it is necessary to optimize the existing packaging structure and reduce the parasitic parameters introduced by the packaging.

[0028] The present application provides a semiconductor device packaging structure, such as Figures 1 to 3 As shown, it includes: a substrate 10; a plurality of driving modules 20 and a power module 30, wherein the driving modules 20 and the power modules 30 are located on the substrate 10, and the power modules 30 are located between adjacent driving modules 20. The power module 30 includes a plurality of power submodules 31, and each of the power submodules 31 includes: a positive electrode layer 32, a negative electrode layer 33, a decoupling structure 34, an upper bridge arm structure 35, and a lower bridge arm structure 39. The positive electrode layer 32 is located at the negative electrode layer 33. On one side, the decoupling structure 34 is electrically connected to the positive electrode layer 32 and the negative electrode layer 33 respectively, the upper bridge arm structure 35 is located on the positive electrode layer 32, and the lower bridge arm structure 39 is located on the side of the negative electrode layer 33 away from the positive electrode layer 32; the positive bus bar and the negative bus bar (not shown), the positive bus bar is electrically connected to the positive electrode layer 32, the negative bus bar is electrically connected to the negative electrode layer 33, and the decoupling structure 34 is electrically connected in parallel with the positive bus bar and the negative bus bar.

[0029] By having multiple drive modules and power modules in the packaging structure of the semiconductor device, the power module includes multiple power sub-modules, and a decoupling structure is set in the power sub-module, the decoupling structure is electrically connected to the positive electrode layer and the negative electrode layer respectively, and is electrically connected in parallel with the above-mentioned positive electrode bus and the above-mentioned negative electrode bus, and there is also an upper bridge arm structure (including two parallel semiconductor chips) and a lower bridge arm structure (including two parallel semiconductor chips) on the positive electrode layer. When the upper bridge arm structure is switched in a high-frequency state, a high-frequency current will be generated, and the current will form a loop with the semiconductor chip near the decoupling structure with low impedance. Compared with the flow path of the current flowing from the positive electrode bus through the upper bridge arm structure (with a current flow path inside), the positive electrode layer (with a circuit structure), the negative electrode layer, the lower bridge arm structure and then to the positive electrode layer in the prior art, the present application forms a very short loop, greatly reducing the current loop area and reducing the equivalent parasitic inductance in the high-frequency loop. The problem of high internal parasitic parameters and low reliability of the packaging structure of semiconductor devices in the prior art is solved.

[0030] In some optional embodiments, such as Figure 1 As shown, the decoupling structure 34 includes two decoupling capacitors 37 , and the decoupling capacitors 37 are symmetrically distributed on the power submodule 31 .

[0031] In the above optional implementation, if Figures 1 to 3 As shown, the semiconductor chips 361 and 362 of the upper bridge arm structure 35, the semiconductor chips 363 and 364 of the lower bridge arm structure 39, and the two decoupling capacitors 37 are symmetrically distributed in the power submodule 31, and the number of semiconductor chips in the lower bridge arm structure 39 and the upper bridge arm structure 35 is consistent with the number of decoupling capacitors 37. The upper bridge arm structure 35 includes two parallel semiconductor chips, the decoupling structure 34 includes two decoupling capacitors 37, and the two semiconductor chips and the two decoupling capacitors 37 are symmetrically distributed in the power submodule 31 (e.g., there is a semiconductor chip 361, a semiconductor chip 363 and a decoupling capacitor 37 on the left, and a semiconductor chip 362, a semiconductor chip 364 and a decoupling capacitor 37 on the right, which are symmetrical on both sides). The positive busbar is electrically connected to the external positive electrode, and the negative busbar is electrically connected to the external negative electrode.

[0032] In some optional embodiments, such as Figure 2 As shown, each of the power submodules includes: an upper structure and a lower structure, wherein: the upper structure includes: an upper conductive layer and an upper heat dissipation layer, the upper conductive layer is located on the side of the upper heat dissipation layer away from the substrate 10, and the positive electrode layer and the negative electrode layer are part of the upper conductive layer; the lower structure includes: a lower conductive layer, a lower heat dissipation layer and an intermediate layer, the intermediate layer is located between the upper heat dissipation layer and the lower heat dissipation layer, and the lower conductive layer is located between the lower heat dissipation layer and the substrate 10.

[0033] In the above optional implementation, the power submodule is composed of a lower conductive layer, a lower heat dissipation layer, an intermediate layer, an upper heat dissipation layer and an upper conductive layer from bottom to top, such as a lower copper layer, a lower ceramic layer, an intermediate copper layer, an upper ceramic layer and an upper copper layer from bottom to top. The ceramic layer material may be aluminum oxide, and the thickness may be 0.5 to 1.5 mm, and the copper layer thickness may be 0.2 to 0.4 mm. The upper conductive layer is etched to form a positive electrode layer and a negative electrode layer, and the positive electrode layer and the upper copper layer, the upper ceramic layer, the intermediate copper layer, the lower ceramic layer and the lower copper layer are sequentially arranged from bottom to bottom. The ceramic layer material is aluminum oxide with an insulating spacing between them, and the insulating spacing may be 1 to 2 mm.

[0034] In some optional embodiments, such as Figure 1 As shown, the upper conductive layer includes an AC layer 38 , which is located on a side of the negative electrode layer 33 away from the positive electrode layer 32 , and the AC layer 38 is electrically connected to the drain of the lower bridge arm structure 39 .

[0035] In the above optional implementation, if Figure 1As shown, the AC layer 38 is a part of the upper conductive layer and is obtained by etching the upper conductive layer. There is an insulation distance between the AC layer 38 and the negative electrode layer 33 , and the insulation distance may be 1 to 2 mm to ensure that there is no short circuit between the negative electrode layer 33 and the AC layer 38 .

[0036] In some optional embodiments, each of the above-mentioned power sub-module 31 includes a lower bridge arm structure 39, and the above-mentioned lower bridge arm structure 39 is located on the AC layer 38 of the above-mentioned power sub-module 31. The above-mentioned upper bridge arm structure 35 and the above-mentioned lower bridge arm structure 39 each include two semiconductor chips, and the above-mentioned upper bridge arm structure 35, the above-mentioned lower bridge arm structure 39 and the above-mentioned decoupling capacitor 37 are all symmetrically distributed on the above-mentioned power sub-module 31.

[0037] By adopting the method of nearby arrangement, a separate commutation circuit is formed between each chip and its corresponding decoupling capacitor. The decoupling capacitor is connected in parallel to the positive and negative busbars of the power submodule, so that the high-frequency circuit terminal inside the module is closed to the decoupling capacitor. During the shutdown process, the decoupling capacitor acts as an energy absorption unit to absorb the energy stored in the circuit inductance, and at the same time divides the parasitic inductance in the power circuit of the original power submodule into two parts, forming a very small high-frequency circuit between the chip and the decoupling capacitor, and the parasitic inductance outside the circuit is shielded by the decoupling capacitor, thereby greatly reducing the equivalent parasitic inductance in the high-frequency circuit.

[0038] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the above-mentioned packaging structure also includes: a positive busbar 40 and a negative busbar 50, wherein: the above-mentioned positive busbar 40 is located on the above-mentioned positive electrode layer 32 of the above-mentioned power sub-module 31, and the above-mentioned positive busbar 40 is electrically connected to the drain of the above-mentioned upper bridge arm structure 35 and the positive electrode of the external power supply respectively; the above-mentioned negative busbar 50 is located on the above-mentioned negative electrode layer 33 of the above-mentioned power sub-module 31, and the above-mentioned negative busbar 50 is electrically connected to the source of the above-mentioned lower bridge arm structure 39 and the negative electrode of the external power supply respectively, and the extension direction of the above-mentioned positive busbar 40 is parallel to that of the above-mentioned negative busbar 50.

[0039] In the above optional implementation, if Figure 1 and Figure 2 As shown, the positive busbar 40 and the negative busbar 50 span across four power submodules 31 and are arranged in parallel on the substrate 10. Among them, the positive busbar 40 is used to connect the drain of the upper bridge arm structure 35 with the external bus positive voltage, and the negative busbar 50 is used to connect the source of the lower bridge arm structure 39 with the external bus negative voltage. There are eight terminal pins at the bottom of each busbar, and the eight terminal pins are welded to four power submodules 31 in pairs, respectively, and the electrical interconnection between the power submodules 31 can be achieved through the substrate 10.

[0040] In addition to the self-inductance of the busbar, the mutual inductance between the busbars cannot be ignored. The essence of mutual inductance is the interaction of electromagnetic fields. When the upper bridge arm structure is turned on, the anti-parallel diode of the lower bridge arm structure is freewheeling, the current direction on the positive busbar is downward and gradually increases, and the current direction on the negative busbar is upward and gradually increases. Therefore, the positive and negative busbars will form magnetic fields in opposite directions in space, and the spatial magnetic field intensity will decrease, that is, the mutual inductance between the two busbars is negative, which cancels out the self-inductance of the busbars and reduces the parasitic inductance in the power circuit. On the premise of ensuring insulation requirements, the positive busbar and the negative busbar are placed closer to each other to enhance the mutual inductance effect, offset the electromagnetic field, and reduce parasitic inductance.

[0041] In some optional embodiments, such as Figures 1 to 3 As shown, the packaging structure further includes: a first connection layer 60 and a second connection layer 70 , wherein: the first connection layer 60 is electrically connected to the source of the upper bridge arm structure 35 and the second connection layer respectively, and the second connection layer 70 is electrically connected to the AC layer 38 .

[0042] In the above optional implementation, if Figures 1 to 3 As shown, the first connection layer 60 is used to realize the connection between the source of the upper bridge arm structure 35 and the AC layer 38. The upper bridge arm structure 35 and the AC layer 38 are connected by the second connection layer 70, and the second connection layer 70 can be an overhead copper bridge.

[0043] In some optional embodiments, such as Figures 1 to 3 As shown, the packaging structure further includes a load busbar 80 , which is located on the AC layer 38 of the power submodule 31 , and is electrically connected to the AC layer 38 and an external load, respectively.

[0044] In the above optional implementation, if Figures 1 to 3 As shown, the load busbar 80 is used to connect the load. There are eight end pins at the bottom of the load busbar 80. The eight end pins are grouped in pairs and are respectively welded on four power sub-modules 31. The electrical interconnection between the power sub-modules 31 can be achieved through the substrate 10.

[0045] In some optional embodiments, such as Figures 1 to 3As shown, the above-mentioned packaging structure also includes: a PCB board 90, a gate lead terminal 100, a source lead terminal 110 and a bonding wire 120, wherein: the above-mentioned PCB board 90 is located on the side of the above-mentioned driving module 20 away from the above-mentioned substrate 10; the above-mentioned gate lead terminal 100 is electrically connected to the gate of the above-mentioned upper bridge arm structure 35 or the above-mentioned lower bridge arm structure 39; the above-mentioned source lead terminal 110 is electrically connected to the source of the above-mentioned upper bridge arm structure 35 or the above-mentioned lower bridge arm structure 39; the above-mentioned bonding wire 120 is respectively connected to the above-mentioned upper bridge arm structure 35 and the above-mentioned upper conductive layer, or the above-mentioned bonding wire 120 is respectively connected to the above-mentioned upper bridge arm structure 35 and the above-mentioned PCB board 90.

[0046] In the above optional implementation, if Figures 1 to 3 As shown, each electrode of the semiconductor chip (361, 362, 363, 364) is connected to the PCB board 90 of the driving module 20 through a bonding wire 120. The power module 30 includes four completely symmetrical power submodules 31, each power submodule 31 includes two completely symmetrical parallel branches. Such a design makes the current flow path length in the parallel branches consistent, which is conducive to improving the dynamic and static current sharing characteristics between the parallel chips. A PCB board 90 is arranged on the top of the power module 30, and the PCB board 90 is used to connect the driving electrodes and driving terminals of the semiconductor chips (361, 362, 363, 364) to uniformly drive the semiconductor chips (361, 362, 363, 364) on the same bridge arm. The PCB board 90 has strong flexibility in circuit design. In addition, it also includes driving terminals located in the middle of the PCB board 90: a gate lead terminal 100 and a source lead terminal 110, and the source lead terminal 110 can be a Kelvin source drive terminal. The material of the bonding wire 120 may be aluminum.

[0047] In the above optional implementation, if Figure 4 As shown, the package module can also be split into a separate power submodule 31, which includes: a substrate 10, a positive electrode layer 32, a negative electrode layer 33, two decoupling capacitors 37, an AC layer 38, a positive busbar 40, a negative busbar 50, a first connection layer 60, a second connection layer 70, a load busbar 80 and a PCB board 90. The power circuit is similar to the above Figure 1 The power circuit in the circuit is the same, which is decoupling capacitor 37-terminal of positive busbar 40-semiconductor chip 361 (or-semiconductor chip 362)-first connection layer 60-second connection layer 70-semiconductor chip 363 (or semiconductor chip 364)-terminal of negative busbar 50-decoupling capacitor 37. The area surrounded by the power circuit is small, which greatly reduces the current circuit area and reduces the equivalent parasitic inductance in the high-frequency circuit.

[0048] The packaging module has a relatively symmetrical power circuit, which can achieve the mutual cancellation of magnetic fields of opposite currents to a large extent, and the packaging module is provided with a decoupling capacitor, which can achieve the decoupling of the parasitic inductance on the terminal, both of which can reduce the parasitic inductance of the entire module. The packaging structure omits unnecessary copper layers, and the electrical path of the AC output part is connected in an overhead manner, which reduces the parasitic capacitance of the entire module. The packaging structure in this application has lower parasitic parameters, which is conducive to improving the reliability and efficiency of the module during operation.

[0049] According to another aspect of the present application, a semiconductor device is provided, including the packaging structure of the semiconductor device described above.

[0050] The above-mentioned packaging module can be applied to the packaging of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and other semiconductor devices.

[0051] This application places the decoupling capacitor in the limited space inside the power submodule, requiring the capacity density of the decoupling capacitor to be as high as possible, while taking into account the capacitance attenuation of the capacitor under high voltage conditions. Multilayer ceramic capacitors have the highest volumetric efficiency among all capacitors and are low in cost, and are widely used in power electronic devices. The decoupling capacitor of this application can be a capacitor of the ST4040N112J103TJXW-1R model with a capacitance of 1.1nF.

[0052] The parasitic inductance from the positive electrode layer to the drain of each chip of the upper bridge arm structure is extracted by ANSYS Q3D electromagnetic simulation software when the decoupling capacitor is not added and when the decoupling capacitor is added. The extraction results are shown in Table 1.

[0053] Table 1

[0054]

[0055] Before adding the decoupling capacitor, the parasitic inductance values ​​between the parallel branches vary greatly, up to 101.47nH. The farther away from the power terminal, the greater the parasitic inductance value of the loop. After adding the decoupling capacitor, the parasitic inductance values ​​of the drain of each chip in the upper bridge arm structure are reduced, and the difference is significantly reduced, up to 3.31nH, indicating that the configuration of the decoupling capacitor can effectively reduce the parasitic inductance and promote the balance of the parasitic inductance inside the device.

[0056] like Figure 5 As shown, Figure 5The overall layout and terminal lead-out method of the package structure of the semiconductor device 130 of the prior art are similar to the commercial HybridPACK Drive power device of Infineon, and this module is used as a comparative module of this application. The parasitic parameters of the power loop of the above two structures at a frequency of 1 MHz are extracted using ANSYS Q3D electromagnetic simulation software, and the results are shown in Table 2.

[0057] Table 2

[0058]

[0059]

[0060] refer to Figure 5 The parasitic inductance of the package structure of the present application is 10.76nH, and the parasitic resistance is 13.97nH. Figure 5 The structure without decoupling capacitors shown in Figure 1 reduces the parasitic resistance by 13.7nH and 46.69nH.

[0061] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0062] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0063] 1) The packaging structure of the semiconductor device of the present application has multiple drive modules and power modules in the packaging structure of the semiconductor device, and the power module includes multiple power sub-modules. A decoupling structure is set in the power sub-module, and the decoupling structure is electrically connected to the positive electrode layer and the negative electrode layer respectively, and is electrically connected in parallel with the above-mentioned positive electrode bus and the above-mentioned negative electrode bus. There is also an upper bridge arm structure on the positive electrode layer. When the upper bridge arm structure is switched in a high-frequency state, a high-frequency current will be generated. The current will form a loop with the semiconductor chip near the decoupling structure with low impedance. Compared with the current flow path from the positive electrode bus through the upper bridge arm structure (with a current flow path inside), the positive electrode layer (with a circuit structure), the negative electrode layer, the lower bridge arm structure and then the positive electrode layer in the prior art, the present application forms a very short loop, greatly reducing the current loop area and reducing the equivalent parasitic inductance in the high-frequency loop. The problem of high internal parasitic parameters and low reliability of the packaging structure of semiconductor devices in the prior art is solved.

[0064] 2) The packaging structure of the semiconductor device of the present application adopts a close arrangement method so that a separate commutation circuit is formed between each chip and its corresponding decoupling capacitor. The decoupling capacitor is connected in parallel to the positive and negative busbars of the power sub-module, so that the high-frequency circuit terminal inside the module is closed to the decoupling capacitor. During the shutdown process, the decoupling capacitor acts as an energy absorption unit to absorb the energy stored in the loop inductance, and at the same time divides the parasitic inductance in the power circuit of the original power sub-module into two parts, forming a very small high-frequency circuit between the chip and the decoupling capacitor, and the parasitic inductance outside the loop is shielded by the decoupling capacitor, thereby greatly reducing the equivalent parasitic inductance in the high-frequency circuit.

[0065] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device packaging structure, characterized in that: include: substrate; A plurality of driving modules and power modules, wherein the driving modules and the power modules are located on the substrate, the power modules are located between adjacent driving modules, the power modules include a plurality of power submodules, each of the power submodules includes: a positive electrode layer, a negative electrode layer, a decoupling structure, an upper bridge arm structure and a lower bridge arm structure, the positive electrode layer is located on one side of the negative electrode layer, the decoupling structure is electrically connected to the positive electrode layer and the negative electrode layer respectively, the upper bridge arm structure is located on the positive electrode layer, and the lower bridge arm structure is located on the side of the negative electrode layer away from the positive electrode layer; A positive bus bar and a negative bus bar, the positive bus bar is electrically connected to the positive electrode layer, the negative bus bar is electrically connected to the negative electrode layer, and the decoupling structure is electrically connected in parallel to the positive bus bar and the negative bus bar.

2. The packaging structure according to claim 1, characterized in that: Each of the power submodules comprises: an upper structure and a lower structure, wherein: The upper structure comprises: an upper conductive layer and an upper heat dissipation layer, wherein the upper conductive layer is located on a side of the upper heat dissipation layer away from the substrate, and the positive electrode layer and the negative electrode layer are part of the upper conductive layer; The lower layer structure includes: a lower conductive layer, a lower heat dissipation layer and an intermediate layer, wherein the intermediate layer is located between the upper heat dissipation layer and the lower heat dissipation layer, and the lower conductive layer is located between the lower heat dissipation layer and the substrate.

3. The packaging structure according to claim 2, characterized in that: The upper conductive layer includes an AC layer, the AC layer is located on a side of the negative electrode layer away from the positive electrode layer, and the AC layer is electrically connected to the drain of the lower bridge arm structure.

4. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a positive busbar and a negative busbar, wherein: The positive busbar is located on the positive electrode layer of the power submodule, and the positive busbar is electrically connected to the drain of the upper bridge arm structure and the positive electrode of the external power supply respectively; The negative busbar is located on the negative electrode layer of the power submodule, and is electrically connected to the source electrode of the lower bridge arm structure and the negative electrode of an external power source respectively. The positive busbar is parallel to the extension direction of the negative busbar.

5. The packaging structure according to claim 3, characterized in that: The packaging structure further includes: a first connection layer and a second connection layer, wherein: The first connection layer is electrically connected to the source electrode of the upper bridge arm structure and the second connection layer respectively, and the second connection layer is electrically connected to the AC layer.

6. The packaging structure according to claim 3, characterized in that: The packaging structure further includes a load busbar, which is located on the AC layer of the power submodule and is electrically connected to the AC layer and an external load, respectively.

7. The packaging structure according to claim 3, characterized in that: The packaging structure further includes: a PCB board, a gate lead terminal, a source lead terminal and a bonding wire, wherein: The PCB board is located on a side of the driving module away from the substrate; The gate lead-out terminal is electrically connected to the gate of the upper bridge arm structure or the lower bridge arm structure; The source lead terminal is electrically connected to the source of the upper bridge arm structure or the lower bridge arm structure; The bonding wires are connected to the upper bridge arm structure and the upper conductive layer respectively, or The bonding wires are respectively connected to the upper bridge arm structure and the PCB board.

8. The packaging structure according to claim 1, characterized in that: The decoupling structure includes two decoupling capacitors, and the decoupling capacitors are symmetrically distributed on the power submodule.

9. The packaging structure according to claim 8, characterized in that: Each of the power sub-modules includes a lower bridge arm structure, which is located on the AC layer of the power sub-module. The upper bridge arm structure and the lower bridge arm structure each include two semiconductor chips. The upper bridge arm structure, the lower bridge arm structure and the decoupling capacitor are all symmetrically distributed on the power sub-module.

10. A semiconductor device, characterized in that: A packaging structure comprising the semiconductor device according to any one of claims 1 to 9.

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