Control method and apparatus for resistive random access memory array

Abstract

The present disclosure provides a control method and device for a resistive random access memory (RRAM) array, which can be applied to the field of microelectronics technology. The control method comprises: for each RRAM in the RRAM array, performing a shaping operation on the RRAM based on a first preset voltage, a second preset voltage and a third preset voltage to obtain an activated RRAM in an activated state; and performing a setting operation on the activated RRAM based on the first preset voltage and the second preset voltage to obtain a first target RRAM with a resistance value in a first preset range, wherein the first preset voltage, the second preset voltage and the third preset voltage are generated by sub-circuits of a voltage generation circuit, and the first preset voltage, the second preset voltage and the third preset voltage are not equal to each other.

Description

Technical Field

[0001] This disclosure relates to the field of microelectronics technology, and more specifically, to a control method and apparatus for resistive random access memory arrays. Background Technology

[0002] In computer system architecture, the processor and memory are the two core components. Each leap forward in memory technology brings about a revolution in the computer industry. Currently, the development speed of semiconductor memory far exceeds that of other types of integrated circuit devices. At the same time, the proportion of chip area occupied by semiconductor memory has also changed significantly. The proportion of semiconductor memory has increased from 20% to 80%. Therefore, the demand for semiconductor memory not only includes low cost, ultra-large capacity, and ultra-fast information transmission speed, but also ultra-high density information storage.

[0003] Resistive random access memory (RRAM) boasts a simple structure, low power consumption, compatibility with CMOS processes, and high integration density, making it a candidate for next-generation non-volatile memory. However, the peripheral circuitry associated with RRAM arrays is complex and occupies a large chip area, significantly reducing the integration density of integrated RRAM arrays. Summary of the Invention

[0004] In view of this, the present disclosure provides a control method and apparatus for resistive random access memory arrays.

[0005] One aspect of this disclosure provides a control method for a resistive random access memory (RRAM) array, comprising: for each RRAM in the RRAM array, performing a shaping operation on the RRAM based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated RRAM in an active state; and performing a setting operation on the activated RRAM based on the first preset voltage and the second preset voltage to obtain a first target RRAM with a resistance value within a first preset range, wherein the first preset voltage, the second preset voltage, and the third preset voltage are generated by each sub-circuit of a voltage generation circuit, and the first preset voltage, the second preset voltage, and the third preset voltage are not equal to each other.

[0006] According to an embodiment of this disclosure, the control method further includes: performing a reset operation on the first target resistive variable memory based on the first preset voltage, the second preset voltage, and the fourth preset voltage to obtain a second target resistive variable memory with a resistance value within a second preset range, wherein the fourth preset voltage is generated by a sub-circuit corresponding to the fourth preset voltage included in the voltage generation circuit, and the first preset voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage are not equal to each other.

[0007] According to embodiments of this disclosure, the above-described setting operation of the activated resistive switching memory based on the first preset voltage and the second preset voltage to obtain the first target resistive switching memory includes: performing a read operation on the activated resistive switching memory based on the first preset voltage and the second preset voltage; performing a write operation on the activated resistive switching memory based on the first preset voltage and the second preset voltage to obtain a target resistive switching memory with a resistance value of the first resistance value; performing a read operation on the target resistive switching memory with a resistance value of the first resistance value based on the first preset voltage and the second preset voltage to obtain a first current flowing through the target resistive switching memory with a resistance value of the first resistance value; and determining the target resistive switching memory with a resistance value of the first resistance value as the first target resistive switching memory when the first resistance value is determined to be within a first preset range based on the second preset voltage and the first current.

[0008] According to embodiments of this disclosure, the above-described method of resetting the first target resistive variable memory (RRAM) based on the first preset voltage, the second preset voltage, and the fourth preset voltage to obtain a second target RRAM with a resistance value within a second preset range includes: performing a read operation on the first target RRAM based on the second preset voltage and the fourth preset voltage; performing a write operation on the first target RRAM based on the first preset voltage and the fourth preset voltage to obtain a target RRAM with a resistance value of the second value; performing a read operation on the target RRAM with a resistance value of the second value based on the second preset voltage and the fourth preset voltage to obtain a second current flowing through the target RRAM with a resistance value of the second value; and, when the second resistance value is determined to be within a second preset range based on the second preset voltage and the second current, identifying the target RRAM with a resistance value of the second value as the second RRAM.

[0009] According to embodiments of this disclosure, the above-described shaping operation of each resistive random access memory (RRAM) in the RRAM array based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated RRAM includes: performing a read operation on the RRAM based on the first preset voltage and the second preset voltage; performing a write operation on the RRAM based on the first preset voltage, the second preset voltage, and the third preset voltage to obtain a RRAM with a resistance value of a third resistance value; performing a read operation on the RRAM with the third resistance value based on the first preset voltage and the second preset voltage to obtain a third current flowing through the RRAM with the third resistance value; and determining that the third resistance value is within a third preset range based on the second preset voltage and the third current, identifying the RRAM with the third resistance value as the activated RRAM.

[0010] According to embodiments of this disclosure, the above-mentioned write operation on the active-state resistive random access memory (RRAM) based on the first preset voltage and the second preset voltage to obtain a target RRAM with a resistance value of the first resistance value includes: applying the first preset voltage for a first preset duration to both the word line and bit line of the active-state RRAM, and applying the second preset voltage for a first preset duration to the source line of the active-state RRAM, thereby obtaining a target RRAM with a resistance value of the first resistance value; the above-mentioned write operation on the RRAM based on the first preset voltage, the second preset voltage, and the third preset voltage to obtain a RRAM with a resistance value of the third resistance value includes: applying the first preset voltage for a second preset duration to the word line of the RRAM, applying the second preset voltage for a second preset duration to the source line of the RRAM, and applying the third preset voltage for a second preset duration to the bit line of the RRAM, thereby obtaining a RRAM with a resistance value of the third resistance value.

[0011] According to an embodiment of this disclosure, the above-mentioned write operation on the first target resistive random access memory based on the first preset voltage and the fourth preset voltage to obtain a target resistive random access memory with a resistance value of the second resistance value includes: applying the fourth preset voltage for a third preset duration to the word line terminal of the first target resistive random access memory, applying the first preset voltage for a third preset duration to the source line terminal of the first target resistive random access memory, and grounding the bit line terminal of the first target resistive random access memory to obtain a target resistive random access memory with a resistance value of the second resistance value.

[0012] According to embodiments of this disclosure, the first preset voltage is greater than or equal to 1.7V and less than or equal to 1.8V; the second preset voltage is greater than or equal to 0.3V and less than or equal to 0.4V; the third preset voltage is greater than or equal to 4.9V and less than or equal to 5V; and the fourth preset voltage is greater than or equal to 3.2V and less than or equal to 3.3V.

[0013] Another aspect of this disclosure provides a control device for a resistive random access memory (RRAM) array, comprising: a control circuit for shaping each RRAM in the RRAM array based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated RRAM in an active state, and for setting the activated RRAM based on the first preset voltage and the second preset voltage to obtain a first target RRAM with a resistance value within a first preset range; and a voltage generation circuit including sub-circuits corresponding to each of the first preset voltage, the second preset voltage, and the third preset voltage, wherein the first preset voltage, the second preset voltage, and the third preset voltage are not equal to each other.

[0014] According to an embodiment of this disclosure, the control circuit is further configured to: perform a reset operation on the first target resistive variable memory based on the first preset voltage, the second preset voltage, and the fourth preset voltage, to obtain a second target resistive variable memory whose resistance value is within a second preset range; the voltage generation circuit further includes: a sub-circuit corresponding to the fourth preset voltage, the sub-circuit corresponding to the fourth preset voltage being used to generate the fourth preset voltage, wherein the first preset voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage are not equal to each other.

[0015] According to the control method for resistive random access memory (RRAM) arrays provided in this disclosure, each RRAM in the RRAM array is shaped based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated RRAM. Then, based on the first and second preset voltages, the activated RRAM is set to obtain a first target RRAM with a resistance value within a first preset range. The first, second, and third preset voltages are generated by sub-circuits of a voltage generation circuit. This allows the RRAM array to be controlled to perform shaping and setting operations based on three preset voltages of different amplitudes. Compared to related technologies, fewer amplitude types of preset voltages are used, thus the voltage generation circuit includes fewer sub-circuits for generating the preset voltages. This simplifies the structure of the voltage generation circuit, thereby simplifying the structure of the peripheral circuits, reducing the chip area occupied by the peripheral circuits, and greatly improving the integration density of the integrated RRAM array. Attached Figure Description

[0016] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of the integrated structure of a resistive random access memory array is shown.

[0018] Figure 2(a) schematically illustrates a pulse used to control the molding operation of a resistive switching memory;

[0019] Figure 2(b) schematically illustrates a pulse used to control a resistive random access memory to perform a set operation;

[0020] Figure 2(c) schematically illustrates a pulse used to control a resistive random access memory (RRAM) to perform a reset operation;

[0021] Figure 3 A flowchart illustrating a control method for a resistive random access memory array according to an embodiment of the present disclosure is shown schematically.

[0022] Figure 4 A schematic diagram illustrating pulses for controlling a resistive random access memory to perform a molding operation according to an embodiment of the present disclosure is shown.

[0023] Figure 5 The diagram illustrates a pulse for controlling a resistive random access memory to perform a set operation according to an embodiment of the present disclosure.

[0024] Figure 6 A schematic diagram illustrating a pulse for controlling a resistive random access memory to perform a reset operation according to an embodiment of the present disclosure;

[0025] Figure 7(a) schematically illustrates the resistive switching memory included in a resistive switching memory array according to an embodiment of the present disclosure;

[0026] Figure 7(b) schematically illustrates the voltage and current used in the control method for a resistive random access memory array according to an embodiment of the present disclosure when performing a set operation on the resistive random access memory;

[0027] Figure 7(c) schematically illustrates the voltage and current used in a control method for a resistive random access memory array according to an embodiment of the present disclosure during a reset operation of the resistive random access memory;

[0028] Figure 8 A schematic diagram of a control device for a resistive random access memory array according to an embodiment of the present disclosure is shown.

[0029] Figure 9(a) schematically shows the area percentage of the control unit and memory array for the resistive random access memory array in the overall integrated chip before optimization;

[0030] Figure 9(b) schematically illustrates the optimized control unit and memory array for the resistive random access memory array, and their area percentage within the overall integrated chip; and

[0031] Figure 10 The diagram illustrates the storage density of the resistive random access memory array before and after optimization using a control device for a resistive random access memory array according to an embodiment of the present disclosure. Detailed Implementation

[0032] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0034] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0035] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0036] Figure 1 The schematic diagram illustrates the integrated structure of a resistive random access memory (RRAM) array.

[0037] like Figure 1 As shown, the integrated structure of the resistive random access memory (RRAM) array includes three modules: a chip select, control, and read / write logic module 110, a RRAM array 120, and a decoder module. The decoder module includes a wordline decoder 131 and a bitline decoder 132.

[0038] The chip select (CS) and read / write control (R / W) signal terminals of the chip select, control, and read / write logic module 110 are connected to the system's control bus, receiving commands from the control bus and activating the chip select, control, and read / write logic module 110 to perform read / write operations on the resistive variable memory array 120. Based on the data received from the control circuit output, the chip select, control, and read / write logic module 110 controls the resistive variable memory array 120 to perform read / write operations. The entire control circuit is divided into three parts: first, an analog circuit (i.e., a voltage generation circuit) that generates specific read / write pulse signals; second, a logic control circuit for controlling the analog circuit, i.e., the logic used by the control circuit to control the analog circuit to implement certain digital signals for specific operations on the resistive variable memory cells in the resistive variable memory array 120; and third, a data read circuit for identifying the resistance state of the resistive variable memory cells in the resistive variable memory array 120.

[0039] Depend on Figure 1 It is evident that not only does the resistive random access memory (RRAM) itself directly affect the final integration and reliability of the device, but the complexity of the peripheral circuits used in RRAM, such as the control circuits, also directly affects the final integration and reliability of the device. Therefore, to further improve the mass production of RRAM, it is necessary not only to study the structure and materials of RRAM cells, but also to focus on the design of the peripheral read / write circuits used in RRAM.

[0040] Figure 2(a) schematically illustrates a conventional pulse used to control a resistive random access memory (RRAM) during a shaping operation. Figure 2(b) schematically illustrates a conventional pulse used to control a resistive random access memory (RRAM) during a setting operation. Figure 2(c) schematically illustrates a conventional pulse used to control a resistive random access memory (RRAM) during a reset operation.

[0041] As shown in Figures 2(a)-2(c), taking a 1T1R structure RRAM (Resistive Random Access Memory) as an example, in traditional cases, the peripheral circuit, such as a voltage generation circuit, needs to generate five different amplitude voltage pulse signals to control the RRAM array to perform read and write operations when performing forming and setting operations on the RRAM. Here, SL (Source Level End) represents the source line terminal of the RRAM, BL (Bit Line End) represents the bit line terminal of the RRAM, and WL (Word Line End) represents the word line terminal of the RRAM.

[0042] When performing shaping operations on the RRAM, and then repeatedly setting and resetting operations, the peripheral circuitry, such as the voltage generation circuit, needs to generate seven different voltage pulse signals of varying amplitudes to control the RRAM array to perform read and write operations. This makes the peripheral circuitry for the RRAM array complex and occupies a large and excessive chip area, which is detrimental to the final integration and greatly reduces the integration density of the integrated resistive random access memory array.

[0043] To address the technical problems existing in related technologies, this disclosure proposes a control method and apparatus for resistive random access memory arrays, which can be applied to the field of microelectronics technology.

[0044] Figure 3 A flowchart illustrating a control method for a resistive random access memory array according to an embodiment of the present disclosure is shown schematically.

[0045] like Figure 3 As shown, the control method for resistive random access memory array in this embodiment includes operations S310 to S320.

[0046] In operation S310, for each resistive random access memory in the resistive random access memory array, a shaping operation is performed on the resistive random access memory based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated resistive random access memory.

[0047] For example, the resistance value of an active resistive random access memory (RRAM) can be in the kΩ range. Successful molding can be confirmed when the RRAM resistance is below 700 kΩ.

[0048] In operation S320, based on the first preset voltage and the second preset voltage, the active state resistive variable memory is set to obtain the first target resistive variable memory whose resistance value is within the first preset range. The first preset voltage, the second preset voltage and the third preset voltage are generated by the sub-circuits of the voltage generation circuit, and the first preset voltage, the second preset voltage and the third preset voltage are not equal to each other.

[0049] For example, the first preset voltage can be generated by the first sub-circuit in the voltage generation circuit, the second preset voltage can be generated by the second sub-circuit in the voltage generation circuit, and the third preset voltage can be generated by the third sub-circuit in the voltage generation circuit.

[0050] According to embodiments of this disclosure, the first preset range can be selected based on actual conditions and is not limited herein. For example, the first preset range can be greater than 0 and less than or equal to 6KΩ.

[0051] According to the control method for resistive random access memory (RRAM) arrays provided in this disclosure, each RRAM in the RRAM array is shaped based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated RRAM. Then, based on the first and second preset voltages, the activated RRAM is set to obtain a first target RRAM with a resistance value within a first preset range. The first, second, and third preset voltages are generated by sub-circuits of a voltage generation circuit. This allows the RRAM array to be controlled to perform shaping and setting operations based on three preset voltages of different amplitudes. Compared to related technologies, fewer amplitude types of preset voltages are used, thus the voltage generation circuit includes fewer sub-circuits for generating the preset voltages. This simplifies the structure of the voltage generation circuit, thereby simplifying the structure of the peripheral circuits, reducing the chip area occupied by the peripheral circuits, and greatly improving the integration density of the integrated RRAM array.

[0052] According to embodiments of this disclosure, for example, Figure 3The operation S310 shown describes a shaping operation performed on each resistive random access memory (RRAM) in the RRAM array based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated RRAM. This operation may include the following steps: performing a read operation on the RRAM based on the first and second preset voltages; performing a write operation on the RRAM based on the first, second, and third preset voltages to obtain a RRAM with a third resistance value; performing a read operation on the RRAM with the third resistance value based on the first and second preset voltages to obtain a third current flowing through the RRAM with the third resistance value; and determining that the third resistance value is within a third preset range based on the second preset voltage and the third current, identifying the RRAM with the third resistance value as an activated RRAM.

[0053] According to embodiments of this disclosure, the first preset voltage can be greater than or equal to 1.7V and less than or equal to 1.8V. The second preset voltage can be greater than or equal to 0.3V and less than or equal to 0.4V. The third preset voltage can be greater than or equal to 4.9V and less than or equal to 5V.

[0054] For example, the first preset voltage can be 1.7V, 1.75V, or 1.8V. The second preset voltage can be 0.3V, 0.35V, or 0.4V. The third preset voltage can be 4.9V or 5V.

[0055] According to embodiments of this disclosure, the third preset range can be selected according to actual circumstances, and is not limited herein.

[0056] For example, a third resistance value can be calculated based on a second preset voltage and a third current. If the third resistance value is greater than 0 and less than 700KΩ, the resistive variable memory with the third resistance value is designated as the active-state resistive variable memory. Therefore, the third preset range can be greater than 0 and less than 700KΩ.

[0057] According to embodiments of this disclosure, performing a read operation on a resistive random access memory (RRAM) based on a first preset voltage and a second preset voltage may include: applying a first preset voltage for a fourth preset duration to the word line terminal of the RRAM, grounding the source line terminal of the RRAM, and applying a second preset voltage for a fourth preset duration to the bit line terminal of the RRAM.

[0058] According to embodiments of this disclosure, the fourth preset duration can be selected based on actual circumstances and is not limited herein. For example, the fourth preset duration can be 1µs.

[0059] According to embodiments of this disclosure, performing a write operation on a resistive random access memory (RRAM) based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain a RRAM with a third resistance value includes: applying a first preset voltage for a second preset duration to the word line terminal of the RRAM, applying a second preset voltage for a second preset duration to the source line terminal of the RRAM, and applying a third preset voltage for a second preset duration to the bit line terminal of the RRAM to obtain a RRAM with a third resistance value.

[0060] According to embodiments of this disclosure, the second preset duration can be selected based on actual circumstances and is not limited thereto. For example, the second preset duration can be 5µs.

[0061] According to embodiments of this disclosure, performing a read operation on a resistive variable memory with a resistance value of a third value based on a first preset voltage and a second preset voltage to obtain a third current flowing through the resistive variable memory with a resistance value of a third value may include: applying a first preset voltage of a fourth preset duration to the word line terminal of the resistive variable memory with a resistance value of a third value, grounding the source line terminal, and simultaneously applying a second preset voltage of a fourth preset duration to the bit line terminal, reading the third current flowing through the resistive variable memory with a resistance value of a third value, and obtaining the third current flowing through the resistive variable memory with a resistance value of a third value.

[0062] Figure 4 A schematic diagram illustrating pulses for controlling a resistive random access memory to perform a molding operation according to an embodiment of the present disclosure is shown.

[0063] like Figure 4 As shown, a voltage of 1.8V is continuously applied to the WL terminal of the resistive switching memory throughout the molding process.

[0064] After grounding the SL terminal of the resistive random access memory (RRAM) and continuously applying a 1µs 0.4V voltage pulse to the BL terminal, followed by a 5µs 0.4V voltage pulse to the SL terminal and a 5µs 5V voltage pulse to the BL terminal, a RRAM with a third resistance value is obtained. Then, the SL terminal of the RRAM with the third resistance value is grounded, and a 1µs 0.4V voltage pulse is continuously applied to the BL terminal. The third current flowing through the RRAM is then read. Based on the second preset voltage and the third current, and after determining that the third resistance value is within the third preset range, the RRAM with the third resistance value can be identified as the active-state RRAM.

[0065] According to embodiments of this disclosure, for example, Figure 3Operation S320, as shown, involves setting an active-state resistive switching memory based on a first preset voltage and a second preset voltage to obtain a first target resistive switching memory. This operation may include the following steps: performing a read operation on the active-state resistive switching memory based on the first preset voltage and the second preset voltage; performing a write operation on the active-state resistive switching memory based on the first preset voltage and the second preset voltage to obtain a target resistive switching memory with a resistance value of the first value; performing a read operation on the target resistive switching memory with the first resistance value based on the first preset voltage and the second preset voltage to obtain a first current flowing through the target resistive switching memory with the first resistance value; and, if the first resistance value is determined to be within a first preset range based on the second preset voltage and the first current, identifying the target resistive switching memory with the first resistance value as the first target resistive switching memory.

[0066] For example, a first resistance value can be calculated based on a second preset voltage and a first current, and if the first resistance value is greater than 0 and less than or equal to 6KΩ, the target resistive variable memory with the first resistance value can be determined as the first target resistive variable memory.

[0067] According to embodiments of this disclosure, performing a read operation on an active-state resistive random access memory (IRRAM) based on a first preset voltage and a second preset voltage may include: applying a first preset voltage for a fourth preset duration to the word line terminal of the active-state IRRAM, grounding the source line terminal of the active-state IRRAM, and applying a second preset voltage for a fourth preset duration to the bit line terminal of the active-state IRRAM.

[0068] According to embodiments of this disclosure, performing a write operation on an active-state resistive random access memory (RRAM) based on a first preset voltage and a second preset voltage to obtain a target RRAM with a resistance value of the first resistance value includes: applying a first preset voltage of a first preset duration to both the word line and bit line of the active-state RRAM, and applying a second preset voltage of a first preset duration to the source line of the active-state RRAM to obtain a target RRAM with a resistance value of the first resistance value.

[0069] According to embodiments of this disclosure, based on a first preset voltage and a second preset voltage, performing a read operation on a target resistive variable memory with a resistance value of the first value to obtain a first current flowing through the target resistive variable memory with a resistance value of the first value may include: applying a first preset voltage of a fourth preset duration to the word line terminal of the target resistive variable memory with a resistance value of the first value, grounding the source line terminal, and simultaneously applying a second preset voltage of a fourth preset duration to the bit line terminal, reading the first current flowing through the target resistive variable memory with a resistance value of the first value, and obtaining the first current flowing through the target resistive variable memory with a resistance value of the first value.

[0070] Figure 5The diagram illustrates a pulse for controlling a resistive random access memory to perform a set operation according to an embodiment of the present disclosure.

[0071] like Figure 5 As shown, during the entire setting process, a voltage of 1.8V is continuously applied to the WL terminal of the active state resistive random access memory.

[0072] By grounding the SL terminal of the active-state resistive random access memory (RRAM) and continuously applying a 1µs 0.4V voltage pulse to the BL terminal, followed by a 200ns 0.4V voltage pulse to the SL terminal and a 200ns 1.8V voltage pulse to the BL terminal, a target RRAM with a first resistance value is obtained. Then, the SL terminal of the target RRAM with the first resistance value is grounded, and a 1µs 0.4V voltage pulse is continuously applied to the BL terminal. The first current flowing through the target RRAM is then read. Based on the second preset voltage and the first current, and after determining that the first resistance value is within a first preset range, the target RRAM with the first resistance value can be identified as the first target RRAM.

[0073] According to embodiments of this disclosure, Figure 3 The control method for the resistive random access memory array may further include the following operation: based on a first preset voltage, a second preset voltage, and a fourth preset voltage, a first target resistive random access memory is reset to obtain a second target resistive random access memory whose resistance value is within a second preset range, wherein the fourth preset voltage is generated by a sub-circuit corresponding to the fourth preset voltage included in the voltage generation circuit, and the first preset voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage are not equal to each other.

[0074] For example, the fourth preset voltage can be generated by the fourth sub-circuit in the voltage generation circuit.

[0075] According to embodiments of this disclosure, the fourth preset voltage can be greater than or equal to 3.2V and less than or equal to 3.3V. For example, the fourth preset voltage can be 3.2V, 3.25V, or 3.3V.

[0076] The control method for resistive random access memory (RRAM) arrays provided in this disclosure can control the RRAM array to perform shaping, setting, and resetting operations based on four preset voltages of different amplitudes. Compared to related technologies, such as those in Figures 2A-2C which use seven preset voltages of different amplitudes to control the RRAM array to perform shaping, setting, and resetting operations, the method uses fewer preset voltage amplitudes, thus requiring fewer sub-circuits for generating the preset voltages in the voltage generation circuit. This simplifies the structure of the voltage generation circuit, significantly reduces its complexity, simplifies the structure of the peripheral circuits, reduces the chip area occupied by the peripheral circuits, and greatly improves the integration density of the integrated RRAM array.

[0077] According to embodiments of this disclosure, resetting a first target resistive variable memory (RRAM) based on a first preset voltage, a second preset voltage, and a fourth preset voltage to obtain a second target RRAM with a resistance value within a second preset range includes: performing a read operation on the first target RRAM based on the second preset voltage and the fourth preset voltage; performing a write operation on the first target RRAM based on the first preset voltage and the fourth preset voltage to obtain a target RRAM with a resistance value of the second value; performing a read operation on the target RRAM with the second resistance value based on the second preset voltage and the fourth preset voltage to obtain a second current flowing through the target RRAM with the second resistance value; and determining the target RRAM with the second resistance value as the second RRAM when the second resistance value is determined to be within a second preset range based on the second preset voltage and the second current.

[0078] According to embodiments of this disclosure, the second preset range can be selected according to actual circumstances, and is not limited herein.

[0079] For example, a second resistance value can be calculated based on a second preset voltage and a second current. If the second resistance value is greater than 33 KΩ and less than 700 KΩ, the target resistive variable memory with the second resistance value is determined as the second resistive variable memory. Therefore, the second preset range can be greater than 33 KΩ and less than 700 KΩ.

[0080] According to embodiments of this disclosure, performing a read operation on a first target resistive random access memory (RRAM) based on a second preset voltage and a fourth preset voltage may include: applying a fourth preset voltage for a fourth preset duration to the word line terminal of the first target RRAM, applying a second preset voltage for a fourth preset duration to the source line terminal of the first target RRAM, and grounding the bit line terminal of the first target RRAM.

[0081] According to embodiments of this disclosure, performing a write operation on a first target resistive random access memory (RRAM) based on a first preset voltage and a fourth preset voltage to obtain a target RRAM with a resistance value of a second resistance value includes: applying a fourth preset voltage for a third preset duration to the word line terminal of the first target RRAM, applying a first preset voltage for a third preset duration to the source line terminal of the first target RRAM, and grounding the bit line terminal of the first target RRAM to obtain a target RRAM with a resistance value of a second resistance value.

[0082] According to embodiments of this disclosure, the third preset duration can be selected based on actual circumstances and is not limited thereto. For example, the third preset duration can be 300 ns.

[0083] According to embodiments of this disclosure, performing a read operation on a target resistive variable memory (RRAM) with a resistance value of the second value, based on a second preset voltage and a fourth preset voltage, to obtain a second current flowing through the target RRAM with a resistance value of the second value, may include: applying a fourth preset voltage of the fourth preset duration to the word line terminal of the target RRAM with a resistance value of the second value, applying a second preset voltage of the fourth preset duration to the source line terminal, while simultaneously grounding the bit line terminal, and reading the second current flowing through the target RRAM with a resistance value of the second value to obtain the second current flowing through the target RRAM with a resistance value of the second value.

[0084] Figure 6 The diagram illustrates a pulse for controlling a resistive random access memory to perform a reset operation according to an embodiment of the present disclosure.

[0085] like Figure 6 As shown, during the entire reset process, a voltage of 3.3V is continuously applied to the WL terminal of the first target resistive random access memory, and the BL terminal of the first target resistive random access memory is grounded.

[0086] After continuously applying a 1µs 0.4V voltage pulse to the SL terminal of the first target resistive random access memory (RRAM), a 300ns 1.8V voltage pulse is then continuously applied to the SL terminal, resulting in a target RRAM with a second resistance value. Next, a 1µs 0.4V voltage pulse is continuously applied to the SL terminal of the target RRAM, and the second current flowing through the target RRAM is read, obtaining the second current flowing through the target RRAM. After determining the second resistance value within a second preset range based on the second preset voltage and the second current, the target RRAM with the second resistance value is identified as the second RRAM.

[0087] According to embodiments of this disclosure, after obtaining the second resistive random access memory (RRAM), a setting operation can be performed on the second RRAM based on a first preset voltage and a second preset voltage to obtain a first target RRAM with a resistance value within a first preset range. The specific setting operation is similar to operation S320, and for simplicity, it will not be described in detail here.

[0088] according to Figures 4-6 As can be seen, the control method for resistive random access memory (RRAM) arrays provided in this disclosure can control the RRAM array to perform forming, setting, and resetting operations based on four preset voltages of different amplitudes: a first preset voltage of 1.8V, a second preset voltage of 0.4V, a third preset voltage of 5V, and a fourth preset voltage of 3.3V. This allows for the "merging" of several similar voltage values ​​shown in Figures 2A-2C. For example, in the SET operation, applying a 0.4V voltage pulse to the SL terminal changes the voltage amplitude at the WL terminal from 1.4V to 1.8V, and the voltage amplitude at the BL terminal from 1.2V to 1.8V. After balancing with a small voltage pulse at the SL terminal, although not exactly the same as the pulse operation method in Figure 2, the voltage values ​​are very similar and correspondingly reduced, achieving the same effect as the operation method in Figure 2. Furthermore, by applying the same balancing method to the Forming operation and RESET operation, the number of voltage values ​​can be reduced from seven to four, significantly reducing the complexity of the voltage generation circuit. This simplifies the structure of the peripheral circuits, reduces the chip area occupied by the peripheral circuits, and greatly improves the integration density of the integrated resistive random access memory array.

[0089] according to Figures 4-6 As can be seen, the control method for resistive random access memory arrays provided in this disclosure adopts a new pulse operation scheme, namely, applying a small voltage pulse at the source end to balance the voltage at each end of the device. This scheme can effectively reduce the voltage value used in the operation process, reduce the complexity of the voltage generation circuit, improve the integration of the device, and achieve higher density information storage.

[0090] The following will use the experimental results in Figures 7(a)-7(c) to illustrate the practicality and corresponding beneficial effects of the control method for resistive random access memory arrays provided in the embodiments of this disclosure.

[0091] Figure 7(a) schematically illustrates a resistive switching memory included in a resistive switching memory array according to an embodiment of the present disclosure.

[0092] As shown in Figure 7(a), each resistive random access memory (RRAM) in the RRAM array of this embodiment can be a 1T1R structure, that is, each RRAM includes a transistor and an RRAM. The 1T1R is the most basic integrated unit of the RRAM array. The current data of the RRAM can be read in any read operation based on the Vo terminal.

[0093] Figure 7(b) schematically illustrates the voltage and current used in the control method for a resistive random access memory array according to an embodiment of the present disclosure when performing a set operation on the resistive random access memory.

[0094] As shown in Figure 7(b), curve 701 represents the voltage applied to the BL terminal of the resistive random access memory at various times during the set operation. Curve 702 represents the current flowing through the resistive random access memory at various times during the set operation. The horizontal axis represents time, and the vertical axis represents voltage and current.

[0095] As shown in Figure 7(b), the resistances determined by the two read operations in the set operation are 34 KΩ and 6 KΩ, respectively. 6 KΩ is within the first preset range, indicating that the set operation was successful. At this time, the first target resistive variable memory storage value is 1.

[0096] Figure 7(c) schematically illustrates the voltage and current used in the control method for a resistive random access memory array according to an embodiment of the present disclosure when performing a reset operation on the resistive random access memory.

[0097] As shown in Figure 7(c), curve 703 represents the voltage applied to the SL terminal of the resistive random access memory at various moments during the reset operation. Curve 704 represents the current flowing through the resistive random access memory at various moments during the reset operation. The horizontal axis represents time, and the vertical axis represents voltage and current.

[0098] As shown in Figure 7(c), the resistances determined by the two read operations in the reset operation are 6KΩ and 36KΩ, respectively. 36KΩ is within the second preset range, indicating that the reset was successful. At this time, the value stored in the second resistive variable memory is 0.

[0099] The experimental results in Figures 7(a)-7(c) illustrate that the control method for resistive random access memory arrays provided in this disclosure, compared to the prior art, can still successfully perform read and write operations while reducing the voltage value. This reduces the complexity of the voltage generation circuit and improves the integration of the device.

[0100] Based on the above-described control method for resistive random access memory (RRAM) arrays, this disclosure also provides a control device for RRAM arrays. The following will be combined with... Figure 8 The device is described in detail.

[0101] Figure 8 A schematic diagram of a control device for a resistive random access memory array according to an embodiment of the present disclosure is shown.

[0102] like Figure 8 As shown, the control device 800 for the resistive random access memory array may include a control circuit 810 and a voltage generation circuit 820.

[0103] The control circuit 810 can be used to perform a shaping operation on each resistive random access memory in the resistive random access memory array based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated resistive random access memory in an active state, and to perform a setting operation on the activated resistive random access memory based on the first preset voltage and the second preset voltage to obtain a first target resistive random access memory whose resistance value is within a first preset range.

[0104] The voltage generation circuit 820 may include sub-circuits corresponding to the first preset voltage, the second preset voltage, and the third preset voltage, respectively. The sub-circuits are used to generate the first preset voltage, the second preset voltage, and the third preset voltage, wherein the first preset voltage, the second preset voltage, and the third preset voltage are not equal to each other.

[0105] exist Figure 8 In the control device 800, the control circuit 810 can also be used to perform a reset operation on the first target resistive variable memory based on the first preset voltage, the second preset voltage, and the fourth preset voltage, to obtain a second target resistive variable memory whose resistance value is within the second preset range. The voltage generation circuit 820 may further include a sub-circuit corresponding to the fourth preset voltage, which is used to generate the fourth preset voltage, wherein the first preset voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage are not equal to each other.

[0106] It should be noted that the control device part for resistive random access memory array in the embodiments of this disclosure corresponds to the control method part for resistive random access memory array in the embodiments of this disclosure. For a detailed description of the control device part for resistive random access memory array, please refer to the control method part for resistive random access memory array, which will not be repeated here.

[0107] Figures 9(a) and 9(b) are schematic diagrams showing the area ratio of the control device and memory array for resistive random access memory array according to embodiments of the present disclosure before and after optimization.

[0108] Figure 9(a) schematically shows the area ratio of the control device and memory array for the resistive random access memory (RRAM) array in the overall integrated chip before optimization. Figure 9(b) schematically shows the area ratio of the control device and memory array for the RRAM array in the overall integrated chip after optimization. The peripheral circuit in Figure 9(a) is the control device for the RRAM array before optimization. The peripheral circuit in Figure 9(b) is the control device for the RRAM array after optimization, which may include control circuit 810 and voltage generation circuit 820. "Memory array" can be an abbreviation for "resistive random access memory array".

[0109] As shown in Figures 9(a) and 9(b), the area occupied by the peripheral circuits in the optimized Figure 9(b) is significantly reduced compared to the area occupied by the peripheral circuits in the unoptimized Figure 9(a). Therefore, the integration density of the resistive switching memory array in the integrated chip is greatly improved.

[0110] Figure 10 The diagram illustrates the storage density of the resistive random access memory array before and after optimization using a control device for a resistive random access memory array according to an embodiment of the present disclosure.

[0111] Depend on Figure 10 It can be seen that after optimizing the control device used for the resistive random access memory array, the storage density of the optimized resistive random access memory array is significantly greater than that before optimization, which further illustrates that the integration level of the resistive random access memory array in the overall integrated chip has been greatly improved.

[0112] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0113] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended embodiments and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A control method for a resistive random access memory array, comprising: For each resistive switching memory in the resistive switching memory array, a shaping operation is performed on the resistive switching memory based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated resistive switching memory in an activated state. The process of setting the active-state resistive random access memory (RRAM) based on the first preset voltage and the second preset voltage to obtain a first target RRAM with a resistance value within a first preset range includes: performing a read operation on the active-state RRAM based on the first preset voltage and the second preset voltage; applying the first preset voltage for a first preset duration to both the word line and bit line of the active-state RRAM, and applying the second preset voltage for a first preset duration to the source line of the active-state RRAM, to obtain a target RRAM with a resistance value of the first value; performing a read operation on the target RRAM with a resistance value of the first value based on the first preset voltage and the second preset voltage, to obtain a first current flowing through the target RRAM with a resistance value of the first value; and determining the target RRAM with a resistance value of the first value as the first target RRAM when the first resistance value is determined to be within a first preset range based on the second preset voltage and the first current, wherein the first preset voltage, the second preset voltage, and the third preset voltage are generated by each sub-circuit of the voltage generation circuit. Based on the first preset voltage, the second preset voltage, and the fourth preset voltage, a reset operation is performed on the first target resistive random access memory (RRAM) to obtain a second target RRAM with a resistance value within a second preset range. This includes: performing a read operation on the first target RRAM based on the second preset voltage and the fourth preset voltage; applying the fourth preset voltage for a third preset duration to the word line terminal of the first target RRAM, applying the first preset voltage for a third preset duration to the source line terminal of the first target RRAM, and grounding the bit line terminal of the first target RRAM to obtain a target RRAM with a resistance value of the second resistance value; based on the... The second preset voltage and the fourth preset voltage are used to perform a read operation on the target resistive variable memory with a resistance value of the second value to obtain a second current flowing through the target resistive variable memory with a resistance value of the second value; when the second resistance value is determined to be within a second preset range according to the second preset voltage and the second current, the target resistive variable memory with a resistance value of the second value is determined as the second target resistive variable memory, wherein the fourth preset voltage is generated by the sub-circuit corresponding to the fourth preset voltage included in the voltage generation circuit, and the first preset voltage, the second preset voltage, the third preset voltage and the fourth preset voltage are not equal to each other.

2. The control method according to claim 1, wherein The step of shaping each resistive random access memory (RRAM) in the RRAM array based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated RRAM includes: The resistive random access memory is read based on the first preset voltage and the second preset voltage. Based on the first preset voltage, the second preset voltage, and the third preset voltage, a write operation is performed on the resistive variable memory to obtain a resistive variable memory with a resistance value of the third resistance value. Based on the first preset voltage and the second preset voltage, a read operation is performed on the resistive variable memory with a resistance value of the third value to obtain the third current flowing through the resistive variable memory with a resistance value of the third value. If the third resistance value is determined to be within the third preset range based on the second preset voltage and the third current, the resistive variable memory with the third resistance value is determined as the active state resistive variable memory.

3. The control method according to claim 2, wherein, The step of performing a write operation on the resistive random access memory based on the first preset voltage, the second preset voltage, and the third preset voltage to obtain a resistive random access memory with a resistance value of the third resistance value includes: A first preset voltage of a second preset duration is applied to the word line terminal of the resistive random access memory (RRAM), a second preset voltage of a second preset duration is applied to the source line terminal of the RRAM, and a third preset voltage of a second preset duration is applied to the bit line terminal of the RRAM to obtain a RRAM with a resistance value of a third value.

4. The control method according to any one of claims 2-3, wherein, The first preset voltage is greater than or equal to 1.7V and less than or equal to 1.8V; The second preset voltage is greater than or equal to 0.3V and less than or equal to 0.4V; The third preset voltage is greater than or equal to 4.9V and less than or equal to 5V; The fourth preset voltage is greater than or equal to 3.2V and less than or equal to 3.3V.

5. A control device for a resistive random access memory array, comprising: A control circuit is configured to, for each resistive random access memory (RRAM) in an array, perform a shaping operation on the RRAM based on a first preset voltage, a second preset voltage, and a third preset voltage to obtain an activated RRAM, and perform a setting operation on the activated RRAM based on the first preset voltage and the second preset voltage to obtain a first target RRAM with a resistance value within a first preset range. This includes: performing a read operation on the activated RRAM based on the first preset voltage and the second preset voltage; applying the first preset voltage for a first preset duration to both the word line and bit line of the activated RRAM, and applying the second preset voltage for a first preset duration to the source line of the activated RRAM, to obtain a target RRAM with a resistance value of the first value; performing a read operation on the target RRAM with the first resistance value based on the first preset voltage and the second preset voltage to obtain a first current flowing through the target RRAM with the first resistance value; and, if the first resistance value is determined to be within a first preset range based on the second preset voltage and the first current, setting a target RRAM with a resistance value within a first preset range. The target resistive variable memory with a first resistance value is determined as the first target resistive variable memory; based on the first preset voltage, the second preset voltage, and the fourth preset voltage, a reset operation is performed on the first target resistive variable memory to obtain a second target resistive variable memory with a resistance value within a second preset range, including: performing a read operation on the first target resistive variable memory based on the second preset voltage and the fourth preset voltage; applying the fourth preset voltage for a third preset duration to the word line terminal of the first target resistive variable memory, applying the first preset voltage for a third preset duration to the source line terminal of the first target resistive variable memory, and grounding the bit line terminal of the first target resistive variable memory to obtain a target resistive variable memory with a resistance value of the second value; performing a read operation on the target resistive variable memory with a resistance value of the second value based on the second preset voltage and the fourth preset voltage to obtain a second current flowing through the target resistive variable memory with a resistance value of the second value; and determining the second resistance value to be within a second preset range based on the second preset voltage and the second current, then determining the target resistive variable memory with a resistance value of the second value as the second target resistive variable memory; The voltage generation circuit includes sub-circuits corresponding to the first preset voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage, respectively. The sub-circuits are used to generate the first preset voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage, wherein the first preset voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage are not equal to each other.

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