Radio frequency receiving end multichannel amplitude phase correction method and system based on FPGA

Abstract

A multi-channel amplitude and phase correction method for a radio frequency receiving end based on an FPGA (Field Programmable Gate Array) comprises the following steps: S1, in a large-scale MIMO (Multiple Input Multiple Output) system, the radio frequency receiving end groups signals received in real time, each group comprises a reference channel signal and a to-be-calibrated channel signal, and the steps S2-S3 are respectively executed by taking the group as a unit to carry out signal correction; s2, preprocessing each group of received signals to obtain preprocessed sampling signals; s3, constructing an amplitude phase correction model, calculating a phase correction factor and an amplitude correction factor to carry out iterative correction operation on the to-be-calibrated channel signal based on the preprocessed sampling signal, and outputting a corrected signal; and S4, after all groups are corrected, M groups of corrected signals are obtained, and the signal correction of the round is completed. According to the design, the calculation resource consumption of the FPGA is reduced while the amplitude phase correction precision is ensured, and meanwhile, the problem that the correction precision is reduced under the condition that the number of sampling points is a non-signal period integer is avoided.

Description

Technical Field

[0001] The present invention relates to a multi-channel amplitude and phase correction method and system for a radio frequency receiving end based on FPGA, and is specifically suitable for performing real-time signal correction by using FPGA. Background Art

[0002] At present, 5G is being further integrated into everyone's life, and the core technologies of 5G technology include massive multiple-input multiple-output (MIMO) system and orthogonal frequency division multiplexing (OFDM). Among them, the massive MIMO system improves spectrum utilization, reduces transmission power, and increases system capacity by increasing the number of antennas. At the same time, the use of a large number of antennas can simplify power control and effectively overcome the frequency selective fading of the channel. However, the massive MIMO system also faces new challenges, one of the key ones is the multi-channel amplitude and phase correction problem. In the massive MIMO system, slight differences in hardware between channels, antenna coupling, environmental interference, etc. will lead to inconsistent amplitudes and phases between different channels at the receiving end, which will affect the normal operation of the system. In order to ensure the normal operation of the system, high-precision amplitude and phase calibration technology must be implemented. Solving this problem is crucial to improving system performance.

[0003] Most of the current multi-channel amplitude and phase correction systems are analog circuits, which can achieve high-precision amplitude and phase correction for specific RF transceiver systems, such as using gain control amplifiers, analog phase shifters, etc. However, their development cycle is long and they are not easy to modify. Once the communication device is adjusted, such as modifying the communication protocol, changing the communication parameters, or the environmental conditions change significantly, recalibration is required, and the modification cost of analog circuits is high, the cycle is long, and the calibration accuracy cannot be guaranteed. However, with the rapid development of wireless communication technology, analog amplitude and phase correction circuits are no longer suitable for the current environment.

[0004] In this context, software radio technology came into being. It configures various parameters in wireless communication through software configuration, including baseband signal type, sampling rate, signal transmission bandwidth, and RF frequency band. At the same time, the software radio platform can not only realize baseband signal processing, but also program and reconstruct intermediate frequency signals. Among the many software radio development platforms, FPGA has unique advantages. Unlike the sequential execution of general processors, FPGA can realize efficient parallel data processing, which is particularly suitable for the implementation of complex algorithms in wireless communications and the processing of high-speed signals. In addition, the FPGA platform can also be dynamically reconstructed according to different communication tasks. Developers can quickly replace algorithms or optimize logic according to application scenarios without redesigning hardware, which greatly shortens the R&D cycle and improves development efficiency.

[0005] Currently, amplitude and phase correction using FPGA can generally only be performed on narrowband signals. When correcting broadband signals, the correction time is long and the accuracy is low. At the same time, the current amplitude and phase correction algorithm consumes a lot of FPGA logic resources and cannot be deployed on resource-constrained FPGAs.

[0006] In summary, the development of a multi-channel amplitude and phase calibration system based on FPGA can not only effectively solve the amplitude and phase correction problem in large-scale MIMO systems, but also meet the needs of future wireless communication systems for high flexibility, low power consumption and high integration, and promote wireless communication technology to a new height. It has far-reaching significance for the development of the entire communication field. Summary of the invention

[0007] The purpose of the present invention is to overcome the problem in the prior art that broadband signals cannot be accurately and quickly corrected, and to provide a FPGA-based RF receiving end multi-channel amplitude and phase correction method and system for accurately and quickly correcting broadband signals.

[0008] To achieve the above objectives, the technical solution of the present invention is:

[0009] In a first aspect, the present invention provides a multi-channel amplitude and phase correction method for a radio frequency receiving end based on FPGA, comprising the following steps:

[0010] S1. In a large-scale MIMO system, the RF receiving end receives the signal of each channel in real time, groups the received signals, each group includes a reference channel signal and a channel signal to be calibrated, and performs steps S2-S3 in groups to perform signal correction;

[0011] S2, sampling each group of received signals, and preprocessing the sampled signals to obtain preprocessed sampled signals;

[0012] S3, construct an amplitude phase correction model, calculate the phase correction factor and the amplitude correction factor based on the preprocessed sampling signal, perform iterative correction operation on the channel signal to be calibrated, and output the corrected signal;

[0013] S4. When all groups have been corrected, M groups of corrected signals are obtained, and this round of signal correction is completed.

[0014] In S1, in the large-scale multi-input multi-output system, the RF receiving end receives the signal of each channel in real time, and sets any one of the channels as the reference channel signal A. a (t), the remaining M channels are the channel signals to be calibrated { B b1 (t), B b2 (t)…B bm (t)…B bM (t)}; Each channel signal to be calibrated Bbm (t) and the reference channel signal A a (t) are combined into a group, and each group executes steps S2-S3 to perform phase amplitude calibration operations.

[0015] In S2, each group of received signals is sampled, and the sampled signals are preprocessed:

[0016] First, the received signal is smoothed and truncated using the Hanning window function to obtain the smoothed signal {A a (n), B bm (n)};

[0017] If {A a (n), B bm (n)} is less than 10% of its signal center frequency, then let {A a (n), B bm (n)} as the preprocessed sampling signal {A a (n), B b (n)} output;

[0018] If {A a (n), B bm (n)} has a bandwidth greater than or equal to 10% of its signal center frequency, then the frequency domain LMS filter is used to filter B bm (n) Perform filtering iteration operation to obtain the filtered channel signal to be calibrated B b (n), let {A a (n), B b (n)} is output as the preprocessed sampling signal.

[0019] In S2, a frequency domain LMS filter is used to filter B bm (n) Perform filtering iterative operation:

[0020] S21, the smoothed reference channel signal A a (n) Perform fast Fourier transform to obtain the reference channel signal M in the frequency domain a (f), for the smoothed channel signal B to be corrected bm (n) Perform fast Fourier transform to obtain the channel signal N to be corrected in the frequency domain b (f) Assume the coefficient of the frequency domain LMS filter is W(K), let K = 0, and set the initial value of the coefficient of the frequency domain LMS filter to W(0);

[0021] S22, the output signal of the frequency domain LMS filter is L(K):

[0022] L(K)= N b (f)* W(K);

[0023] The reference channel signal M a (f) After delay, we get M del (f), M del (f) and L(K) to calculate the error and obtain the error value e(K) between the reference channel signal and the channel signal to be calibrated:

[0024] e(K)= M del (f) -L(K);

[0025] S23. If the error value e(K) is greater than the set threshold and has not reached the maximum number of iterations, the coefficients of the frequency domain LMS filter are updated:

[0026] W(K+1)= W(K)+µ(K)* e(K)* N b (f);

[0027] Where µ(K) is the iteration step, µ(K)=kµ(K-1)+b*e 2 (K-1), k is the coefficient of dynamic adjustment in actual test, b is the adjustment factor, b=αµ(K-2)+(1-α)*e 2 (K-2), α is the fine-tuning factor;

[0028] If the error value e(K) is less than the set threshold or reaches the maximum number of iterations, L(K) is subjected to inverse fast Fourier transform to obtain the filtered channel signal to be calibrated B b (n) .

[0029] The S3 includes:

[0030] S31, construct an amplitude phase correction model, receive the preprocessed sampling signal {A a (n), B b (n)}, setting: the preprocessed reference channel signal A a The I-way signal and Q-way signal of (n) are I a (n), Q a (n), let the preprocessed signal B of the channel to be corrected b (n) is the signal B of the channel to be calibrated during the first calibration b (n) 1 , B b (n) 1 The I and Q signals are I b (n) 1 , Q b (n) 1 ;

[0031] S32, calculate the amplitude correction factor of the sth correction :

[0032] S33, calculate the phase correction factor of the sth correction: use the cordic algorithm to calculate the phase difference The angle value of the sth correction is then calculated;

[0033] S34, based on the amplitude correction factor and phase correction factor of the sth correction, correct the channel signal to be corrected to obtain a correction result B b (n) s+1 :

[0034] If the amplitude correction factor or phase difference If the set threshold is not met, then set s=s+1 and correct the result B b (n) s+1 Return to S32 to continue iterative calculation;

[0035] If the amplitude correction factor Phase Difference If all meet the set threshold or reach the maximum number of iterations, the correction result B b (n) s+1 Output as a corrected signal.

[0036] In S32, the amplitude correction factor of the sth correction is calculated. :

[0037] ;

[0038] in, is the power ratio between the reference channel signal in the s-th calibration and the channel signal to be corrected in the s-th calibration;

[0039] ;

[0040] Among them, I b (n) s is the I-channel signal of the channel to be calibrated for the sth time, Q b (n) s is the Q-channel signal of the channel to be corrected for the sth time, N is the length of the Hanning window, and n is the current sampling point.

[0041] against Design a divider with limited bit width, set the bit width of the divisor and dividend of the divider, and the bit width of the dividend is:

[0042] ;

[0043] The divisor width is:

[0044] ;

[0045] The bit width of the quotient is: quotient = integer + decimal;

[0046] Among them, integer is the bit width of the integer part of the quotient, which is the set value, and decimal is the bit width of the decimal part of the quotient, as shown in the following formula:

[0047] ;

[0048] Amp is the set amplitude difference threshold, Amp res is the resolution of the amplitude difference threshold;

[0049] against The square root module sets its input bit width to match the bit width of the decimal and integer parts of the divider quotient, and sets the square root module output bit width to:

[0050] ;

[0051] Wherein, root is the output bit width of the amplitude correction factor square root module.

[0052] In S33, the phase correction factor of the sth correction is calculated:

[0053] The reference channel signal A is calculated using fast Fourier transform a (n) and the channel signal B to be corrected after the sth correction bm (n) Tangent of the phase difference , use the cordic algorithm to calculate the phase difference The angle value is used to obtain the phase correction factor for the sth correction:

[0054] ;

[0055] Set the iteration round of the cordic algorithm, and index the cordic tangent table value in an incremental manner, that is, the cordic tangent table address value is no longer recalculated in each iteration, but is incremented according to the table address value of the previous iteration;

[0056] In S34, the channel signal to be corrected is corrected based on the amplitude correction factor and the phase correction factor corrected for the sth time, and a correction result is obtained:

[0057] ;

[0058] Among them, I b (n) s+1 The I-channel signal in the correction result is also the I-channel signal of the channel to be corrected in the s+1th correction; Qb (n) s+1 The Q-path signal in the correction result is also the Q-path signal of the channel to be corrected in the (s+1)th correction.

[0059] In a second aspect, the present invention provides a multi-channel amplitude phase correction system for a radio frequency receiving end based on FPGA, the system is used to execute the aforementioned multi-channel amplitude phase correction method for a radio frequency receiving end based on FPGA, specifically comprising: a sampling grouping module, a preprocessing module, an amplitude phase correction module, and a data integration module;

[0060] Sampling grouping module: used in large-scale MIMO systems, the RF receiver receives the signal of each channel in real time, groups the received signals, each group includes a reference channel signal and a channel signal to be calibrated, and performs signal correction on a group basis;

[0061] Preprocessing module: used to sample each group of received signals, preprocess the sampled signals, and obtain preprocessed sampled signals;

[0062] Amplitude and phase correction module: used to construct an amplitude and phase correction model, calculate the phase correction factor and amplitude correction factor based on the preprocessed sampling signal, perform iterative correction operations on the channel signal to be calibrated, and output the corrected signal;

[0063] Data integration module: used to obtain M groups of corrected signals after all groups have been corrected, thus completing this round of signal correction.

[0064] In a third aspect, the present invention provides a multi-channel amplitude phase correction device for a radio frequency receiving end based on FPGA, comprising a memory and a processor, wherein the memory is used to store a computer program code and transmit the computer program code to the processor;

[0065] The processor is used to execute the aforementioned FPGA-based RF receiving end multi-channel amplitude and phase correction method according to the instructions in the computer program code.

[0066] Compared with the prior art, the present invention has the following beneficial effects:

[0067] 1. In a multi-channel amplitude and phase correction method for a radio frequency receiving end based on FPGA of the present invention, after signal sampling, a Hanning window is added to smooth the sampled signal, while avoiding the problem of decreased correction accuracy when the number of sampling points is not an integer of the signal period.

[0068] 2. In the FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiving end of the present invention, when performing amplitude and phase correction on the signal, a variable step-size frequency domain LMS filter is designed for broadband signals to perform frequency domain equalization on the broadband signal, thereby ensuring the correction accuracy of the broadband signal.

[0069] 3. In the FPGA-based RF receiving end multi-channel amplitude phase correction method of the present invention, when performing amplitude correction, a divider and square root module with limited bit width are designed according to the amplitude correction accuracy for the divider and square root module required for amplitude correction, which greatly reduces the logic resource consumption of FPGA.

[0070] 4. In a multi-channel amplitude phase correction method for a radio frequency receiving end based on FPGA of the present invention, when performing phase correction, the Verilog implementation of the cordic algorithm used is optimized, and according to the calculation principle of cordic, the calculation relationship between the iteration round and the address value of the cordic tangent table is established to optimize the algorithm implementation logic and reduce the logic resource consumption of FPGA.

[0071] 5. The present invention provides a multi-channel amplitude phase correction system for a radio frequency receiving end based on FPGA, including: a sampling grouping module, a preprocessing module, an amplitude phase correction module, and a data integration module; the system is used to implement the steps of the multi-channel amplitude phase correction method for a radio frequency receiving end based on FPGA provided in any of the above technical solutions. Therefore, the system also includes all the beneficial effects of the multi-channel amplitude phase correction method for a radio frequency receiving end based on FPGA provided in any of the above technical solutions, which will not be repeated here.

[0072] 6. A multi-channel amplitude phase correction device for a radio frequency receiving end based on FPGA of the present invention includes a processor and a memory, the memory is used to store computer program codes and transmit the computer program codes to the processor, and the processor is used to execute the multi-channel amplitude phase correction method for a radio frequency receiving end based on FPGA provided in any of the above technical solutions according to the instructions in the computer program codes. Therefore, the device also includes all the beneficial effects of the multi-channel amplitude phase correction method for a radio frequency receiving end based on FPGA provided in any of the above technical solutions, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 It is a flow chart of the method of the present invention.

[0074] Figure 2 Schematic diagram of the variable step-size frequency domain LMS filter in Example 1.

[0075] Figure 3 This is a waveform comparison diagram before and after the multi-channel amplitude and phase correction in Example 1.

[0076] Figure 4 It is a system schematic diagram of the present invention.

[0077] Figure 5 It is a diagram of the equipment of the present invention.

[0078] Figure 6 Schematic diagram of the vector and rotation mode of the cordic algorithm in embodiment 1 of the present invention. DETAILED DESCRIPTION

[0079] The present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0080] Embodiment 1:

[0081] See also Figures 1 to 3 The present invention discloses a multi-channel amplitude phase correction method and system for a radio frequency receiving end based on FPGA. By adding a Hanning window function during sampling, the problem of spectrum leakage and reduced correction accuracy is avoided when the number of sampling points is not an integer of the signal period. At the same time, a frequency domain equalization filter is designed so that the entire method can correct narrowband and broadband signals. When performing amplitude correction, the bit width of the square root extraction module and the division module are designed according to the amplitude difference threshold. When performing phase correction, the cordic algorithm is used to establish a calculation relationship between the iteration round and the address value of the cordic tangent table, thereby reducing the consumption of logic resources and improving the correction accuracy. Finally, the correction data is transmitted back through Ethernet to ensure the accuracy of the correction.

[0082] The specific process of a multi-channel amplitude phase correction method for a radio frequency receiving end based on FPGA of the present invention is as follows:

[0083] S1. In a large-scale MIMO system, the RF receiving end receives the signal of each channel in real time, groups the received signals, each group includes a reference channel signal and a channel signal to be calibrated, and performs steps S2-S3 in groups to perform signal correction;

[0084] In a large-scale MIMO system, the RF receiver receives the signal of each channel in real time and sets any one of the channels as the reference channel signal A. a (t), the remaining M channels are the channel signals to be calibrated {B b1 (t), B b2 (t)…B bm (t)…B bM (t)}; Each channel signal to be calibrated B bm (t) and the reference channel signal A a (t) are combined into a group, and each group executes steps S2-S3 to perform phase amplitude calibration operations.

[0085] In essence, each channel transmits the same signal, but due to losses, interference and errors in the transmission process, the signals received by different channels are different.

[0086] S2, sampling each group of received signals, and preprocessing the sampled signals to obtain preprocessed sampled signals;

[0087] Collect the signal of the RF front end, and process the sampled signal through the Hanning window function to obtain the discrete reference channel sampling signal and the sampling signal of the channel to be calibrated;

[0088] When sampling the signal, a Hanning window function is added to reduce the impact of reduced amplitude and phase correction accuracy caused by spectrum leakage.

[0089] Specifically, the signal of the RF front end is divided into reference channel signal A a (t) and the channel signal B to be calibrated bm (t), where t represents continuous time.

[0090] For reference channel signal A a (t) is sampled to obtain a discrete reference channel signal , for the calibration channel signal B bm (t) is sampled to obtain the discrete channel signal to be corrected ;

[0091] Discrete reference channel signal With the discrete channel signal to be corrected After passing through the Hanning window, the smoothed reference channel sampling signal A is obtained a (n) and the smoothed channel sampling signal B to be calibrated bm (n);

[0092] If {A a (n), B bm (n)} is less than 10% of its signal center frequency, then let {A a (n), B bm (n)} as the preprocessed sampling signal {A a (n), B b (n)} output;

[0093] If {A a (n), B bm (n)} has a bandwidth greater than or equal to 10% of its signal center frequency, then the frequency domain LMS filter is used to filter B bm (n) Perform filtering iteration operation to obtain the filtered channel signal to be calibrated B b (n), let {A a (n), Bb (n)} is output as the preprocessed sampling signal.

[0094] The signal A a (n), B bm (n), input into an improved frequency domain LMS filter, perform frequency domain equalization on the signals of the reference channel and the channel to be corrected. The overall structure block diagram of the variable step size frequency domain LMS filter is as follows: Figure 2 shown.

[0095] Using frequency domain LMS filter to filter B bm (n) Perform filtering iterative operation:

[0096] S21, the smoothed reference channel signal A a (n) Perform fast Fourier transform (FFT) to obtain the reference channel signal M in the frequency domain a (f), for the smoothed channel signal B to be corrected bm (n) Perform fast Fourier transform to obtain the channel signal N to be corrected in the frequency domain b (f), f refers to the frequency component index obtained after FFT transformation, and its value range is 0 to N-1, where N is the length of the Hanning window in step S1, which is also the length of the discrete signal; let the coefficient of the frequency domain LMS filter be W(K), let K=0, and set the initial value of the coefficient of the frequency domain LMS filter to W(0);

[0097] S22, the output signal of the frequency domain LMS filter is L(K):

[0098] L(K)= N b (f)* W(K);

[0099] The reference channel signal M a (f) After delay, we get M del (f), M del (f) and L(K) to calculate the error and obtain the error value e(K) between the reference channel signal and the channel signal to be calibrated:

[0100] e(K)= M del (f) -L(K);

[0101] S23. If the error value e(K) is greater than the set threshold and has not reached the maximum number of iterations, the coefficients of the frequency domain LMS filter are updated:

[0102] W(K+1)= W(K)+µ(K)* e(K)* N b (f);

[0103] Where µ(K) is the iteration step, µ(K)=kµ(K-1)+b*e2 (K-1), k is the coefficient of dynamic adjustment in actual test, b is the adjustment factor, b=αµ(K-2)+ (1-α)*e 2 (K-2), α is the fine-tuning factor;

[0104] If the error value e(K) is less than the set threshold or reaches the maximum number of iterations, L(K) is subjected to inverse fast Fourier transform to obtain the filtered channel signal to be calibrated B b (n) .

[0105] S3, construct an amplitude phase correction model, calculate the phase correction factor and the amplitude correction factor based on the preprocessed sampling signal, perform iterative correction operation on the channel signal to be calibrated, and output the corrected signal;

[0106] S31, construct an amplitude phase correction model, receive the preprocessed sampling signal {A a (n), B b (n)}, setting: the preprocessed reference channel signal A a The I-way signal and Q-way signal of (n) are I a (n), Q a (n), let the preprocessed signal B of the channel to be corrected b (n) is the signal B of the channel to be calibrated during the first calibration b (n) 1 , B b (n) 1 The I and Q signals are I b (n) 1 , Q b (n) 1 ;

[0107] S32, calculate the amplitude correction factor of the sth correction : Using the principle of signal strength (RSSI), the amplitude ratio between the two channels is calculated to obtain the amplitude correction factor.

[0108] Assuming that the received baseband I and Q signals are expressed in complex form I+jQ, the sample power calculation formula for the current sampling is: , according to the sampling value of S2, the average power of the reference channel during the sampling time is:

[0109] ;

[0110] The average power of the signal of the channel to be corrected within the same sampling time is:

[0111] ;

[0112] Among them, Ib (n) s is the I-channel signal of the channel to be calibrated for the sth time, Q b (n) s is the Q-channel signal of the channel to be corrected for the sth time, N is the length of the Hanning window, and n is the current sampling point.

[0113] The power ratio between the reference channel and the channel to be corrected for the sth time for:

[0114] ;

[0115] Amplitude correction factor for the sth correction :

[0116] ;

[0117] against Design a divider with limited bit width to reduce FPGA logic resource consumption. Set the bit width of the divisor and dividend of the divider. The bit width is determined by the size of the divisor and dividend. That is, the bit width of the dividend is:

[0118] ;

[0119] The divisor width is:

[0120] ;

[0121] The bit width of the quotient is: quotient = integer + decimal;

[0122] Among them, integer is the bit width of the integer part of the quotient, which is a set value and is generally taken as 8; decimal is the bit width of the decimal part of the quotient, as shown in the following formula:

[0123] ;

[0124] Amp is the set amplitude difference threshold, Amp res is the resolution of the amplitude difference threshold;

[0125] against The square root module sets its input bit width to match the bit width of the decimal and integer parts of the divider quotient, and sets the square root module output bit width to:

[0126] ;

[0127] Wherein, root is the output bit width of the amplitude correction factor square root module.

[0128] S33, calculate the phase correction factor of the sth correction: use the cordic algorithm to calculate the phase difference The angle value of the sth correction is then calculated;

[0129] The reference channel signal A is calculated using fast Fourier transform a (n) and the channel signal B to be corrected after the sth correction bm (n) Tangent of the phase difference , use the cordic algorithm to calculate the phase difference The angle value is used to obtain the phase correction factor for the sth correction:

[0130] ;

[0131] Set the iteration number of the cordic algorithm to 16, and index the cordic tangent table value in an incremental manner, that is, the cordic tangent table address value is no longer recalculated in each iteration, but is incremented according to the table address value of the previous iteration; for example, in the nth iteration, only a fixed address increment needs to be added based on the previous iteration.

[0132] S34, based on the amplitude correction factor and phase correction factor of the sth correction, correct the channel signal to be corrected to obtain a correction result B b (n) s+1 :

[0133] ;

[0134] Among them, I b (n) s+1 The I-channel signal in the correction result is also the I-channel signal of the channel to be corrected in the s+1th correction; Q b (n) s+1 The Q-path signal in the correction result is also the Q-path signal of the channel to be corrected in the (s+1)th correction.

[0135] If the amplitude correction factor or phase difference If the set threshold is not met, then set s=s+1 and correct the result B b (n) s+1 Return to S32 to continue iterative calculation;

[0136] If the amplitude correction factor Phase Difference If all meet the set threshold or reach the maximum number of iterations, the correction result B b (n) s+1 Output as a corrected signal.

[0137] See also Figure 3The specific model of the FPGA chip used is XC7K325T, and the RF transceiver chip used is two AD9361 chips.

[0138] The specific test conditions are as follows: the four receiving channels are set to K0-K3, and K0 is selected as the reference channel. For narrowband signals, the received signal type is QPSK signal, the bandwidth is 1MHz, the center frequency of the received signal is 200MHz, and the sampling rate is 122.88MHz. The amplitude errors of K1-K3 relative to K0 before correction are set to -4.32dB, 1.51dB, and 2.61dB; the phase errors are 116°, -57°, and 55°. The amplitude errors after correction are 0.18dB, -0.19dB, and -0.26dB respectively; the phase errors after correction are -0.882°, 0.427°, and -0.621° respectively. The average amplitude error is 0.21dB, which is less than 0.5dB; the average phase error is 0.643°, which is less than 1°.

[0139] For broadband signals, the bandwidth is set to 20MHz, and the others remain unchanged. The amplitude errors after correction are: 0.15dB, 0.36dB, -0.25dB; the phase errors after correction are: 1.652°, 0.927°, -1.421°. The average amplitude error is 0.29dB, less than 0.5dB; the average phase error is 1.333°, less than 2°.

[0140] The invention discloses a multi-channel amplitude phase correction method and system for a radio frequency receiving end based on FPGA. The divider and square root module with limited bit width designed for the amplitude correction module reduce LUT (lookup table) resources by 57.8% compared with the general amplitude correction module.

[0141] The present invention discloses a FPGA-based RF receiving end multi-channel amplitude phase correction method and system. The Cordic algorithm designed for the phase correction module reduces LUT resources by 60.4% compared with the general Cordic algorithm implementation.

[0142] Embodiment 2:

[0143] Based on Example 1:

[0144] See also Figure 6 In S33, the tangent value of the phase difference between the reference channel and the channel to be corrected is calculated.

[0145] Specifically, the reference channel signal A is calculated using the fast Fourier transform (FFT) a (n) and the channel signal to be corrected B b (n) The tangent value of the phase difference (I / Q channel), denoted as .Will This angle is mapped to a two-dimensional coordinate space, with the vertex of the angle as the origin, one side extending in the positive direction of the x-axis, and the coordinates of the end point of the other side being (x, y). It can be expressed as x / y.

[0146] Calculate the sine and cosine values ​​corresponding to the tangent values ​​of the phase difference between the two and the corresponding angle value.

[0147] Specifically, the known phase difference The tangent value of is x / y. First, use the vector mode of cordic to calculate the specific size of the phase difference. Corresponding to the initial vector (x, y) in the two-dimensional coordinate space, let the initial vector (x, y) of the cordic algorithm be Figure 6 x in vector mode 0 ,y 0 . Assume the initial angle θ of the cordic algorithm 0 The following is the iterative process, the number of iterations I, the value is 0 to I-1; x i ,y i In the iterative process Corresponding to a vector in two-dimensional coordinate space.

[0148] (1) In each iteration, according to the current y i The sign of the value selects the direction of rotation.

[0149] (2) Calculate the rotation angle θ of this iteration i =arctan(2 -i ).

[0150] (3) Update the calculated angle, θ i+1 =(1-d i )θ i , where d i is the rotation factor of the i-th iteration process, and its value is based on y i The sign of y i <0 then d i =1, if y i >0 then d i = -1;

[0151] (4) Calculate the new coordinate point:

[0152] ;

[0153] The iteration termination condition of the above iterative calculation algorithm is that the calculation reaches the required round I, where I is 16. The final calculation result of θ is the angle of the phase difference. The specific size.

[0154] After obtaining the specific size of the phase difference, The specific size is input into the rotation mode of the cordic algorithm to calculate The sine and cosine of .

[0155] Initial vector initial point x 0 The coordinate values ​​are calculated as follows: 0 The coordinate value is 0.

[0156] ;

[0157] When the algorithm is initialized, the remaining rotation angle θ is set to be the angle calculated by the above rotation mode. The following is the iterative process, j is the number of iterations, ranging from 0 to J-1; x j ,y j In the iterative process The corresponding cosine value and sine .

[0158] (1) In each iteration, according to the current remaining angle θ j , select the direction of rotation.

[0159] (2) Calculate the rotation angle θ of this iteration j =arctan(2 -j ).

[0160] (3) Update the calculated angle, θ j+1 =(1-d j )θ j , where d j is the rotation factor of the jth iteration process, and its value is based on y j The sign of y j <0 then d j =1, if y j >0 then d j =-1.

[0161] (4) Calculate the new coordinate point:

[0162] ;

[0163] The termination condition is the same as that of the vector mode, and the final x J ,y J Corresponding angles The cosine value of and sine , which is the phase correction factor, where j is the iteration round and the size of J is 16.

[0164] Embodiment 3:

[0165] See also Figure 4 , a RF receiving end multi-channel amplitude phase correction system based on FPGA, the system is used to execute the aforementioned RF receiving end multi-channel amplitude phase correction method based on FPGA, specifically including: a sampling grouping module, a preprocessing module, an amplitude phase correction module, and a data integration module;

[0166] Sampling grouping module: used in large-scale MIMO systems, the RF receiver receives the signal of each channel in real time, groups the received signals, each group includes a reference channel signal and a channel signal to be calibrated, and performs signal correction on a group basis;

[0167] Preprocessing module: used to sample each group of received signals, preprocess the sampled signals, and obtain preprocessed sampled signals;

[0168] Amplitude and phase correction module: used to construct an amplitude and phase correction model, calculate the phase correction factor and amplitude correction factor based on the preprocessed sampling signal, perform iterative correction operations on the channel signal to be calibrated, and output the corrected signal;

[0169] Data integration module: used to obtain M groups of corrected signals after all groups have been corrected, thus completing this round of signal correction.

[0170] Embodiment 4:

[0171] See also Figure 5 , a FPGA-based RF receiving end multi-channel amplitude phase correction device, including a memory and a processor, the memory is used to store computer program code and transmit the computer program code to the processor; the processor is used to execute the aforementioned FPGA-based RF receiving end multi-channel amplitude phase correction method according to the instructions in the computer program code.

[0172] Embodiment 5:

[0173] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the multi-channel amplitude and phase correction method of a radio frequency receiving end based on FPGA is implemented.

Claims

1. A multi-channel amplitude and phase correction method for a radio frequency receiving end based on FPGA, characterized in that: The steps include: S1. In a large-scale MIMO system, the RF receiving end receives the signal of each channel in real time, groups the received signals, each group includes a reference channel signal and a channel signal to be calibrated, and performs steps S2-S3 in groups to perform signal correction; S2, sampling each group of received signals, and preprocessing the sampled signals to obtain preprocessed sampled signals; S3, construct an amplitude phase correction model, calculate the phase correction factor and the amplitude correction factor based on the preprocessed sampling signal, perform iterative correction operation on the channel signal to be calibrated, and output the corrected signal; S4. When all groups have been corrected, M groups of corrected signals are obtained, and this round of signal correction is completed.

2. The method for multi-channel amplitude and phase correction at a radio frequency receiving end based on FPGA according to claim 1, characterized in that: In S1, in the large-scale multi-input multi-output system, the RF receiving end receives the signal of each channel in real time, and sets any one of the channels as the reference channel signal A. a (t), the remaining M channels are the channel signals to be calibrated { B b1 (t), B b2 (t)…B bm (t)…B bM (t)}; Each channel signal to be calibrated B bm (t) and the reference channel signal A a (t) are combined into a group, and each group executes steps S2-S3 to perform phase amplitude calibration operations.

3. The method for multi-channel amplitude and phase correction at a radio frequency receiving end based on FPGA according to claim 1, characterized in that: In S2, each group of received signals is sampled, and the sampled signals are preprocessed: First, the Hanning window function is used to smooth and truncate the sampled signal to obtain the smoothed signal {A a (n), B bm (n)}; If {A a (n), B bm (n)} is less than 10% of its signal center frequency, then let {A a (n), B bm (n)} as the preprocessed sampled signal {A a (n), B b (n)} output; If {A a (n), B bm (n)} has a bandwidth greater than or equal to 10% of its signal center frequency, then the frequency domain LMS filter is used to filter B bm (n) Perform filtering iteration operation to obtain the filtered channel signal to be calibrated B b (n), let {A a (n), B b (n)} is output as the preprocessed sampling signal.

4. The method for multi-channel amplitude and phase correction at a radio frequency receiving end based on FPGA according to claim 3, characterized in that: In S2, a frequency domain LMS filter is used to filter B bm (n) Perform filtering iterative operation: S21, the smoothed reference channel signal A a (n) Perform fast Fourier transform to obtain the reference channel signal M in the frequency domain a (f), for the smoothed channel signal B to be corrected bm (n) Perform fast Fourier transform to obtain the channel signal N to be corrected in the frequency domain b (f) Assume the coefficient of the frequency domain LMS filter is W(K), let K = 0, and set the initial value of the coefficient of the frequency domain LMS filter to W(0); S22, the output signal of the frequency domain LMS filter is L(K): L(K)= N b (f)* W(K); The reference channel signal M a (f) After delay, M is obtained del (f), M del (f) and L(K) to calculate the error and obtain the error value e(K) between the reference channel signal and the channel signal to be calibrated: e(K)= M del (f)-L(K); S23. If the error value e(K) is greater than the set threshold and has not reached the maximum number of iterations, the coefficients of the frequency domain LMS filter are updated: W(K+1)= W(K)+µ(K)* e(K)* N b (f); Where µ(K) is the iteration step, µ(K)=kµ(K-1)+b*e 2 (K-1), k is the coefficient of dynamic adjustment in actual test, b is the adjustment factor, b=αµ(K-2)+ (1-α)*e 2 (K-2), α is the fine-tuning factor; If the error value e(K) is less than the set threshold or reaches the maximum number of iterations, L(K) is subjected to inverse fast Fourier transform to obtain the filtered channel signal to be calibrated B b (n) .

5. The method for multi-channel amplitude and phase correction at a radio frequency receiving end based on FPGA according to claim 1, characterized in that: The S3 includes: S31, construct an amplitude phase correction model, receive the preprocessed sampling signal {A a (n), B b (n)}, setting: the preprocessed reference channel signal A a The I-way signal and Q-way signal of (n) are I a (n), Q a (n), let the preprocessed signal B of the channel to be corrected b (n) is the signal B of the channel to be calibrated during the first calibration b (n)1,B b (n)1's I and Q signals are I b (n)1, Q b (n) 1; S32, calculate the amplitude correction factor of the sth correction : S33, calculate the phase correction factor of the sth correction: use the cordic algorithm to calculate the phase difference The angle value of the sth correction is then calculated; S34, based on the amplitude correction factor and phase correction factor of the sth correction, correct the channel signal to be corrected to obtain a correction result B b (n) s+1 : If the amplitude correction factor or phase difference If the set threshold is not met, then set s=s+1 and correct the result B b (n) s+1 Return to S32 to continue iterative calculation; If the amplitude correction factor Phase Difference If all meet the set threshold or reach the maximum number of iterations, the correction result B b (n) s+1 Output as a corrected signal.

6. The method for multi-channel amplitude and phase correction at a radio frequency receiving end based on FPGA according to claim 5, characterized in that: In S32, the amplitude correction factor of the sth correction is calculated. : ； in, is the power ratio between the reference channel signal in the s-th calibration and the channel signal to be corrected in the s-th calibration; ； Among them, I b (n) s is the I-channel signal of the channel to be calibrated for the sth time, Q b (n) s is the Q-channel signal of the channel to be corrected for the sth time, N is the length of the Hanning window, and n is the current sampling point.

7. The method for multi-channel amplitude and phase correction at a radio frequency receiving end based on FPGA according to claim 6, characterized in that: against Design a divider with limited bit width, set the bit width of the divisor and dividend of the divider, and the bit width of the dividend is: ； The divisor width is: ； The bit width of the quotient is: quotient = integer + decimal; Among them, integer is the bit width of the integer part of the quotient, which is the set value, and decimal is the bit width of the decimal part of the quotient, as shown in the following formula: ； Amp is the set amplitude difference threshold, Amp res is the resolution of the amplitude difference threshold; against The square root module sets its input bit width to match the bit width of the decimal and integer parts of the divider quotient, and sets the square root module output bit width to: ； Wherein, root is the output bit width of the amplitude correction factor square root module.

8. The method for multi-channel amplitude and phase correction at a radio frequency receiving end based on FPGA according to claim 5, characterized in that: In S33, the phase correction factor of the sth correction is calculated: The reference channel signal A is calculated using fast Fourier transform a (n) and the channel signal B to be corrected after the sth correction bm (n) Tangent of the phase difference , use the cordic algorithm to calculate the phase difference The angle value is used to obtain the phase correction factor for the sth correction: ； Set the iteration round of the cordic algorithm, and index the cordic tangent table value in an incremental manner, that is, the cordic tangent table address value is no longer recalculated in each iteration, but is incremented according to the table address value of the previous iteration; In S34, the channel signal to be corrected is corrected based on the amplitude correction factor and the phase correction factor corrected for the sth time, and a correction result is obtained: ； Among them, I b (n) s+1 The I-channel signal in the correction result is also the I-channel signal of the channel to be corrected in the s+1th correction; Q b (n) s+1 The Q-path signal in the correction result is also the Q-path signal of the channel to be corrected in the (s+1)th correction.

9. A multi-channel amplitude and phase correction system for a radio frequency receiving end based on FPGA, characterized in that: The system is used to execute the FPGA-based RF receiving end multi-channel amplitude phase correction method according to any one of claims 1 to 8, specifically comprising: a sampling grouping module, a preprocessing module, an amplitude phase correction module, and a data integration module; Sampling grouping module: used in large-scale MIMO systems, the RF receiver receives the signal of each channel in real time, groups the received signals, each group includes a reference channel signal and a channel signal to be calibrated, and performs signal correction on a group basis; Preprocessing module: samples each group of received signals, preprocesses the sampled signals, and obtains preprocessed sampled signals; Amplitude and phase correction module: used to construct an amplitude and phase correction model, calculate the phase correction factor and amplitude correction factor based on the preprocessed sampling signal, perform iterative correction operations on the channel signal to be calibrated, and output the corrected signal; Data integration module: used to obtain M groups of corrected signals after all groups have been corrected, thus completing this round of signal correction.

10. A multi-channel amplitude and phase correction device for a radio frequency receiving end based on FPGA, characterized in that: The method comprises a memory and a processor, wherein the memory is used to store computer program code and transmit the computer program code to the processor; The processor is used to execute the FPGA-based RF receiving end multi-channel amplitude and phase correction method according to any one of claims 1 to 8 according to the instructions in the computer program code.

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