Method, device and equipment for automatically generating chip power consumption management controller

Abstract

The invention relates to an automatic generation method, device and equipment for a chip power consumption management controller, which customizes and configures a code of a network transmission protocol by adopting a parameter transmission mode so as to achieve accurate control of a communication network transmission process between the power consumption management controller and a chip system. The method comprises the following steps: firstly, taking a power supply module as a specific array for processing in an array member mode, matching a turn-off process of the power supply module through a regular expression to automatically generate a hardware design code of the power supply module, and finally, quickly building a test model suitable for specific chip design by flexibly adjusting array members and variable setting. And the hardware design code of the power consumption management controller is interconnected with the test environment of the test model, and test information is transmitted. The time and workload of manual code writing and model testing are reduced, hardware design codes can be quickly changed, and the design flexibility and maintainability are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and relates to a method, device and equipment for automatically generating a chip power consumption management controller. Background Art

[0002] With the rapid development of chip technology, the integration of chips has been continuously improved, and the scale has become larger and larger. With the growth of chip scale, the power consumption problem has become a key factor restricting the performance and application of chips. To solve this problem, a power consumption management controller (PSC) has emerged. By implementing power or clock control on different modules in the chip, the PSC can effectively reduce the overall energy consumption without affecting the normal operation of the system, which is crucial for the stable operation and performance optimization of large-scale chips. Due to the diversity of chip development, the modules of different chips are different, and each chip requires a customized power consumption management controller. However, the traditional manual writing of the hardware design code and test model of the power consumption management controller is not only time-consuming and laborious, but also prone to errors. Therefore, it is of great practical significance to develop a technology for efficiently and accurately automatically generating a power consumption management controller and its test model. Summary of the Invention

[0003] Aiming at the problems existing in the above traditional technologies, the present invention proposes a method for automatically generating a chip power consumption management controller, a device for automatically generating a chip power consumption management controller, and a computer device, which can efficiently and accurately automatically generate a power consumption management controller and its test model.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions: On the one hand, a method for automatically generating a chip power consumption management controller is provided, including the steps of: Customizing the code for configuring the network transmission protocol by using parameter passing based on the Perl language to complete the bus interface configuration between the power consumption management controller and the chip system; Writing address decoding logic for each module of the chip during the module address decoding process by using the Perl language; Based on the Perl language, taking the power supply module of the chip as a specific array by using the array member method and matching the power-off process of the power supply module through regular expressions to generate the hardware design code of the power supply module; Based on the Perl language, using a special character matching mode to determine the network status and network request initiation method of the modules that require low-power control in the system, and generating a clear network request signal corresponding to the network request initiation method; the network status includes a network host or a network slave, and the network request initiation method includes active or passive; Use wildcards to match the control logic of the clock module and generate scripts for the clock logic, reset logic, and isolation control logic of the modules in the chip that require low-power control; After quickly building a test model suitable for chip design by adjusting the array elements based on the Perl language, script the assertion syntax of the test stimulus through variable settings to complete the automatic generation of the chip power management controller.

[0005] On the other hand, a device for automatically generating a chip power management controller is also provided, including: A bus configuration module, which is used to customize the code for configuring the network transmission protocol in a parameter-passing manner based on the Perl language to complete the bus interface configuration between the power management controller and the chip system; An address decoding module, which is used to write address decoding logic for each module of the chip during the module address decoding process using the Perl language; A power supply configuration module, which is used to use the array elements based on the Perl language to treat the power supply module of the chip as a specific array and match the power-off process of the power supply module through regular expressions to generate the hardware design code of the power supply module; A network request module, which is used to determine the network status and network request initiation method of the modules that require low-power control in the system based on the Perl language using a special character matching pattern, and generate a clear network request signal corresponding to the network request initiation method; the network status includes a network host or a network slave, and the network request initiation method includes active or passive; A clock configuration module, which is used to use wildcards to match the control logic of the clock module and generate scripts for the clock logic, reset logic, and isolation control logic of the modules in the chip that require low-power control; A test stimulus module, which is used to quickly build a test model suitable for chip design by adjusting the array elements based on the Perl language, and then script the assertion syntax of the test stimulus through variable settings to complete the automatic generation of the chip power management controller.

[0006] On yet another aspect, a computer device is also provided, including a memory and a processor. When the processor executes the computer program, the steps of the above method for automatically generating a chip power management controller are implemented.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The above method, device, and equipment for automatically generating a chip power consumption management controller customize and configure the code of the network transmission protocol by means of parameter passing, so as to achieve precise control of the communication network transmission process between the power consumption management controller and the chip system. Then, the power supply module is processed as a specific array by means of array members, and the power-off process of the power supply module is matched through regular expressions to automatically generate the hardware design code of the power supply module. Finally, by flexibly adjusting the array members and variable settings, a test model suitable for a specific chip design is quickly built, and the hardware design code of the power consumption management controller is interconnected with the test environment of the test model to transmit test information.

[0008] Compared with the traditional technology, through the above-mentioned automatic generation method based on parameter passing, only by confirming the low-power control method of the chip module and passing it into the script in the form of parameters, the corresponding hardware design code and module-level test environment and excitation can be quickly generated, thus greatly improving the customization design work efficiency of the power consumption management controller and reducing the time and workload of manual code writing and test model creation. Since the scripted generation method is adopted, if a module needs to be added or deleted during the chip design process, only the passed-in parameters need to be modified to quickly implement the change of the hardware design code, improving the flexibility and maintainability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0010] Figure 1 It is a schematic diagram of the main structure of the power consumption management controller; Figure 2 It is a schematic flowchart of the method for automatically generating a chip power consumption management controller in an embodiment; Figure 3 It is a schematic structural diagram of the automatic generation of parameters in an embodiment; Figure 4 It is a schematic processing flowchart of the hardware design generation in an embodiment; Figure 5 It is a schematic diagram of the parameter passing and test set in an embodiment; Figure 6 It is a block diagram of the modules of the device for automatically generating a chip power consumption management controller in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0012] It should be noted that referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. The phrase is shown at various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the description and appended claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0013] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0014] With the evolution of chip technology, the number of transistors integrated in a chip has increased exponentially. This has caused the power consumption of the chip to rise sharply. Excessive power consumption will not only cause the chip to heat severely, affecting its performance and reliability, but also increase the energy consumption of the system. The power management controller can intelligently control the power supply and clock of each module in the chip according to the operating state of the chip. For example, when a certain module is in an idle state, the power management controller can timely turn off the power supply or clock of the module, thereby significantly reducing the power consumption of the entire chip. Moreover, there are a wide variety of chips. As the integration degree of chips gets higher and higher and the process continues to improve, the complexity of power management becomes higher and higher, and the demand for efficiently generating a power management controller is more urgent.

[0015] Currently, when customizing a power management controller for each chip, the hardware design code and test model of the power management controller are usually written manually, and this method has many drawbacks. First of all, writing the hardware design code of the power management controller requires in-depth understanding of each module of the chip and familiarity with the hardware description language, which is a time-consuming and energy-consuming process. Secondly, the writing of the test model of the power management controller is equally complex, and various boundary conditions and abnormal situations need to be considered to ensure the correctness and reliability of the power management controller. During the process of manually writing the hardware design code of the power management controller, errors are likely to occur due to the negligence and fatigue of the writing personnel, and these errors are often difficult to detect and repair during the later debugging and verification, resulting in an extended design cycle and increased cost of the entire chip. In addition, when the chip design changes (such as adding or deleting modules), the hardware design code of the power management controller also needs to be modified accordingly, which further increases the design complexity.

[0016] The main structure of the power management controller is as Figure 1 shown, and its main structure includes a bus interface module, a clock power control module, a state transition control module, and a state transition monitoring module. Among them, the bus interface module undertakes important responsibilities and is mainly used to realize the bidirectional data interaction between the chip system network and the controller, complete the read and write access operations to the controller and process the configuration request access, ensuring the efficient transmission of the system information flow.

[0017] The clock power control module is used to enter the configuration stage orderly under the strict control of the state transition control module according to the specific requirements of the configuration request. This process is the core hub of the controller: the clock power control module first performs a network clearing operation to ensure a pure network request environment for the low-power module, and at the same time maintains the network isolation state to lay a solid foundation for the safe and stable operation of the system; subsequently, the clock power control module accurately regulates and outputs a series of key control signals such as power supply, clock, and reset to provide stable operating conditions for the normal operation of each part of the system. The state transition monitoring module is used to always play a guarantee role, monitor the whole process of each state transition of the system, ensure the accuracy and integrity of the state transition, and guarantee the stability and reliability of the system operation.

[0018] The present invention proposes an automatic generation method of a chip power management controller based on parameter drive and implemented using the Perl language, which is used to generate the hardware design code and its test model of the power management controller. This method can not only perform customized design according to the requirements of different chip modules, but also greatly improve the development efficiency and accuracy.

[0019] In one embodiment, as Figure 2As shown, a method for automatically generating a chip power consumption management controller may include the following steps S10 to S20: S10, customize the code for configuring the network transmission protocol by means of parameter passing based on the Perl language to complete the bus interface configuration between the power consumption management controller and the chip system; S12, write the address decoding logic for each module of the chip during the module address decoding process using the Perl language; S14, based on the Perl language, use the array members to treat the power supply module of the chip as a specific array and match the power-off process of the power supply module through regular expressions to generate the hardware design code for the power supply module; S16, based on the Perl language, use the special character matching mode to determine the network status and network request initiation method of the modules that require low-power control in the system, and generate a clear network request signal corresponding to the network request initiation method; the network status includes network host or network slave, and the network request initiation method includes active or passive; S18, use wildcards to match the control logic of the clock module to generate scripts for the clock logic, reset logic, and isolation control logic of the modules that require low-power control in the chip; S20, based on the Perl language, quickly build a test model suitable for chip design by adjusting the array members, and then script the assertion syntax of the test stimulus through variable settings to complete the automatic generation of the chip power consumption management controller.

[0020] It can be understood that this embodiment is implemented using the Perl language. By passing parameters, the module names of the power supply that the power consumption management controller needs to control and the module names of the clock that need to be controlled are customized to automatically generate the hardware design code and test model of the corresponding power consumption management controller. This method can be divided into five key parts, as Figure 3 shown, which are the bus interface configuration, module address decoding, power supply module configuration, clock module configuration, and generation of test environment and test stimulus in the hardware design code in sequence.

[0021] Among them, the power consumption management controller is an important module in the chip for reducing power consumption. The communication between this power consumption management controller and the chip system depends on the network protocol interaction to complete. Since different network protocols have their own unique handshake methods, in the design of this embodiment, the bus interface configuration uses the parameter passing method to customize the code for configuring the network transmission protocol, so as to achieve precise control of the transmission process of the communication network between the power consumption management controller and the chip system.

[0022] In the power consumption management controller, the number of clock power control modules comes from the number of modules in the incoming parameters. During the module address decoding process, address decoding logic is written for each module, enabling the chip to access the power consumption management controller through the bus interface and accurately identify the addresses of different modules, providing a basis for subsequent power and clock control of each module.

[0023] During system operation, for those modules that need to have their power turned off, the PSC needs to control their power switches. In this solution, the power module configuration uses the method of array members to process the power modules as specific arrays, and matches the power-off process of the power modules through regular expressions to automatically generate the hardware design code of the power modules.

[0024] In the power consumption management system, for all modules in the chip that need to be power consumption management controlled, reducing their power consumption by turning off the clocks of these modules is a key strategy. When implementing this strategy during the clock module configuration process, first, a special character matching pattern needs to be used to accurately determine whether the modules that need low-power control are network hosts or network slaves in the system. At the same time, according to whether the network request initiation method of the module is active or passive, a clear network request signal corresponding to the network request initiation method is generated. The core point of this link is to perform multi-dimensional screening from the array members, accurately locate and extract the unique network request signals of each module that needs low-power control. After completing the above steps, the control logic of the clock module is cleverly matched with wildcards to generate scripts for the clock, reset, and isolation control, etc. of the modules that need low-power control.

[0025] The test environment part quickly builds a test framework (model) suitable for a specific chip design by flexibly adjusting the array members and variable settings, supporting various test scenarios from simple to complex; through variable settings, the assertion syntax of the test stimuli is scripted, and finally, module-level test stimuli generation including address testing, single-module power consumption control process, and concurrent power consumption control process is achieved, providing strong guarantee for the correctness and reliability of the power consumption management controller. In the generation process of this test environment and test stimuli, the design difficulty is that the test scenarios of different chips need to match different output variables, and it is necessary to ensure that the hardware design code of the power consumption management controller is always consistent with the control results of the test model.

[0026] The above method for automatically generating a chip power consumption management controller customizes the code of the network transmission protocol by parameter passing, so as to achieve precise control of the communication network transmission process between the power consumption management controller and the chip system. Then, the power supply module is processed as a specific array by the method of array members, and the power-off process of the power supply module is matched through regular expressions to automatically generate the hardware design code of the power supply module. Finally, by flexibly adjusting the array members and variable settings, a test model suitable for a specific chip design is quickly built, and the hardware design code of the power consumption management controller is interconnected with the test environment of the test model to transmit test information.

[0027] Compared with the traditional technology, through the above automatic generation method based on parameter passing, only need to confirm the low-power control method of the chip module and pass it into the script in the form of parameters, then the corresponding hardware design code and module-level test environment and excitation can be quickly generated, thus greatly improving the customization design work efficiency of the power consumption management controller and reducing the time and workload of manual code writing and test model; because of the scripted generation method, if you need to add or delete modules during the chip design process, you only need to modify the passed parameters to quickly implement the change of the hardware design code, improving the flexibility and maintainability of the design.

[0028] In one embodiment, during the module address decoding process, the module name of the module to be controlled is stored in an array as a member of the array.

[0029] It can be understood that the processing flow of hardware design generation is as Figure 4 shown. Regarding module address decoding, the way of passing parameters is to use different modules as members of the array, and based on this, a script for module address decoding is implemented. For example, assume that the modules to be controlled passed in include module A, module B, and module C of the chip. By storing the module names of these modules in an array, such as array @modules = ("moduleA", "moduleB", "moduleC"). The core of this specific implementation method is: by matching each member in the array with the data (this data is the address information of the module in the old version of the chip, used to ensure that users do not need to reconfigure the address information of the unchanged modules in the driver in the revised chip) to calculate the address, so as to accurately complete the address decoding of the corresponding module and lay a foundation for the stable operation and efficient control of the system.

[0030] In one embodiment, regarding the process of generating the hardware design code of the power supply module by matching the power-off process of the power supply module through regular expressions, it can specifically include: After screening out the control signals related to the power supply module by matching special characters, a power control signal list is generated; Automatically generate the power module control script according to the matching result.

[0031] Regarding the specific implementation of the power module configuration, for example: If the control process of the power module follows a specific naming rule, such as "power_down_moduleX" for turning off the power of module X. In this process, a crucial step is to accurately distinguish the different power domains in the power module. The power module configuration can filter out relevant control signals by matching special characters, and then generate a detailed list of power control signals for module X, such as Figure 4 In the example for the power control domain "domain", the power control domain can be matched by matching special characters such as "domain a", "domain b", etc.; then, according to the matching result, automatically generate the power module control script for module X to ensure that when the system needs to turn off the power of module X, the operation can be accurately executed to turn off the power of module X, ensuring the stable and low-power operation of the system.

[0032] In one embodiment, regarding the clock module configuration process, specifically for example: When processing clock signals, wildcards can be used to match the clock signal names of all modules that require low-power control, such as in the form of "clk_*" for the clock signal name, covering various clock signals comprehensively. Subsequently, write the corresponding clock control logic script for these matched clock signal names to achieve reliable clock shutdown operations for the corresponding modules. In this process, synchronously take into account relevant logics such as reset and isolation control, as Figure 4 shown in the figure, to ensure that the system runs stably and reliably during the clock shutdown period, avoiding various potential problems caused by clock shutdown.

[0033] In one embodiment, it can be understood that regarding the generation process of the above test environment and test stimuli, specifically, the test environment part quickly builds a test model suitable for a specific chip design by flexibly adjusting the array members and variable settings, supporting various test scenarios from simple to complex. Interconnect the hardware design code of the power management controller with the test environment and transmit test information such as Figure 5As shown below. First, store the module address information to be tested in an array, such as the test address array @test_addresses = ("address1", "address2",...). Then, based on this address information, start the power management control process. Through variable settings, the assertion syntax of the test stimulus is scripted. Specifically, for example: define the variable $expected_result to represent the expected test result, and use the assertion statement in Perl language if ($actual_result == $expected_result) { print "Test Passed";} else { print "TestFailed";} to verify whether the power management control process is correct. Finally, a module-level test stimulus including address testing, single-module power control process, and concurrent power control process is implemented, providing a strong guarantee for the verification of the correctness and reliability of the power management controller.

[0034] It should be understood that although the various steps in the above process Figure 2 are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the above process Figure 2 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0035] In one embodiment, as Figure 6As shown in the figure, a chip power consumption management controller automatic generation device 100 is provided, which includes a bus configuration module 11, an address decoding module 13, a power supply configuration module 15, a network request module 17, a clock configuration module 19, and a test stimulus module 21. Among them, the bus configuration module 11 is used to customize and configure the code of the network transmission protocol by means of parameter passing based on the Perl language, and complete the bus interface configuration between the power consumption management controller and the chip system. The address decoding module 13 is used to write the address decoding logic for each module of the chip during the module address decoding process using the Perl language. The power supply configuration module 15 is used to use the members of an array based on the Perl language to treat the power supply module of the chip as a specific array and match the power-off process of the power supply module through a regular expression to generate the hardware design code of the power supply module. The network request module 17 is used to determine the network status and network request initiation method of the module that requires low-power control in the system based on the Perl language using a special character matching pattern, and generate a clear network request signal corresponding to the network request initiation method; the network status includes a network host or a network slave, and the network request initiation method includes active or passive. The clock configuration module 19 is used to match the control logic of the clock module using wildcards to generate scripts for the clock logic, reset logic, and isolation control logic of the modules that require low-power control in the chip. The test stimulus module 21 is used to quickly build a test model suitable for chip design by adjusting the members of the array based on the Perl language, and then script the assertion syntax of the test stimulus through variable settings to complete the automatic generation of the chip power consumption management controller.

[0036] The above-mentioned chip power consumption management controller automatic generation device 100 customizes and configures the code of the network transmission protocol by means of parameter passing, so as to achieve precise control of the communication network transmission process between the power consumption management controller and the chip system. Then, the power supply module is treated as a specific array by means of the members of the array, and the power-off process of the power supply module is matched through a regular expression to automatically generate the hardware design code of the power supply module. Finally, by flexibly adjusting the members of the array and variable settings, a test model suitable for a specific chip design is quickly built, and the hardware design code of the power consumption management controller is interconnected with the test environment of the test model and test information is transmitted. It reduces the time and workload of manually writing code and test models, can quickly implement changes to the hardware design code, and improves the flexibility and maintainability of the design.

[0037] In one embodiment, during the module address decoding process, the module names of the modules to be controlled are stored in an array as members of the array.

[0038] In one embodiment, the process of generating the hardware design code of the power supply module by matching the power-off process of the power supply module through regular expressions may include: generating a list of power control signals related to the power supply module by screening out the control signals related to the power supply module through the matching of special characters; automatically generating a power supply module control script for the module according to the matching result.

[0039] For the specific limitations of the above-mentioned chip power consumption management controller automatic generation device 100, reference may be made to the corresponding limitations of the chip power consumption management controller automatic generation method in the foregoing text, which will not be elaborated herein.

[0040] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the following processing steps are implemented: customizing and configuring the code of the network transmission protocol by means of parameter passing based on the Perl language to complete the bus interface configuration between the power consumption management controller and the chip system; writing address decoding logic for each module of the chip during the module address decoding process based on the Perl language; using the members of an array based on the Perl language to take the power supply module of the chip as a specific array and generating the hardware design code of the power supply module by matching the power-off process of the power supply module through regular expressions; determining the network status and network request initiation method of the modules that require low-power control in the system based on the special character matching mode of the Perl language and generating a clear network request signal corresponding to the network request initiation method; the network status includes a network host or a network slave, and the network request initiation method includes active or passive; using wildcard matching to match the control logic of the clock module and generating scripts for the clock logic, reset logic, and isolation control logic of the modules that require low-power control in the chip; after quickly building a test model suitable for chip design by adjusting the members of the array based on the Perl language, scripting the assertion syntax of the test stimulus through variable setting to complete the automatic generation of the chip power consumption management controller.

[0041] In one embodiment, when the processor executes the computer program, it may also implement the additional steps or sub-steps in each embodiment of the above-mentioned power consumption management controller automatic generation method.

[0042] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided by the present invention can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, abbreviated as RDRAM), and interface dynamic random access memory (DRDRAM), etc.

[0043] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0044] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it cannot be understood as a limitation on the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A method for automatically generating a chip power management controller, characterized in that: Includes steps: Based on the Perl language, the code for configuring the network transmission protocol is customized by passing parameters to complete the bus interface configuration between the power management controller and the chip system; Use Perl language to write address decoding logic for each module of the chip during module address decoding process; Based on the Perl language, the chip's power module is used as a specific array by using array members and the power module's shutdown process is matched through regular expressions to generate the hardware design code of the power module; Based on the Perl language, a special character matching pattern is used to determine the network position and network request initiation mode of the module requiring low power consumption control in the system, and a clear network request signal corresponding to the network request initiation mode is generated; the network position includes a network host or a network slave, and the network request initiation mode includes active or passive; Use wildcards to match the control logic of the clock module and generate scripts for the clock logic, reset logic, and isolation control logic of the modules in the chip that require low-power control; After quickly building a test model suitable for chip design by adjusting array members based on Perl language, the assertion syntax of test stimulus is scripted through variable setting to complete the automatic generation of chip power consumption management controller.

2. The method for automatically generating a chip power management controller according to claim 1, characterized in that: During the module address decoding process, the module name of the module to be controlled is stored in the array as a member of the array.

3. The method for automatically generating a chip power management controller according to claim 1 or 2, characterized in that: The process of generating the hardware design code of the power module by matching the shutdown process of the power module through regular expressions includes: By matching special characters, control signals related to the power module are screened out and a power control signal list is generated; Automatically generate the power module control script of the module according to the matching results.

4. A device for automatically generating a chip power management controller, characterized in that: include: The bus configuration module is used to customize the code for configuring the network transmission protocol by parameter passing based on the Perl language, and complete the bus interface configuration between the power management controller and the chip system; An address decoding module is used to write address decoding logic for each module of the chip in the process of module address decoding using Perl language; The power configuration module is used to use the array member method based on the Perl language to treat the power module of the chip as a specific array and match the shutdown process of the power module through a regular expression to generate the hardware design code of the power module; A network request module, used to determine the network position of the module requiring low power consumption control in the system and the network request initiation method based on the Perl language using a special character matching pattern, and generate a clear network request signal corresponding to the network request initiation method; the network position includes a network host or a network slave, and the network request initiation method includes active or passive; The clock configuration module is used to use wildcard matching to control the clock module's control logic and generate scripts for the clock logic, reset logic, and isolation control logic of the module in the chip that requires low-power control; The test stimulus module is used to quickly build a test model suitable for chip design by adjusting array members based on the Perl language, and then script the assertion syntax of the test stimulus through variable settings to complete the automatic generation of the chip power consumption management controller.

5. The chip power management controller automatic generation device according to claim 4, characterized in that: During the module address decoding process, the module name of the module to be controlled is stored in the array as a member of the array.

6. The chip power management controller automatic generation device according to claim 4 or 5, characterized in that: The process of generating the hardware design code of the power module by matching the shutdown process of the power module through regular expressions includes: By matching special characters, control signals related to the power module are screened out and a power control signal list is generated; Automatically generate the power module control script of the module according to the matching results.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method for automatically generating a chip power consumption management controller according to any one of claims 1 to 3 are implemented.

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