Solar cell and preparation method of solar cell

Abstract

The invention discloses a solar cell and a preparation method thereof. The solar cell comprises a semiconductor substrate, the semiconductor substrate is provided with a light receiving surface and a backlight surface which are oppositely arranged, and the backlight surface of the semiconductor substrate is provided with a first area and a second area; a tunneling dielectric layer and a first doping layer, wherein the tunneling dielectric layer and the first doping layer are sequentially stacked on the first region; the intrinsic passivation layer and the second doping layer are sequentially arranged on the second area in a stacked mode, the intrinsic passivation layer is made of intrinsic silicon, and the doping type of the second doping layer is opposite to that of the first doping layer; and the oxidation isolation layer is arranged between the first doping layer and the second doping layer and is used for isolating the first doping layer from the second doping layer in an insulating manner. The problem of electric leakage can be improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and particularly to a solar cell and a method for manufacturing the same. Background Art

[0002] A back contact (BC) solar cell is a solar cell in which both the positive electrode and the negative electrode are disposed on the backlight surface. The light-receiving surface of the back contact solar cell is not blocked by grid line electrodes, which is not only more aesthetically pleasing but also has a high photoelectric conversion efficiency.

[0003] A passivation contact structure is usually provided on the backlight surface of the back contact solar cell to reduce the recombination of carriers and increase the extraction amount of carriers. There are usually two types of passivation contact structures in the traditional technology, namely a passivation contact structure based on a tunneling dielectric material and a doped silicon material, and a passivation contact structure based on an intrinsic silicon material and a doped silicon material. A design in which the N region and the P region of a back contact solar cell respectively adopt the above two passivation contact structures has high efficiency potential and a wide process window, and is expected to be industrially applied. However, such a structural design has a problem of easy leakage. Summary of the Invention

[0004] Based on this, it is necessary to provide a solar cell that can improve the leakage problem for the problems in the above background art.

[0005] The present disclosure provides a solar cell, which includes:

[0006] A semiconductor substrate having a light-receiving surface and a backlight surface disposed opposite to each other, and having a first region and a second region on the backlight surface of the semiconductor substrate;

[0007] A tunneling dielectric layer and a first doped layer, the tunneling dielectric layer and the first doped layer are sequentially stacked on the first region;

[0008] An intrinsic passivation layer and a second doped layer, the intrinsic passivation layer and the second doped layer are sequentially stacked on the second region, the material of the intrinsic passivation layer includes intrinsic silicon, and the doping type of the second doped layer is opposite to the doping type of the first doped layer; and,

[0009] An oxidation isolation layer disposed between the first doped layer and the second doped layer, and insulatingly spacing the first doped layer and the second doped layer.

[0010] In some embodiments of the present disclosure, one side of the oxidation isolation layer contacts the sidewalls of the tunneling dielectric layer and the first doped layer, the other side of the oxidation isolation layer contacts the intrinsic passivation layer, and the intrinsic passivation layer is disposed between the second doped layer and the oxidation isolation layer.

[0011] In some embodiments of the present disclosure, on the backlight surface, the surface of the first region protrudes from the surface of the second region. The oxidation isolation layer includes a sidewall isolation portion and a bottom wall isolation portion that are integrally formed. The sidewall isolation portion contacts the sidewall of the semiconductor substrate in the first region close to the second region, and the bottom wall isolation portion contacts the semiconductor substrate in the second region.

[0012] In some embodiments of the present disclosure, the width of the oxidation isolation layer on the backlight surface is 5 μm to 20 μm; and / or,

[0013] the thickness of the oxidation isolation layer is 1 nm to 10 nm.

[0014] In some embodiments of the present disclosure, the first region includes an overlapping sub-region adjacent to the second region. The solar cell further includes an insulating barrier layer, and the insulating barrier layer is disposed in the overlapping sub-region and stacked on the side of the first doped layer away from the semiconductor substrate;

[0015] the intrinsic passivation layer and the second doped layer further extend onto the overlapping sub-region and are sequentially stacked on the side of the insulating barrier layer away from the semiconductor substrate.

[0016] In some embodiments of the present disclosure, the solar cell further includes an insulating antireflection layer, and the insulating antireflection layer is disposed on the sides of the first doped layer and the second doped layer away from the semiconductor substrate.

[0017] In some embodiments of the present disclosure, the solar cell further includes a first transparent conductive layer and a second transparent conductive layer. The first transparent conductive layer is disposed on the side of the first doped layer away from the semiconductor substrate and is electrically connected to the first doped layer. The second transparent conductive layer is disposed on the side of the second doped layer away from the semiconductor substrate and is electrically connected to the second doped layer. An isolation groove is disposed on the overlapping sub-region between the first transparent conductive layer and the second transparent conductive layer.

[0018] In some embodiments of the present disclosure, the doping type of the first doped layer is N-type, and the doping type of the second doped layer is P-type.

[0019] In some embodiments of the present disclosure, on the backlight surface, the surface of the second region has a matte structure; and / or,

[0020] The light-receiving surface has a matte structure.

[0021] In some embodiments of the present disclosure, the solar cell further includes a light-receiving surface functional layer disposed on the light-receiving surface of the semiconductor substrate, and the light-receiving surface functional layer includes one or more of a passivation film and an antireflection film; and / or,

[0022] The solar cell further includes a first electrode and a second electrode disposed on the backlight surface of the semiconductor substrate, the first electrode is electrically connected to the first doping layer, and the second electrode is electrically connected to the second doping layer.

[0023] Furthermore, the present disclosure also provides a method for manufacturing a solar cell, which includes the following steps:

[0024] Provide a semiconductor substrate having opposite light-receiving and backlight surfaces, and the backlight surface has a first region and a second region;

[0025] Form a tunneling dielectric layer and a first doping layer stacked in sequence on the first region;

[0026] Oxidize the sidewalls of the tunneling dielectric layer and the first doping layer close to the second region to form an oxidation isolation layer;

[0027] Form an intrinsic passivation layer and a second doping layer stacked in sequence on the second region, the material of the intrinsic passivation layer includes intrinsic silicon, and the doping type of the second doping layer is opposite to that of the first doping layer.

[0028] In some embodiments of the present disclosure, the step of oxidizing the sidewalls of the tunneling dielectric layer and the first doping layer close to the second region includes:

[0029] Place the semiconductor substrate in an environment containing an oxidizing gas, and irradiate the sidewalls of the tunneling dielectric layer and the first doping layer close to the second region with a laser.

[0030] In some embodiments of the present disclosure, during the laser irradiation, the laser is inclined towards the sidewalls of the tunneling dielectric layer and the first doping layer close to the second region, and the inclination angle of the laser with respect to the backlight surface is 30° - 60°.

[0031] In some embodiments of the present disclosure, the power of the laser is 5W - 15W, and the spot size of the laser is 5μm - 20μm.

[0032] In some embodiments of the present disclosure, the first region includes an overlapping sub-region adjacent to the second region;

[0033] The step of forming a tunneling dielectric layer and a first doped layer which are sequentially stacked on the first region includes:

[0034] Deposit a tunneling precursor layer and a first doped precursor layer on the backlight surface in sequence, form an insulating precursor layer on the first doped precursor layer, and etch away the tunneling precursor layer and the first doped precursor layer located outside the first region, so that the remaining tunneling precursor layer and the first doped precursor layer serve as the tunneling dielectric layer and the first doped layer respectively;

[0035] After forming the first doped layer, it further includes: etching away the insulating precursor layer located outside the overlapping sub-region, so that the remaining insulating precursor layer serves as an insulating barrier layer.

[0036] In some embodiments of the present disclosure, the step of forming an intrinsic passivation layer and a second doped layer which are sequentially stacked on the second region includes:

[0037] Deposit an intrinsic precursor layer and a second doped precursor layer on the backlight surface in sequence, and etch away the intrinsic precursor layer and the second doped precursor layer located outside the second region and the overlapping sub-region, so that the remaining intrinsic precursor layer and the second doped precursor layer serve as the intrinsic passivation layer and the second doped layer respectively.

[0038] In some embodiments of the present disclosure, after forming the first doped layer and the second doped layer, it further includes the step of depositing an insulating antireflection layer on the backlight surface, and the insulating antireflection layer is disposed on a side of the first doped layer and the second doped layer away from the semiconductor substrate.

[0039] In some embodiments of the present disclosure, after forming the first doped layer and the second doped layer, it further includes the following steps:

[0040] Form a transparent conductive precursor layer on a side of the first doped layer and the second doped layer away from the semiconductor substrate; and,

[0041] Form an isolation groove on the overlapping sub-region, which penetrates through the insulating antireflection layer, the transparent conductive precursor layer, the second doped layer and the intrinsic passivation layer.

[0042] In some embodiments of the present disclosure, after forming the first doped layer and before forming the oxidation isolation layer, it further includes the following steps:

[0043] Texturize the light-receiving surface; and / or,

[0044] Texturize the second region on the backlight surface.

[0045] In the solar cell of at least one of the above embodiments, a first carrier extraction structure and a second carrier extraction structure for extracting two types of carriers are provided respectively. The first carrier extraction structure includes a tunneling dielectric layer and a first doping layer, and the second carrier extraction structure includes an intrinsic passivation layer and a second doping layer. An oxidation isolation layer is further provided between the first carrier extraction structure and the second carrier extraction structure. The oxidation isolation layer insulates and spaces the first doping structure and the second doping structure, and can suppress or avoid carrier recombination between the first doping structure and the second doping structure, thereby improving the leakage problem of the solar cell.

[0046] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly and to be implemented in accordance with the content of the description, the following describes the preferred embodiments of the present invention in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the present application, the drawings used in the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0048] Figure 1 It is a schematic cross-sectional structure diagram of a solar cell of the present disclosure;

[0049] Figure 2 It is a schematic diagram of the steps of a preparation method of a solar cell;

[0050] Figure 3 It is a schematic cross-sectional structure diagram of a semiconductor substrate;

[0051] Figure 4 For depositing a tunneling precursor layer and a first doping precursor layer on the basis of the structure shown in Figure 3 It is a schematic structure diagram;

[0052] Figure 5 For forming a tunneling dielectric layer and a first doping layer on the basis of the structure shown in Figure 4 It is a schematic structure diagram;

[0053] Figure 6 For forming a light-receiving surface functional layer on the basis of the structure shown in Figure 5 It is a schematic structure diagram;

[0054] Figure 7 For forming an oxidation isolation layer on the basis of the structure shown in Figure 6 It is a schematic structure diagram;

[0055] Figure 8 For depositing a tunneling precursor layer and a first doping precursor layer on the basis of the structure shown in Figure 7Schematic diagram of the structure of the intrinsic precursor layer and the second doped precursor layer formed on the basis of the shown structure;

[0056] Figure 9 For forming Figure 8 Schematic diagram of the structure of the second doped layer and the intrinsic passivation layer formed on the basis of the shown structure;

[0057] Figure 10 For forming Figure 9 Schematic diagram of the structure of the transparent conductive precursor layer and the insulating antireflection layer formed on the basis of the shown structure;

[0058] Figure 11 For forming Figure 10 Schematic diagram of the structure of the isolation groove formed on the basis of the shown structure.

[0059] Among them, the meanings of the respective reference numerals are as follows:

[0060] 100, semiconductor substrate; 101, first region; 1011, overlapping sub-region; 102, second region; 103, isolation groove; 104, first conductive contact groove; 105, second conductive contact groove; 110, first doped layer; 1100, first doped precursor layer; 111, tunneling dielectric layer; 1110, tunneling precursor layer; 120, second doped layer; 1200, second doped precursor layer; 121, intrinsic passivation layer; 1210, intrinsic precursor layer; 130, oxidation isolation layer; 131, sidewall isolation portion; 132, bottom wall isolation portion; 140, insulating barrier layer; 1400, insulating precursor layer; 151, passivation film; 152, antireflection film; 160, first transparent conductive layer, second transparent conductive layer; 170, insulating antireflection layer; 180, first electrode; 190, second electrode. Detailed implementation manners

[0061] Hereinafter, embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and thus are only examples and cannot be used to limit the protection scope of the present application.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above accompanying drawing descriptions are intended to cover non-exclusive inclusion.

[0063] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality of" is more than two, unless otherwise specifically and clearly defined.

[0064] Reference to "embodiments" in this context means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0065] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this text generally represents an "or" relationship between the associated objects before and after.

[0066] In the description of the embodiments of the present application, the term "a plurality of" means more than two (including two). Similarly, "a plurality of groups" means more than two groups (including two groups), and "a plurality of pieces" means more than two pieces (including two pieces).

[0067] In the description of the embodiments of the present application, technical terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the embodiments of the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0068] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0069] In some traditional back-contact solar cells, the intrinsic silicon material in the passivation contact structure can be used not only to passivate the surface of the semiconductor substrate but also to separate the N region and the P region. However, the intrinsic silicon material still has certain conductivity, which makes different carriers prone to recombination at the intrinsic silicon material at the interface, resulting in the problem of leakage current.

[0070] The present disclosure provides a solar cell, which includes a semiconductor substrate, a tunneling dielectric layer, a first doped layer, an intrinsic passivation layer, a second doped layer, and an oxidation isolation layer. The semiconductor substrate has a light-receiving surface and a backlight surface disposed opposite to each other, and a first region and a second region are provided on the backlight surface of the semiconductor substrate. The tunneling dielectric layer and the first doped layer are sequentially stacked on the first region. The intrinsic passivation layer and the second doped layer are sequentially stacked on the second region. The material of the intrinsic passivation layer includes intrinsic silicon, and the doping type of the second doped layer is opposite to that of the first doped layer. The oxidation isolation layer is disposed between the first doped layer and the second doped layer and insulates and separates the first doped layer and the second doped layer.

[0071] The solar cell of the present disclosure respectively disposes a tunneling dielectric layer, a first doped layer, an intrinsic passivation layer, and a second doped layer on the back of the semiconductor substrate, and the material of the intrinsic passivation layer includes intrinsic silicon. Moreover, the solar cell also disposes an oxidation isolation layer. Compared with the traditional technology, the introduction of the oxidation isolation layer can enhance the insulation effect of the intrinsic silicon. Using the oxidation isolation layer and the intrinsic silicon together to separate the first doped layer and the second doped layer can effectively avoid the recombination of different carriers, thereby significantly improving the problem of leakage current.

[0072] Figure 1 is a schematic cross-sectional structure diagram of a solar cell of the present disclosure. Refer to Figure 1 As shown, the solar cell includes a semiconductor substrate 100, a tunneling dielectric layer 111, a first doped layer 110, an intrinsic passivation layer 121, a second doped layer 120, and an oxidation isolation layer 130.

[0073] Refer to Figure 1 As shown, the semiconductor substrate 100 has a light-receiving surface (such as the upper surface in Figure 1 ) and a backlight surface (such as the lower surface shown in Figure 1 ) disposed opposite to each other, and a first region 101 and a second region 102 are provided on the backlight surface of the semiconductor substrate 100. The tunneling dielectric layer 111 and the first doped layer 110 are sequentially stacked on the first region 101. The intrinsic passivation layer 121 and the second doped layer 120 are sequentially stacked on the second region 102, and the material of the intrinsic passivation layer 121 includes intrinsic silicon. The oxidation isolation layer 130 is disposed between the first doped layer 110 and the second doped layer 120 and insulates and separates the first doped layer 110 and the second doped layer 120.

[0074] As an example of this embodiment, the material of the semiconductor substrate 100 includes silicon. For example, the semiconductor substrate 100 is a single crystal silicon wafer or a polycrystalline silicon wafer.

[0075] As an example of this embodiment, the material of the semiconductor substrate 100 is a doped semiconductor material. The doping type of the semiconductor substrate 100 can be N-type or P-type.

[0076] In this embodiment, the doping type of the second doping layer 120 is opposite to that of the first doping layer 110. As an example of this embodiment, the doping type of the first doping layer 110 is the same as that of the semiconductor substrate 100.

[0077] As an example of this embodiment, the material of the first doping layer 110 is doped polysilicon, so that the first doping layer 110 has good electrical contact performance.

[0078] As an example of this embodiment, the material of the second doping layer 120 is selected from doped amorphous silicon, doped microcrystalline silicon or doped nanocrystalline silicon.

[0079] As an example of this embodiment, the thickness of the second doping layer 120 is 10 nm to 30 nm.

[0080] As an example, the doping type of the first doping layer 110 is N-type. For example, the doping element in the first doping layer 110 is phosphorus. Optionally, the thickness of the first doping layer 110 is 100 nm to 250 nm. Optionally, the doping concentration in the first doping layer 110 is 1×10 20 cm -3 ~8×10 20 cm -3 . Further optionally, the doping concentration in the first doping layer 110 is 2×10 20 cm -3 ~5×10 20 cm -3 . Further still, the sheet resistance of the first doping layer 110 is 30 Ω / sq to 50 Ω / sq.

[0081] Correspondingly, the doping type of the second doping layer 120 is P-type. For example, the doping element in the second doping layer 120 is boron. Optionally, the doping concentration in the second doping layer 120 is 1×10 19 cm -3 ~8×10 19 cm -3 . Further optionally, the doping concentration in the second doping layer 120 is 3×10 19 cm -3 ~6×10 19 cm -3Furthermore, the sheet resistance of the second doping layer 120 is 120 Ω / sq to 150 Ω / sq.

[0082] As another example, the doping type of the first doping layer 110 is P-type. For example, the doping element in the first doping layer 110 is boron. Optionally, the thickness of the first doping layer 110 is 250 nm to 400 nm. Optionally, the doping concentration in the first doping layer 110 is 1×10 19 cm -3 ~8×10 19 cm -3 . Further optionally, the doping concentration in the first doping layer 110 is 3×10 19 cm -3 ~6×10 19 cm -3 . Furthermore, the sheet resistance of the first doping layer 110 is 120 Ω / sq to 150 Ω / sq.

[0083] Correspondingly, the doping type of the second doping layer 120 is N-type. For example, the doping element in the second doping layer 120 is phosphorus. Optionally, the doping concentration in the second doping layer 120 is 1×10 20 cm -3 ~8×10 20 cm -3 . Further optionally, the doping concentration in the second doping layer 120 is 2×10 20 cm -3 ~5×10 20 cm -3 . Furthermore, the sheet resistance of the second doping layer 120 is 30 Ω / sq to 50 Ω / sq.

[0084] As an example of this embodiment, on the backlight surface of the semiconductor substrate 100, the region where the first doping layer 110 is located is the first region 101, and the region outside the first region 101 is the second region 102. The width of the first region 101 can be selected correspondingly according to the doping type of the first doping layer 110, and the width of the second region 102 can be selected correspondingly according to the doping type of the second doping layer 120.

[0085] As an example, the doping type of the first doping layer 110 is N-type. At this time, the width of the first region 101 can be 400 μm to 500 μm, and the width of the second region 102 can be 550 μm to 700 μm.

[0086] As another example, the doping type of the first doping layer 110 is P-type. The width of the first region 101 can be 550 μm to 700 μm, and the width of the second region 102 can be 400 μm to 500 μm.

[0087] As an example of this embodiment, the material of the tunneling dielectric layer 111 is the oxide of the semiconductor substrate 100, such as silicon oxide. The tunneling dielectric layer 111 is used to passivate the surface of the semiconductor substrate 100, and the tunneling dielectric layer 111 should also allow carriers to tunnel through and conduct from the semiconductor substrate 100 into the first doped layer 110.

[0088] As an example of this embodiment, the thickness of the tunneling dielectric layer 111 is 1 nm to 2.5 nm. Optionally, the thickness of the tunneling dielectric layer 111 is 1.5 nm to 2 nm.

[0089] The intrinsic passivation layer 121 is used to passivate the surface of the semiconductor substrate 100. As an example of this embodiment, the thickness of the intrinsic passivation layer 121 can be 5 nm to 15 nm.

[0090] Refer to Figure 1 As shown, as an example of this embodiment, one side of the oxidation isolation layer 130 is in contact with the side walls of the tunneling dielectric layer 111 and the first doped layer 110, and the other side of the oxidation isolation layer 130 is in contact with the intrinsic passivation layer 121. An intrinsic passivation layer 121 is provided between the second doped layer 120 and the oxidation isolation layer 130. It can be understood that at this time, the second doped layer 120 and the first doped layer 110 are spaced apart by the oxidation isolation layer 130 and the intrinsic passivation layer 121. Using the oxidation isolation layer 130 and the intrinsic passivation layer 121 together as the spacer structure can more significantly improve the problem of carrier recombination and improve the conversion efficiency of the solar cell.

[0091] Refer to Figure 1 As shown, as a further example of this embodiment, on the backlight surface, the surface of the first region 101 protrudes from the surface of the second region 102. The oxidation isolation layer 130 includes a sidewall isolation portion 131 and a bottom wall isolation portion 132 having an integral structure. The sidewall isolation portion 131 is in contact with the side wall of the semiconductor substrate 100 in the first region 101 close to the second region 102, and the bottom wall isolation portion 132 is in contact with the semiconductor substrate 100 in the second region 102. Among them, the intrinsic passivation layer 121 and the second doped layer 120 are also sequentially provided on the side of the sidewall isolation portion 131 away from the first doped layer 110, so that the sidewall isolation portion 131 and the intrinsic passivation layer 121 are jointly located between the first doped layer 110 and the second doped layer 120. The bottom wall isolation portion 132 can be used to further insulate and space the intrinsic passivation layer 121 and the first region 101 of the semiconductor substrate 100.

[0092] As an example of this embodiment, the height difference between the first region 101 and the second region 102 is 1 μm to 8 μm. Optionally, the height difference between the first region 101 and the second region 102 can be 2 μm to 5 μm.

[0093] Referring to Figure 1 as shown, along the direction parallel to the surface of the second region 102, the oxidation isolation layer 130 has a width. As an example of this embodiment, the width of the oxidation isolation layer 130 on the backlight surface is 5 μm to 20 μm. For example, the width of the oxidation isolation layer 130 can be 5 μm, 6 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm. Alternatively, the width of the oxidation isolation layer 130 can also be between any two of the above widths.

[0094] Referring to Figure 1 as shown, as an example of this embodiment, the thickness of the oxidation isolation layer 130 is 1 nm to 10 nm. For example, the thickness of the oxidation isolation layer 130 can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 7 nm, 9 nm, 10 nm. Alternatively, the thickness of the oxidation isolation layer 130 can also be between any two of the above thicknesses. The oxidation isolation layer 130 with this thickness can more fully insulate and separate the first doped layer 110 and the second doped layer 120.

[0095] It can be understood that the oxidation isolation layer 130 includes a sidewall isolation portion 131 and a bottom wall isolation portion 132 with different extending directions, and the thicknesses of different parts should be understood differently in combination with the general knowledge of those skilled in the art. For example, the thickness of the sidewall isolation portion 131 should be understood as the distance between the side close to the first doped layer 110 and the side far from the first doped layer 110, and the thickness of the bottom wall isolation portion 132 should be understood as the distance between the side close to the semiconductor substrate 100 and the side far from the semiconductor substrate 100.

[0096] Referring to Figure 1 as shown, as an example of this embodiment, the first region 101 includes an overlapping sub-region 1011 adjacent to the second region 102. The solar cell further includes an insulating barrier layer 140, and the insulating barrier layer 140 is disposed in the overlapping sub-region 1011 and is stacked on the side of the first doped layer 110 away from the semiconductor substrate 100. The intrinsic passivation layer 121 and the second doped layer 120 also extend and are disposed on the overlapping sub-region 1011, and are sequentially stacked on the side of the insulating barrier layer 140 away from the semiconductor substrate 100. Among them, the insulating barrier layer 140 is used to avoid electrical connection between the first doped layer 110 and the second doped layer 120 located on the overlapping sub-region 1011. Extending part of the second doped layer 120 on the insulating barrier layer 140 is not only beneficial to broadening the process window during the preparation process, but also beneficial to the subsequent preparation of the transparent conductive layer 160.

[0097] As an example of this embodiment, the width of the overlapping sub-region 1011 is 60 μm to 220 μm. Optionally, the width of the overlapping sub-region 1011 can be 100 μm to 180 μm.

[0098] As an example of this embodiment, the thickness of the insulating barrier layer 140 is 30 nm to 70 nm.

[0099] As an example of this embodiment, the material of the insulating barrier layer 140 can be selected from one or more of doped silicon oxide, silicon oxide, silicon oxynitride, and silicon nitride. Among them, the doped silicon oxide can be phosphosilicate glass (PSG) or borosilicate glass (BSG).

[0100] Refer to Figure 1 As shown, as an example of this embodiment, the solar cell further includes an insulating antireflection layer 170, and the insulating antireflection layer 170 is disposed on the sides of the first doping layer 110 and the second doping layer 120 away from the semiconductor substrate 100. Among them, the insulating antireflection layer 170 is used to enhance the insulation effect between the first region 101 and the second region 102 and prevent short - circuiting between the surfaces of the first doping layer 110 and the second doping layer 120 caused by foreign object bridging.

[0101] As a further example of this embodiment, the material of the insulating antireflection layer 170 includes silicon oxide. Silicon oxide not only has an insulating effect but also can reduce the reflectivity of the backlight surface to light, which is beneficial to improving the bifaciality of the solar cell and further improving the performance of the solar cell.

[0102] As a further example of this embodiment, the thickness of the insulating antireflection layer 170 is 80 nm to 200 nm.

[0103] Refer to Figure 1 As shown, as an example of this embodiment, the solar cell further includes a first transparent conductive layer 160 and a second transparent conductive layer 160. The first transparent conductive layer 160 is disposed on the side of the first doping layer 110 away from the semiconductor substrate 100 and is electrically connected to the first doping layer 110. The second transparent conductive layer 160 is disposed on the side of the second doping layer 120 away from the semiconductor substrate 100 and is electrically connected to the second doping layer 120. An isolation groove 103 is provided on the overlapping sub - region 1011 between the first transparent conductive layer 160 and the second transparent conductive layer 160. Among them, the first transparent conductive layer 160 and the second transparent conductive layer 160 are respectively used to improve the electrical contact performance between the first doping layer 110 and the second doping layer 120 and the first electrode 180 and the second electrode 190. The isolation groove 103 is used to prevent short - circuiting between the first transparent conductive layer 160 and the second transparent conductive layer 160.

[0104] Refer to Figure 1 As shown, as an example of this embodiment, the insulating antireflection layer 170 is disposed on the sides of the first transparent conductive layer 160 and the second transparent conductive layer 160 away from the semiconductor substrate 100.

[0105] As an example of this embodiment, the materials and thicknesses of the first transparent conductive layer 160 and the second transparent conductive layer 160 are the same. Further, the materials of the first transparent conductive layer 160 and the second transparent conductive layer 160 include one or more of indium tin oxide (ITO), indium tungsten oxide (IWO), and aluminum-doped zinc oxide (AZO). The thicknesses of the first transparent conductive layer 160 and the second transparent conductive layer 160 are 70 nm to 110 nm.

[0106] Referring to Figure 1 As shown, as an example of this embodiment, the isolation groove 103 also penetrates through the insulating antireflection layer 170, the second doping layer 120, and the intrinsic passivation layer 121 located on the overlapping sub-region 1011.

[0107] Referring to Figure 1 As shown, as an example of this embodiment, the width of the isolation groove 103 is less than the width of the overlapping sub-region 1011. For example, the width of the isolation groove 103 is 80 μm to 160 μm.

[0108] Referring to Figure 1 As shown, as an example of this embodiment, the light-receiving surface has a matte structure. The matte structure can enhance the absorption of light by the light-receiving surface, thereby improving the utilization rate of the front light by the solar cell.

[0109] Referring to Figure 1 As shown, as an example of this embodiment, on the backlight surface, the surface of the second region 102 has a matte structure. The matte structure can enhance the absorption of light by the surface of the second region 102, thereby improving the utilization rate of the backlight by the solar cell.

[0110] As a further example of this embodiment, the above-mentioned matte structure includes a plurality of pyramid-shaped protrusions, the height of the pyramid-shaped protrusion is 1 μm to 3 μm, and the radial dimension of the bottom surface of the pyramid-shaped protrusion is 1 μm to 3 μm.

[0111] Referring to Figure 1 As shown, as an example of this embodiment, the solar cell further includes a light-receiving surface functional layer, and the light-receiving surface functional layer is disposed on the light-receiving surface of the semiconductor substrate 100. The light-receiving surface functional layer includes one or more of a passivation film 151 and an antireflection film 152.

[0112] As a further example of this embodiment, the material of the passivation film 151 includes one or more of silicon oxide and aluminum oxide.

[0113] As a further example of this embodiment, the thickness of the passivation film 151 is 3 nm to 8 nm.

[0114] As a further example of this embodiment, the material of the antireflection film 152 includes one or more of silicon nitride and silicon oxynitride. Further, the material of the antireflection film 152 may also include silicon oxide. For example, a stacked structure composed of one or more of a silicon nitride thin film, a silicon oxynitride thin film, and a silicon oxide thin film may be used as the antireflection film 152.

[0115] As a further example of this embodiment, the thickness of the antireflection film 152 is 70 nm to 110 nm. The refractive index of the entire antireflection film 152 may be 2.0 to 2.1.

[0116] Referring to Figure 1 As shown, as an example of this embodiment, the solar cell further includes a first electrode 180 and a second electrode 190 disposed on the backlight surface of the semiconductor substrate 100. The first electrode 180 is electrically connected to the first doping layer 110, and the second electrode 190 is electrically connected to the second doping layer 120.

[0117] As a further example of this embodiment, the first electrode 180 passes through the insulating antireflection layer 170 and is in electrical contact with the first transparent conductive layer 160, and the second electrode 190 passes through the insulating antireflection layer 170 and is in electrical contact with the second transparent conductive layer 160.

[0118] As an example of this embodiment, the material of the first electrode 180 is metal. For example, the first electrode 180 is a silver electrode, a copper electrode, or a silver-coated copper electrode.

[0119] As an example of this embodiment, the material of the second electrode 190 is metal. For example, the second electrode 190 is a silver electrode, a copper electrode, or a silver-coated copper electrode.

[0120] The present disclosure also provides a method for manufacturing a solar cell. Figure 2 It is a schematic diagram of the steps of a method for manufacturing a solar cell. Referring to Figure 2 As shown, the manufacturing method includes the following steps to step S4.

[0121] Step S1, providing a semiconductor substrate 100.

[0122] Figure 3 It is a schematic cross-sectional structure diagram of a semiconductor substrate 100. Referring to Figure 3 As shown, the semiconductor substrate 100 has opposite light-receiving surfaces (such as Figure 3 the upper surface in Figure 3 shown) and a backlight surface (such as

[0123] As an example of this embodiment, the material of the semiconductor substrate 100 includes silicon. For example, a single-crystal silicon wafer or a polycrystalline silicon wafer can be used as the semiconductor substrate 100.

[0124] As an example of this embodiment, the material of the semiconductor substrate 100 is a doped semiconductor material. The doping type of the semiconductor substrate 100 can be N-type or P-type. In this embodiment, the doping type of the semiconductor substrate 100 is N-type.

[0125] As an example of this embodiment, it further includes the step of chemically polishing the semiconductor substrate 100. Further, an alkaline solution can be used to chemically polish the semiconductor substrate 100. During the chemical polishing process, the polishing temperature can be controlled at 60°C to 70°C, and the time of the chemical polishing process can be controlled at 150 s to 250 s.

[0126] In some examples, the alkali in the alkaline solution can be selected from sodium hydroxide, and the mass concentration of sodium hydroxide in the alkaline solution is 1.2% to 2%. It can be understood that in other examples, the alkali in the alkaline solution can also be selected from strong alkalis other than sodium hydroxide, such as potassium hydroxide.

[0127] As an example of this embodiment, after chemically polishing the semiconductor substrate 100, the reflectivity of the semiconductor substrate 100 is ≥39%.

[0128] Step S2, forming a tunneling dielectric layer 111 and a first doped layer 110 stacked in sequence on the first region 101.

[0129] As an example of this embodiment, the step of forming a tunneling dielectric layer 111 and a first doped layer 110 stacked in sequence on the first region 101 includes: sequentially depositing a tunneling precursor layer 1110 and a first doping precursor layer 1100 on the backlight surface, forming an insulating precursor layer 1400 on the first doping precursor layer 1100, and etching away the tunneling precursor layer 1110 and the first doping precursor layer 1100 located outside the first region 101, so that the remaining tunneling precursor layer 1110 and first doping precursor layer 1100 serve as the tunneling dielectric layer 111 and the first doped layer 110 respectively.

[0130] Figure 4 For depositing Figure 3 Schematic diagram of the structure of the tunneling precursor layer 1110 and the first doping precursor layer 1100 deposited on the basis of the shown structure.

[0131] As an example of this embodiment, the material of the tunneling precursor layer 1110 can be an oxide of the semiconductor substrate 100, such as silicon oxide.

[0132] As an example of this embodiment, the thickness of the tunneling precursor layer 1110 is 1 nm to 2.5 nm. Optionally, the thickness of the tunneling precursor layer 1110 is 1.5 nm to 2 nm.

[0133] As an example of this embodiment, the tunneling precursor layer 1110 is deposited by chemical vapor deposition. For example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) can be used.

[0134] As an example of this embodiment, the material of the first doped precursor layer 1100 is polysilicon. The doping type of the first doped precursor layer 1100 is N-type or P-type.

[0135] As some examples of this embodiment, the steps of forming the first doped precursor layer 1100 include: depositing intrinsic polysilicon on the semiconductor substrate 100, doping the intrinsic polysilicon by thermal diffusion to form doped polysilicon and a doped oxide film on the doped polysilicon, where the doped polysilicon can be used as the first doped precursor layer 1100, and the doped oxide film can be used as the insulating precursor layer 1400.

[0136] In a further example, the intrinsic polysilicon is deposited on the semiconductor substrate 100 by chemical vapor deposition, such as low-pressure chemical vapor deposition. Among them, during the deposition of the intrinsic polysilicon, the temperature in the deposition chamber can be controlled to be 550 °C to 650 °C.

[0137] In a further example, when doping the intrinsic polysilicon by thermal diffusion, a doping source gas is introduced into the diffusion furnace. The doping source gas can be selected according to the required doping type. For example, when the doping type of the first doped layer 110 is N-type, a phosphorus-containing gas can be used as the doping source gas. Another example is that when the doping type of the first doped layer 110 is P-type, a boron-containing gas can be used as the doping source gas.

[0138] In a further example, the doping source gas contains a phosphorus-containing gas, such as phosphorus oxychloride (POCl3). During the thermal diffusion process, the temperature of the diffusion furnace is controlled to be 800 °C to 900 °C. The doping concentration in the doped polysilicon formed after diffusion is 1×10 20 cm -3 ~8×10 20 cm -3 . Optionally, the doping concentration in the doped polysilicon is 2×10 20 cm -3 ~5×10 20 cm -3Further, the sheet resistance of the doped polysilicon is 30 Ω / sq to 50 Ω / sq. In a further example, the material of the corresponding formed insulating precursor layer 1400 is phosphosilicate glass (PSG), and its thickness is 80 nm to 120 nm.

[0139] In a further example, the doping source gas contains a boron-containing gas, such as one or more of boron tribromide (BBr3) and boron trichloride (BCl3). During the thermal diffusion process, the temperature of the diffusion furnace is controlled to be 850 °C to 950 °C. The doping concentration in the formed doped polysilicon after diffusion is 1×10 19 cm -3 ~8×10 19 cm -3 . Optionally, the doping concentration in the doped polysilicon is 3×10 19 cm -3 ~6×10 19 cm -3 . Further, the sheet resistance of the doped polysilicon is 120 Ω / sq to 150 Ω / sq. In a further example, the material of the corresponding formed insulating precursor layer 1400 is borosilicate glass (BSG), and its thickness is 80 nm to 120 nm.

[0140] As some other examples of this embodiment, the step of forming the first doped precursor layer 1100 includes: sequentially depositing a silicon material containing a doping element and an insulating precursor layer 1400 on the semiconductor substrate 100, and annealing the deposited silicon material to form doped polysilicon, which can be used as the first doped precursor layer 1100.

[0141] In a further example, the method of depositing the silicon material containing a doping element on the semiconductor substrate 100 is chemical vapor deposition, such as plasma-enhanced chemical vapor deposition. Among them, during the deposition of the silicon material containing a doping element, the temperature in the deposition chamber can be controlled to be 350 °C to 450 °C.

[0142] In a further example, when depositing the silicon material containing a doping element, a silicon source gas and a doping source gas are introduced into the deposition chamber. The silicon source gas can be selected from silicon hydrides, such as silane (SiH4). The doping source gas can be selected according to the required doping type. For example, when the doping type of the first doping layer 110 is N-type, a phosphorus-containing gas can be used as the doping source gas. Another example is that when the doping type of the first doping layer 110 is P-type, a boron-containing gas can be used as the doping source gas.

[0143] In a further example, the doping source gas contains a phosphorus-containing gas, such as phosphine (PH3). The doping source gas may also contain other auxiliary gases, such as one or more of phosphorus trifluoride (PF3) and trimethylgallium. The doping concentration in the doped polysilicon formed after the annealing treatment is 1×10 20 cm -3 ~8×10 20 cm -3 . Optionally, the doping concentration in the doped polysilicon is 2×10 20 cm -3 ~5×10 20 cm -3 . Further, the sheet resistance of the doped polysilicon is 30Ω / sq~50Ω / sq.

[0144] In a further example, the doping source gas contains a boron-containing gas, such as one or more of diborane (B2H6) and trimethylboron (B(CH3)3). The doping concentration in the doped polysilicon formed after the annealing treatment is 1×10 19 cm -3 ~8×10 19 cm -3 . Optionally, the doping concentration in the doped polysilicon is 3×10 19 cm -3 ~6×10 19 cm -3 . Further, the sheet resistance of the doped polysilicon is 120Ω / sq~150Ω / sq.

[0145] In a further example, the insulating precursor layer 1400 is deposited by chemical vapor deposition, such as plasma-enhanced chemical vapor deposition. Optionally, the material of the insulating precursor layer 1400 may be selected from insulating compounds of silicon, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0146] In this embodiment, the doping type of the first doping precursor layer 1100 is the same as that of the substrate, which is N-type.

[0147] Referring to Figure 4 as shown, it can be understood that during the above deposition process, the tunneling precursor layer 1110, the first doping precursor layer 1100, and the insulating precursor layer 1400 cover the entire backlight surface of the semiconductor substrate 100.

[0148] Figure 5 For Figure 4 is a schematic structural diagram of forming the tunneling dielectric layer 111 and the first doping layer 110 on the basis of the structure shown. Combining Figure 1 , Figure 4 and Figure 5As can be understood, the pre-tunneling layer 1110 and the first doped precursor layer 1100 located on the second region 102 are etched away, and the remaining portions are located on the first region 101 and serve as the tunneling dielectric layer 111 and the first doped layer 110, respectively. Also, a portion of the insulating precursor layer 1400 located on the second region 102 is removed, and the portion of the insulating precursor layer 1400 located on the first region 101 is retained.

[0149] As an example of this embodiment, the steps of etching away the pre-tunneling layer 1110, the first doped precursor layer 1100, and the insulating precursor layer 1400 include: sequentially performing a laser ablation process and a texturing process on the second region 102 to remove the pre-tunneling layer 1110, the first doped precursor layer 1100, and the insulating precursor layer 1400 on the second region 102. It can be understood that the laser ablation is used to remove the insulating precursor layer 1400 so that the exposed first doped precursor layer 1100 and pre-tunneling layer 1110 are etched away during the texturing process. Further, during the texturing process, the light-receiving surface of the semiconductor substrate 100 and the surface of the second region 102 can be textured simultaneously so that the light-receiving surface and the surface of the second region 102 can both form a textured surface structure. In addition, during the texturing process, the film layer plated around on the light-receiving surface of the semiconductor substrate 100 will also be removed.

[0150] As a further example of this embodiment, during the laser ablation process, picosecond laser or femtosecond laser can be used for ablation to reduce the damage to the film layers around the second region 102. Further, the laser power used can be 40W - 60W, and the spot size of the laser is 30μm - 120μm. Optionally, the spot size of the laser is 60μm - 80μm.

[0151] As an example of this embodiment, during the texturing process, the texturing agent includes an alkali and a texturing additive. The alkali can include sodium hydroxide, and the concentration of sodium hydroxide in the texturing agent is 0.5% - 1.2%. Further, the texturing temperature can be 75°C - 85°C. In this example, the reflectivity of the formed textured surface structure for visible light < 12%.

[0152] In this embodiment, since the texturing agent will etch away the semiconductor substrate 100 on the second region 102, the surface of the first region 101 is more prominent than the surface of the second region 102, that is, there is a height difference between the surface of the first region 101 and the surface of the second region 102. As an example of this embodiment, after the texturing process, the height difference between the surface of the first region 101 and the surface of the second region 102 is 1μm - 8μm. Optionally, the height difference between the surface of the first region 101 and the surface of the second region 102 is 2μm - 5μm.

[0153] As an example of this embodiment, when the doping type of the first doping layer 110 is N-type, the width of the first region 101 can be 400 μm to 500 μm, and the width of the second region 102 can be 550 μm to 700 μm. When the doping type of the first doping layer 110 is P-type, the width of the first region 101 can be 550 μm to 700 μm, and the width of the second region 102 can be 400 μm to 500 μm.

[0154] It can be understood that through the above process, the preparation of the tunneling dielectric layer 111 and the first doping layer 110 in step S2 can be completed.

[0155] Step S3: Oxidize the sidewalls of the tunneling dielectric layer 111 and the first doping layer 110 close to the second region 102 to form an oxidation isolation layer 130.

[0156] As an example of this embodiment, before forming the oxidation isolation layer 130, it further includes the step of forming a light-receiving surface functional layer on the light-receiving surface of the semiconductor substrate 100. Figure 6 For Figure 5 The structural schematic diagram of forming a light-receiving surface functional layer based on the shown structure. Refer to Figure 6 As shown, the light-receiving surface functional layer is disposed on the light-receiving surface of the semiconductor substrate 100.

[0157] As an example of this embodiment, the light-receiving surface functional layer includes one or more of a passivation film 151 and an antireflection film 152. Further, the step of forming the light-receiving surface functional layer includes: sequentially depositing the passivation film 151 and the antireflection film 152 on the light-receiving surface of the semiconductor substrate 100.

[0158] As a further example of this embodiment, the material of the passivation film 151 includes one or more of silicon oxide and aluminum oxide. Among them, when the material of the passivation film 151 includes silicon oxide, the passivation film 151 can be prepared by plasma-enhanced chemical vapor deposition, and the deposition temperature can be 450 °C to 550 °C. When the material of the passivation film 151 includes aluminum oxide, the passivation film 151 can be prepared by atomic layer deposition, and the deposition temperature can be 250 °C to 300 °C.

[0159] As a further example of this embodiment, the thickness of the passivation film 151 is 3 nm to 8 nm.

[0160] As a further example of this embodiment, the material of the antireflection film 152 includes one or more of silicon nitride and silicon oxynitride. Further, the material of the antireflection film 152 can also include silicon oxide. For example, a stacked structure composed of one or more of a silicon nitride thin film, a silicon oxynitride thin film, and a silicon oxide thin film can be used as the antireflection film 152.

[0161] As a further example of this embodiment, the antireflection film 152 can be formed by plasma enhanced chemical vapor deposition, and the deposition temperature can be 450°C to 550°C. The thickness of the antireflection film 152 is 70 nm to 110 nm. The refractive index of the entire antireflection film 152 can be 2.0 to 2.1.

[0162] As an example of this embodiment, after the light-receiving surface functional layer is formed, the film layer coated on the backlight surface can also be removed by cleaning. For example, a mixed solution of hydrofluoric acid and hydrochloric acid can be used to remove the film layer coated on the backlight surface. During this process, the insulating precursor layer 1400 can play a certain protective role for the first doped layer 110, and at the same time, the insulating precursor layer 1400 will also be thinned. The process time can be controlled to retain at least part of the insulating precursor layer 1400.

[0163] It can be understood that after the light-receiving surface functional layer is formed, the oxidation isolation layer 130 can be prepared. Figure 7 For Figure 6 FIG. is a schematic structural diagram of the oxidation isolation layer 130 formed on the basis of the shown structure.

[0164] As an example of this embodiment, the steps of oxidizing the sidewalls of the tunneling dielectric layer 111 and the first doped layer 110 close to the second region 102 include: placing the semiconductor substrate 100 in an environment containing an oxidizing gas, and irradiating the sidewalls of the tunneling dielectric layer 111 and the first doped layer 110 close to the second region 102 with a laser. Among them, the semiconductor material irradiated by the laser will be instantaneously heated to a relatively high temperature, which enables the semiconductor material to react rapidly with the oxidizing gas to form the oxidation isolation layer 130.

[0165] As an example of this embodiment, the environment of the oxidizing gas can be an oxygen atmosphere or an air atmosphere.

[0166] As an example of this embodiment, during the process of laser irradiation, the laser is inclined towards the sidewalls of the tunneling dielectric layer 111 and the first doped layer 110 close to the second region 102, and the inclination angle of the laser with respect to the backlight surface is 30° to 60°. The inclined laser can fully oxidize the sidewalls of the first doped layer 110 while minimizing the damage to the first doped layer 110.

[0167] It can be understood that during the process of laser irradiation, the surface of part of the second region 102 will also be irradiated to form the oxidation isolation layer 130. As an example of this embodiment, during the process of laser irradiation, the power of the laser is 5 W to 15 W, and the spot size of the laser is 5 μm to 20 μm. This laser can ensure that the oxidation isolation layer 130 has a moderate thickness and reduce the damage to the semiconductor substrate 100. Optionally, the spot size of the laser is 5 μm to 10 μm.

[0168] Reference Figure 7 As shown in the figure, as an example of this embodiment, the formed oxidation isolation layer 130 includes a sidewall isolation portion 131 and a bottom wall isolation portion 132 that are integrally structured. Among them, the sidewall isolation portion 131 contacts the sidewall of the semiconductor substrate 100 in the first region 101 close to the second region 102, and the bottom wall isolation portion 132 contacts the semiconductor substrate 100 in the second region 102.

[0169] As an example of this embodiment, the thickness of the oxidation isolation layer 130 is 1 nm to 10 nm. Optionally, the thickness of the oxidation isolation layer 130 is 2 nm to 5 nm. The oxidation isolation layer 130 with this thickness has less influence on the region occupied by the doping layer, and can also cooperate with the intrinsic passivation layer 121 to play a better role in isolating carriers.

[0170] Step S4: Form an intrinsic passivation layer 121 and a second doping layer 120 that are stacked in sequence on the second region 102.

[0171] As an example of this embodiment, the step of forming an intrinsic passivation layer 121 and a second doping layer 120 that are stacked in sequence on the second region 102 includes: depositing an intrinsic precursor layer 1210 and a second doping precursor layer 1200 in sequence on the backlight surface, and etching and removing the intrinsic precursor layer 1210 and the second doping precursor layer 1200 outside the second region 102 and the overlapping sub-region 1011, so that the remaining intrinsic precursor layer 1210 and the second doping precursor layer 1200 serve as the intrinsic passivation layer 121 and the second doping layer 120 respectively.

[0172] Figure 8 For forming Figure 7 The structural schematic diagram of forming the intrinsic precursor layer 1210 and the second doping precursor layer 1200 based on the shown structure. Refer to Figure 8 As shown in the figure, the intrinsic precursor layer 1210 and the second doping precursor layer 1200 are stacked in sequence on the backlight surface of the semiconductor substrate 100, and the intrinsic precursor layer 1210 and the second doping precursor layer 1200 cover the surface of the second region 102 and extend to cover the surface of the first region 101.

[0173] As an example of this embodiment, the material of the intrinsic precursor layer 1210 includes an intrinsic amorphous silicon thin film. The method of forming the intrinsic precursor layer 1210 is chemical vapor deposition, such as plasma enhanced chemical vapor deposition or hot wire chemical vapor deposition (HWCVD). The temperature during the deposition process is 170 °C to 230 °C.

[0174] As an example of this embodiment, the thickness of the intrinsic precursor layer 1210 can be 5 nm to 15 nm.

[0175] As an example of this embodiment, the material of the second doped precursor layer 1200 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The second doped precursor layer 1200 is formed by chemical vapor deposition, such as plasma enhanced chemical vapor deposition or hot wire chemical vapor deposition. The temperature during the deposition process is 170°C to 250°C.

[0176] As an example of this embodiment, the thickness of the second doped precursor layer 1200 can be 10 nm to 30 nm.

[0177] It can be understood that the doping type of the second doped precursor layer 1200 is opposite to that of the first doped layer 110.

[0178] Figure 9 For Figure 8 is a schematic structural diagram of forming the second doped layer 120 and the intrinsic passivation layer 121 on the basis of the shown structure. Referring to Figure 1 , Figure 8 and Figure 9 shown, the first region 101 includes an overlapping sub-region 1011 adjacent to the second region 102, and the second doped precursor layer 1200 and the intrinsic precursor layer 1210 located on the second region 102 and the overlapping sub-region 1011 are retained as the second doped layer 120 and the intrinsic passivation layer 121 respectively.

[0179] As an example of this embodiment, the steps of etching away the second doped precursor layer 1200 and the intrinsic precursor layer 1210 include: performing a laser ablation treatment on the first region 101 outside the overlapping sub-region 1011 to remove the second doped precursor layer 1200 and the intrinsic precursor layer 1210.

[0180] As a further example of this embodiment, during the laser ablation treatment, picosecond laser or femtosecond laser can be used for ablation treatment to reduce the damage to the film layer around the overlapping sub-region 1011. Further, the laser power used can be 15 W to 25 W, and the spot size of the laser is 30 μm to 120 μm. Optionally, the spot size of the laser is 60 μm to 100 μm.

[0181] Further, referring to Figure 8 and Figure 9 shown, after etching the second doped precursor layer 1200 and the intrinsic precursor layer 1210, the insulating precursor layer 1400 outside the overlapping sub-region 1011 is also removed, and only the insulating precursor layer 1400 located on the overlapping sub-region 1011 is retained as the insulating barrier layer 140. The insulating barrier layer 140 is disposed on the side of the first doped layer 110 away from the semiconductor substrate 100, and the second doped layer 120 and the intrinsic passivation layer 121 located on the overlapping sub-region 1011 are disposed on the side of the insulating barrier layer 140 away from the semiconductor substrate 100.

[0182] As an example of this embodiment, the step of removing the insulating precursor layer 1400 except for the overlapping sub-region 1011 includes: cleaning and removing the insulating precursor layer 1400 by using an acidic etchant containing hydrofluoric acid and hydrochloric acid. Optionally, in the acidic etchant, the mass concentration of hydrofluoric acid is 5% - 8%, the mass concentration of hydrochloric acid is 2.5% - 4%, and the process time for cleaning and removing the insulating precursor layer 1400 is 30s - 60s.

[0183] As an example of this embodiment, the width of the overlapping sub-region 1011 is 60μm - 220μm. Optionally, the width of the overlapping sub-region 1011 can be 100μm - 180μm.

[0184] It can be understood that through the above steps, the second doping layer 120, the intrinsic passivation layer 121, and the insulating barrier layer 140 can be formed.

[0185] Further, after forming the first doping layer 110 and the second doping layer 120, the following steps are further included: forming a transparent conductive precursor layer on the backlight surface on the side of the first doping layer 110 and the second doping layer 120 away from the semiconductor substrate 100. After forming the transparent conductive precursor layer, the step of depositing an insulating antireflection layer 170 on the backlight surface is further included, and the insulating antireflection layer 170 is disposed on the side of the transparent conductive precursor layer away from the semiconductor substrate 100.

[0186] Figure 10 For Figure 9 FIG. is a schematic structural diagram of forming a transparent conductive precursor layer and an insulating antireflection layer 170 on the basis of the shown structure. Referring to Figure 10 As shown, the transparent conductive precursor layer can be formed on the first region 101 and the second region 102, and the transparent conductive precursor layer entirely covers the surfaces of the first doping layer 110 and the second doping layer 120. The insulating antireflection layer 170 is disposed on the side of the transparent conductive precursor layer away from the semiconductor substrate 100.

[0187] As an example of this embodiment, the material of the transparent conductive precursor layer includes one or more of indium tin oxide (ITO), indium tungsten oxide (IWO), and aluminum-doped zinc oxide (AZO). The method of depositing the transparent conductive precursor layer can be physical vapor deposition or reactive plasma deposition. The temperature during the deposition of the transparent conductive precursor layer is 150°C - 200°C.

[0188] As an example of this embodiment, the thickness of the transparent conductive precursor layer is 70nm - 110nm.

[0189] As an example of this embodiment, the material of the insulating antireflection layer 170 includes silicon oxide. The method of depositing the insulating antireflection layer 170 can be physical vapor deposition. The temperature during the deposition of the insulating antireflection layer 170 is 150°C to 200°C.

[0190] As an example of this embodiment, the thickness of the insulating antireflection layer 170 is 80 nm to 200 nm.

[0191] After forming the insulating antireflection layer 170, the following steps are further included: forming an isolation groove 103 on the overlapping sub-region 1011 that penetrates through the insulating antireflection layer 170, the transparent conductive precursor layer, the second doping layer 120, and the intrinsic passivation layer 121. Figure 11 For Figure 10 The structural schematic diagram of forming the isolation groove 103 based on the shown structure. Combining Figure 10 and Figure 11 As shown, the isolation groove 103 isolates a first transparent conductive layer 160 and a second transparent conductive layer 160 in the transparent conductive precursor layer. The first transparent conductive layer 160 is disposed on the side of the first doping layer 110 away from the semiconductor substrate 100 and is electrically connected to the first doping layer 110. The second transparent conductive layer 160 is disposed on the side of the second doping layer 120 away from the semiconductor substrate 100 and is electrically connected to the second doping layer 120. The isolation groove 103 is used to avoid short-circuiting between the first doping layer 110 and the second doping layer 120.

[0192] As a further example of this embodiment, the step of forming the isolation groove 103 includes: removing part of the materials of the insulating antireflection layer 170, the transparent conductive precursor layer, the second doping layer 120, and the intrinsic passivation layer 121 on the overlapping sub-region 1011 by laser etching to form the isolation groove 103.

[0193] As a further example of this embodiment, during the formation of the isolation groove 103, picosecond laser or femtosecond laser can be used for ablation treatment to reduce the damage to the film layers around the isolation groove 103. Further, the laser power used can be 15 W to 25 W. The width of the formed isolation groove 103 is smaller than the width of the overlapping sub-region 1011. For example, the width of the isolation groove 103 is 80 μm to 160 μm.

[0194] Referring to Figure 11 As shown, as an example of this embodiment, during the formation of the isolation groove 103, the following is further included: forming a first conductive contact groove 104 exposing the first transparent conductive layer 160 and a second conductive contact groove 105 exposing the second transparent conductive layer 160 on the insulating antireflection layer 170 by laser etching.

[0195] As a further example of this embodiment, in the step of forming the first conductive contact groove 104 and the second conductive contact groove 105, the laser power used can be 15W to 25W. The widths of the formed first conductive contact groove 104 and second conductive contact groove 105 are 5μm to 30μm.

[0196] As an example of this embodiment, after forming the first conductive contact groove 104 and the second conductive contact groove 105, it further includes the step of forming a first electrode 180 and a second electrode 190. The first electrode 180 passes through the first conductive contact groove 104 to achieve electrical contact with the first transparent conductive layer 160, and the second electrode 190 passes through the second conductive contact groove 105 to achieve electrical contact with the second transparent conductive layer 160. After forming the first electrode 180 and the second electrode 190, the structure as shown in Figure 1 can be obtained.

[0197] Further, the manner of forming the first electrode 180 and the second electrode 190 can be screen printing or laser transfer printing. For example, the steps of forming the first electrode 180 and the second electrode 190 include: screen printing conductive paste in the first conductive contact groove 104 and the second conductive contact groove 105, and then performing sintering and curing treatment to form the first electrode 180 and the second electrode 190 respectively. During the sintering and curing treatment, the curing temperature is 180°C to 220°C, and the curing time is 20min to 40min.

[0198] It can be understood that through the above steps, the preparation method of this solar cell can be completed and the solar cell in the present disclosure can be prepared.

[0199] The following further describes the present application in detail with several specific embodiments, and these embodiments should not be construed as limiting the scope claimed in the present application.

[0200] Unless otherwise defined, all professional terms used hereinafter have the same meaning as commonly understood by those skilled in the art. The professional terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the protection scope of the present invention.

[0201] The following lists some specific embodiments. It should be noted that the embodiments described below are exemplary and are only used to explain the present application and should not be construed as limiting the present application. For those without specific techniques or conditions noted in the embodiments, they shall be carried out according to the techniques or conditions described in the literature in the art or according to the product specifications. For reagents or instruments without indicating the manufacturer, they are all conventional products that can be obtained through commercial purchase.

[0202] Example 1

[0203] An N-type silicon wafer is provided as a semiconductor substrate and polished with a sodium hydroxide solution having a mass concentration of 1.5%.

[0204] On the backlight surface of the N-type silicon wafer, a silicon oxide film with a thickness of 2 nm, a phosphorus-doped polysilicon film with a thickness of 300 nm, and a silicon nitride film with a thickness of 100 nm are sequentially deposited.

[0205] The second region on the backlight surface of the N-type silicon wafer is subjected to laser ablation treatment, and then both the light-receiving surface and the backlight surface of the N-type silicon wafer are textured to remove the silicon nitride film, the phosphorus-doped polysilicon film, and the silicon oxide film located on the second region, and retain the silicon nitride film, the phosphorus-doped polysilicon film, and the silicon oxide film located on the first region. The retained phosphorus-doped polysilicon film and silicon oxide film serve as the first doping layer and the tunneling dielectric layer, respectively. The width of the first region is designed to be 450 μm, and the width of the second region is designed to be 600 μm.

[0206] On the light-receiving surface of the N-type silicon wafer, an aluminum oxide film with a thickness of 5 nm and a silicon nitride film with a thickness of 100 nm are sequentially deposited as a passivation film and an antireflection film, respectively, and then the circumferential coating layer on the backlight surface is removed by pickling. The thickness of the silicon nitride film after pickling is 50 nm.

[0207] In an air atmosphere, a laser with a power of 10 W and a spot size of 8 μm is used to irradiate the sidewall of the first region adjacent to the second region, so that the first doping layer and the silicon substrate adjacent to the sidewall of the second region are oxidized, and at the same time, a part of the second region adjacent to the first region is oxidized to form a silicon oxide with a thickness of 3 nm as an oxidation barrier layer.

[0208] On the first region, an overlapping sub-region adjacent to the second region with a width of 120 μm is designed. On the backlight surface of the N-type silicon wafer, an undoped amorphous silicon film with a thickness of 10 nm and a boron-doped amorphous silicon film with a thickness of 20 nm are sequentially deposited, and then the first region except the overlapping sub-region is subjected to laser ablation treatment to remove the boron-doped amorphous silicon film and the undoped amorphous silicon film outside the overlapping sub-region and the second region, and the retained boron-doped amorphous silicon film and undoped amorphous silicon film serve as the second doping layer and the undoped passivation layer, respectively. Then, a mixed solution of hydrofluoric acid and hydrochloric acid is used to remove the silicon nitride film outside the overlapping sub-region, and only the silicon nitride film located on the overlapping sub-region is retained and used as an insulating barrier layer.

[0209] On the backlight surface of the N-type silicon wafer, an indium tin oxide film with a thickness of 100 nm and a silicon oxide film with a thickness of 150 nm are sequentially deposited, and then a laser ablation method is used to form an isolation groove on the overlapping sub-region that penetrates the silicon oxide film, the indium tin oxide film, the second doping layer, and the undoped passivation layer. The indium tin oxide film is separated into a first transparent conductive layer and a second transparent conductive layer by the isolation groove, and the silicon oxide film serves as an insulating antireflection layer.

[0210] The insulating antireflection layer in the first region and the second region is grooved by means of laser ablation, and then conductive silver paste is screen-printed on the grooved region and sintered and cured to form the first electrode and the second electrode respectively.

[0211] Example 2

[0212] The difference between Example 2 and Example 1 is only that: during the formation of the oxidation barrier layer, the power of the laser is 10 W and the spot size is 30 μm.

[0213] Example 3

[0214] The difference between Example 3 and Example 1 is only that: during the formation of the oxidation barrier layer, the power of the laser is 10 W and the spot size is 3 μm.

[0215] Example 4

[0216] The difference between Example 4 and Example 1 is only that: during the formation of the oxidation barrier layer, the power of the laser is 16 W and the spot size is 8 μm.

[0217] Example 5

[0218] The difference between Example 5 and Example 1 is only that: during the formation of the oxidation barrier layer, the power of the laser is 4 W and the spot size is 8 μm.

[0219] It should be noted that this application is not limited to the above embodiments. The above embodiments are only examples, and embodiments with the same structure and the same function and effect as the technical idea within the scope of the technical solution of this application are all included in the technical scope of this application. In addition, within the scope of not departing from the main idea of this application, various modifications that can be thought of by those skilled in the art to the embodiments and other ways constructed by combining some constituent elements of the embodiments are also included in the scope of this application.

Claims

1. A solar cell, characterized in that, Comprising: A semiconductor substrate having a light-receiving surface and a backlight surface disposed opposite to each other, and a first region and a second region on the backlight surface of the semiconductor substrate; A tunneling dielectric layer and a first doped layer, which are sequentially stacked on the first region; An intrinsic passivation layer and a second doped layer, which are sequentially stacked on the second region, the material of the intrinsic passivation layer includes intrinsic silicon, and the doping type of the second doped layer is opposite to the doping type of the first doped layer; and, An oxidation isolation layer disposed between the first doped layer and the second doped layer and insulatingly spacing the first doped layer and the second doped layer.

2. The solar cell according to claim 1, characterized in that, One side of the oxidation isolation layer is in contact with the side walls of the tunneling dielectric layer and the first doped layer, the other side of the oxidation isolation layer is in contact with the intrinsic passivation layer, and the intrinsic passivation layer is disposed between the second doped layer and the oxidation isolation layer.

3. The solar cell according to claim 2, wherein On the backlight surface, the surface of the first region protrudes from the surface of the second region, the oxidation isolation layer includes a side wall isolation portion and a bottom wall isolation portion having an integral structure, the side wall isolation portion contacts the side wall of the semiconductor substrate in the first region close to the second region, and the bottom wall isolation portion contacts the semiconductor substrate in the second region.

4. The solar cell according to claim 3, characterized in that, The width of the oxidation isolation layer on the backlight surface is 5 μm to 20 μm; and / or, The thickness of the oxidation isolation layer is 1 nm to 10 nm.

5. The solar cell according to any one of claims 1 to 4, characterized in that, The first region includes an overlapping sub-region adjacent to the second region, and the solar cell further includes an insulating barrier layer disposed in the overlapping sub-region and stacked on the side of the first doped layer away from the semiconductor substrate; The intrinsic passivation layer and the second doped layer further extend onto the overlapping sub-region and are sequentially stacked on the side of the insulating barrier layer away from the semiconductor substrate.

6. The solar cell according to claim 5, characterized in that, The solar cell further includes an insulating antireflection layer disposed on the sides of the first doped layer and the second doped layer away from the semiconductor substrate.

7. The solar cell according to claim 6, wherein The solar cell further includes a first transparent conductive layer and a second transparent conductive layer, the first transparent conductive layer is disposed on the side of the first doped layer away from the semiconductor substrate and electrically connected to the first doped layer, the second transparent conductive layer is disposed on the side of the second doped layer away from the semiconductor substrate and electrically connected to the second doped layer, and an isolation groove is disposed between the first transparent conductive layer and the second transparent conductive layer on the overlapping sub-region.

8. The solar cell according to any one of claims 1 to 4 and 6 to 7, characterized in that, The doping type of the first doped layer is N-type, and the doping type of the second doped layer is P-type.

9. The solar cell according to any one of claims 1 to 4 and 6 to 7, characterized in that On the backlight surface, the surface of the second region has a matte structure; and / or, The light-receiving surface has a matte structure.

10. The solar cell according to any one of claims 1 to 4 and 6 to 7, characterized in that, The solar cell further includes a light-receiving surface functional layer disposed on the light-receiving surface of the semiconductor substrate, and the light-receiving surface functional layer includes one or more of a passivation film and an antireflection film; and / or, The solar cell further includes a first electrode and a second electrode disposed on the backlight surface of the semiconductor substrate, the first electrode being electrically connected to the first doped layer, and the second electrode being electrically connected to the second doped layer.

11. A method for preparing a solar cell, characterized in that, The method includes the following steps: Providing a semiconductor substrate having opposite light-receiving and backlight surfaces, and a first region and a second region on the backlight surface; Forming a tunneling dielectric layer and a first doped layer stacked in sequence on the first region; Oxidizing the sidewalls of the tunneling dielectric layer and the first doped layer close to the second region to form an oxidation isolation layer; Forming an intrinsic passivation layer and a second doped layer stacked in sequence on the second region, the material of the intrinsic passivation layer including intrinsic silicon, and the doping type of the second doped layer being opposite to that of the first doped layer.

12. The manufacturing method of the solar cell according to claim 11, characterized in that, The step of oxidizing the sidewalls of the tunneling dielectric layer and the first doped layer close to the second region includes: Placing the semiconductor substrate in an environment containing an oxidizing gas, and irradiating the sidewalls of the tunneling dielectric layer and the first doped layer close to the second region with a laser.

13. The method for preparing a solar cell according to claim 12, wherein, During the laser irradiation, the laser is inclined towards the sidewalls of the tunneling dielectric layer and the first doped layer close to the second region, and the angle of inclination of the laser with respect to the backlight surface is 30° - 60°.

14. The manufacturing method of the solar cell according to claim 12, characterized in that, The power of the laser is 5W - 15W, and the spot size of the laser is 5μm - 20μm.

15. The manufacturing method of the solar cell according to any one of claims 11 to 14, characterized in that, The first region includes an overlapping sub-region adjacent to the second region; The step of forming a tunneling dielectric layer and a first doped layer stacked in sequence on the first region includes: Depositing a tunneling precursor layer and a first doping precursor layer in sequence on the backlight surface, forming an insulating precursor layer on the first doping precursor layer, and etching away the tunneling precursor layer and the first doping precursor layer outside the first region to use the remaining tunneling precursor layer and first doping precursor layer as the tunneling dielectric layer and the first doped layer respectively; After forming the first doped layer, it further includes: etching away the insulating precursor layer outside the overlapping sub-region to use the remaining insulating precursor layer as an insulating barrier layer.

16. The manufacturing method of the solar cell according to claim 15, characterized in that, The step of forming an intrinsic passivation layer and a second doped layer stacked in sequence on the second region includes: Depositing an intrinsic precursor layer and a second doping precursor layer in sequence on the backlight surface, and etching away the intrinsic precursor layer and the second doping precursor layer outside the second region and the overlapping sub-region to use the remaining intrinsic precursor layer and second doping precursor layer as the intrinsic passivation layer and the second doped layer respectively.

17. The manufacturing method of the solar cell according to claim 16, characterized in that, After forming the first doped layer and the second doped layer, it further includes the step of depositing an insulating antireflection layer on the backlight surface, and the insulating antireflection layer is disposed on the side of the first doped layer and the second doped layer away from the semiconductor substrate.

18. The method for preparing a solar cell according to claim 17, wherein After forming the first doped layer and the second doped layer, it further includes the following steps: Forming a transparent conductive precursor layer on the side of the first doped layer and the second doped layer away from the semiconductor substrate; and, An isolation groove penetrating through the insulating antireflection layer, the transparent conductive precursor layer, the second doping layer and the intrinsic passivation layer is formed on the overlapping sub-region.

19. The manufacturing method of a solar cell according to any one of claims 11 to 14 and 16 to 18, characterized in that, After forming the first doping layer and before forming the oxide isolation layer, the following steps are further included: Texturing the light-receiving surface; and / or Texturing the second region on the backlight surface.

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