Nanowire avalanche photodiode with gate regulation and control of barrier height of electron barrier layer
By introducing Class II superlattice materials and gate voltage regulation into nanowire avalanche photodiodes, the barrier height of the electron barrier layer is dynamically adjusted, which solves the problem of unreasonable design of the electron barrier layer thickness and material type, and improves the photodetection performance.
Patent Information
- Application Number
- CN202510374483.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2025-08-08
AI Technical Summary
In the prior art, the barrier height of the electron barrier layer is fixed and difficult to adjust, resulting in unreasonable design of the thickness and material type of the electron barrier layer, affecting the lattice quality and photoelectric detection performance of the electron barrier layer.
Nanowire avalanche photodiodes that use gate to regulate the barrier height of the electron barrier layer are used to introduce Class II superlattice materials and gate voltage regulation into the nanowire structure to achieve dynamic adjustment of the barrier height of the electron barrier layer, enhancing the binding effect on electrons.
It improves the separation effect of photogenerated carriers, enhances the transport capacity of holes, reduces the collection of electron currents, and improves the photoelectric detection performance of avalanche photodiodes.
Smart Images
Figure CN120456629A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a nanowire avalanche photodiode, in particular to a nanowire avalanche photodiode with a gate regulating the potential barrier height of an electron blocking layer. Background Art
[0002] In existing avalanche diode devices fabricated using InAs / GaSb type II superlattice materials, electron blocking layers are considered to enhance the separation of electrons and holes. This is done by raising the electron barrier height to reduce electron collection. However, despite research on the use of electron blocking layers, existing electron blocking layers rarely change significantly after the superlattice and electron blocking layer material are grown, with their barrier height remaining fixed.
[0003] Therefore, the existing electron blocking layer technology may have problems with unreasonable design of the electron blocking layer thickness and material type, which will cause the electron blocking layer barrier to be too low or the electron blocking layer to have a serious lattice mismatch with the superlattice material. On the one hand, if the electron blocking layer barrier is too low, it will make it easier for electrons to cross the barrier, increase the collection of electrons, weaken the superlattice's binding effect on electrons, and reduce the collision probability of holes, which will ultimately lead to a decrease in the device's photoelectric detection performance. On the other hand, the electron blocking layer has a serious lattice mismatch with the superlattice material, which will directly affect the lattice quality of the electron blocking layer, resulting in high and low electron potential barriers at different lattices, and electrons will more easily tunnel through the electron blocking layer from the lattice with a low electron potential barrier, which will also weaken the superlattice's binding effect on electrons. In addition, precisely because of the need to consider the lattice mismatch problem, the types of electron blocking layer materials in the existing technology have strict requirements on both high electron potential barriers and small lattice mismatch. Summary of the Invention
[0004] To solve the above problems, the present application provides a nanowire avalanche photodiode with a gate-controlled electron blocking layer barrier height.
[0005] The present invention provides the following technical solution: a nanowire avalanche photodiode with a gate-controlled electron blocking layer barrier height, comprising a back electrode and an ohmic contact layer, arranged sequentially from bottom to top, and a first portion disposed on the ohmic contact layer, with a second portion disposed overlying the first portion to form a nanowire structure; the first portion is a lattice matching layer, the second portion is a light absorption layer, and a first superlattice material layer is disposed between the first and second portions; an electron blocking layer is disposed overlying the second portion, with a second superlattice material layer disposed overlying the electron blocking layer; the electron blocking layer is blocked between the second portion and the second superlattice material layer; the electron blocking layer is led out through a first top electrode, and the second superlattice material layer is led out through the second top electrode, with a first insulating layer disposed between the first top electrode and the second superlattice material layer; the first and second superlattice material layers are both made of Type II superlattice material; the first superlattice material layer, the second portion, the electron blocking layer, and the second superlattice material layer are all not in contact with the ohmic contact layer. Type II superlattice material has a stronger electron confinement effect.
[0006] Furthermore, the back electrode is heavily doped with P-type; the ohmic contact layer is made of Si; the first part is made of heavily doped P-type InAs; the first superlattice material layer is made of lightly doped P-type GaSb / InAs superlattice material; the second part is composed of 7 single-atomic layers of InAs and 7 single-atomic layers of GaSb; the electron blocking layer is made of GaSb; the second superlattice material layer is made of heavily doped N-type GaSb / InAs superlattice material; the back electrode is a P-type ohmic contact electrode; the first top electrode is a gate electrode; and the second top electrode is an N-type ohmic contact electrode.
[0007] Furthermore, the back electrode is heavily N-type doped; the ohmic contact layer is Si; the first part is heavily N-type doped InAs; the first superlattice material layer is N-type lightly doped GaSb / InAs superlattice material; the second part is composed of 7 monolayers (ML) of InAs and 7 atomic layers of GaSb; the electron blocking layer is GaSb; the second superlattice material layer is P-type heavily doped GaSb / InAs superlattice material; the back electrode is an N-type ohmic contact electrode; the first top electrode is a gate electrode; and the second top electrode is a P-type ohmic contact electrode.
[0008] Furthermore, the back electrode, the first top electrode, and the second top electrode use Ti, Pt, or Au as metal electrodes.
[0009] Furthermore, a second insulating layer is provided between the first superlattice material layer, the second portion, the electron blocking layer, the second superlattice material layer and the ohmic contact layer.
[0010] The beneficial effects of the present invention are as follows: (1) Utilize the binding effect of type II superlattice materials on electrons to enhance the transport capacity of holes and improve the separation effect on photogenerated carriers.
[0011] (2) An electrode is introduced to the electron blocking layer to achieve the purpose of regulating the potential barrier height of the electron blocking layer by the gate voltage, thereby reducing the collection of electron current. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 It is a structural schematic diagram of the present invention; Figure 2 Schematic diagram of carrier migration in Example 1 of the present invention; Figure 3 Schematic diagram of the energy band structure of the GaSb / InAs superlattice material of the present invention; Figure 4 Schematic diagram of the energy band structure of the superlattice material of the present invention working under reverse bias voltage; Figure 5 Schematic diagram of carrier migration in Example 2 of the present invention; Among them, the back electrode 1, the ohmic contact layer 2, the first part 3, the first superlattice material layer 4, the second part 5, the electron blocking layer 6, the second superlattice material layer 7, the first top electrode 8, the first insulating layer 9, the second top electrode 10, the second insulating layer 11, e is an electron, and H is a hole. DETAILED DESCRIPTION
[0013] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the specific implementation methods, structures, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.
[0014] The present application applies voltage to the electron blocking layer through the first top electrode, thereby changing the energy level of the electron blocking layer, and then changing the barrier height of the electron blocking layer, so that the barrier height of the electron blocking layer can be freely adjusted, meeting the use requirements of the InAs / GaSb type II superlattice material to be made into an avalanche photodiode to block electrons and reduce the collection of electron current.
[0015] The embodiments of the present invention are further described below with reference to a number of embodiments.
[0016] Example 1 like Figure 1A nanowire avalanche photodiode with a gate-controlled electron blocking layer barrier height includes a back electrode 1 and an ohmic contact layer 2 arranged in sequence from bottom to top, and a first part 3 arranged on the ohmic contact layer 2, the first part 3 is covered with a second part 5, and the two parts form a nanowire structure; the first part 3 is a lattice matching layer, the second part 5 is a light absorption layer, and a first superlattice material layer 4 is provided between the first part 3 and the second part 5; an electron blocking layer 6 is provided outside the second part 5, and a second superlattice material layer 7 is provided outside the electron blocking layer 6; the electron blocking layer 6 is blocked between the second part 5 and the second superlattice material layer 7; the electron blocking layer 6 is led out through a first top electrode 8, and the second superlattice material layer 7 is led out through a second top electrode 10, and a first insulating layer 9 is provided between the first top electrode 8 and the second superlattice material layer 7.
[0017] A second insulating layer 11 is provided between the first superlattice material layer 4 , the second portion 5 , the electron blocking layer 6 , the second superlattice material layer 7 and the ohmic contact layer.
[0018] The back electrode 1 is heavily doped with P-type; the ohmic contact layer 2 is made of Si; the first part 3 is made of heavily doped P-type InAs; the first superlattice material layer 4 is made of lightly doped P-type GaSb / InAs superlattice material; the second part 5 is composed of 7 monoatomic layers of InAs and 7 atomic layers of GaSb; the electron blocking layer 6 is made of GaSb; the second superlattice material layer 7 is made of heavily doped N-type GaSb / InAs superlattice material; the back electrode 1 is a P-type ohmic contact electrode; the first top electrode 8 is a gate electrode; and the second top electrode 10 is an N-type ohmic contact electrode.
[0019] The back electrode 1 , the first top electrode 8 , and the second top electrode 10 use Ti as metal electrodes, and in some embodiments, Pt or Au may also be used.
[0020] This embodiment is a PIN type, and the carrier migration path is as follows Figure 2 As shown, when the device is in operation, that is, in the reverse bias state, a negative voltage is applied to the back electrode 1, that is, to the P-type doped first superlattice material layer 4 (P region). A positive voltage is applied to the top electrode 10, that is, to the N-type doped second superlattice material layer 7 (N region). At this time, the direction of the applied electric field is the same as the direction of the built-in electric field within the device's PN junction. The majority carrier diffusion motion within the device is weaker than the minority carrier drift motion, with drift motion dominating. Consequently, minority carrier electrons in the P-type doped first superlattice material layer 4 (P region) drift from the P-type doped first superlattice material layer 4 to the N-type doped second superlattice material layer 7 (N region). Simultaneously, minority carrier holes in the N-type doped second superlattice material layer 7 (N region) drift from the N-type doped second superlattice material layer 7 to the P-type doped first superlattice material layer 4 (P region).
[0021] If a photon of suitable wavelength happens to enter the light-absorbing layer, namely the second portion 5, the electron-hole pairs in the second portion 5 absorb the photon energy and undergo transitions. The photogenerated electrons enter the bottom of the conduction band, and the photogenerated holes enter the top of the valence band. Under the influence of the reverse-biased external electric field, the photogenerated carriers move in the same direction as the minority carriers and are collected by the electrodes. Specifically, the photogenerated holes enter the P-type doped first superlattice material layer 4 (P region) and are collected by the back electrode 1. Meanwhile, the photogenerated electrons enter the N-type doped second superlattice material layer 7 (N region) and are collected by the top electrode 10.
[0022] like Figure 3 As shown in the energy band structure diagram of GaSb / InAs superlattice material, InAs is a potential well for electrons and GaSb is a potential well for holes. c Ratio ΔE v This makes it less likely that electrons will escape from the electron well of InAs by jumping out of the electron potential well than holes from the hole potential well of GaSb. Therefore, the GaSb / InAs type II superlattice material has a stronger electron confinement effect. Furthermore, in theory, avalanche diodes made from GaSb / InAs type II superlattice materials experience hole-type avalanche breakdown.
[0023] E c1 =GaSb conduction band bottom energy level; E v1 =GaSb valence band top energy level; E c2 = the bottom energy level of the conduction band of InAs; E v2 =InAs valence band top energy level; ΔE c = the energy level difference between the bottom of the conduction band of GaSb and the bottom of the conduction band of InAs, i.e., the conduction band step; ΔE v =The energy level difference between the top of the valence band of GaSb and the top of the valence band of InAs, that is, the valence band step.
[0024] like Figure 4 The energy band structure diagram of a superlattice material operating under reverse bias (see Figure 2) illustrates that under the influence of a reverse bias electric field, electrons in the P region and the light-absorbing region tend to drift into the N region. However, due to the high electron potential barrier of the electron blocking layer, the probability of electrons crossing the barrier and entering the N region is very small. Meanwhile, holes in the N region and the light-absorbing region drift to the P region under the influence of a reverse bias electric field without being hindered by the hole potential barrier. Therefore, thanks to the electron blocking layer, the hole current is much larger than the electron current.
[0025] Example 2 like Figure 1A nanowire avalanche photodiode with a gate-controlled electron blocking layer barrier height includes a back electrode 1 and an ohmic contact layer 2 arranged in sequence from bottom to top, and a first part 3 arranged on the ohmic contact layer 2, the first part 3 is covered with a second part 5, and the two parts form a nanowire structure; the first part 3 is a lattice matching layer, the second part 5 is a light absorption layer, and a first superlattice material layer 4 is provided between the first part 3 and the second part 5; an electron blocking layer 6 is provided outside the second part 5, and a second superlattice material layer 7 is provided outside the electron blocking layer 6; the electron blocking layer 6 is blocked between the second part 5 and the second superlattice material layer 7; the electron blocking layer 6 is led out through a first top electrode 8, and the second superlattice material layer 7 is led out through a second top electrode 10, and a first insulating layer 9 is provided between the first top electrode 8 and the second superlattice material layer 7.
[0026] A second insulating layer 11 is provided between the first superlattice material layer 4 , the second portion 5 , the electron blocking layer 6 , the second superlattice material layer 7 and the ohmic contact layer.
[0027] The back electrode is heavily N-type doped; the ohmic contact layer is Si; the first part is heavily N-type doped InAs; the first superlattice material layer is lightly N-type doped GaSb / InAs superlattice material; the second part consists of 7 monolayers (ML) of InAs and 7 atomic layers of GaSb; the electron blocking layer is GaSb; the second superlattice material layer is heavily P-type doped GaSb / InAs superlattice material; the back electrode is an N-type ohmic contact electrode; the first top electrode is a gate electrode; and the second top electrode is a P-type ohmic contact electrode.
[0028] The back electrode 1 , the first top electrode 8 , and the second top electrode 10 use Au as metal electrodes, and in some embodiments, Ti or Pt may also be used.
[0029] This embodiment is a NIP type, and the carrier migration path is as follows Figure 5 As shown, when the device is in operation, that is, in the reverse bias state, a positive voltage is applied to the back electrode 1, that is, a positive voltage is applied to the N-type doped first superlattice material layer 4 (N region). A negative voltage is applied to the top electrode 10, that is, a negative voltage is applied to the P-type doped second superlattice material layer 7 (P region). At this time, the direction of the applied electric field is the same as the direction of the built-in electric field of the device's PN junction. The majority carrier diffusion motion within the device is weaker than the minority carrier drift motion, and drift motion dominates. Therefore, minority carrier holes in the N-type doped first superlattice material layer 4 (N region) drift from the N-type doped first superlattice material layer 4 to the P-type doped second superlattice material layer 7 (P region). Simultaneously, minority carrier electrons in the P-type doped second superlattice material layer 7 (P region) drift from the P-type doped second superlattice material layer 7 to the N-type doped first superlattice material layer 4 (N region).
[0030] If a photon of suitable wavelength happens to enter the light-absorbing layer, namely the second portion 5, the electron-hole pairs in the second portion 5 absorb the photon energy and undergo transitions. The photogenerated electrons enter the bottom of the conduction band, and the photogenerated holes enter the top of the valence band. Under the influence of the reverse-biased external electric field, the photogenerated carriers move in the same direction as the minority carriers and are collected by the electrodes. Specifically, the photogenerated electrons enter the n-type doped first superlattice material layer 4 (n region) and are collected by the back electrode 1. Meanwhile, the photogenerated holes enter the p-type doped second superlattice material layer 7 (p region) and are collected by the top electrode 10.
[0031] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as above in terms of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can, without departing from the scope of the technical solution of the present invention, make some changes or modifications to equivalent embodiments using the technical contents disclosed above. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.
Claims
1. A nanowire avalanche photodiode with a gate-controlled electron blocking layer barrier height, characterized in that: The device comprises a back electrode and an ohmic contact layer arranged in sequence from bottom to top, and a first portion arranged on the ohmic contact layer, the first portion being covered with a second portion to form a nanowire structure; the first portion being a lattice matching layer, the second portion being a light absorption layer, a first superlattice material layer being provided between the first portion and the second portion; an electron blocking layer being provided outside the second portion, and a second superlattice material layer being provided outside the electron blocking layer; The electron blocking layer is blocked between the second portion and the second superlattice material layer; The electron blocking layer is led out through the first top electrode, the second superlattice material layer is led out through the second top electrode, and there is a first insulating layer between the first top electrode and the second superlattice material layer; the first superlattice material layer and the second superlattice material layer both use Type II superlattice material; the first superlattice material layer, the second part, the electron blocking layer, and the second superlattice material layer are not in contact with the ohmic contact layer.
2. The nanowire avalanche photodiode device with gate-controlled electron blocking layer barrier height according to claim 1, characterized in that: The back electrode is heavily P-type doped; the ohmic contact layer is Si; the first part is heavily P-type doped InAs; the first superlattice material layer is P-type lightly doped GaSb / InAs superlattice material; the second part is composed of 7 single-atomic layers of InAs and 7 single-atomic layers of GaSb; the electron blocking layer is GaSb; the second superlattice material layer is N-type heavily doped GaSb / InAs superlattice material; the first top electrode is the gate electrode; the second top electrode is the N-type ohmic contact electrode.
3. The nanowire avalanche photodiode device with gate-controlled electron blocking layer barrier height according to claim 1, characterized in that: The back electrode is heavily N-type doped; the ohmic contact layer is Si; the first part is heavily N-type doped InAs; the first superlattice material layer is N-type lightly doped GaSb / InAs superlattice material; the second part is composed of 7 single-atomic layers of InAs and 7 single-atomic layers of GaSb; the electron blocking layer is GaSb; the second superlattice material layer is heavily P-type doped GaSb / InAs superlattice material; the first top electrode is the gate electrode; the second top electrode is the P-type ohmic contact electrode.
4. The nanowire avalanche photodiode device with gate-controlled electron blocking layer barrier height according to claim 1, characterized in that: The back electrode, the first top electrode and the second top electrode use Ti, Pt or Au as metal electrodes.
5. The nanowire avalanche photodiode device with gate-controlled electron blocking layer barrier height according to claim 1, characterized in that: A second insulating layer is provided between the first superlattice material layer, the second portion, the electron blocking layer, the second superlattice material layer and the ohmic contact layer.