In-memory encryption method based on cross-point array ferroelectric capacitor array

Abstract

The invention discloses an in-memory encryption method based on a cross-point array ferroelectric capacitor array, and belongs to the field of data security and computing security. According to the invention, a cross-point array ferroelectric capacitor FeCAP array is respectively adopted as a key array and a complementary key array, and array-level XOR operation is executed between a plaintext and a key by the generated operation through a diagonal data coding mode and a coupling signal subtraction circuit, so that high-parallel XOR encryption in a memory is realized. And data decryption can be symmetrically realized by applying the ciphertext to the input and using the same key array and the complementary key array. In combination with the artificial intelligence calculation accelerator based on the cross point array ferroelectric capacitor array, high-density, high-energy-efficiency and data security enhanced in-memory calculation application can be realized.

Description

Technical Field

[0001] The present invention relates to the fields of data security and computing security, and specifically to an in-memory encryption method based on a cross-lattice ferroelectric capacitor array, which is suitable for high-energy-efficiency and secure artificial intelligence applications in edge devices. Background Art

[0002] With the rapid development of artificial intelligence and big data technologies, the bottleneck of the traditional von Neumann computing architecture, which separates memory and computation, has become increasingly prominent. The transfer of data between memory and computation units causes significant latency and energy waste, placing higher demands on speed and energy efficiency in computing systems. Inspired by the computational model of the human brain, researchers have proposed an in-memory computing architecture that can avoid the latency and energy consumption issues caused by data transfer in traditional von Neumann computing architectures. In hardware deployment solutions for in-memory computing architectures, AI computing accelerators based on traditional CMOS circuits require significant hardware overhead. Furthermore, data retention relies on a long-term power supply, resulting in high energy consumption. Therefore, researchers have proposed using various non-volatile memory devices (NVMs), such as resistive random-access random access memory (RRAM), phase-change random access memory (PCRAM), ferroelectric field-effect transistors (FeFETs), and ferroelectric capacitors (FeCAPs). Leveraging the non-volatility and low power consumption of these memory devices, they can construct artificial neural networks based on synapses. These NVMs offer the advantages of low hardware overhead and high computational efficiency. Furthermore, the high area efficiency of these new NVMs has attracted widespread attention in resource-constrained edge applications.

[0003] This new type of NVM typically maintains the integrity of original data for extended periods even when powered off. However, this inherent characteristic also makes it vulnerable to unauthorized data retrieval, posing a significant data breach risk. Because data is stored in the form of the unique physical properties of the storage medium, attackers can steal data through side-channel attacks, chip cloning, and direct extraction. Therefore, data encryption for NVM is urgently needed. Traditional NVM encryption typically utilizes system-level methods such as the Advanced Encryption Standard (AES). This approach typically requires significant hardware area overhead to house the encryption-specific CMOS circuit modules. This poses process compatibility issues with new NVM devices in resource-constrained edge systems, and the complex encryption process further increases latency and power consumption. Furthermore, AES-based encryption utilizes serial, row-by-row operations, which conflicts with the high parallelism of in-memory computing architectures and compromises computational parallelism. Data obfuscation based on bitwise logic operations is a simple and efficient encryption method that can leverage the computational properties of new NVM devices to implement cell-level operations such as exclusive-OR (XOR) and exclusive-NOR (XNOR). This approach has the potential for high-level integration with in-memory computing architectures, but its parallelism and operation methods require further optimization. In summary, the design of an encryption method that can be directly integrated into the storage array, supports parallel operations, and maintains high energy efficiency and high parallelism is of significant significance for achieving a highly reliable in-memory computing architecture. Summary of the Invention

[0004] In response to the above problems in the prior art, the present invention proposes an in-memory encryption method based on a cross-lattice ferroelectric capacitor array, which can achieve high energy efficiency, high parallelism and high signal recognition data encryption and decryption.

[0005] The technical solutions of the present invention are as follows:

[0006] A method for in-memory encryption based on a cross-lattice ferroelectric capacitor array comprises the following steps:

[0007] 1) A cross-lattice ferroelectric capacitor (FeCAP) array is used as a key array and a complementary key array, respectively. One end of the FeCAP cell in the cross-lattice ferroelectric capacitor array is a word line (WL) for programming and inputting plain text (PT), and the other end of the FeCAP cell is a bit line BL for programming and output. The FeCAP has the functions of cell-level XOR operation and array-level local accumulation operation.

[0008] 2) During the programming array key storage phase, a diagonal data encoding mode is adopted. The FeCAP cells on the diagonal of the key array and the complementary key array are selected as the physical storage locations of the actual key data, which are called key cells. Other FeCAP cells not on the diagonal do not contain key information and are called non-key cells.

[0009] 3) During the FeCAP storage state programming phase, set / reset write pulses are applied to the WL and BL of the key cell; the polarization state of the FeCAP cell is programmed to positive / negative saturation polarization, representing the storage of Key 1 and Key 0, respectively; set write pulses or reset write pulses are applied to the WL and BL of all non-key cells to ensure that the polarization states of all non-key cells remain completely consistent;

[0010] 4) For bias at V + / V - All WLs simultaneously apply input small signal pulses, representing PT 1 and PT0 to be encrypted, respectively, and apply them in parallel to the input ends of the key array and the complementary key array. When the input PT is inconsistent with the stored Key, the FeCAP unit presents a high capacitance state and generates a higher flip charge; when the input PT is consistent with the stored Key, the FeCAP unit presents a low capacitance state and generates a smaller flip charge. The key array and the complementary key array output ciphertext (Cipher Text, CT) respectively.

[0011] Furthermore, the key array stores a binary code value of Key as 0 or 1, and the complementary key array stores a binary complementary code value of Key as 1 or 0.

[0012] Furthermore, the BL outputs of the key array and the complementary key array are output as Q through the recognition and amplification of the charge integrating amplifier. out + and Q out - .

[0013] Furthermore, the BL outputs of the key array and the complementary key array are simultaneously input into the subtractor to eliminate the common mode signal from the non-key unit.

[0014] The technical effects of the present invention are as follows:

[0015] 1. The in-memory encryption method proposed in this invention utilizes the non-volatile characteristics and in-situ computing features of a single FeCAP to achieve in-situ execution of encryption and key storage within the storage array, reducing the power consumption and latency overhead of data transfer compared to traditional AES-based encryption methods.

[0016] 2. The present invention is based on two cross-lattice ferroelectric capacitor arrays and a new diagonal data encoding mode, which can process plaintext input data in parallel for encryption and decryption, overcome the limitations of row-by-row operation, and improve the parallelism of calculation.

[0017] 3. By combining a double-layer FeCAP array and coupled signal subtraction design, the present invention eliminates common-mode signal noise from non-key units, while enhancing the differential-mode signal between the corresponding outputs of the key array and the complementary key array, providing a larger signal margin than the traditional bitwise XOR operation, thereby improving the reliability of the system and the output signal recognition.

[0018] 4. The present invention utilizes the ultra-low power XOR operation characteristics of FeCAP and the AC small signal readout method to realize frequent encryption and decryption of plaintext input data, reducing the frequency of rewriting or refreshing the storage key. At the same time, the charge transfer principle is combined with the charge integrating amplifier to achieve the high energy efficiency advantage of no DC power consumption.

[0019] 5. The hafnium oxide-based FeCAP used in the present invention has high CMOS process compatibility and excellent scalability, thus having huge potential for three-dimensional stacking integration, which can further reduce the actual hardware cost of the in-memory encryption system and provide higher storage density and smaller unit area overhead.

[0020] 6. The present invention can implement configurable data encryption and decryption based on the existing storage and computing integrated architecture based on the cross-lattice ferroelectric capacitor array, without the need for additional encryption and decryption circuits, thereby reducing the hardware cost of resource-constrained edge devices and providing a highly secure and lightweight encryption solution for high-density storage and computing integrated accelerators. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the in-memory encryption architecture and diagonal data encoding mode based on the cross-lattice ferroelectric capacitor array of the present invention;

[0022] In the figure: 1 - key array; 2 - complementary key array; 3 - peripheral circuit module consisting of charge integrator amplifier and subtractor;

[0023] Figure 2 This is a schematic diagram of the key storage and cell-level XOR encryption and its truth value representation implemented based on the FeCAP small-signal capacitance characteristics of the present invention;

[0024] Figure 3 Schematic diagram of the array-level parallel XOR calculation and coupling signal elimination method of the in-memory encryption architecture proposed by the present invention;

[0025] Figure 4The diagram shows the truth table for symmetric data encryption and decryption and the mapping relationship between output physical quantities and logical values of the in-memory encryption design based on the cross-lattice ferroelectric capacitor array of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further clearly and completely described below through specific embodiments in conjunction with the accompanying drawings.

[0027] like Figure 1 As shown, the in-memory encryption architecture based on the cross-matrix ferroelectric capacitor FeCAP array of the present invention includes a key array for storing key information, a complementary key array for storing complementary key information, and a peripheral circuit module composed of a charge integration amplifier and a subtractor. The WL end of the FeCAP unit in the two cross-matrix ferroelectric capacitor FeCAP arrays is used as the plaintext input end, and the BL end of the FeCAP unit in the two arrays is connected to the charge integration amplifier as the output end. The output end of the corresponding charge integration amplifier is further connected to the two input ends of the subtractor circuit to eliminate the coupling noise and output the ciphertext. In the key storage stage, the key units in the two arrays are selected by the diagonal data encoding pattern and the set / reset write pulse is applied to the corresponding WL and BL to program the polarization state of the FeCAP to positive / negative saturation polarization (P r + / P r - ), representing the storage of Key 1 and Key 0 respectively.

[0028] The present invention realizes key storage and cell-level XOR encryption based on the small signal capacitance characteristics of FeCAP and its calculation results are as follows: Figure 2 As shown in the figure, FeCAPs in different saturation polarization states show different responses under the capacitance-voltage sweep test, representing the storage of keys in different states. In the voltage range less than 0V, the capacitance value of FeCAP storing Key 1 is greater than that of FeCAP storing Key 0; in the voltage range greater than 0V, the capacitance value of FeCAP storing Key 1 is less than that of FeCAP storing Key 0. + / V - All WLs of simultaneously apply a small positive signal pulse, representing the input PT 1 and PT 0 to be encrypted, which are applied to the input terminals of the two arrays in parallel. When the input PT is inconsistent with the stored Key, that is, FeCAP will produce a higher reversal charge (Q high ), otherwise FeCAP will produce less flip charge (Q low ), thereby realizing the unit-level XOR operation based on a single FeCAP, and the calculation results are as follows Figure 2 As shown in the table.

[0029] In the first stage of encryption, the bias is at V + / V - All WLs of the array simultaneously apply small signal input pulses, representing the PT 1 and PT 0 to be encrypted, and apply them to the input terminals of the two arrays in parallel. Only when the input PT is inconsistent with the stored Key, the current FeCAP presents a high capacitance state and generates a higher flip charge (Q high ), otherwise FeCAP presents a low capacitance state and generates less flip charge (Q low The total charge ΔQ finally accumulated on BL BL Represents the multiplication-accumulation (MAC) calculation result of all units on the BL, where the output result of the BL in the i-th column of the key array is recorded as The input PT of the i-th row WL is denoted as x i , the storage state of the key unit in row i and column i is recorded as Key i , the output expression is:

[0030]

[0031] The output result of column i BL on the complementary key array is recorded as The storage state of the key unit in row i and column i is recorded as The output expression is:

[0032]

[0033] In the second stage of encryption, the corresponding BL outputs from the key array and the complementary key array are output as Q through the recognition and amplification of the charge integrating amplifier. out + and Q out - , and then input to the subtractor at the same time to eliminate the common mode signal from the non-key unit, and finally generate only the PT input by the i-th row (denoted as x i ) and the mth column stores the Key (denoted as Key m ) jointly determine the mth column output CT (denoted as y m ), whose expression is:

[0034]

[0035] The array-level parallel XOR calculation and coupling signal elimination method of the in-memory encryption architecture proposed by the present invention are as follows: Figure 3As shown, in the first stage of encryption, the flip charge generated by each unit can be obtained by formulas (1) and (2) according to the WL input and storage state; in the second stage of encryption, the BL corresponding to the key array and the complementary key array simultaneously transfers the accumulated total charge to the positive input of the charge integration amplifier. Based on the charge transfer mechanism, the total charge on the BL can be integrated by the integration capacitor to obtain the local MAC calculation result. Furthermore, the MAC results obtained by the BL corresponding to the two arrays are simultaneously input into the subtractor to eliminate the common mode signal from the non-key unit contained in the MAC result, and finally the ciphertext output is obtained. The calculation method of the ciphertext is shown in formula (3). Compared with formulas (1) and (2), it can be seen that compared with the traditional bit-by-bit XOR operation encryption method, the array-level XOR calculation with a larger output signal margin is achieved. The calculation results of each stage are as follows Figure 3 As shown in the table.

[0036] The truth table of the in-memory XOR encryption and decryption based on the cross-point ferroelectric capacitor array proposed by the present invention is as follows: Figure 4 As shown, according to the magnitude relationship of the output charge physical quantity, (Q low -Q high ) is logic 0, (Q high -Q low ) is logically 1, resulting in a logical relationship between the input plaintext, stored key, and output charge in a data obfuscation method that conforms to XOR logic. Furthermore, based on the symmetry of XOR calculations, data decryption can be achieved symmetrically by applying the ciphertext to the input and using the same key array and complementary key array. The logical relationship between the input plaintext, stored key, and output charge during the decryption operation is shown in the truth table.

[0037] Unlike conventional cell-level XOR operations implemented using FeCAP non-destructive readout methods, this invention utilizes a diagonal data encoding pattern and coupled signal subtraction circuitry to generate an array-level XOR operation between plaintext and the key, achieving highly parallel in-memory XOR encryption. Furthermore, based on the complementary relationship between the outputs of the key array and the complementary key array, the peripheral circuit module also features differential-mode signal enhancement, providing greater signal margin than conventional bitwise XOR encryption. Data decryption can be achieved symmetrically by applying ciphertext to the input and using the same key array and complementary key array.

[0038] The present invention proposes an in-memory encryption design based on a cross-lattice ferroelectric capacitor array, wherein the ferroelectric material can be a new ferroelectric material based on HfO2 that produces ferroelectricity under specific treatment (doping, stress, annealing, etc.), or other types of multi-domain ferroelectric materials.

[0039] This embodiment fully and in detail explains the in-memory encryption design based on a cross-lattice ferroelectric capacitor array. It utilizes two cross-lattice ferroelectric capacitor arrays, a charge integrating amplifier, and a subtractor to implement array-level XOR data encryption and decryption operations. Compared with traditional AES-based encryption schemes, it has higher computational parallelism and lower hardware and energy consumption overhead. Compared with traditional bit-by-bit XOR operations, it achieves enhanced output signal margin and has higher signal recognition and reliability.

[0040] Finally, it should be noted that the purpose of disclosing the embodiments is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for in-memory encryption based on a cross-lattice ferroelectric capacitor array, the specific steps of which are as follows: 1) A cross-lattice ferroelectric capacitor (FeCAP) array is used as a key array and a complementary key array, respectively. One end of an FeCAP cell in the cross-lattice ferroelectric capacitor (FeCAP) array is a word line (WL) for programming and inputting plaintext, and the other end of the FeCAP cell is a bit line (BL) for programming and outputting. The FeCAP cell has the functions of cell-level XOR operation and array-level local accumulation operation. 2) During the programming array key storage phase, a diagonal data encoding mode is adopted. The FeCAP cells on the diagonal of the key array and the complementary key array are selected as the physical storage locations of the actual key data, which are called key cells. Other FeCAP cells not on the diagonal do not contain key information and are called non-key cells. 3) During the FeCAP storage state programming phase, set / reset write pulses are applied to the WL and BL of the key cell; the polarization state of the FeCAP cell is programmed to positive / negative saturation polarization, representing the storage of Key 1 and Key 0, respectively; set write pulses or reset write pulses are applied to the WL and BL of all non-key cells to ensure that the polarization states of all non-key cells remain completely consistent; 4) For bias at V + / V - All WLs simultaneously apply input small signal pulses, representing PT 1 and PT 0 to be encrypted, respectively, and apply them in parallel to the input ends of the key array and the complementary key array. When the input PT is inconsistent with the stored Key, the FeCAP unit presents a high capacitance state and generates a higher flip charge; when the input PT is consistent with the stored Key, the FeCAP unit presents a low capacitance state and generates a smaller flip charge. The key array and the complementary key array respectively output ciphertext.

2. The in-memory encryption method based on a cross-lattice ferroelectric capacitor array according to claim 1, wherein: The key array stores a binary code value of Key of 0 or 1, and the complementary key array stores a binary complementary code value of Key of 1 or 0.

3. The in-memory encryption method based on a cross-lattice ferroelectric capacitor array according to claim 1, wherein: The BL outputs of the key array and the complementary key array are respectively output as Q through identification and amplification of the charge integrating amplifier. out + and Q out - .

4. The in-memory encryption method based on a cross-lattice ferroelectric capacitor array as claimed in claim 3, wherein: The BL outputs of the key array and the complementary key array are simultaneously input into a subtractor to eliminate the common mode signal from the non-key unit.

5. The in-memory encryption method based on a cross-lattice ferroelectric capacitor array according to claim 1, wherein: The ferroelectric material of the FeCAP unit is a new type of ferroelectric material based on HfO2 that generates ferroelectricity under specific treatment, or other types of multi-domain ferroelectric materials.

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