Method for detecting silicon single crystal COP free region distribution

Abstract

The invention provides a method for detecting silicon single crystal COP free area distribution, and relates to the technical field of silicon single crystal quality detection.The method comprises the steps that a silicon wafer to be detected is cleaned to obtain a first silicon wafer; uniformly smearing a transition metal ion solution on the surface of the first silicon wafer to obtain a second silicon wafer; placing the second silicon wafer in a high-temperature environment, and performing heat treatment under three temperature gradients to obtain a third silicon wafer; wherein in the first stage, transition metal ions are diffused to the surface layer of the silicon wafer to activate oxygen precipitates in a Pv region, in the second stage, the transition metal ions are promoted to be diffused into the silicon wafer to develop a Pi low-oxygen region, and in the third stage, nuclei coalescence in a B-band region is activated at high temperature to form a differential arrangement ring; cleaning the third silicon wafer through a mixed acid solution to obtain a fourth silicon wafer; and placing the fourth silicon wafer in a preferential corrosion liquid for preferential corrosion, and carrying out COP free area distribution detection on the obtained detection sample wafer. According to the scheme, the definition of each region boundary can be improved, so that the detection accuracy of COP free region distribution is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon single crystal quality detection, and in particular to a method for detecting COP free area distribution of a silicon single crystal. Background Art

[0002] Crystal Originated Particles (COPs) are nanoscale defects formed during the growth of silicon single crystals due to thermodynamic instability or impurity aggregation. They primarily manifest as microvoids or particles within the crystal. Their formation mechanisms primarily include oxygen impurities, thermal stress induction, and impurity contamination. Oxygen impurities are responsible for the precipitation of oxygen atoms from the silicon melt during crystal cooling, forming oxygen precipitates that serve as nuclei for COP defects. When the oxygen concentration exceeds the solid solubility, the oxygen atoms aggregate to form SiO2 clusters, causing local lattice distortion. Thermal stress induction occurs when the temperature gradient during crystal growth leads to localized thermal stress concentrations, causing an imbalance in the recombination of self-interstitial silicon atoms with vacancies, resulting in COP defects. Impurity contamination occurs when metallic impurities such as copper and iron introduced into the molten silicon degrade the integrity of the silicon crystal and exacerbate defect formation.

[0003] COP-free silicon single crystals refer to silicon single crystals in which specific process controls are used to reduce or eliminate the COP defects inherent in the crystal's native particles. In practice, the COP-free region of a silicon single crystal can be divided into three key areas based on oxygen precipitation behavior and defect type: the Pv region (oxygen precipitation promoting region), the Pi region (low-oxygen inert region), and the B-band region (displacement ring). Different regions are suitable for different device fabrication types due to their varying material properties. For example, the Pv region, with its high oxygen concentration and dense distribution of oxygen precipitates, is suitable for devices with high defect tolerance, such as power devices like IGBTs and MOSFETs. The Pi region, with its ultra-low oxygen content and lack of COP and oxygen precipitates, is suitable for high-precision devices such as CPUs, GPUs, DRAM, and filters, ensuring low leakage and high carrier mobility. The B-band region, where interstitial silicon atoms coalesce to form displacement rings, can be used in non-functional peripheral areas of devices to prevent damage to core circuitry. Therefore, accurate regional distribution monitoring of silicon wafers is crucial.

[0004] However, existing solutions make it difficult to fully develop each area, which leads to the inability to accurately quantify the boundaries of the Pv area, Pi area and B-band area, and the detection accuracy of the COP free area distribution is low. Summary of the Invention

[0005] In view of this, to address the above shortcomings, it is necessary to propose a method for detecting the COP free area distribution of silicon single crystals to improve the clarity of the boundaries of the Pv region, Pi region and B-band region, and thus improve the detection accuracy of the COP free area distribution.

[0006] The present invention provides a method for detecting the COP-free region distribution of a silicon single crystal, comprising the following steps: Step 1: Cleaning the silicon wafer to be tested to obtain a first silicon wafer; Step 2: Evenly apply the transition metal ion solution on the surface of the first silicon wafer to obtain a second silicon wafer; Step 3: The second silicon wafer is placed in a high-temperature environment and heat-treated at three temperature gradients to obtain a third silicon wafer. The treatment temperatures in the first, second, and third stages are increased sequentially, such that in the first stage, transition metal ions diffuse to the surface of the silicon wafer to activate oxygen precipitates in the Pv region; in the second stage, transition metal ions diffuse into the interior of the silicon wafer to develop the Pi low-oxygen region; and in the third stage, high temperature activates the agglomeration of atomic nuclei in the B-band region to form clear differential rings. Step 4: Cleaning the third silicon wafer with a mixed acid solution to obtain a fourth silicon wafer, thereby removing the transition metal ion solution and the oxide film on the surface of the silicon wafer; Step 5: Place the fourth silicon wafer in a preferential etching solution for preferential etching, and send the obtained test sample into a darkroom for testing the COP free area distribution.

[0007] Preferably, in step 1, the silicon wafer to be tested is alkaline washed with a NaOH solution having a concentration of 8-10% to remove dirt and grease on the surface of the silicon wafer; and after the alkaline washing, it is rinsed with deionized water to obtain a first silicon wafer.

[0008] Preferably, the transition metal ion is an iron ion, a copper ion, a chromium ion, a cobalt ion, or a nickel ion.

[0009] Preferably, the transition metal ion solution is a copper nitrate solution, and the copper ion concentration is 100-500 ppma.

[0010] Preferably, the heat treatment temperature of the first stage is 800±10℃, and the treatment time is 80~100min, the heat treatment temperature of the second stage is 900±10℃, and the treatment time is 80~100min, and the heat treatment temperature of the third stage is 950±10℃, and the treatment time is 40~50min.

[0011] Preferably, the nitrogen flow rate in the first stage is 5-7 L / min to prevent the oxide layer from interfering with the copper ion diffusion value of the silicon wafer surface; after the second stage is completed, when the temperature is raised to the third stage, the heating rate is not greater than 5°C / min to avoid rapid heating to generate thermal stress, which may cause the silicon wafer to warp; after the third stage is completed, the silicon wafer is rapidly cooled at a rate of not less than 5°C / s after being taken out of the furnace to lock in morphological defects.

[0012] Preferably, in step 4, the mixed acid solution is prepared from hydrofluoric acid, nitric acid, acetic acid and water in a volume ratio of (2-3): (4-6): (2-3): (4-7).

[0013] Preferably, in step 5, the preferential etching solution is prepared from chromic acid solution, copper acid solution, nitric acid, acetic acid and hydrofluoric acid in a volume ratio of 1:(1-3):1:(1-3):(2-4).

[0014] Preferably, the step 5, when detecting the COP-free area distribution of the test sample, may further include enhancing the development effect of each COP-free area in the silicon wafer by using image processing.

[0015] Preferably, the use of image processing to enhance the development effect of each COP-free area in the silicon wafer includes: The detection silicon wafer is imaged using ultraviolet light source, visible light source and infrared light source respectively to obtain ultraviolet light image, visible light image and infrared light image; The ultraviolet image and the infrared image are processed using non-local means denoising to obtain a denoised ultraviolet image and a denoised infrared image; and the visible light image is processed using Gaussian filtering to obtain a denoised visible light image; Using a SIFT algorithm to perform feature point matching on the denoised visible light image to obtain a registered visible light image; Affine transformation algorithm is used to align the denoised ultraviolet image and denoised infrared image with the denoised visible light image to obtain the registered ultraviolet image and the registered infrared image. Wavelet decomposition is used to extract high-frequency and low-frequency components of the registered ultraviolet image, registered infrared image and registered visible light image respectively. For high-frequency components and low-frequency components, the features extracted from the registered ultraviolet image, the registered infrared image, and the registered visible light image are weightedly fused to obtain fused features. The image after feature fusion is color restored, and the restored image is processed by the image enhancement algorithm Retinex to obtain the image after development and enhancement of each area.

[0016] As can be seen from the above technical solution, in the method for detecting the COP-free regional distribution of silicon single crystals provided by the present invention, it is considered to first clean the silicon wafer to be tested to obtain a first silicon wafer, and then evenly apply a transition metal ion solution on the surface of the first silicon wafer to decorate the defects with transition metal ions to obtain a second silicon wafer. Further, it is considered to heat treat the second silicon wafer with three temperature gradients, so that the transition metal ions diffuse to the surface of the silicon wafer in the first stage, activate the oxygen precipitates in the Pv area, promote the diffusion of transition metal ions into the interior of the silicon wafer in the second stage, develop the Pi low-oxygen area, and activate the B-band area at high temperature in the third stage, so that the atomic nuclei condense to form clear differential rings. In this way, the Pv area, Pi area and B-band area can be fully developed through the heat treatment of three temperature gradients, so that the boundaries of the three areas are clearer, and the detection personnel can clearly distinguish the regional distribution of COP free, thereby improving the detection accuracy of the COP-free regional distribution. Further, the third silicon wafer is cleaned by mixed acid, which can remove the transition metal ion solution and oxide film on the surface of the silicon wafer, thereby preventing the impact on preferential corrosion. Finally, the fourth silicon wafer is treated with a selective etching solution, which can effectively etch the defects and highlight the defects on the surface of the silicon wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flow chart of a method for detecting COP-free area distribution of a silicon single crystal provided by an embodiment of the present invention.

[0018] Figure 2 This is the corresponding morphology image of silicon wafer a.

[0019] Figure 3 This is the corresponding morphology image of silicon wafer A.

[0020] Figure 4 This is the corresponding morphology image of silicon wafer b.

[0021] Figure 5 This is the corresponding morphology image of silicon wafer B.

[0022] Figure 6 This is the corresponding morphology image of silicon wafer c.

[0023] Figure 7 This is the corresponding morphology image of silicon wafer C. DETAILED DESCRIPTION

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] The COPfree region is divided into the Pv region, the Pi region, and the B-band region. The Pv region is a crystal region where oxygen precipitates exist and no COP is detected, i.e., an oxygen precipitation promoting region. The Pi region is a crystal region where oxygen precipitation is not easily caused and no COP is detected. The B-Band region is a differential ring formed by the aggregation of inserted silicon atoms. Due to customer demand for silicon wafers in different regions, it is necessary to accurately detect the regional distribution of the sample. Based on this, Figure 1 As shown, the present invention provides a method for detecting the COP free area distribution of a silicon single crystal, comprising the following steps: Step 1: Cleaning the silicon wafer to be tested to obtain a first silicon wafer; Step 2: Evenly apply the transition metal ion solution on the surface of the first silicon wafer to obtain a second silicon wafer; Step 3: The second silicon wafer is placed in a high-temperature environment and heat-treated at three temperature gradients to obtain a third silicon wafer. The treatment temperatures in the first, second, and third stages are increased sequentially, such that in the first stage, transition metal ions diffuse to the surface of the silicon wafer to activate oxygen precipitates in the Pv region; in the second stage, transition metal ions diffuse into the interior of the silicon wafer to develop the Pi low-oxygen region; and in the third stage, high temperature activates the agglomeration of atomic nuclei in the B-band region to form clear differential rings. Step 4: Cleaning the third silicon wafer with a mixed acid solution to obtain a fourth silicon wafer, thereby removing the transition metal ion solution and the oxide film on the surface of the silicon wafer; Step 5: Place the fourth silicon wafer in a preferential etching solution for preferential etching, and send the obtained test sample into a darkroom for testing the COP free area distribution.

[0026] In this embodiment, it is considered that the silicon wafer to be tested is first cleaned to obtain a first silicon wafer, and then a transition metal ion solution is evenly applied to the surface of the first silicon wafer to decorate the defects with transition metal ions to obtain a second silicon wafer. Furthermore, it is considered to heat treat the second silicon wafer with three temperature gradients, so that in the first stage, the transition metal ions are diffused to the surface of the silicon wafer to activate the oxygen precipitates in the Pv area, in the second stage, the transition metal ions are promoted to diffuse into the interior of the silicon wafer to develop the Pi low-oxygen area, and in the third stage, the B-band area is activated at high temperature to cause the atomic nuclei to coalesce to form clear differential rings. In this way, the Pv area, Pi area and B-band area can be fully developed through the heat treatment with three temperature gradients, so that the boundaries of the three areas are clearer, and the test personnel can clearly distinguish the regional distribution of COP free, thereby improving the detection accuracy of the COP free regional distribution. Furthermore, the third silicon wafer is cleaned with mixed acid to remove the transition metal ion solution and oxide film on the surface of the silicon wafer, thereby preventing the impact on preferential corrosion. Finally, the fourth silicon wafer is treated with a selective etching solution, which can effectively etch the defects and highlight the defects on the surface of the silicon wafer.

[0027] In one embodiment, step 1 uses a NaOH solution with a concentration of 8-10% to alkaline wash the silicon wafer to remove dirt and grease on the surface of the silicon wafer; and after the alkaline washing, rinse with deionized water to obtain a first silicon wafer, and place the first silicon wafer on dust-free paper with the engraved side facing up.

[0028] In one embodiment, the transition metal ions may be iron ions, copper ions, chromium ions, cobalt ions, or nickel ions, so that the transition metal ions are precipitated at defects in the silicon wafer, thereby decorating the defects. Of course, the transition metal ions may also be silver ions, gold ions, manganese ions, etc.

[0029] In one embodiment, the transition metal ion solution used can be a copper nitrate solution with a copper ion concentration of 100-500 ppma. At this concentration, the copper ions can be effectively diffused throughout the silicon wafer while avoiding insufficient copper ion diffusion or even excessive copper ion waste. Specifically, the copper nitrate solution can be evenly wiped over the entire surface of the silicon wafer using a dust-free cloth and then left to dry for 1-2 minutes.

[0030] In one embodiment, a silicon wafer is placed on a quartz boat, which is then placed in a muffle furnace using a quartz boat fork for heat treatment. Specifically, the heat treatment temperature for the first stage is 800±10°C, and the treatment time is 80-100 minutes. The heat treatment temperature for the second stage is 900±10°C, and the treatment time is 80-100 minutes. The heat treatment temperature for the third stage is 950±10°C, and the treatment time is 40-50 minutes. Thus, by treating at 800±10°C for 80-100 minutes in the first stage, copper ions can be initially diffused to a depth of about 5 microns on the surface of the silicon wafer, thereby activating oxygen precipitates in the Pv region. Further increasing the temperature and maintaining the temperature at 900±10°C for 80-100 minutes in the second stage can promote the diffusion of copper ions into the interior of the silicon wafer to a depth of about 20 microns, thereby developing the low-oxygen region in the Pi region. Further heating, followed by a third stage of holding at 950±10°C for 40-50 minutes, activates the self-interstitial atomic coalescence in the B-band region, forming distinct dislocation rings. This gradient heat treatment increases the density of oxygen precipitates in the Pv region by approximately 25%, while simultaneously increasing the diameter of the B-band dislocation rings by over 30%.

[0031] In one embodiment, the nitrogen flow rate in the first stage is 5-7 L / min, which can prevent the oxide layer from interfering with the diffusion of copper ions into the silicon wafer surface. The specific principle is: nitrogen, as an inert gas, can inhibit oxidation of the silicon wafer surface during the heat treatment process by reducing the oxygen partial pressure and the gas blanketing effect. To reduce the oxygen partial pressure, the continuous introduction of high-purity nitrogen can displace the oxygen in the furnace, reducing the oxygen partial pressure below the silicon oxidation threshold. At high temperatures of 800-950°C, the reaction between silicon and oxygen is suppressed, preventing the formation of a surface oxide layer. Without the interference of the oxide layer, the diffusion efficiency of copper ions can also be improved, allowing copper ions to evenly penetrate into the silicon lattice. Regarding the gas blanketing effect, a flow rate of 5-7 L / min ensures that a stable nitrogen laminar flow is formed in the furnace to cover the silicon wafer surface, preventing residual oxygen from contacting. It has been verified that when the nitrogen flow rate is greater than 5 L / min, the thickness of the oxide layer on the silicon wafer surface is less than 1 nm.

[0032] In one embodiment, after the second stage, the temperature is raised to the third stage at a rate of no more than 5°C / min to avoid rapid heating, which can cause thermal stress and warping of the silicon wafer. The specific principle is that thermal stress is generated during the heating process due to differences in thermal expansion coefficients. A rapid heating rate can lead to temperature gradients that induce stress or lattice slip, which can cause distortion. If the heating rate is too high, a temperature difference between the edge and center of the silicon wafer due to heat conduction lags can result in localized expansion differences. When the thermal stress exceeds the yield strength of silicon, the silicon wafer undergoes plastic deformation, or warping. By increasing the temperature slowly, at a rate of no more than 5°C / min, the overall temperature of the silicon wafer rises uniformly, keeping thermal stress within the elastic deformation range and avoiding dislocation slip and lattice distortion. Experiments have shown that when the heating rate is no more than 5°C / min, silicon wafer warpage can be controlled within 10 microns. However, when the heating rate exceeds 10°C / min, the warpage can even exceed 50 microns.

[0033] In one embodiment, after the third stage, the silicon wafer is rapidly cooled at a rate of no less than 5°C / s after exiting the furnace to lock in morphological defects. The specific principle is that after high-temperature heat treatment, defects such as COPs and dislocation loops in the silicon wafer are in a metastable state, and the cooling rate directly affects their evolutionary behavior. At 950°C, self-interstitial silicon atoms and vacancies have high mobility. Slow cooling allows atoms ample time to migrate and recombine, leading to structural changes in the defects, such as dislocation loop expansion or merging. Cooling rates greater than 5°C / s, however, freeze the atoms, preserving the post-heat treatment defect morphology. Furthermore, rapid cooling methods such as nitrogen jet cooling can form a high density of dislocation pinning sites on the silicon wafer surface, preventing dislocation loop slip and proliferation. It has been verified that the dislocation loop diameter in the B-band region stabilizes at 50-100 nm after rapid cooling, while it can increase by over 200 nm with slower cooling.

[0034] In one embodiment, step 4 involves etching the silicon wafer with a mixed acid solution for 1-2 minutes to remove the copper nitrate solution and oxide film on the surface of the silicon wafer, thereby preventing the oxide film from affecting the preferential etching. The mixed acid solution can be prepared from hydrofluoric acid, nitric acid, acetic acid, and water in a volume ratio of (2-3):(4-6):(2-3):(4-7).

[0035] In one embodiment, step 5 considers etching the silicon wafer with a preferential etching solution for 1-5 minutes to fully reveal the defects. The preferential etching solution can be prepared from chromic acid solution, copper acid solution, nitric acid, acetic acid, and hydrofluoric acid in a volume ratio of 1:(1-3):1:(1-3):(2-4).

[0036] Furthermore, in one embodiment, in order to further improve the accuracy of silicon wafer COP free observation, it is also possible to consider enhancing the development effect of each area of the silicon wafer through image processing. Specifically, this can be achieved through the following steps: S51: using an ultraviolet light source, a visible light source, and an infrared light source to capture images of the detection silicon wafer, respectively, to obtain an ultraviolet light image, a visible light image, and an infrared light image; In this step, a high-resolution CCD camera is used to capture images of the silicon wafer. The camera is equipped with a multi-band tube-slice switching system that can use 365nm ultraviolet light, 550nm visible light, and 850nm infrared light as light sources. Ultraviolet light can excite the fluorescent signal of COP defects on the surface of the silicon wafer, thereby highlighting the white mist-like features of the Pv area. Visible light can capture the macroscopic morphology of the surface, such as uniform bright spots in the Pi area and annular stripes in the B-band area. Infrared light can penetrate the surface of the silicon wafer to a depth of about 50 microns, thereby displaying the differential ring structure inside the B-band area. In this way, this step provides a global morphology reference through visible light, enhances the local contrast of COP defects through ultraviolet light, and reveals deep defect characteristics through infrared light, thereby helping to improve the accuracy of COP free area distribution detection.

[0037] S52: Processing the ultraviolet image and the infrared image using non-local means denoising to obtain a denoised ultraviolet image and a denoised infrared image; and processing the visible light image using Gaussian filtering to obtain a denoised visible light image. In this step, we consider using algorithms such as NL-Means to perform non-local mean denoising on UV and infrared images while preserving edge details. For visible light images, we consider using Gaussian filtering to smooth out the interference of surface scratches.

[0038] S53: performing feature point matching on the denoised visible light image using a local feature detection algorithm SIFT to obtain a registered visible light image; In this step, key points of the visible light image are extracted using the SIFT algorithm, which can achieve scale-invariant feature transformation. The visible light image can be used as a reference to combine the ultraviolet light image and the infrared light image for feature extraction and fusion.

[0039] S54: using an affine transformation algorithm to align the denoised ultraviolet image and the denoised infrared image with the denoised visible light image to obtain a registered ultraviolet image and a registered infrared image; This step and step S53 can ensure that the spatial positions of the three-channel images of visible light, ultraviolet light and infrared light are strictly consistent, thereby avoiding artifacts during fusion.

[0040] S55: using wavelet decomposition to extract high-frequency and low-frequency components of the registered ultraviolet image, the registered infrared image, and the registered visible light image respectively; In this step, a three-layer wavelet decomposition is performed on each channel image to extract the high-frequency components containing edge and texture information and the low-frequency components containing background information.

[0041] S56: performing weighted fusion on the features extracted from the registered ultraviolet image, the registered infrared image, and the registered visible light image for the high-frequency component and the low-frequency component, respectively, to obtain a fused feature; In this step, when fusing the features extracted from each image, consider using a weighted fusion approach. For example, for high-frequency components, a weight of 0.5 is assigned to ultraviolet light, 0.3 to visible light, and 0.2 to infrared light, thereby fully highlighting the COP details. For low-frequency components, a weight of 0.2 is assigned to ultraviolet light, 0.5 to visible light, and 0.3 to infrared light, thereby preserving the overall morphology as much as possible.

[0042] S57: Performing color restoration on the image after feature fusion, and processing the restored image by using the image enhancement algorithm Retinex to obtain an image after development and enhancement of each region.

[0043] In this step, we consider color restoration on the fused image to enhance the color contrast between the Pv region and the B-band region. Specifically, we use a multi-scale Retinex algorithm. This approach improves the contrast between the white fog-like features in the Pv region and the annular stripes in the B-band region by over 60%.

[0044] The following describes the effect of the heat treatment process of the present invention by adopting a three-stage temperature gradient through the detection process and results of the embodiment of the method of the present invention and the comparative example of the traditional method.

[0045] Three types of silicon wafers with known COP-free area distributions were selected: Pv-region wafers, Pi+Pv-region wafers, and B-band-region wafers. All three wafers were previously split into four quarter wafers, with one of the remaining wafers tested to determine the COP-free area distribution. For the Pv-region wafers, two wafers were selected, labeled a and A. Similarly, for the Pi+Pv-region wafers, two wafers were selected, labeled b and B. For the B-band-region wafers, two wafers were selected, labeled c and C.

[0046] Wafers a, b, and c were treated using a traditional wafer treatment process. The specific treatment process is as follows: The wafers were alkaline-washed with an 8% NaOH solution to remove surface dirt and grease. After rinsing with deionized water, they were placed on a sheet of dust-free paper with the engraved surface facing up. One to three drops of copper nitrate solution (with a copper ion concentration of 100-500 ppma) were applied to the wafer surface. The copper nitrate solution was evenly wiped across the entire surface with a dust-free cloth and allowed to dry for 1-2 minutes. The wafers were then placed on a quartz boat, which was then positioned in a muffle furnace using a quartz boat fork. After heat treatment at 700-1000°C for 3-6 hours, the boat was removed and rapidly cooled. After cooling, the wafers were etched with a mixed acid solution consisting of hydrofluoric acid, nitric acid, acetic acid, and water in a volume ratio of (2-3):(4-6):(2-3):(4-7) for 1-2 minutes to remove the copper nitrate solution and oxide film from the surface. Then, a selective etching solution made of chromic acid solution, copper acid solution, nitric acid, acetic acid and hydrofluoric acid in a volume ratio of 1: (1-3): 1: (1-3): (2-4) was used to etch for 1-5 minutes to make the defects appear. Finally, it was cleaned with deionized water, and the surface water droplets were blown away with a water gun before being sent to the darkroom for inspection. The test results were as follows: Figure 2 、 Figure 4 and Figure 6 shown.

[0047] Silicon wafers A, B, and C were treated using the method of the present invention. The specific treatment process is as follows: The sample was alkaline-washed with an 8% NaOH solution to remove surface dirt and grease. After rinsing with deionized water, the sample was placed on a sheet of clean paper with the engraved surface facing up. One to three drops of copper nitrate solution were added to the surface of the silicon wafer, with a copper ion concentration of 100-500 ppma. The copper nitrate solution was evenly wiped onto the entire surface of the silicon wafer with a clean cloth and allowed to dry for 1-2 minutes. The silicon wafer was placed on a quartz boat, which was then positioned in a muffle furnace using a quartz boat fork. The temperature was maintained at 800±10°C for 80-100 minutes, followed by 900±10°C for 80-100 minutes, and then at 950±10°C for 40-50 minutes. The boat was then removed and rapidly cooled. After the sample is cooled, it is corroded for 1-2 minutes with a mixed acid solution composed of hydrofluoric acid, nitric acid, acetic acid and water in a volume ratio of (2-3): (4-6): (2-3): (4-7) to remove the copper nitrate solution and oxide film on the surface. Then, it is corroded for 1-5 minutes with a preferential etching solution composed of chromic acid solution, copper acid solution, nitric acid, acetic acid and hydrofluoric acid in a volume ratio of 1: (1~3): 1: (1~3): (2~4) to make the defects appear. Finally, it is cleaned with deionized water, and the surface water droplets are blown away with a water gun and sent to the darkroom of the inspection room for inspection. The test results are as follows: Figure 3 、 Figure 5 and Figure 7 shown.

[0048] In summary, by comparison Figure 2 and Figure 3 It can be seen that the surface pattern of the silicon wafer a obtained by the traditional solution is not clear, and the Pv area is not fully developed. However, the white fog pattern on the surface of the silicon wafer A obtained by this solution is clear, and the Pv area is fully developed. By comparison Figure 4 and Figure 5 It can be seen that the Pi and Pv areas on the surface of the silicon wafer b obtained by the traditional method are completely indistinguishable and not effectively developed. However, the Pi and Pv areas on the surface of the silicon wafer B obtained by this method are fully developed, and the boundary between the two can be clearly distinguished. By comparison Figure 6 and Figure 7 As can be seen, the B-band region of wafer c obtained using the traditional method is not clearly distinguishable, with only scattered dots in the central foggy band. However, wafer C obtained using this method can be clearly identified as a B-band type wafer, with distinct boundaries between its components. This demonstrates that compared to the traditional single-temperature heat treatment process, this method's three-stage temperature gradient heat treatment fully reveals the distribution of various COP-free regions, thereby improving the accuracy of COP-free regional distribution detection.

[0049] The modules or units in the apparatus of the embodiments of the present invention may be combined, divided, or deleted as needed. The above disclosure is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Persons skilled in the art will appreciate that any equivalent variations made by implementing all or part of the processes of the above embodiments in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A method for detecting the COP-free area distribution of a silicon single crystal, characterized in that: The following steps are involved: Step 1: Cleaning the silicon wafer to be tested to obtain a first silicon wafer; Step 2: Evenly apply the transition metal ion solution on the surface of the first silicon wafer to obtain a second silicon wafer; Step 3: The second silicon wafer is placed in a high-temperature environment and heat-treated at three temperature gradients to obtain a third silicon wafer. The treatment temperatures in the first, second, and third stages are increased sequentially, such that in the first stage, transition metal ions diffuse to the surface of the silicon wafer to activate oxygen precipitates in the Pv region; in the second stage, transition metal ions diffuse into the interior of the silicon wafer to develop the Pi low-oxygen region; and in the third stage, high temperature activates the agglomeration of atomic nuclei in the B-band region to form clear differential rings. Step 4: Cleaning the third silicon wafer with a mixed acid solution to obtain a fourth silicon wafer, thereby removing the transition metal ion solution and the oxide film on the surface of the silicon wafer; Step 5: Place the fourth silicon wafer in a preferential etching solution for preferential etching, and send the obtained test sample into a darkroom for testing the COP free area distribution.

2. The method for detecting the COP-free area distribution of a silicon single crystal according to claim 1, characterized in that: In the step 1, the silicon wafer to be tested is alkaline washed with a NaOH solution having a concentration of 8-10% to remove dirt and grease on the surface of the silicon wafer; and after the alkaline washing, it is rinsed with deionized water to obtain a first silicon wafer.

3. The method for detecting the COP-free area distribution of a silicon single crystal according to claim 1, characterized in that: The transition metal ion is an iron ion, a copper ion, a chromium ion, a cobalt ion or a nickel ion.

4. The method for detecting the COP-free area distribution of a silicon single crystal according to claim 3, characterized in that: The transition metal ion solution is a copper nitrate solution, and the copper ion concentration is 100-500 ppma.

5. The method for detecting the COP-free area distribution of a silicon single crystal according to claim 1, characterized in that: The heat treatment temperature of the first stage is 800±10℃, and the treatment time is 80~100min. The heat treatment temperature of the second stage is 900±10℃, and the treatment time is 80~100min. The heat treatment temperature of the third stage is 950±10℃, and the treatment time is 40~50min.

6. The method for detecting the COP-free area distribution of a silicon single crystal according to claim 5, characterized in that: The nitrogen flow rate in the first stage is 5-7 L / min to prevent the oxide layer from interfering with the copper ion diffusion value of the silicon wafer surface. After the second stage, when the temperature is raised to the third stage, the heating rate is no more than 5 ° C / min to avoid thermal stress caused by rapid heating, which may cause silicon wafer warping. After the third stage is completed, the silicon wafer is rapidly cooled at a rate of not less than 5° C. / s after being taken out of the furnace to lock in morphological defects.

7. The method for detecting COP-free area distribution of silicon single crystal according to claim 1, characterized in that: In step 4, the mixed acid solution is prepared by mixing hydrofluoric acid, nitric acid, acetic acid and water in a volume ratio of (2-3): (4-6): (2-3): (4-7).

8. The method for detecting COP-free area distribution of a silicon single crystal according to claim 1, characterized in that: In step 5, the preferential etching solution is prepared by mixing chromic acid solution, copper acid solution, nitric acid, acetic acid and hydrofluoric acid in a volume ratio of 1:(1-3):1:(1-3):(2-4).

9. The method for detecting COP-free area distribution of a silicon single crystal according to claim 1, characterized in that: The step 5, when testing the COP-free area distribution of the test sample, may also include enhancing the development effect of each COP-free area in the silicon wafer by using image processing.

10. The method for detecting COP-free area distribution of silicon single crystal according to claim 9, characterized in that: The image processing is used to enhance the development effect of each COP-free area in the silicon wafer, including: The detection silicon wafer is imaged using ultraviolet light source, visible light source and infrared light source respectively to obtain ultraviolet light image, visible light image and infrared light image; The ultraviolet image and the infrared image are processed using non-local means denoising to obtain a denoised ultraviolet image and a denoised infrared image; and the visible light image is processed using Gaussian filtering to obtain a denoised visible light image; Using a SIFT algorithm to perform feature point matching on the denoised visible light image to obtain a registered visible light image; Affine transformation algorithm is used to align the denoised ultraviolet image and denoised infrared image with the denoised visible light image to obtain the registered ultraviolet image and the registered infrared image. Wavelet decomposition is used to extract high-frequency and low-frequency components of the registered ultraviolet image, registered infrared image and registered visible light image respectively. For high-frequency components and low-frequency components, the features extracted from the registered ultraviolet image, the registered infrared image, and the registered visible light image are weightedly fused to obtain fused features. The image after feature fusion is color restored, and the restored image is processed by the image enhancement algorithm Retinex to obtain the image after development and enhancement of each area.

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