Instruction-level code optimization method and device based on template matching, medium and equipment

Abstract

The invention discloses an instruction-level code optimization method and device based on template matching, a medium and equipment. According to the method, instruction-level codes serve as input, the input instruction-level codes are firstly constructed into corresponding control flow diagrams, then value ranges of active variables and register quantities are initialized based on the control flow diagrams, then variable assignment instructions and related instructions are found out from instruction sequences of basic blocks to form instruction segments to be optimized, and the instruction segments to be optimized are optimized. The method comprises the following steps of: optimizing an instruction fragment, obtaining an optimized instruction fragment through template matching, performing SMT equivalence verification on the instruction fragment before and after optimization based on an active variable and a value range of a register quantity, and finally optimizing an input instruction-level code in a manner of replacing the instruction fragment before optimization with the optimized instruction fragment which is verified to be equivalent. And finally, the optimized instruction-level code is obtained.

Description

Technical Field

[0001] The present invention relates to code optimization, and in particular to instruction-level code optimization at the bytecode level. Background Art

[0002] Due to its privileged role in monitoring the entire system, the operating system kernel has always been an ideal location for implementing internal system observation, security monitoring, and networking functions. However, due to the need for stability and security, operating system kernel updates are infrequent and do not support user-modified kernel code to obtain kernel data or add new features. To address the conflict between developers' demand for kernel extensions and the practical considerations of maintaining kernel security and stability, a technical solution is urgently needed that ensures kernel stability while allowing for flexible expansion of kernel functionality.

[0003] The emergence of eBPF (extended Berkeley Packet Filter) technology has greatly improved this dilemma. By running sandboxed programs within the operating system, eBPF technology can securely obtain kernel data or extend kernel functionality without changing the kernel source code or adding any kernel modules, thereby improving the kernel's observability and scalability. Currently, eBPF technology has been widely used in high-performance networking, kernel observation, security detection and other fields. For example, eBPF can be used to provide high-performance networking and load balancing in modern data centers and cloud-native environments, extract fine-grained security observable data with low overhead, and help application developers trace applications and troubleshoot performance issues.

[0004] In application scenarios with high program execution performance requirements, such as high-performance networking, eBPF code often requires high performance optimization. Common performance issues with current eBPF code include redundant register allocation, inefficient memory operations, and inefficient register operation modes. Since eBPF code is often called frequently, even small performance losses can lead to significant performance degradation when the code is called frequently without effective optimization. These issues significantly increase the processing time of each packet, significantly reducing system throughput.

[0005] Furthermore, since eBPF programs must be loaded into the kernel for execution, a static checker (verifier) for eBPF is implemented in the kernel to ensure that these programs do not cause kernel-damaging operations. This verifier enforces strict security requirements for eBPF programs. The verifier performs a comprehensive static analysis of eBPF programs, checking their size, control flow structure, and instruction validity to ensure that the program terminates, does not crash, does not access kernel memory beyond its bounds, and does not leak privileged kernel data. Only programs that pass these rigorous checks are allowed to run in the kernel environment, thus ensuring system stability and security. Summary of the Invention

[0006] The problem to be solved by the present invention is: to achieve code optimization at the bytecode level with lower time consumption, with the optimization goal of reducing the number of instructions or the overall running time of the instruction sequence, and ensuring that the optimization result passes the verification of the static checker in the kernel on the basis of semantic equivalence with the original program.

[0007] To solve the above problems, the present invention adopts the following solutions: The instruction-level code optimization method based on template matching according to the present invention includes an initialization step, a fragment optimization step and an instruction reorganization step; The initialization step includes: A control flow graph construction step is to construct a control flow graph for the instruction-level code to be optimized; the control flow graph is a directed graph with basic blocks as nodes and jumps between basic blocks as edges; the basic block is an instruction sequence that is only entered at the first instruction; The active variable determination step involves traversing each basic block according to the control flow graph, finding variable assignment instructions and forward and backward reference relationships in the instruction sequence through the traversal of the basic block, and then determining the active variables of each instruction based on the variable assignment instructions and forward and backward reference relationships; the variables are register quantities and memory segment quantities; the active variables of the instruction are register quantities and memory segment quantities that are referenced but not assigned in subsequent instructions; The register value range determination step is to traverse each basic block according to the control flow graph, and to determine the value range of each register value before and after the execution of each instruction by performing path-based simulation execution on the instruction sequence of the traversed basic block; The fragment optimization steps include: Instruction fragment extraction step, find the variable assignment instruction from the instruction sequence of the basic block, then find the continuous and associated instructions of the variable assignment instruction in the basic block based on the variable assignment instruction, and then the variable assignment instruction and its continuous and associated instructions constitute the instruction fragment to be optimized; The fragment template matching step is to perform template matching on the instruction fragment to be optimized and each optimization template in the optimization template library. If the instruction fragment template before optimization of the optimization template in the optimization template library matches the instruction fragment to be optimized, the instruction fragment to be optimized is optimized according to the instruction fragment template after optimization of the optimization template to obtain the corresponding optimized instruction fragment; The fragment equivalence verification step determines the register quantity input range of the instruction fragment to be optimized based on the value range of each register quantity before each instruction is executed and the instruction fragment to be optimized, and then uses the instruction fragment before optimization and the instruction fragment after optimization themselves as SMT constraint items, and combines the SMT constraint items of the register quantity input range, the SMT constraint items of the same input variable values of the instruction fragment before optimization and the instruction fragment after optimization, and the SMT constraint items of different active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization to construct a fragment equivalence verification SMT constraint, and then inputs the constructed fragment equivalence verification SMT constraint into the SMT solver for solution, and verifies whether the optimized instruction fragment is equivalent to the pre-optimization instruction fragment based on the solution result of the SMT solver, thereby obtaining an equivalence verification pair consisting of the verified equivalent post-optimization instruction fragment and the pre-optimization instruction fragment; In the instruction reorganization step, based on the equivalence verification pairs obtained from the basic block, the basic block instruction sequence is optimized and reorganized by replacing the corresponding pre-optimization instruction fragments with the optimized instruction fragments that are verified to be equivalent in the equivalence verification pairs.

[0008] Further, according to the instruction-level code optimization method of the present invention, in the instruction fragment extraction step, The continuous and associated instructions of the variable assignment instructions include memory segment quantity assignment instructions whose memory addresses are adjacent to the variable and can form a larger integer with the variable when the variable is a memory segment quantity.

[0009] Furthermore, according to the instruction-level code optimization method of the present invention, the active variable determination step includes the following steps: Step S121: Initialize the corresponding BR_U(i), BM_U(i), BR_A(i), BM_A(i), BR_I(i), BM_I(i), BR_O(i) and BM_O(i) for each basic block by traversing the basic block instruction sequence and the variables contained in the instructions; wherein, BR_U(i) represents the set of registers referenced in basic block i. BM_U(i) represents the set of memory segments referenced in basic block i. BR_A(i) represents the set of assigned registers in basic block i. BM_A(i) represents the set of memory segments assigned in basic block i. BR_I(i) represents the set of active registers at the entry of basic block i, BM_I(i) represents the set of active memory segments at the entry of basic block i. BR_O(i) represents the set of active registers at the exit of basic block i, BM_O(i) represents the set of active memory segments at the exit of basic block i; Initially, the sets BR_I(i), BM_I(i), BR_O(i) and BM_O(i) are empty; Step S122: Traverse the basic blocks according to the control flow graph, and calculate the traversed basic blocks according to the following set operation formula: BR_O(i)=⋃s∈next(i) BR_I(s); BM_O(i)=⋃s∈next(i) BM_I(s); Then calculate according to the following set operation formula: BR_I(i) = BR_U(i)⋃(BR_O(i)-BR_A(i)); BM_I(i) = BM_U(i)⋃(BM_O(i)-BM_A(i)); Where i represents the basic block currently being traversed, and next(i) represents the set of basic blocks following basic block i. Step S123: Repeat step S122 until the active register quantity set BR_I(i) at the entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit of each basic block no longer change; Step S124: According to the limitations of the active register quantity set BR_I(i) at the basic block entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit and the variables contained in each instruction in the basic block, the active register quantity set and the active memory segment quantity set corresponding to each instruction of each basic block are obtained in an iterative manner.

[0010] Furthermore, according to the instruction-level code optimization method of the present invention, the construction formula of the fragment equivalence verification SMT constraint is expressed as: E≡S_origin∧S_candidate∧ (input_reg_origin∈[min_value,max_value])∧ (input_origin=input_candidate )∧ (output_origin≠output_candidate )(output∈live); in, E represents the fragment equivalence verification SMT constraint, S_origin represents the SMT constraint item constructed by the instruction fragment itself before optimization. S_candidate represents the SMT constraint item constructed by the optimized instruction fragment itself; (input_reg_origin∈[min_value,max_value]) represents the SMT constraint item constructed by the input range of each register. (input_origin=input_candidate ) indicates the SMT constraint item constructed when the input variable values of the instruction fragment before optimization and the instruction fragment after optimization are the same. (output_origin≠output_candidate )(output∈live) indicates that the SMT constraint item is constructed when the active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization are different.

[0011] The instruction-level code optimization device based on template matching according to the present invention includes an initialization module, a fragment optimization module and an instruction reorganization module; The initialization module includes: A control flow graph construction module is used to: construct a control flow graph for the instruction-level code to be optimized; the control flow graph is a directed graph with basic blocks as nodes and jumps between basic blocks as edges; the basic block is an instruction sequence that is only entered at the first instruction; An active variable determination module is configured to: traverse each basic block according to the control flow graph, find variable assignment instructions and forward and backward reference relationships in the instruction sequence by traversing the basic blocks, and then determine the active variables of each instruction based on the variable assignment instructions and forward and backward reference relationships; the variables are register quantities and memory segment quantities; the active variables of an instruction are register quantities and memory segment quantities that are referenced but not assigned in subsequent instructions; A register value range determination module is used to: traverse each basic block according to the control flow graph, and determine the value range of each register value before and after the execution of each instruction by performing path-based simulation execution on the instruction sequence of the traversed basic block; The fragment optimization module includes: An instruction fragment extraction module is used to: find the variable assignment instruction from the instruction sequence of the basic block, then find the continuous and associated instructions of the variable assignment instruction in the basic block based on the variable assignment instruction, and then the variable assignment instruction and its continuous and associated instructions form the instruction fragment to be optimized; The fragment template matching module is used to: perform template matching between the instruction fragment to be optimized and each optimization template in the optimization template library. If the instruction fragment template before optimization of the optimization template in the optimization template library matches the instruction fragment to be optimized, the instruction fragment to be optimized is optimized according to the instruction fragment template after optimization of the optimization template to obtain the corresponding optimized instruction fragment; The fragment equivalence verification module determines the register quantity input range of the instruction fragment to be optimized based on the value range of each register quantity before the execution of each instruction and the instruction fragment to be optimized, and then uses the instruction fragment before optimization and the instruction fragment after optimization themselves as SMT constraint items, and combines the SMT constraint items of the register quantity input range, the SMT constraint items of the same input variable values of the instruction fragment before optimization and the instruction fragment after optimization, and the SMT constraint items of different active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization to construct a fragment equivalence verification SMT constraint, and then inputs the constructed fragment equivalence verification SMT constraint into the SMT solver for solution, and verifies whether the optimized instruction fragment is equivalent to the pre-optimization instruction fragment based on the solution result of the SMT solver, thereby obtaining an equivalence verification pair consisting of the verified equivalent post-optimization instruction fragment and the pre-optimization instruction fragment; The instruction reorganization module is used to optimize and reorganize the basic block instruction sequence according to each equivalence verification pair obtained from the basic block, by replacing the corresponding pre-optimization instruction fragments with the optimized instruction fragments in the equivalence verification pair that have been verified to be equivalent.

[0012] Further, according to the instruction-level code optimization device of the present invention, in the instruction fragment extraction module, The continuous and associated instructions of the variable assignment instructions include memory segment quantity assignment instructions whose memory addresses are adjacent to the variable and can form a larger integer with the variable when the variable is a memory segment quantity.

[0013] Furthermore, according to the instruction-level code optimization device of the present invention, the active variable determination module includes the following modules: Module M121 is used to initialize the corresponding BR_U(i), BM_U(i), BR_A(i), BM_A(i), BR_I(i), BM_I(i), BR_O(i) and BM_O(i) for each basic block by traversing the basic block instruction sequence and the variables contained in the instructions; wherein, BR_U(i) represents the set of registers referenced in basic block i. BM_U(i) represents the set of memory segments referenced in basic block i. BR_A(i) represents the set of assigned registers in basic block i. BM_A(i) represents the set of memory segments assigned in basic block i. BR_I(i) represents the set of active registers at the entry of basic block i, BM_I(i) represents the set of active memory segments at the entry of basic block i. BR_O(i) represents the set of active registers at the exit of basic block i, BM_O(i) represents the set of active memory segments at the exit of basic block i; Initially, the sets BR_I(i), BM_I(i), BR_O(i) and BM_O(i) are empty; Module M122 is used to traverse the basic blocks according to the control flow graph, and calculate the traversed basic blocks according to the following set operation formula: BR_O(i)=⋃s∈next(i) BR_I(s); BM_O(i)=⋃s∈next(i) BM_I(s); Then calculate according to the following set operation formula: BR_I(i) = BR_U(i)⋃(BR_O(i)-BR_A(i)); BM_I(i) = BM_U(i)⋃(BM_O(i)-BM_A(i)); Where i represents the basic block currently being traversed, and next(i) represents the set of basic blocks following basic block i. Module S123 is used to repeat module S122 until the active register quantity set BR_I(i) at the entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit of each basic block no longer change; Module S124 is used to iteratively obtain the active register quantity set and active memory segment quantity set corresponding to each instruction of each basic block according to the restrictions of the active register quantity set BR_I(i) at the basic block entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit, and the variables contained in each instruction in the basic block.

[0014] The instruction-level code optimization device according to claim 5, wherein the construction formula of the fragment equivalence verification SMT constraint is expressed as: E≡S_origin∧S_candidate∧ (input_reg_origin∈[min_value,max_value])∧ (input_origin=input_candidate )∧ (output_origin≠output_candidate )(output∈live); in, E represents the fragment equivalence verification SMT constraint, S_origin represents the SMT constraint item constructed by the instruction fragment itself before optimization. S_candidate represents the SMT constraint item constructed by the optimized instruction fragment itself; (input_reg_origin∈[min_value,max_value]) represents the SMT constraint item constructed by the input range of each register. (input_origin=input_candidate ) indicates the SMT constraint item constructed when the input variable values of the instruction fragment before optimization and the instruction fragment after optimization are the same. (output_origin≠output_candidate )(output∈live) indicates that the SMT constraint item is constructed when the active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization are different.

[0015] According to a machine-readable medium of the present invention, a program instruction set is stored. When the program instruction set stored in the medium is loaded and executed by a machine, the machine can implement the above-mentioned instruction-level code optimization method.

[0016] According to an electronic device of the present invention, the device includes a connected processor and a memory, wherein the memory stores a program instruction set, and the processor is capable of loading and executing the program instruction set stored in the memory. When the program instruction set stored in the memory is loaded and executed by the processor, the device is capable of implementing the above-mentioned instruction-level code optimization method.

[0017] The technical effects of the present invention are as follows: the present invention realizes instruction-level code optimization by optimizing template matching in combination with equivalence verification, and equivalence verification ensures that the effects of instruction fragments before and after optimization remain consistent. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flow chart of an embodiment of the instruction-level code optimization method based on template matching of the present invention.

[0019] Figure 2 It is a structural schematic diagram of the electronic device of the present invention.

[0020] Figure 3 This is a control flow graph of the example code of an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described in detail below with reference to the accompanying drawings.

[0022] FIG2 illustrates an electronic device, which is a general-purpose computer device in a von Neumann architecture, comprising at least a processor 201 and a memory 202 connected thereto. Memory 202 is used to store computer program instruction sets and data. Processor 201 implements the template matching-based instruction-level code optimization method of the present invention by loading and executing the computer program instruction sets stored in memory 202. Memory 202, also referred to as a machine-readable medium in the present invention, is typically a persistent storage device, including but not limited to a disk, tape, solid-state drive, and the like.

[0023] Reference Figure 1 The template matching-based instruction-level code optimization method of this embodiment is divided into three stages: initialization step S1, fragment optimization step S2, and instruction reorganization step S3. The input of the present invention is instruction-level code, which is an intermediate code generated by compiling the source code. Specifically in this embodiment, it is the instruction-level code at the bytecode level. For ease of explanation, this specification uses the following instruction-level code at the bytecode level as an example: Disassembly of section xdp1: 0000000000000000<xdp_prog1> : 0: r2 = *(u32 *)(r1 + 4) 1: r1 = *(u32 *)(r1 + 0) 2: r3 = r1 3: r3 += 14 4: if r3>r2 goto +54<LBB0_20> 5: r3 = *(u8 *)(r1 + 12) 6: r4 = *(u8 *)(r1 + 13) 7: r4<<= 8 8: r4 |= r3 9: if r4 == 129 goto +2<LBB0_3> 10: r3 = 14 11: if r4 != 43144 goto +5<LBB0_5> 0000000000000060<LBB0_3> : 12: r3 = r1 13: r3 += 18 14: if r3>r2 goto +44<LBB0_20> 15: r3 = 18 16: r4 = *(u16 *)(r1 + 16) 00000000000000088<LBB0_5> : 17: r5 = r4 18: r5&= 65535 19: if r5 == 129 goto +1<LBB0_7> 20: if r5 != 43144 goto +9<LBB0_9> 000000000000000a8<LBB0_7> : 21: r5 = r3 22: r5 += 4 23: r4 = r1 24: r4 += r5 25: if r4>r2 goto +33<LBB0_20> 26: r4 = r1 27: r4 += r3 28: r4 = *(u16 *)(r4 + 2) 29: r3 = r5 000000000000000f0<LBB0_9> : 30: r4&= 65535 31: if r4 == 56710 goto +8<LBB0_14> 32: if r4 != 8 goto +15<LBB0_17> 33: r1 += r3 34: r3 = 0 35: r4 = r1 36: r4 += 20 37: if r4>r2 goto +8<LBB0_13> 38: r3 = *(u8 *)(r1 + 9) 39: goto +6<LBB0_13> 00000000000000140<LBB0_14> : 40: r1 += r3 41: r3 = 0 42: r4 = r1 43: r4 += 40 44: if r4>r2 goto +1<LBB0_13> 45: r3 = *(u8 *)(r1 + 6) 0000000000000170<LBB0_13> : 46: *(u32 *)(r10 - 4) = r3 47: goto +2<LBB0_18> 0000000000000180<LBB0_17> : 48: r1 = 0 49: *(u32 *)(r10 - 4) = r1 0000000000000190<LBB0_18> : 50: r2 = r10 51: r2 += -4 52: r1 = 0 ll 54: call 1 55: if r0 == 0 goto +3<LBB0_20> 56: r1 = *(u64 *)(r0 + 0) 57: r1 += 1 58: *(u64 *)(r0 + 0) = r1 00000000000001d8<LBB0_20> : 59: r0 = 1 60: exit The instruction-level code in the above example input is compiled from the following eBPF source code: struct { __uint(type, BPF_MAP_TYPE_PERCPU_ARRAY); __type(key, u32); __type(value, long); __uint(max_entries, 256); } rxcnt SEC(".maps"); static int parse_ipv4(void *data, u64 nh_off, void *data_end) { struct iphdr *iph = data + nh_off; if (iph + 1>data_end) return 0; return iph->protocol; } static int parse_ipv6(void *data, u64 nh_off, void *data_end) { struct ipv6hdr *ip6h = data + nh_off; if (ip6h + 1>data_end) return 0; return ip6h->nexthdr; } SEC("xdp1") int xdp_prog1(struct xdp_md *ctx) { void *data_end = (void *)(long)ctx->data_end; void *data = (void *)(long)ctx->data; struct ethhdr *eth = data; int rc = XDP_DROP; long *value; u16 h_proto; u64 nh_off; u32 ipproto; nh_off = sizeof(*eth); if (data + nh_off>data_end) return rc; h_proto = eth->h_proto; / * Handle VLAN tagged packet * / if (h_proto == htons(ETH_P_8021Q) || h_proto == htons(ETH_P_8021AD)) { struct vlan_hdr *vhdr; vhdr = data + nh_off; nh_off += sizeof(struct vlan_hdr); if (data + nh_off>data_end) return rc; h_proto = vhdr->h_vlan_encapsulated_proto; } / * Handle double VLAN tagged packet * / if (h_proto == htons(ETH_P_8021Q) || h_proto == htons(ETH_P_8021AD)) { struct vlan_hdr *vhdr; vhdr = data + nh_off; nh_off += sizeof(struct vlan_hdr); if (data + nh_off>data_end) return rc; h_proto = vhdr->h_vlan_encapsulated_proto; } if (h_proto == htons(ETH_P_IP)) ipproto = parse_ipv4(data, nh_off, data_end); else if (h_proto == htons(ETH_P_IPV6)) ipproto = parse_ipv6(data, nh_off, data_end); else ipproto = 0; value = bpf_map_lookup_elem(&rxcnt,&ipproto); if (value) *value += 1; return rc; } char _license[] SEC("license") = "GPL"; Reference Figure 1 Initialization step S1 initializes the control flow graph, active variables, and register value ranges. That is, initialization step S1 includes control flow graph construction step S11, active variable determination step S12, and register value range determination step S13. Active variable determination step S12 and register value range determination step S13 depend on control flow graph construction step S11. Therefore, active variable determination step S12 and register value range determination step S13 must be performed after control flow graph construction step S11.

[0024] The control flow graph construction step S11 constructs a control flow graph for the instruction-level code to be optimized. A control flow graph is a directed graph with basic blocks as nodes and jumps between basic blocks as edges. A basic block is an instruction sequence that is entered only at the first instruction. The basic concepts and construction methods of control flow graphs and basic blocks are familiar to those skilled in the art and will not be elaborated upon in this specification.

[0025] Taking the instruction-level code input in the above example as an example, the control flow graph constructed is as follows Figure 3 shown. Figure 3 In the figure, the numbers in the circles represent basic blocks 1 to 10. The instruction sequences contained in each basic block are as follows: Basic block 1, the instruction sequence is: instructions 0 to 11; Basic block 2, the instruction sequence is: instructions 12 to 16; Basic block 3, the instruction sequence is: instructions 17 to 20; Basic block 4, the instruction sequence is: instructions 21 to 29; Basic block 5, the instruction sequence is: instructions 30 to 39; Basic block 6, the instruction sequence is: instructions 40 to 45; Basic block 7, the instruction sequence is: instructions 46 to 47; Basic block 8, the instruction sequence is: instructions 48 to 49; Basic block 9, the instruction sequence is: instructions 50 to 58; Basic block 10, the instruction sequence is: instructions 59 to 60.

[0026] In the above instructions 0 to 60, 0 to 60 are instruction numbers.

[0027] Active variable determination step S12, traverses each basic block according to the control flow graph, finds the variable assignment instructions and forward and backward reference relationships in the instruction sequence by traversing the basic blocks, and then determines the active variables of each instruction based on the variable assignment instructions and forward and backward reference relationships. The variables here refer to register quantities and memory segment quantities. Register quantity refers to the value stored in the register, and memory segment quantity refers to the value stored in the memory segment. For example, in the instruction-level code instruction 0 of the above example, that is, r2 = *(u32 *)(r1 + 4), r1 and r2 are represented as registers, and r1 and r2 are register quantities. (u32 *)(r1 + 4) represents a 32-bit memory segment with a memory address of (r1 + 4), and *(u32 *)(r1 + 4) represents the memory segment quantity of an unsigned 32-bit integer with a memory address of (r1 + 4). Active variables refer to the registers and memory segments that are referenced but not assigned in subsequent instructions. Active variables of instructions refer to the registers and memory segments that are referenced but not assigned in subsequent instructions. Active variables of basic blocks refer to the registers and memory segments that are referenced but not assigned in subsequent basic blocks.

[0028] The assignments are represented by the "=" symbol in the instruction-level code of the above example. For example, instruction 0 in the instruction-level code of the above example assigns a value to register r2, and instruction 58 assigns a value to the memory segment *(u64 *)(r0 + 0). Those skilled in the art will appreciate that in other instruction-level codes, assignments to memory segment quantities may also be represented by the STORE instruction, where STORE indicates storage into memory.

[0029] The active variables here refer to the concept of variable activity in the present invention. Variable activity is related to the life cycle of the variable value. After the variable is assigned a value, the life cycle of the original variable value ends. However, active variables mean that the variable value is still in its life cycle. In the instruction-level code of the above example: From the instruction perspective, for instruction 0, register r1 is referenced in the subsequent instruction 1, and register r2 is referenced in the subsequent instruction 4. Therefore, registers r1 and r2 are both active. However, register r3 is inactive because it is assigned a value in the subsequent instruction 2. There is no reference to r3 between instructions 0 and 2. For instruction 2, register r3 is active because it is referenced in the subsequent instruction 3.

[0030] From the perspective of basic blocks, for basic block 1, register r5 is inactive because it is assigned in instruction 17 in the subsequent basic block 3, and basic blocks 1 and 2 do not reference register r5. Although register r3 is assigned by instruction 12 in the subsequent basic block 2, it is referenced in basic block 4 without being assigned. Therefore, register r3 is active.

[0031] The activity of the variables determined in step S12 is based on the instruction perspective. To facilitate processing, this embodiment first determines the activity from the perspective of the basic block, and then determines the variable activity of each instruction within the basic block based on the basic block activity. The specific implementation steps are as follows: Step S121: Initialize the corresponding BR_U(i), BM_U(i), BR_A(i), BM_A(i), BR_I(i), BM_I(i), BR_O(i) and BM_O(i) for each basic block by traversing the basic block instruction sequence and the variables contained in the instructions; where BR_U(i) represents the set of register quantities referenced in basic block i, BM_U(i) represents the set of memory segments referenced in basic block i, and BR_A(i) represents the set of values assigned in basic block i. Register quantity set, BM_A(i) represents the set of memory segments assigned in basic block i, BR_I(i) represents the set of active register quantities at the entry of basic block i, BM_I(i) represents the set of active memory segments at the entry of basic block i, BR_O(i) represents the set of active register quantities at the exit of basic block i, and BM_O(i) represents the set of active memory segments at the exit of basic block i. During initialization, the sets BR_I(i), BM_I(i), BR_O(i) and BM_O(i) are empty. Step S122: Traverse the basic blocks according to the control flow graph, and calculate the traversed basic blocks according to the following set operation formula: BR_O(i)=⋃s∈next(i) BR_I(s); BM_O(i)=⋃s∈next(i) BM_I(s); Then calculate according to the following set operation formula: BR_I(i) = BR_U(i)⋃(BR_O(i)-BR_A(i)); BM_I(i) = BM_U(i)⋃(BM_O(i)-BM_A(i)); Where i represents the basic block currently being traversed, and next(i) represents the set of basic blocks following basic block i. Step S123: Repeat step S122 until the active register quantity set BR_I(i) at the entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit of each basic block no longer change; Step S124: According to the limitations of the active register quantity set BR_I(i) at the basic block entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit and the variables contained in each instruction in the basic block, the active register quantity set and the active memory segment quantity set corresponding to each instruction of each basic block are obtained in an iterative manner.

[0032] In the above steps, step S122 and step S123 are a cyclic iterative process.

[0033] The processing of step S124 is the same as steps S121 to S123, and specifically includes the following steps: Step S1241: Initialize the corresponding IR_U(j), IM_U(j), IR_A(j), IM_A(j), IR_I(j), IM_I(j), IR_O(j) and IM_O(j) for each instruction by traversing the basic block instruction sequence and the variables contained in the instruction; wherein, IR_U(j) represents the set of register quantities referenced in instruction j, IM_U(j) represents the set of memory segment quantities referenced in instruction j, IR_A(j) represents the set of register quantities assigned in instruction j, and IM_A(j) represents the set of memory segment quantities assigned in instruction j. , IR_I(j) represents the set of active register quantities input by instruction j, IM_I(j) represents the set of active memory segments input by instruction j, IR_O(j) represents the set of active register quantities output by instruction j, and IM_O(j) represents the set of active memory segments output by instruction j; during initialization, the sets IR_I(j), IM_I(j), IR_O(j) and IM_O(j) are copied from the set of active register quantities at the basic block entry, the set of active memory segments at the basic block entry, the set of active register quantities at the basic block exit, and the set of active memory segments at the basic block exit, respectively; Step S1242: Traverse the instructions in the basic block and calculate the traversed instructions according to the following set operation formula: IR_O(j)= IR_I(next(j)); IM_O(j)= IM_I(next(j)); Then calculate according to the following set operation formula: IR_I(j) = IR_U(j)⋃(IR_O(j)-IR_A(j)); IM_I(j) = IM_U(j)⋃(IM_O(j)-IM_A(j)); Among them, j represents the current traversed instruction, and next(j) represents the subsequent instruction of instruction j; Step S1243: Repeat step S1242 until the instruction sets IR_I(j), IM_I(j), IR_O(j), and IM_O(j) no longer change.

[0034] In this embodiment, the active variables of each instruction ultimately come from the sets IR_O(j) and IM_O(j), that is, the register quantity in the set IR_O(j) is used as the active register quantity of the instruction, and the memory segment quantity in the set IM_O(j) is used as the active memory segment quantity of the instruction.

[0035] In step S13, the register quantity value range is determined. Each basic block is traversed according to the control flow graph, and the instruction sequence of the traversed basic block is simulated and executed based on the path to determine the value range of each register quantity before and after the execution of each instruction. The value range of the register quantity can be represented as a set of intervals. Each interval in the set of intervals represents the value allowed for the register quantity. Since the infinity of the interval cannot be represented by a specific numerical value, the interval boundary is divided into open intervals and closed intervals. Therefore, in this embodiment, the interval information used to represent the upper and lower limits of the interval, in addition to two numerical information used to represent the upper and lower limits, also contains two tag information. The tag information is used to indicate whether the upper or lower limit of the interval is an open interval and whether the value is infinite. Initially, the interval set used to represent the value range of the register quantity is empty. The empty interval set indicates that the value range of the corresponding register quantity is uncertain. When traversing the instruction for simulation execution, if the value range of the register quantity is uncertain, the corresponding arithmetic calculation instruction can be exempted from simulation execution. The determination of the register quantity value range comes from two instructions: The first type of instruction is the conditional jump instruction. The two branch paths after the conditional jump instruction can differentiate the corresponding register quantity into two corresponding branch path value ranges based on the conditional judgment. For example, in the instruction-level code of the above example, the conditional jump instruction in instruction 9 makes the register quantity r4 have a value range of {[129,129]} at the entrance of basic block 2, and a value range of {(-∞,129),(129,∞)} in instruction 10; the conditional jump instruction in instruction 11 makes the register quantity r4 have a value range of {[43144,43144]} at the entrance of basic block 2, and a value range of {[43144,43144]} in basic block 11. The entry of basic block 3 has a value range of {(-∞,129), (129,43144), (43144,∞)}; after the two are combined, at the entry of basic block 2, the register r4 has a value range of {[129,129], [43144,43144]}, that is, in instructions 12 to 15, the register r4 has a value range of {[129,129], [43144,43144]}.

[0036] The second type of instruction is an assignment instruction that performs arithmetic calculations with a known value range. For example, in the instruction-level code in the example above, the assignment instruction in instruction 10 causes register r3 to have a value range of {[14, 14]} after the instruction is executed. Another example is that at the entry of basic block 4, register r3 has a value range of {[14, 14], [18, 18]}. After the assignment instruction in instruction 21 is executed, register r5 has a value range of {[14, 14], [18, 18]}. After the assignment instruction in instruction 22 is executed, register r5 has a value range of {[18, 18], [22, 22]}.

[0037] It should be pointed out that there may be no dependency relationship between the active variable determination step S12 and the register quantity value range determination step S13. Therefore, there is no order relationship between the active variable determination step S12 and the register quantity value range determination step S13. That is, the active variable determination step S12 can be executed first and then the register quantity value range determination step S13, or the register quantity value range determination step S13 can be executed first and then the active variable determination step S12.

[0038] Considering that inactive registers are essentially at the end of their lifecycle, calculating their value ranges is meaningless. Therefore, in this embodiment, all registers processed in register value range determination step S13 are active registers. Therefore, register value range determination step S13 is dependent on active variable determination step S12. That is, active variable determination step S12 must be performed before register value range determination step S13.

[0039] It should also be noted that the determination of the value range in the register value range determination step S13 is limited to the register value, and the memory segment value is not processed due to too many uncertain factors.

[0040] The fragment optimization step S2 includes an instruction fragment extraction step S21 , a fragment template matching step S22 , and a fragment equivalence verification step S23 .

[0041] Instruction fragment extraction step S21, the variable assignment instruction is found from the instruction sequence of the basic block, and then the continuous and associated instructions of the variable assignment instruction are found in the basic block according to the variable assignment instruction. Then the variable assignment instruction and its continuous and associated instructions constitute the instruction fragment to be optimized. The continuous and associated instructions here refer to the instructions related to the assignment result of the variable assignment instruction. The first requirement here is the variable assignment instruction. Since it is related to the assignment result, the continuous and associated instructions must be the predecessor instructions of the variable assignment instruction. For example, in the instruction-level code of the above example: For instructions 4, 9, and 11, since they are not assignment instructions, they cannot form the instruction fragment to be optimized with other instructions; For instruction 0, since there is no associated instruction, it cannot form an instruction fragment to be optimized with other instructions; For instruction 1, since there is no associated instruction, it cannot form an instruction fragment to be optimized with other instructions; For instruction 2, the register value r1 in instruction 2 depends on instruction 1, and instruction 1 and instruction 2 are continuous. Therefore, instruction 2 and its associated instruction 1 can form the instruction fragment to be optimized; For instruction 3, the register quantity r3 in instruction 3 depends on instruction 2, instruction 2 depends on instruction 1, and instruction 3 is continuous with instruction 2 and instruction 1. Therefore, instruction 3 and its associated instructions 2 and instruction 1 can form the instruction fragment to be optimized.

[0042] In addition, when a variable is a memory segment, if the memory address of the variable is adjacent to the memory segment and can form a larger integer with the variable, the continuous memory segment can be regarded as the same integer. Therefore, the instructions before and after the variable can be regarded as a whole and related. For example, in the instruction-level code of the above example: For instruction 5, the register value r1 depends on instruction 1, but instruction 1 and instruction 5 are not continuous, so they cannot form the instruction skewness to be optimized with other preceding instructions; However, for instruction 6, the register value r1 depends on instruction 1, but instruction 1 and instruction 6 are not continuous. Although they cannot form an instruction fragment to be optimized with instruction 1, since the address (r1+12) in instruction 5 and the address (r1+13) in instruction 6 are continuous, instruction 5 can be regarded as an instruction associated with instruction 6, so instructions 6 and 5 can form an instruction fragment to be optimized.

[0043] According to the above definition of the instruction fragment to be optimized, the following example of the instruction fragment to be optimized can be found in basic block 1: Fragment 1: Instructions 1 and 2; Fragment 2: Instructions 1, 2, 3; Fragment 3: Instructions 5 and 6; Fragment 4: Instructions 5, 6, and 7; Snippet 5: Instructions 5, 6, 7, 8.

[0044] In the fragment template matching step, the instruction fragment to be optimized is template-matched with each optimization template in the optimization template library. If the instruction fragment template before optimization of the optimization template in the optimization template library matches the instruction fragment to be optimized, the instruction fragment to be optimized is optimized according to the instruction fragment template after optimization of the optimization template to obtain the corresponding optimized instruction fragment. The optimization templates in the optimization template library here are pre-set, and the optimization templates include the instruction template before optimization and the instruction template after optimization. For example, an optimization template in the optimization template library is defined as follows: Instruction template before optimization: R2 = *(u8 *)(R1 + n) R3 = *(u8 *)(R1 + n + 1) R3<<= 8 R3 |= r2 Optimized instruction template: R3 = *(u16 *)(R1 + n) Among them, R1, R2, and R3 are register quantity templates, and n is a numerical template.

[0045] According to the definition of the optimization template, in the above example of the instruction fragment to be optimized, through template matching, it can be found that fragment 5 matches the above pre-optimization instruction template. The specific fragment 5 is as follows: 5: r3 = *(u8 *)(r1 + 12) 6: r4 = *(u8 *)(r1 + 13) 7: r4<<= 8 8: r4 |= r3 When the register quantity templates R1, R2, and R3 in the pre-optimization instruction template are replaced with register quantities r1, r3, and r4, respectively, and the value template is replaced with 12, the above snippet 5 is essentially the same as the pre-optimization instruction template. Therefore, based on the replacement of the register quantity templates, the optimized instruction snippet can be obtained: r4 = *(u16 *)(r1 + 12) Compared to the 4 instructions before optimization, only one instruction remains after optimization, thereby reducing the number of instructions. In other words, the optimization of instructions in the present invention is based on the optimization of the number of instructions.

[0046] The fragment equivalence verification step determines the register quantity input range of the instruction fragment to be optimized based on the value range of each register quantity before each instruction is executed and the instruction fragment to be optimized. Then, the instruction fragment before optimization and the instruction fragment after optimization are used as SMT constraints. The SMT constraints of the register quantity input range, the SMT constraints of the same input variable values of the instruction fragment before optimization and the instruction fragment after optimization, and the SMT constraints of different active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization are combined to construct a fragment equivalence verification SMT constraint. Then, the constructed fragment equivalence verification SMT constraint is input into the SMT solver for solution. According to the solution result of the SMT solver, it is verified whether the optimized instruction fragment is equivalent to the pre-optimized instruction fragment, thereby obtaining an equivalence verification pair consisting of the verified equivalent post-optimization instruction fragment and the pre-optimization instruction fragment. The construction formula of the above-mentioned fragment equivalence verification SMT constraint is expressed as follows: E≡S_origin∧S_candidate∧ (input_reg_origin∈[min_value,max_value])∧ (input_origin=input_candidate)∧ (output_origin≠output_candidate )(output∈live); in, E represents the fragment equivalence verification SMT constraint, S_origin represents the SMT constraint item constructed by the instruction fragment itself before optimization. S_candidate represents the SMT constraint item constructed by the optimized instruction fragment itself. (input_reg_origin∈[min_value,max_value]) represents the SMT constraint item constructed by the input range of each register. (input_origin=input_candidate) indicates the SMT constraint item constructed by the same input variable value of the instruction fragment before optimization and the instruction fragment after optimization. (output_origin≠output_candidate )(output∈live) indicates that the SMT constraint item is constructed when the active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization are different.

[0047] Taking the above instruction snippets before and after optimization as examples, the instruction snippet before optimization is as follows: 5: r3 = *(u8 *)(r1 + 12) 6: r4 = *(u8 *)(r1 + 13) 7: r4<<= 8 8: r4 |= r3 The optimized instruction fragment is as follows: 5:r4 = *(u16 *)(r1 + 12) In the pre-optimization instruction snippet, the active register count for instruction 5 is {r1, r2, r10}, and the active register count for instruction 8 is {r1, r2, r4, r10}. Considering that the pre-optimization instruction snippet does not involve r2 and r10, the active register count for instruction 5 is {r1}, and the active register count for instruction 8 is {r1, r4}. The input range of active register r1 is {(0, ∞)}.

[0048] Therefore, the SMT constraints constructed by the instruction fragment itself before optimization are: S_origin≡ rs31=Ms(rs11+12,1)∧ rs41=Ms(rs11+13,1)∧ rs42=rs41<<8∧ rs43=rs42|rs31; The SMT constraints constructed by the optimized instruction fragment itself: S_candidate≡ rd41=Md(rd11+12,2); SMT constraints constructed by the input range of each register: (input_reg_origin∈[min_value,max_value])≡rs11>0; SMT constraint items constructed when the input variable values of the instruction fragment before and after optimization are the same: (input_origin=input_candidate)≡Ms=Md∧rs11=rd11; The SMT constraints constructed by the different active variable outputs of the instruction snippet before and after optimization are: (output_origin≠output_candidate )(output∈live)≡rs11≠rd11∨rs43≠rd41; Since s11≠rd11 in the above SMT constraint conflicts with the previous rs11=rd11, the SMT constraint constructed by the different active variable outputs of the instruction fragment before and after optimization can be simplified to: (output_origin≠output_candidate )(output∈live)≡rs43≠rd41; Therefore, the fragment equivalence verification SMT constraint finally constructed by combining the above SMT constraints is: E≡rs31=Ms(rs11+12,1)∧rs41=Ms(rs11+13,1)∧rs42=rs41<<8∧rs43=rs 42|rs31∧rd41=Md(rd11+12,2)∧rs11>0∧Ms=Md∧rs11=rd11∧rs43≠rd41; In the above formula, rs11, rs31, rs41, rs42, rs43, rd11, and rd41 are variables constructed according to the register quantities r1, r3, and r4 in different instructions; Ms and Md are memory space variables constructed according to the instructions, Ms(rs11+12,1) and Ms(rs11+13,1) mean taking one byte at the corresponding memory space addresses rs11+12 and rs11+13, and Md(rd11+12,2) means taking two bytes at the corresponding memory space address rd11+12.

[0049] In addition, among the instruction fragments to be optimized found in basic block 1, there is an instruction inclusion relationship between the fragments. For example, instructions 1, 2, and 3 of fragment 2 include instructions 1 and 2 of fragment 1; instructions 5, 6, and 7 of fragment 4 include instructions 5 and 6 of fragment 3; instructions 5, 6, 7, and 8 of fragment 5 include fragment 4 and also include fragment 3. For this situation, as long as the fragment optimization is successful and passes the equivalence verification, the corresponding fragments with inclusion relationships are directly discarded, thereby reducing the amount of calculation. In addition, since the instruction fragments to be optimized found are continuous instructions, there is no intersection but not inclusion relationship between the fragments. In other words, the intersection between the fragments necessarily means that there is an inclusion relationship between the fragments.

[0050] Instruction reorganization step S3, based on the equivalence verification pairs obtained for the basic block, the basic block instruction sequence is optimized and reorganized by replacing the corresponding pre-optimized instruction fragments with the optimized instruction fragments that have been verified to be equivalent in the equivalence verification pairs. This step is a simple replacement of instruction fragments. For example, after finding the equivalence verification pairs in the example above, the original instruction code is directly replaced in basic block 1 to obtain the following instruction sequence for basic block 1: 0: r2 = *(u32 *)(r1 + 4) 1: r1 = *(u32 *)(r1 + 0) 2: r3 = r1 3: r3 += 14 4: if r3>r2 goto +54<LBB0_20> 5: r4 = *(u16 *)(r1 + 12) 6: NULL 7: NULL 8: NULL 9: if r4 == 129 goto +2<LBB0_3> 10: r3 = 14 11: if r4 != 43144 goto +5<LBB0_5> In another preferred embodiment, the above NULL instruction can be deleted to obtain a compressed instruction sequence: 0: r2 = *(u32 *)(r1 + 4) 1: r1 = *(u32 *)(r1 + 0) 2: r3 = r1 3: r3 += 14 4: if r3>r2 goto +54<LBB0_20> 5: r4 = *(u16 *)(r1 + 12) 6: if r4 == 129 goto +2<LBB0_3> 7: r3 = 14 8: if r4 != 43144 goto +5<LBB0_5> In addition, the fragment optimization step S2 is a processing process for a certain basic block, while the instruction reorganization step S3 uses the equivalence verification pairs output by the fragment optimization step S2 as input. Therefore, when this embodiment is specifically implemented, the basic blocks are first traversed, and the fragment optimization step S2 is executed one by one on the traversed basic blocks to obtain an equivalence verification pair set composed of each equivalence verification pair of each basic block, and then the equivalence verification pairs in the equivalence verification pair set are processed one by one through the instruction reorganization step S3. In another optional implementation method, when traversing the basic blocks, the fragment optimization step S2 is executed on the traversed basic blocks to obtain an equivalence verification pair set composed of each equivalence verification pair of the traversed basic blocks, and then the equivalence verification pairs in the equivalence verification pair set are processed one by one in the basic block of the instruction reorganization step S3, and after the processing is completed, the next basic block is traversed.

[0051] In addition, it should be pointed out that the instruction-level code optimization device based on template matching referred to above in the present invention is a virtual device implemented by executing computer program instructions. The modules it contains correspond one-to-one to the steps in the instruction-level code optimization method based on template matching, and no further elaboration is needed.

Claims

1. An instruction-level code optimization method based on template matching, characterized in that: It includes an initialization step, a fragment optimization step, and an instruction reorganization step; The initialization step includes: A control flow graph construction step is to construct a control flow graph for the instruction-level code to be optimized; the control flow graph is a directed graph with basic blocks as nodes and jumps between basic blocks as edges; the basic block is an instruction sequence that is only entered at the first instruction; The active variable determination step involves traversing each basic block according to the control flow graph, finding variable assignment instructions and forward and backward reference relationships in the instruction sequence through the traversal of the basic block, and then determining the active variables of each instruction based on the variable assignment instructions and forward and backward reference relationships; the variables are register quantities and memory segment quantities; the active variables of the instruction are register quantities and memory segment quantities that are referenced but not assigned in subsequent instructions; The register value range determination step is to traverse each basic block according to the control flow graph, and to determine the value range of each register value before and after the execution of each instruction by performing path-based simulation execution on the instruction sequence of the traversed basic block; The fragment optimization steps include: Instruction fragment extraction step, find the variable assignment instruction from the instruction sequence of the basic block, then find the continuous and associated instructions of the variable assignment instruction in the basic block based on the variable assignment instruction, and then the variable assignment instruction and its continuous and associated instructions constitute the instruction fragment to be optimized; The fragment template matching step is to perform template matching on the instruction fragment to be optimized and each optimization template in the optimization template library. If the instruction fragment template before optimization of the optimization template in the optimization template library matches the instruction fragment to be optimized, the instruction fragment to be optimized is optimized according to the instruction fragment template after optimization of the optimization template to obtain the corresponding optimized instruction fragment; The fragment equivalence verification step determines the register quantity input range of the instruction fragment to be optimized based on the value range of each register quantity before each instruction is executed and the instruction fragment to be optimized, and then uses the instruction fragment before optimization and the instruction fragment after optimization themselves as SMT constraint items, and combines the SMT constraint items of the register quantity input range, the SMT constraint items of the same input variable values of the instruction fragment before optimization and the instruction fragment after optimization, and the SMT constraint items of different active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization to construct a fragment equivalence verification SMT constraint, and then inputs the constructed fragment equivalence verification SMT constraint into the SMT solver for solution, and verifies whether the optimized instruction fragment is equivalent to the pre-optimization instruction fragment based on the solution result of the SMT solver, thereby obtaining an equivalence verification pair consisting of the verified equivalent post-optimization instruction fragment and the pre-optimization instruction fragment; In the instruction reorganization step, based on the equivalence verification pairs obtained from the basic block, the basic block instruction sequence is optimized and reorganized by replacing the corresponding pre-optimization instruction fragments with the optimized instruction fragments that are verified to be equivalent in the equivalence verification pairs.

2. The instruction-level code optimization method according to claim 1, wherein: In the instruction fragment extraction step, The continuous and associated instructions of the variable assignment instructions include memory segment quantity assignment instructions whose memory addresses are adjacent to the variable and can form a larger integer with the variable when the variable is a memory segment quantity.

3. The instruction-level code optimization method according to claim 1, wherein: The active variable determination step includes the following steps: Step S121: Initialize the corresponding BR_U(i), BM_U(i), BR_A(i), BM_A(i), BR_I(i), BM_I(i), BR_O(i) and BM_O(i) for each basic block by traversing the basic block instruction sequence and the variables contained in the instructions; wherein, BR_U(i) represents the set of registers referenced in basic block i. BM_U(i) represents the set of memory segments referenced in basic block i. BR_A(i) represents the set of assigned registers in basic block i. BM_A(i) represents the set of memory segments assigned in basic block i. BR_I(i) represents the set of active registers at the entry of basic block i, BM_I(i) represents the set of active memory segments at the entry of basic block i. BR_O(i) represents the set of active registers at the exit of basic block i, BM_O(i) represents the set of active memory segments at the exit of basic block i; Initially, the sets BR_I(i), BM_I(i), BR_O(i) and BM_O(i) are empty; Step S122: Traverse the basic blocks according to the control flow graph, and calculate the traversed basic blocks according to the following set operation formula: BR_O(i)=⋃ s∈next(i) BR_I(s); BM_O(i)=⋃ s∈next(i) BM_I(s); Then calculate according to the following set operation formula: BR_I(i) = BR_U(i)⋃(BR_O(i)-BR_A(i)); BM_I(i) = BM_U(i)⋃(BM_O(i)-BM_A(i)); Where i represents the basic block currently being traversed, and next(i) represents the set of basic blocks following basic block i. Step S123: Repeat step S122 until the active register quantity set BR_I(i) at the entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit of each basic block no longer change; Step S124: According to the limitations of the active register quantity set BR_I(i) at the basic block entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit and the variables contained in each instruction in the basic block, the active register quantity set and the active memory segment quantity set corresponding to each instruction of each basic block are obtained in an iterative manner.

4. The instruction-level code optimization method according to claim 1, wherein: The construction formula of the fragment equivalence verification SMT constraint is expressed as: E≡S_origin∧S_candidate∧ (input_reg_origin∈[min_value,max_value])∧ (input_origin=input_candidate )∧ (output_origin≠output_candidate )(output∈live); in, E represents the fragment equivalence verification SMT constraint, S_origin represents the SMT constraint item constructed by the instruction fragment itself before optimization. S_candidate represents the SMT constraint item constructed by the optimized instruction fragment itself; (input_reg_origin∈[min_value,max_value]) represents the SMT constraint item constructed by the input range of each register. (input_origin=input_candidate ) indicates the SMT constraint item constructed when the input variable values of the instruction fragment before optimization and the instruction fragment after optimization are the same. (output_origin≠output_candidate )(output∈live) indicates that the SMT constraint item is constructed when the active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization are different.

5. An instruction-level code optimization device based on template matching, characterized in that: Includes initialization module, fragment optimization module and instruction reorganization module; The initialization module includes: A control flow graph construction module is used to: construct a control flow graph for the instruction-level code to be optimized; the control flow graph is a directed graph with basic blocks as nodes and jumps between basic blocks as edges; the basic block is an instruction sequence that is only entered at the first instruction; An active variable determination module is configured to: traverse each basic block according to the control flow graph, find variable assignment instructions and forward and backward reference relationships in the instruction sequence by traversing the basic blocks, and then determine the active variables of each instruction based on the variable assignment instructions and forward and backward reference relationships; the variables are register quantities and memory segment quantities; the active variables of an instruction are register quantities and memory segment quantities that are referenced but not assigned in subsequent instructions; A register value range determination module is used to: traverse each basic block according to the control flow graph, and determine the value range of each register value before and after the execution of each instruction by performing path-based simulation execution on the instruction sequence of the traversed basic block; The fragment optimization module includes: An instruction fragment extraction module is used to: find the variable assignment instruction from the instruction sequence of the basic block, then find the continuous and associated instructions of the variable assignment instruction in the basic block based on the variable assignment instruction, and then the variable assignment instruction and its continuous and associated instructions form the instruction fragment to be optimized; The fragment template matching module is used to: perform template matching between the instruction fragment to be optimized and each optimization template in the optimization template library. If the instruction fragment template before optimization of the optimization template in the optimization template library matches the instruction fragment to be optimized, the instruction fragment to be optimized is optimized according to the instruction fragment template after optimization of the optimization template to obtain the corresponding optimized instruction fragment; The fragment equivalence verification module determines the register quantity input range of the instruction fragment to be optimized based on the value range of each register quantity before the execution of each instruction and the instruction fragment to be optimized, and then uses the instruction fragment before optimization and the instruction fragment after optimization themselves as SMT constraint items, and combines the SMT constraint items of the register quantity input range, the SMT constraint items of the same input variable values of the instruction fragment before optimization and the instruction fragment after optimization, and the SMT constraint items of different active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization to construct a fragment equivalence verification SMT constraint, and then inputs the constructed fragment equivalence verification SMT constraint into the SMT solver for solution, and verifies whether the optimized instruction fragment is equivalent to the pre-optimization instruction fragment based on the solution result of the SMT solver, thereby obtaining an equivalence verification pair consisting of the verified equivalent post-optimization instruction fragment and the pre-optimization instruction fragment; The instruction reorganization module is used to optimize and reorganize the basic block instruction sequence according to each equivalence verification pair obtained from the basic block, by replacing the corresponding pre-optimization instruction fragments with the optimized instruction fragments in the equivalence verification pair that have been verified to be equivalent.

6. The instruction-level code optimization device according to claim 5, characterized in that: In the instruction fragment extraction module, The continuous and associated instructions of the variable assignment instructions include memory segment quantity assignment instructions whose memory addresses are adjacent to the variable and can form a larger integer with the variable when the variable is a memory segment quantity.

7. The instruction-level code optimization device according to claim 5, characterized in that: The active variable determination module includes the following modules: Module M121 is used to initialize the corresponding BR_U(i), BM_U(i), BR_A(i), BM_A(i), BR_I(i), BM_I(i), BR_O(i) and BM_O(i) for each basic block by traversing the basic block instruction sequence and the variables contained in the instructions; wherein, BR_U(i) represents the set of registers referenced in basic block i. BM_U(i) represents the set of memory segments referenced in basic block i. BR_A(i) represents the set of assigned registers in basic block i. BM_A(i) represents the set of memory segments assigned in basic block i. BR_I(i) represents the set of active registers at the entry of basic block i, BM_I(i) represents the set of active memory segments at the entry of basic block i. BR_O(i) represents the set of active registers at the exit of basic block i, BM_O(i) represents the set of active memory segments at the exit of basic block i; Initially, the sets BR_I(i), BM_I(i), BR_O(i) and BM_O(i) are empty; Module M122 is used to traverse the basic blocks according to the control flow graph, and calculate the traversed basic blocks according to the following set operation formula: BR_O(i)=⋃ s∈next(i) BR_I(s); BM_O(i)=⋃ s∈next(i) BM_I(s); Then calculate according to the following set operation formula: BR_I(i) = BR_U(i)⋃(BR_O(i)-BR_A(i)); BM_I(i) = BM_U(i)⋃(BM_O(i)-BM_A(i)); Where i represents the basic block currently being traversed, and next(i) represents the set of basic blocks following basic block i. Module S123 is used to repeat module S122 until the active register quantity set BR_I(i) at the entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit of each basic block no longer change; Module S124 is used to iteratively obtain the active register quantity set and active memory segment quantity set corresponding to each instruction of each basic block according to the restrictions of the active register quantity set BR_I(i) at the basic block entry, the active memory segment quantity set BM_I(i) at the entry, the active register quantity set BR_O(i) at the exit, and the active memory segment quantity set BM_O(i) at the exit, and the variables contained in each instruction in the basic block.

8. The instruction-level code optimization device according to claim 5, wherein: The construction formula of the fragment equivalence verification SMT constraint is expressed as: E≡S_origin∧S_candidate∧ (input_reg_origin∈[min_value,max_value])∧ (input_origin=input_candidate )∧ (output_origin≠output_candidate )(output∈live); in, E represents the fragment equivalence verification SMT constraint, S_origin represents the SMT constraint item constructed by the instruction fragment itself before optimization. S_candidate represents the SMT constraint item constructed by the optimized instruction fragment itself; (input_reg_origin∈[min_value,max_value]) represents the SMT constraint item constructed by the input range of each register. (input_origin=input_candidate ) indicates the SMT constraint item constructed when the input variable values of the instruction fragment before optimization and the instruction fragment after optimization are the same. (output_origin≠output_candidate )(output∈live) indicates that the SMT constraint item is constructed when the active variable outputs of the instruction fragment before optimization and the instruction fragment after optimization are different.

9. A machine-readable medium storing a program instruction set, characterized in that: When the program instruction set stored in the medium is loaded and executed by a machine, the machine can implement the instruction-level code optimization method according to any one of claims 1 to 4.

10. An electronic device comprising a processor and a memory connected together, wherein the memory stores a program instruction set, and the processor is capable of loading and executing the program instruction set stored in the memory, characterized in that: When the program instruction set stored in the memory is loaded and executed by the processor, the device can implement the instruction-level code optimization method according to any one of claims 1 to 4.

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