Integrated circuit structure with direct backside source or drain contacts implemented by silicon germanium etch stops

Abstract

Integrated circuit structures having direct backside source or drain contacts implemented by silicon germanium etch stops are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fins and the second plurality of horizontally stacked nanowires or fins, the epitaxial source or drain structure over and electrically coupled to the corresponding conductive back contact, the conductive back contact extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

Description

Background Art

[0001] Over the past few decades, the scaling of features in integrated circuits has been a driving force behind the continued growth of the semiconductor industry. Scaling to smaller and smaller features has enabled an increase in the density of functional units within the limited chip area of ​​a semiconductor chip. For example, shrinking transistor size allows for the incorporation of an increasing number of memory or logic devices on a chip, thereby enabling the manufacture of products with increased capacity. However, the pursuit of greater capacity is not without its challenges. The need to optimize the performance of each device has become increasingly important.

[0002] Variability in conventional and currently known manufacturing processes may limit the possibility of further scaling them to the 10 nm node or sub-10 nm node range. Therefore, manufacturing functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into current manufacturing processes, or the introduction of new methods or the integration of new technologies in place of current manufacturing processes.

[0003] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-volume bulk silicon substrate infrastructure.

[0004] However, scaling multi-gate transistors is not without consequences. As the dimensions of these fundamental building blocks of microelectronic circuitry decrease, and as the sheer number of these building blocks that can be fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate them have become overwhelming. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1A-1G Angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure with direct backside source or drain contacts are illustrated, in accordance with an embodiment of the present disclosure.

[0006] Figure 2A Depicted are cross-sectional views representing various operations in a method of fabricating a nanowire and release layer stack including a bottom etch stop layer, in accordance with an embodiment of the present disclosure.

[0007] Figure 2B Depicted are cross-sectional views representing various operations in another method of fabricating a nanowire and release layer stack including a bottom etch stop layer, in accordance with another embodiment of the present disclosure.

[0008] Figure 3 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0009] Figure 4-9 Angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having differentiated backside source or drain contact accessible features are illustrated, in accordance with an embodiment of the present disclosure.

[0010] Figure 10A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0011] Figure 10B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0012] Figure 11A A plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0013] Figure 11B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0014] Figures 12A-12J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0015] Figure 13 A computing device according to one embodiment of the present disclosure is shown.

[0016] Figure 14 An interposer including one or more embodiments of the present disclosure is shown.

[0017] Figure 15 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or more features described herein, according to an embodiment of the present disclosure.

[0018] Figure 16 A cross-sectional view of a flip-chip mounted die is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Integrated circuit structures with direct backside source or drain contacts are described. In the following description, numerous specific details, such as specific integration and material schemes, are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0020] The following detailed description is merely illustrative in nature and is not intended to limit the present subject matter or the embodiments of the present application or the uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, no intention is to be bound by any expressed or implied theory presented in the preceding technical field, background technology, summary of the invention, or the following detailed description.

[0021] This description includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0022] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0023] The term "comprising" is open-ended. As used in the appended claims, the term does not exclude additional structures or operations.

[0024] "Configured to." Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to represent a structure by indicating that the unit or component includes structure to perform one or more tasks during operation. Thus, a unit or component may be said to be configured to perform a task even when the specified unit or component is not currently in operation (e.g., not turned on or active). Reciting a unit or circuit or component as "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, sixth paragraph, with respect to that unit or component.

[0025] "First," "second," etc. As used herein, these terms serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0026] "Coupled" - The following description refers to elements or nodes or features being "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.

[0027] In addition, certain terms may also be used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the accompanying drawings to which reference is made. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation or position, or both, of a portion of a component within a consistent but arbitrary reference frame, which is made clear by reference to the text describing the component in question and the associated drawings. Such terminology may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0028] "Inhibit" - As used herein, inhibit is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, motion, or condition, it can completely prevent the result, consequence, or future state. Additionally, "inhibit" can also mean reducing or lessening a consequence, property, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or condition, it need not completely prevent or eliminate the result or condition.

[0029] Embodiments described herein may relate to front-end-of-the-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all operations up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0030] The embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where the various devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. With modern IC processes, more than 10 metal layers may be added in the BEOL.

[0031] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to BEOL processing. Similarly, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to FEOL processing.

[0032] One or more embodiments relate to back side (BS) contacts with deep source or drain (SD) implemented using a silicon germanium (SiGe) etch stop (ES) layer. One or more embodiments relate to direct back side (BS) source drain contacts implemented with increased process margin using back side gate recesses. One or more embodiments described herein relate to full-all-around gate integrated circuit structures fabricated with direct back side source or drain contacts. It should be understood that references to nanowires herein may indicate nanowires or nanoribbons or nanosheets or forksheets unless otherwise stated. One or more embodiments described herein relate to fin-based integrated circuit structures fabricated with direct back side source or drain contacts.

[0033] To provide context, backside (BS) power delivery decouples power and signal wires, allowing for decongestion of the BEOL, further scaling standard cells, and reducing on-chip IR drop. Nano-metal vias or trenches running parallel to the standard cells are typically used to deliver power back to the front side of the transistor.

[0034] In accordance with one or more embodiments described herein, rather than delivering power from the back side to the front side via nanometal vias or trenches, direct power delivery is provided from the back side to the source region to provide improved scaling options both in terms of size and electrical. This can be achieved by directly patterning and etching back side (BS) vias to connect the back side power conductors directly to the source of the transistor. However, the proximity of the gate bottom and the source bottom may require very strict EPE control to avoid via shorting to the gate and may be a key limiting factor in achieving a direct source via connection. Additionally, non-uniformity in source / drain depth may result in unlanded back side contacts.

[0035] In an embodiment, a process flow and strategy are described to provide extended source / drain depth and backside gate recess to widen process margins, thereby enabling direct source connection from the backside.

[0036] To provide further context, previous approaches involved nanometal vias or trenches running parallel to the standard cell to deliver power to the source at the front side of the transistor. Specifically, deep trenches were etched after the spacer etch and before the SD epitaxy. The trenches were then filled with dummy metal, which was exposed during the BS process and replaced with contact metal. Drawbacks of this approach can include the nanometal vias or trenches consuming cell area footprint and increasing the standard cell area. Furthermore, the BS source contact formation via the front side process can increase process complexity.

[0037] In an embodiment, a process scheme for increasing the source / drain depth and backside gate etching is described. This increases the process margin and thus enables direct patterning of contact vias to the source of the transistor from the backside. Advantages for implementing the embodiments described herein may include simplifying the process flow and increasing the process margin to allow backside contact of the source / drain, thereby enabling direct BS power contact and delivery. Reducing the gate height (from the backside) can also reduce parasitic capacitance (performance benefit).

[0038] As an exemplary treatment scheme, Figures 1A-1G Angled cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure with direct backside source or drain contacts are shown in accordance with an embodiment of the present disclosure. It will be understood that the described and illustrated embodiments may also be applicable to fin structures in lieu of stacks of nanowires, nanoribbons, nanosheets, or prongs.

[0039] refer to Figure 1A , a starting structure 100 includes a stack of nanowires 106, such as a stack of silicon nanowires, which may be above a corresponding doped silicon structure 105. The doped silicon structure 105 is on an etch stop layer 103, such as a silicon germanium etch stop layer. The etch stop layer 103 is on a corresponding sub-fin structure 102, such as a silicon sub-fin structure, which may be within a trench isolation structure 104. A gate electrode 108 surrounds the nanowire 106, and the gate electrode 108 may be, for example, a metal gate electrode that may include a work function layer and a conductive fill. The gate electrode 108 is separated from the nanowire 106 by a gate dielectric layer, such as a high-k gate dielectric layer. A dielectric gate cap 114 may be included on the gate electrode, as depicted. Dielectric gate sidewall spacers, such as silicon nitride gate sidewall spacers, may be along the sides of the gate electrode 108. Inner portions of the gate sidewall spacers may also be included vertically between adjacent nanowires.

[0040] The starting structure 100 may also include an epitaxial source or drain structure 110, such as an epitaxial silicon or silicon germanium source or drain structure, at the end of the stack of nanowires 106. In the case of a silicon germanium source or drain structure, in one embodiment, the etch stop layer 103 has a different SiGe composition than the silicon germanium source or drain structure. Corresponding conductive trench contacts 116 are located above and coupled to the epitaxial source or drain structure 110.

[0041] The starting structure 100 also includes a dielectric gate cut plug 112. A gate contact 118 is included in a dielectric layer 120. The upper portion of the structure 100 includes a lower conductive line 122, a conductive via 124, and an upper conductive line 126 in a respective dielectric layer stack 128. At this stage in the process, from the bottom or back side, the starting structure 100 has been planarized to remove the bulk silicon substrate.

[0042] refer to Figure 1B The starting structure 100 is subjected to recessing of the dielectric gate cut plug 112 to form a recessed dielectric gate cut plug 112A, and removal of the trench isolation structure 104. A dielectric filler 130, such as a silicon nitride filler, is then formed and planarized to form a dielectric backside structure 130.

[0043] refer to Figure 1C The sub-fin structure 102 is removed, for example, by a selective etching process that lands on the etch stop layer 103. Any exposed oxide and / or dielectric is then removed, leaving a cavity 132 that exposes the gate electrode 108 and the epitaxial source or drain structure 110 from the bottom or backside of the structure.

[0044] refer to Figure 1D , removing the etch stop layer 103 and the doped silicon structure 105. Gate electrode 108 is then recessed, for example using atomic layer etching, to form a recessed gate electrode 108A and an extended cavity 132A. Compared to the starting gate electrode 108, the recessed gate electrode 108A has a lowermost surface that is further vertically away from the bottom of the epitaxial source or drain structure.

[0045] refer to Figure 1E A backside dielectric liner 133, such as a silicon nitride liner, is formed in the extended cavity 132A. A dielectric filler 134, such as a silicon oxide filler, is then formed to fill the remaining portion of the extended cavity 132A.

[0046] refer to Figure 1F ,exist Figure 1FA mask structure 136 / 138, such as a mask including a hard mask layer 136 and a resist 138, is formed on the bottom of the structure. The mask 136 / 138 includes an opening 140 that exposes locations of selected ones of the epitaxial source or drain structures 110 for the eventual backside contact. The dielectric fill 134 is then etched at those locations to form a recessed dielectric fill 134A.

[0047] refer to Figure 1G An integrated circuit structure 199 is formed by removing the masks 136 / 138 and removing the exposed portions of the back dielectric liner 133, exposing selected ones of the epitaxial source or drain structures 110. A silicide layer 135 can then be formed on the bottoms of the selected ones of the epitaxial source or drain structures 110. A conductive fill is then formed in the recesses, and the structure is planarized to form a planarized dielectric fill 130A, a planarized dielectric fill 134B, and a conductive back contact 142. The integrated circuit structure 199 can include epitaxial source or drain structures 110A coupled to corresponding conductive back contacts 142, and epitaxial source or drain structures 110B not coupled to corresponding conductive back contacts. In one embodiment, the conductive back contacts 142 extend laterally beyond the corresponding epitaxial source or drain structures 110A without contacting the adjacent gate electrode or gate stack.

[0048] In an embodiment, the epitaxial source or drain structure 110A and the epitaxial source or drain structure 110B are composed of the same material. In one such embodiment, the epitaxial source or drain structure 110A and the epitaxial source or drain structure 110B are composed of silicon, germanium, and boron, for example, such as materials found in a PMOS source or drain structure. In another such embodiment, the epitaxial source or drain structure 110A and the epitaxial source or drain structure 110B are composed of silicon and phosphorus, for example, such as materials found in an NMOS source or drain structure.

[0049] As described above, one or more embodiments relate to backside (BS) contacts with deep source or drain (SD) implemented using a silicon germanium (SiGe) etch stop (ES) layer. In an embodiment, the etch stop layer 103 may be a silicon germanium etch stop layer, for example, having a different SiGe composition than the silicon germanium source or drain structure 110. In an embodiment, the etch stop layer 103 may be a silicon germanium etch stop layer, for example, having a different SiGe composition than the silicon germanium source or drain structure 110. In an embodiment, the etch stop layer 103 may be a silicon germanium etch stop layer, for example, having a different SiGe composition than the silicon germanium source or drain structure 110. Figure 7 and Figure 8 The sacrificial SiGe layer used in the nanowire release process described herein has different SiGe compositions.

[0050] To provide context, a process strategy can be implemented to increase source / drain depth and introduce SiGe etch stops to ensure uniform SD depth. This approach can reduce the need for extensive over-etching. The combination of deep SD and SiGe ES can pave the way for patterning contact vias directly to the transistor source from the backside. In embodiments, the concept can be extended to implement multiple SiGe etch stop layers for both front-side and back-side etching.

[0051] Advantages of implementing the embodiments described herein may include simplifying process steps and increasing process margins to allow backside contacting of source / drain, thereby enabling direct BS power contact and delivery.

[0052] Detectability of implementations of the embodiments described herein can include: the SD depth of the transistor can appear uniform. Due to selectivity for SiGe, there may be a slight wobble at the bottom of the SD after the final SD etch. For some analog mixed-signal devices and diodes, the Si sub-fin may not be removed, and the presence of a SiGe etch stop may be found in such devices.

[0053] As a first exemplary process scheme, Figure 2A Depicted are cross-sectional views representing various operations in a method of fabricating a nanowire and release layer stack including a bottom etch stop layer, in accordance with an embodiment of the present disclosure.

[0054] refer to Figure 2A In part (a) of FIG. 1 , a starting structure 200 includes a bottom silicon layer or substrate 202, a silicon germanium etch stop layer 204, an intermediate silicon layer 206, and a plurality of alternating silicon germanium sacrificial release layers 208 and silicon nanowire layers 210. In one embodiment, the silicon germanium sacrificial release layers 208 have a different silicon germanium composition and / or a different dopant composition than the silicon germanium etch stop layers 204. The starting structure 200 also includes a capping layer 212, a sacrificial gate structure 214, and gate spacers 216.

[0055] refer to Figure 2A The starting structure 200 is then subjected to a non-selective etching process that etches the stack to form a stack including a patterned capping layer 212A, a plurality of alternating patterned silicon germanium sacrificial release layers 208A and patterned silicon nanowire layers 210A, and a patterned intermediate silicon layer 206A. In one embodiment, the etching partially touches down into the silicon germanium etch stop layer 204 to form a partially patterned silicon germanium etch stop layer 204A.

[0056] refer to Figure 2AThe portion (c) of the patterned SiGe etch stop layer 204A is then subjected to a selective etching process that forms a patterned SiGe etch stop layer 204B without affecting the patterned SiGe sacrificial release layer 208A having a different SiGe composition and / or a different dopant composition. The resulting structure 220 can later be subjected to replacement gate and nanowire release processes, examples of which are described below, and can be used in conjunction with, for example, Figures 1A-1G The process described uses a patterned silicon germanium etch stop layer 204B (eg, as layer 103).

[0057] As a second exemplary process scheme, Figure 2B Depicted are cross-sectional views representing various operations in a method of fabricating a nanowire and release layer stack including a bottom etch stop layer, in accordance with another embodiment of the present disclosure.

[0058] refer to Figure 2B , a starting structure 250 includes a bottom silicon layer or substrate 252, a silicon germanium etch stop layer 254, an intermediate silicon layer 256, and a plurality of alternating silicon germanium sacrificial release layers 258 and silicon nanowire layers 260. In one embodiment, the silicon germanium sacrificial release layers 258 have a different silicon germanium composition and / or a different dopant composition than the silicon germanium etch stop layers 254. The starting structure 250 also includes a capping layer 262, a sacrificial gate structure 264, and gate spacers 266.

[0059] refer to Figure 2B , and then subjecting the starting structure 250 to a non-selective etching process that etches the stack to form a stack including a patterned capping layer 262A, a plurality of alternating patterned silicon germanium sacrificial release layers 258A and patterned silicon nanowire layers 260A, and a partially patterned intermediate silicon layer 256A.

[0060] refer to Figure 2B The portion (c) of the patterned intermediate silicon layer 256A is then subjected to a selective etching process that forms a patterned intermediate silicon layer 256B. The resulting structure 270 can later be subjected to a replacement gate and nanowire release process, examples of which are described below and can be used in conjunction with, for example, Figures 1A-1G A silicon germanium etch stop layer 254 (eg, as layer 103) is used in the described process.

[0061] On the other hand, to provide further context, as semiconductor scaling continues to squeeze interconnects into ever-tighter spaces, low-resistance power delivery solutions are needed. Backside power delivery, where the power delivery interconnect network runs directly to the transistors from the backside of the wafer rather than sharing space with frontside wiring, is a possible solution for future semiconductor technology generations.

[0062] Traditionally, power is delivered from the front interconnect. At the standard cell level, power can be delivered directly on top of the transistor or from the top and bottom cell boundaries. Power delivered from the top and bottom cell boundaries enables a relatively short standard cell height and slightly higher power network resistance. However, the front power network shares the interconnect stack with the signal wiring and reduces the signal wiring traces. In addition, for high-performance designs, the top and bottom cell boundary power metal wires must be wide enough to reduce the power network resistance and improve performance. This typically results in an increase in cell height. According to one or more embodiments of the present disclosure, power delivery from the back of the wafer or substrate can be implemented to address area and performance issues. At the cell level, the wider metal 0 power at the top and bottom cell boundaries may no longer be required, and therefore the cell height can be reduced. In addition, the power network resistance can be significantly reduced, resulting in improved performance. At the block and chip level, due to the removal of power wiring, the front signal wiring traces increase, and due to very wide wires, large vias, and reduced interconnect layers, the power network resistance is significantly reduced.

[0063] In earlier technologies, the power delivery network from the bumps to the transistors required significant block resources. The use of such resources on the metal stack manifested itself in some process nodes as a standard cell architecture with layout revision control or cell placement restrictions at the block level. In embodiments, eliminating the power delivery network from the front-side metal stack allows for free-sliding cell placement within the block without power delivery complexity and placement-related delay timing variations.

[0064] As an illustrative comparison, Figure 3 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0065] refer to Figure 3 , an interconnect stack with front-side power delivery 300 includes a transistor 302 and a signal and power delivery metallization 304. The transistor 302 includes a bulk substrate 306, a semiconductor fin 308, a terminal 310, and a device contact 312. The signal and power delivery metallization 304 includes a conductive via 314, a conductive line 316, and a metal bump 318.

[0066] Reference again Figure 3, an interconnect stack 350 with backside power delivery includes a transistor 352, a frontside signal metallization 354A, and a power delivery metallization 354B. Transistor 352 includes a semiconductor nanowire or nanoribbon 358, a terminal 360, a device contact 362, and a boundary deep via 363. Frontside signal metallization 354A includes a conductive via 364A, a conductive line 366A, and a metal bump 368A. Power delivery metallization 354B includes a conductive via 364B, a conductive line 366B, and a metal bump 368B. It should be understood that backside power methods can also be implemented for structures including semiconductor fins.

[0067] To provide further context, a fundamental component of the backside power delivery network is the electrically functional feature that interfaces the source or drain contact of a transistor with the backside interconnect network. Therefore, a design and method for fabricating interface features that is compatible with existing library cell design conventions and transistor contact process flows is needed.

[0068] There are currently no solutions that are being adopted in high-volume manufacturing because backside power delivery has not yet been introduced in high-volume manufacturing. Approaches may ultimately include deep trench contacts (TCNs), direct source-drain contacts from the backside, or replacing the gate contact track with backside power contacts. Depending on the proposed solution, the solution may suffer from high-resistance contacts, which negates the inherent value of co-optimizing backside power delivery with front-end transistor processing, resulting in defects and performance risks and tradeoffs.

[0069] In another aspect, differentiated backside accessible features are described.

[0070] One or more embodiments are directed to forming self-aligned accessible features for back side source or drain contact structures (e.g., for back side epitaxial (epi) contacts). One or more embodiments are directed to self-aligned back side accessible features. One or more embodiments are directed to differentiated back side accessible features, where deeper features can ultimately be accessed while shallower features are not accessed and effectively become dummy features that can be referred to as mirrors (such as titanium nitride (TiN)). One or more embodiments described herein are directed to gate-all-around integrated circuit structures fabricated using differentiated back side accessible features. It should be understood that references herein to nanowires may indicate nanowires or nanoribbons or nanosheets or forksheets unless otherwise stated. One or more embodiments described herein are directed to fin-based integrated circuit structures fabricated using differentiated back side accessible features using a back side hard mask.

[0071] As an exemplary treatment scheme, Figure 4-9Angled cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure having differentiated backside source or drain contact accessible features in accordance with an embodiment of the present disclosure are shown. It should be understood that the embodiments described and illustrated may also be applicable to fin structures that replace stacks of nanowires or nanoribbons or nanosheets or forks. It should also be understood that in embodiments, such as incorporating Figure 4-9 The described differential accessibility approach can be combined with a direct backside source or drain contact approach using a silicon germanium (SiGe) etch stop (ES) layer, such as the one described above. Figures 1A-1G 、 Figure 2A and Figure 2B described) integration.

[0072] refer to Figure 4 , the starting structure 400 includes a sub-fin structure 404 protruding from a substrate 402, such as a silicon sub-fin structure protruding from a silicon substrate. An isolation structure 406, such as a silicon oxide or silicon dioxide shallow trench isolation structure, separates the sub-fin structures along the gate line direction. Fins 408 are located above corresponding sub-fin structures 404 in the sub-fin structures 404, and the fins 408 are, for example, fins of alternating stacks of silicon nanowires 410 and silicon germanium release layers 412. A channel cap layer 415, such as a silicon nitride channel cap, is located above the fins 408. A dummy gate structure extends above the fins 408, such as a polysilicon 416 and silicon nitride 418 dummy gate structure (and possible dummy gate oxide 414). Gate spacers 420, such as silicon nitride gate spacers, are located above and along the sides of the dummy gate structure. At this stage, a protective helmet layer 422, such as a titanium helmet, is located on top of the gate spacers 420 as an artifact of the etching process used to etch the fins 408 between the gate structures, e.g., in locations for eventual source or drain formation. In an embodiment, the etching process extends deeper than the fins 408 to form deep trenches 424 etched into the sub-fins 404, as depicted.

[0073] refer to Figure 5 , using photolithographic patterning and then continuing with an etching process, selected ones of the deep trenches 424 are extended to form deeper trenches 426. The etching process may be referred to as a self-aligned etch, which is non-selective because deep trenches are formed in all locations.

[0074] refer to Figure 6A contact placeholder material, such as titanium nitride, is formed in the deep trench 424 and the deeper trench 426, and the contact placeholder material is etched back to form a contact placeholder 430 and a dummy contact placeholder 428. In an embodiment, the contact placeholder 430 is ultimately accessed from the backside, while the dummy contact placeholder 428 is not.

[0075] refer to Figure 7 , release layer 412 is laterally recessed relative to nanowire 410 to form recessed release layer 412A. Inner spacer material 432, such as a silicon nitride inner spacer material, is formed in the recess formed by recessed release layer 412A and over contact placeholders 430 and dummy contact placeholders 428 to form structure 700.

[0076] refer to Figure 8 , Figure 7 The structure 700 is exposed to an epitaxial source or drain growth process, a replacement gate and nanowire release process, an inversion, and a backside exposure process. The resulting structure includes a front side protective dielectric layer 802, a metal gate electrode 804, a high-k gate dielectric 806, a gate cap (e.g., silicon nitride) 808, an epitaxial source or drain structure (e.g., epitaxial silicon or epitaxial silicon germanium) 812 (which can be formed by patterning the internal spacer material 432 to form a placeholder cap 432A and an internal spacer 432B), a front side trench contact 814, a dielectric sub-fin structure 816 (e.g., a replacement from a silicon sub-fin), and a dielectric gate cut plug 818. The contact placeholder 430 is backside exposed to form a planarized contact placeholder 430A. The dummy contact placeholder 428 is not exposed.

[0077] refer to Figure 9 , the contact placeholder 430 and the placeholder cap 432A are removed and replaced with a permanent back contact 902, such as a cobalt or tungsten contact, to form structure 900. The permanent back contact 902 contacts the corresponding source or drain structure 812A in the source or drain structures 812. The dummy contact placeholder 428 remains on the corresponding source or drain structure 812 in the source or drain structures 812 that is not selected for back contact. In an embodiment, the permanent back contact 902 may ultimately be coupled to one or more back metallization lines or layers.

[0078] Reference again Figure 4-9 (especially with reference to the inverted Figure 9), according to an embodiment of the present disclosure, the integrated circuit structure 900 includes a first plurality of horizontally stacked nanowires or fins 412 that are laterally spaced apart from a second plurality of horizontally stacked nanowires or fins 412, the second plurality of horizontally stacked nanowires or fins 412 being laterally spaced apart from a third plurality of horizontally stacked nanowires or fins 412. A first gate stack 804 / 806 is above the first plurality of horizontally stacked nanowires or fins 412, a second gate stack 804 / 806 is above the second plurality of horizontally stacked nanowires or fins 412, and a third gate stack 804 / 806 is above the third plurality of horizontally stacked nanowires or fins 412. A first epitaxial source or drain structure 812 is disposed between the first plurality of horizontally stacked nanowires or fins 412 and the second plurality of horizontally stacked nanowires or fins 412. The first epitaxial source or drain structure 812 is disposed above the first conductive material 428, which has a first depth below the first epitaxial source or drain structure 812. A second epitaxial source or drain structure 812A is disposed between the second plurality of horizontally stacked nanowires or fins 412 and the third plurality of horizontally stacked nanowires or fins 412. The second epitaxial source or drain structure 812A is disposed above the second conductive material 902, which has a second depth below the second epitaxial source or drain structure 812A, and the second depth is greater than the first depth.

[0079] In an embodiment, the first conductive material and the second conductive material have different compositions. In an embodiment, the first conductive material comprises titanium and nitrogen, and the second conductive material comprises tungsten or cobalt.

[0080] In an embodiment, a dielectric spacer cap is located between the first epitaxial source or drain structure 812 and the first conductive material 428, as depicted. In an embodiment, the second conductive material 902 is in direct contact with the second epitaxial source or drain structure 812A, as depicted.

[0081] It will be understood that the direct back source or drain contacts and / or differentiated accessibility methods described above may be detectable in the final product. The cross-sections may show epitaxial structures with different widths on respective sides of the gate structure. The cross-sections may show unaccessed or short contact "placeholders". It will be understood that although the above figures show transistors based on full-ring gates, the embodiments may be applied to channels of any shape or material (fins, nanowires, nanoribbons, nanocombs / forks, etc.). It will be understood that although the figures show single-layer transistors, the embodiments may also be applied to multi-layer transistor architectures.

[0082] It should be understood that, as used throughout this disclosure, the sub-fins, nanowires, nanoribbons or fins described herein may be silicon sub-fins, silicon nanowires, silicon nanoribbons or silicon fins. As used throughout, a silicon layer or structure may be used to describe a silicon material that is composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form and may therefore include a very small percentage of carbon, germanium or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may "contaminate" Si when diffused during post-deposition processing. Therefore, the embodiments described herein involving silicon layers or structures may include silicon layers or structures that contain relatively small amounts (e.g., "impurity" levels) of non-Si atoms or substances (e.g., Ge, C or Sn). It should be understood that the silicon layer or structure as described herein may be undoped, or may be doped with dopant atoms such as boron, phosphorus or arsenic.

[0083] It should be understood that as used throughout this disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein may be silicon germanium sub-fins, silicon germanium nanowires, silicon germanium nanoribbons, or silicon germanium fins. As used throughout, a silicon germanium layer or structure may be used to describe a silicon germanium material that is composed of a majority of both silicon and germanium (e.g., at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In a specific embodiment, the silicon germanium layer or structure comprises approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer or structure comprises approximately 30% germanium and approximately 70% silicon (Si 70 Ge 30 ). It will be understood that, in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form, and therefore may include very small percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may "contaminate" the SiGe when diffused during post-deposition processing. Accordingly, embodiments described herein involving silicon germanium layers or structures may include silicon germanium layers or structures that include relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It will be understood that silicon germanium layers or structures as described herein may be undoped, or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0084] On the other hand, it will be appreciated that a direct back source or drain contact structure may be implemented with a front side architecture. In one example, a direct back source or drain contact structure may be implemented using a contact over active gate (COAG) structure and process. It will also be appreciated that the following "colored" hard mask COAG features may be applicable to the concepts regarding back side contacts described above. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed over an active portion of a gate electrode of a semiconductor structure or device. One or more embodiments of the present disclosure relate to a method of fabricating a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of a semiconductor structure or device. The methods described herein may be used to reduce a standard cell area by implementing gate contact formation over an active gate area. According to one or more embodiments, tapered gates and trench contacts are implemented to enable COAG fabrication. Embodiments may be implemented to achieve tight pitch patterning.

[0085] To provide further context for the importance of the COAG process scheme, in technologies where space and layout constraints are somewhat looser than those of current generations, a contact to the gate structure may be made by contacting a portion of the gate electrode disposed over the isolation region. As an example, Figure 10A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0086] refer to Figure 10A , semiconductor structure or device 1000A includes a diffusion or active region 1004 disposed in substrate 1002 and within isolation region 1006. One or more gate lines (also known as polysilicon lines), such as gate lines 1008A, 1008B, and 1008C, are disposed over diffusion or active region 1004 and over a portion of isolation region 1006. Source or drain contacts (also known as trench contacts), such as contacts 1010A and 1010B, are disposed over the source and drain regions of semiconductor structure or device 1000A. Trench contact vias 1012A and 1012B provide contact to trench contacts 1010A and 1010B, respectively. A separate gate contact 1014 and an overlying gate contact via 1016 provide contact to gate line 1008B. Compared to the source or drain trench contacts 1010A or 1010B, from a plan view perspective, the gate contact 1014 is disposed over the isolation region 1006 but not over the diffusion or active region 1004. Furthermore, neither the gate contact 1014 nor the gate contact via 1016 is disposed between the source or drain trench contacts 1010A and 1010B.

[0087] Figure 10B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown. Figure 10B , semiconductor structure or device 1000B (e.g., Figure 10A A non-planar version of the device 1000A (e.g., a fin structure) includes a non-planar diffusion or active region 1004B (e.g., a fin structure) formed from a substrate 1002 and within an isolation region 1006. A gate line 1008B is disposed over the non-planar diffusion or active region 1004B and over a portion of the isolation region 1006. As shown, the gate line 1008B includes a gate electrode 1050 and a gate dielectric layer 1052 and a dielectric cap layer 1054. Also visible from this angle are the gate contact 1014 and overlying gate contact via 1016, as well as the overlying metal interconnect 1060, all disposed in an interlayer dielectric stack or layer 1070. Figure 10B It can also be seen from the perspective that the gate contact 1014 is disposed over the isolation region 1006 but not over the non-planar diffusion or active region 1004B.

[0088] Reference again Figure 10A and Figure 10B , the arrangement of semiconductor structures or devices 1000A and 1000B respectively places the gate contact above the isolation region. This arrangement wastes layout space. However, placing the gate contact above the active area would require an extremely tight registration budget or the gate size would have to be increased to provide sufficient space for the gate contact to land. In addition, historically, gate contacts above the diffusion region have been avoided because there is a risk of drilling through other gate materials (e.g., polysilicon) and contacting the active region below. One or more embodiments described herein address the above-mentioned problems by providing a feasible method to manufacture a contact structure that contacts the portion of the gate electrode formed above the diffusion or active region, and the resulting structure.

[0089] As an example, Figure 11A FIG2 shows a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. Figure 11A, a semiconductor structure or device 1100A includes a diffusion or active region 1104 disposed in a substrate 1102 and within an isolation region 1106. One or more gate lines, such as gate lines 1108A, 1108B, and 1108C, are disposed over the diffusion or active region 1104 and over a portion of the isolation region 1106. Source or drain trench contacts, such as trench contacts 1110A and 1110B, are disposed over the source and drain regions of the semiconductor structure or device 1100A. Trench contact vias 1112A and 1112B provide contact to the trench contacts 1110A and 1110B, respectively. A gate contact via 1116 (without an intervening separate gate contact layer) provides contact to the gate line 1108B. Figure 10A In contrast, from a plan view perspective, gate contact 1116 is disposed over diffusion or active region 1104 and between source or drain contacts 1110A and 1110B.

[0090] Figure 11B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is shown. Figure 11B , semiconductor structure or device 1100B (e.g., Figure 11A A non-planar version of the device 1100A (e.g., a fin structure) includes a non-planar diffusion or active region 1104B (e.g., a fin structure) formed from a substrate 1102 and within an isolation region 1106. A gate line 1108B is disposed over the non-planar diffusion or active region 1104B and over a portion of the isolation region 1106. As shown, the gate line 1108B includes a gate electrode 1150 and a gate dielectric layer 1152 and a dielectric cap layer 1154. Also visible from this angle are the gate contact via 1116 and the overlying metal interconnect 1160, both disposed in an interlayer dielectric stack or layer 1170. Figure 11B It can also be seen from the perspective that the gate contact via 1116 is disposed above the non-planar diffusion or active region 1104B.

[0091] Therefore, refer again to Figure 11A and Figure 11B In an embodiment, the trench contact vias 1112A, 1112B and the gate contact via 1116 are formed in the same layer and are substantially coplanar. Figure 10A and Figure 10B In contrast, the contact with the gate line will otherwise include an additional gate contact layer, which may, for example, extend perpendicularly to the corresponding gate line. Figure 11A and Figure 11BIn the described (one or more) structures, the fabrication of structures 1100A and 1100B respectively enables the contact portion to land directly on the active gate portion from the metal interconnect layer without shorting to the adjacent source and drain regions. In an embodiment, such an arrangement provides a large area reduction in the circuit layout by eliminating the need to extend the transistor gate on the isolation portion to form a reliable contact portion. As used throughout, in an embodiment, reference to the active portion of the gate refers to the portion of the gate line or structure that is disposed above the active or diffusion region of the underlying substrate (from a plan view perspective). In an embodiment, reference to the non-active portion of the gate refers to the portion of the gate line or structure that is disposed above the isolation region of the underlying substrate (from a plan view perspective).

[0092] In an embodiment, the semiconductor structure or device 1100 is a non-planar device, such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is formed by or in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 1108A and 1108B surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is formed as a separate three-dimensional body, such as in a gate-all-around device. In one such embodiment, the gate electrode stacks of gate lines 1108A and 1108B each completely surround the channel region.

[0093] In general, one or more embodiments relate to methods for landing gate contact vias directly on the gates of active transistors and structures formed thereby. Such methods can eliminate the need to extend the gate line on the isolation portion for contact purposes. Such methods can also eliminate the need for a separate gate contact (GCN) layer for conducting signals from the gate line or structure. In an embodiment, the elimination of the above-mentioned features is achieved by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric material in the process flow (e.g., trench insulation layer (TILA)). The additional dielectric material is included as a trench contact dielectric cap layer, which has different etching characteristics than the gate dielectric material cap layer used for trench contact alignment in a gate aligned contact process (GAP) processing scheme (e.g., using a gate insulation layer (GILA)).

[0094] As an exemplary manufacturing scheme, the starting structure includes one or more gate stack structures disposed above a substrate. The gate stack structure may include a gate dielectric layer and a gate electrode. A trench contact (e.g., a diffusion region leading to the substrate or a contact to an epitaxial region formed in the substrate) is separated from the gate stack structure by a dielectric spacer. An insulating cap layer may be disposed on the gate stack structure (e.g., a GILA). In one embodiment, a contact barrier region or "contact plug" that may be made of an interlayer dielectric material is included in the region where the barrier contact is formed.

[0095] In an embodiment, the contact pattern is substantially perfectly aligned with the existing gate pattern while eliminating the use of lithography operations with very tight registration budgets. In one such embodiment, the method enables the use of inherently highly selective wet etches (or anisotropic dry etching processes, some of which are non-plasma, gas phase isotropic etches (e.g., relative to classical dry or plasma etches)) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for otherwise critical lithography operations used in other methods to generate the contact pattern. This also allows for perfect or near-perfect self-alignment with large edge placement error margins. In an embodiment, the trench contact grid is not patterned separately, but is formed between the polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0096] In addition, the gate stack structure can be manufactured by a replacement gate process. In such a scheme, the dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than being performed in an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including an aqueous solution of NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including an aqueous solution of phosphoric acid.

[0097] In embodiments, one or more of the methods described herein generally contemplate a combination of dummy and replacement gate processes and dummy and replacement contact processes. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high-temperature annealing of at least a portion of the permanent gate stack. For example, in certain such embodiments, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than approximately 600 degrees Celsius, for example, after forming the gate dielectric layer. The annealing is performed before forming the permanent contact.

[0098] Next, the trench contact can be recessed to provide a recessed trench contact having a height lower than the top surface of the adjacent spacer. An insulating capping layer (e.g., TILA) is then formed on the recessed trench contact. According to an embodiment of the present disclosure, the insulating capping layer on the recessed trench contact is composed of a material having different etching characteristics than the insulating capping layer on the gate stack structure.

[0099] The trench contact can be recessed by a process that is selective for the materials of the spacer and the gate insulating cap layer. For example, in one embodiment, the trench contact is recessed by an etching process such as a wet etching process or a dry etching process. The trench contact insulating cap layer can be formed by a process suitable for providing a conformal and sealed layer over the exposed portion of the trench contact. For example, in one embodiment, the trench contact insulating cap layer is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, for example by chemical mechanical polishing (CMP), to provide the trench contact insulating cap layer material only over the recessed trench contact.

[0100] Regarding suitable material combinations for the gate or trench contact insulating capping layers, in one embodiment, one of the pair of gate and trench contact insulating capping materials is composed of silicon oxide, while the other is composed of silicon nitride. In another embodiment, one of the pair of gate and trench contact insulating capping materials is composed of silicon oxide, while the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair of gate and trench contact insulating capping materials is composed of silicon oxide, while the other is composed of silicon carbide. In another embodiment, one of the pair of gate and trench contact insulating capping materials is composed of silicon nitride, while the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair of gate and trench contact insulating capping materials is composed of silicon nitride, while the other is composed of silicon carbide. In another embodiment, one of the pair of gate and trench contact insulating capping materials is composed of silicon nitride, while the other is composed of silicon carbide. In another embodiment, one of the pair of gate and trench contact insulating capping materials is composed of carbon-doped silicon nitride, while the other is composed of silicon carbide.

[0101] In another aspect, a direct backside source or drain contact is achieved using a nanowire or nanoribbon structure. In a specific example, a nanowire or nanoribbon release process can be performed by replacing the gate trench. An example of such a release process is described below. Additionally, in yet another aspect, back-end (BE) interconnect scaling can result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein can be implemented to achieve front-side and back-side interconnect integration of nanowire transistors. The embodiments described herein can provide a method for achieving a relatively wide interconnect spacing. The result can be improved product performance and lower patterning costs. The embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0102] One or more embodiments described herein are directional bi-epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depths. In an embodiment, an integrated circuit structure is fabricated by forming a source-drain opening for a nanowire / nanoribbon transistor partially filled with an SD epitaxial portion. The remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides enables direct contact to a backside interconnect level.

[0103] As an exemplary process flow for fabricating another gate-all-around device, Figures 12A-12J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0104] refer to Figure 12A , a method of fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 1204 and nanowires 1206 above a fin 1202, such as a silicon fin. Nanowires 1206 may be referred to as a vertical arrangement of nanowires. As depicted, a protective cap 1208 may be formed above the alternating sacrificial layers 1204 and nanowires 1206. As also depicted, a relaxed buffer layer 1252 and a defect modification layer 1250 may be formed below the alternating sacrificial layers 1204 and nanowires 1206.

[0105] refer to Figure 12B , a gate stack 1210 is formed over the vertical arrangement of horizontal nanowires 1206. The vertically arranged portion of the horizontal nanowires 1206 is then released by removing a portion of the sacrificial layer 1204 to provide a recessed sacrificial layer 1204' and a cavity 1212, as shown in FIG. Figure 12C Depicted.

[0106] It will be appreciated that the complete contact can be manufactured without first performing the deep etch and asymmetric contact processing described below. Figure 12CIn either case (e.g., with or without asymmetric contact processing), in an embodiment, the fabrication process involves using a process scheme that provides a gate-all-around integrated circuit structure having an epitaxial block, which may be a vertically discrete source or drain structure.

[0107] refer to Figure 12D , an upper gate spacer 1214 is formed at the sidewalls of the gate structure 1210. A cavity spacer 1216 is formed in the cavity 1212 below the upper gate spacer 1214. A deep trench contact etch is then optionally performed to form a trench 1218 and form a recessed nanowire 1206'. There may also be a patterned relaxed buffer layer 1252' and a patterned defect modification layer 1250', as depicted.

[0108] A sacrificial material 1220 is then formed in the trench 1218, such as Figure 12E In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0109] refer to Figure 12F , a first epitaxial source or drain structure (e.g., left feature 1222) is formed at a first end of the vertical arrangement of horizontal nanowire 1206'. A second epitaxial source or drain structure (e.g., right feature 1222) is formed at a second end of the vertical arrangement of horizontal nanowire 1206'. In an embodiment, as depicted, epitaxial source or drain structure 1222 is a vertically discrete source or drain structure and can be referred to as an epitaxial block.

[0110] Then, an interlayer dielectric (ILD) material 1224 is formed at the sides of the gate electrode 1210 and the adjacent source or drain structure 1222, such as Figure 12G Depicted. Reference Figure 12H , a replacement gate process is used to form a permanent gate dielectric 1228 and a permanent gate electrode 1226. The ILD material 1224 is then removed, as shown in FIG. Figure 12I The sacrificial material 1220 is then removed from one of the source drain locations (eg, the right side) to form a trench 1232 , but the sacrificial material 1220 is not removed from the other of the source drain locations, thereby forming a trench 1230 .

[0111] refer to Figure 12J , forming a first conductive contact structure 1234 coupled to the first epitaxial source or drain structure (e.g., left feature 1222). Forming a second conductive contact structure 1236 coupled to the second epitaxial source or drain structure (e.g., right feature 1222). The second conductive contact structure 1236 is formed deeper along the fin 1202 than the first conductive contact structure 1234. In an embodiment, although Figure 12JNot depicted, but the method also includes forming an exposed surface of a second conductive contact structure 1236 at the bottom of the fin 1202. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, where examples may include Ti, Ni, Co (for the former and W, Ru, Co for the latter).

[0112] In an embodiment, the second conductive contact structure 1236 is deeper along the fin 1202 than the first conductive contact structure 1234, as depicted. In one such embodiment, the first conductive contact structure 1234 is not along the fin 1202, as depicted. In another such embodiment, not depicted, the first conductive contact structure 1234 is partially along the fin 1202.

[0113] In an embodiment, second conductive contact structure 1236 is along the entire fin 1202. In an embodiment, although not depicted, second conductive contact structure 1236 has an exposed surface at the bottom of fin 1202 if the bottom of fin 1202 is exposed by a backside substrate removal process.

[0114] In another aspect, in order to enable access to both conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structures described herein may be manufactured using a backside exposure manufacturing method for a frontside structure. In some exemplary embodiments, exposure of the backside of a transistor or other device structure requires wafer-level backside processing. Compared to conventional TSV-type technologies, exposure of the backside of a transistor as described herein may be performed at the density of a device cell and even within a sub-region of the device. In addition, such exposure of the backside of the transistor may be performed to remove substantially all of the donor substrate on which the device layer was disposed during frontside processing. Thus, micron-deep TSVs become unnecessary in cases where the thickness of the semiconductor in the device cell after exposure of the backside of the transistor may be only tens or hundreds of nanometers.

[0115] The exposure technology described herein can enable a paradigm shift from "bottom-up" device manufacturing to "center-out" manufacturing, where the "center" is any layer employed in front-side manufacturing, exposed from the backside, and employed again in back-side manufacturing. Processing both the front side and the exposed backside of the device structure can address many of the challenges associated with manufacturing 3DICs, when relying primarily on front-side processing.

[0116] A backside exposure method for the transistor can be used, for example, to remove at least a portion of the carrier layer and the intervening layer of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0117] In some embodiments, the above operations are preceded by cleaving the carrier layer along a fracture plane substantially parallel to the intermediate layer. The cleaving or fracture process can be used to remove a large portion of the carrier layer as a large block, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved by practicing any uniform thickness implant known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer to a uniform target depth at which a fracture plane is desired to be produced. After such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove the larger thickness of the carrier layer.

[0118] Next, the exposure of the intervening layer is detected. Detection is used to identify the point at which the back surface of the donor substrate has advanced close to the device layer. Any endpoint detection technique known to be suitable for detecting the transition between the materials used for the carrier layer and the intervening layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting changes in light absorption or emission from the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are associated with changes in light absorption or emission from byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproducts can vary depending on the different compositions of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are associated with changes in the mass of substances in the byproducts of polishing or etching the back surface of the donor substrate. For example, the byproducts of the process can be sampled by a quadrupole mass analyzer, and the changes in the mass of the substances can be related to the different compositions of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criteria are associated with changes in the friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0119] Detection of an intervening layer can be enhanced where the removal process is selective for the carrier layer relative to the intervening layer because non-uniformities in the carrier removal process can be mitigated by the difference in etch rates between the carrier and intervening layers. Detection can even be skipped if the grinding, polishing, and / or etching operation removes the intervening layer at a rate sufficiently slower than the rate at which the carrier layer is removed. If an endpoint criterion is not employed, then a grinding, polishing, and / or etching operation of a predetermined fixed duration can be stopped at the intervening layer material if the thickness of the intervening layer is sufficient for etch selectivity. In some examples, the carrier etch rate:intervening layer etch rate is 3:1-10:1 or higher.

[0120] When exposing the intervening layer, at least a portion of the intervening layer can be removed. For example, one or more component layers of the intervening layer can be removed. For example, the thickness of the intervening layer can be uniformly removed by polishing. Alternatively, the thickness of the intervening layer can be removed using a mask or blanket etching process. This process can employ the same polishing or etching process used to thin the carrier, or it can be a different process with different process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that is more favorable for removing the intervening layer than for removing the device layer. Where the intervening layer thickness is to be removed to a thickness of less than a few hundred nanometers, the removal process can be relatively slow, optimized for cross-wafer uniformity, and more precisely controlled than the removal process used to remove the carrier layer. The CMP process employed can, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or greater) between semiconductor (e.g., silicon) and dielectric material (e.g., SiO), which surrounds the device layer and is embedded within the intervening layer, for example, to serve as electrical isolation between adjacent device regions.

[0121] For embodiments in which the device layer is exposed by completely removing the intervening layer, backside processing can begin on the exposed backside of the device layer or on specific device regions therein. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and a device region previously fabricated in the device layer, such as a source or drain region.

[0122] In some embodiments where wet and / or plasma etching is used to recess the backside of the carrier layer, intervening layer, or device layer, such etching can be a patterned etch or a material-selective etch that imparts significant non-planarity or topography to the backside surface of the device layer. As further described below, patterning can be within a device cell (i.e., "intra-cell" patterning) or can be across device cells (i.e., "inter-cell" patterning). In some patterned etch embodiments, at least a portion of the thickness of the intervening layer is used as a hard mask for patterning the backside device layer. Thus, the masked etch process can serve as the beginning of a corresponding masked device layer etch.

[0123] The above-described processing scheme can produce a donor-host substrate assembly including an IC device having a backside of an intervening layer, a backside of a device layer, and / or a backside of one or more semiconductor regions within a device layer, and / or exposed front-side metallization. Additional backside processing of any of these exposed regions can then be performed during downstream processing.

[0124] As described throughout this application, the substrate can be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate described herein is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 79%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown atop a different crystalline substrate, for example, a silicon epitaxial layer grown atop a boron-doped bulk silicon single crystal substrate. The bulk substrate can alternatively be composed of a III-V material. In an embodiment, the bulk substrate is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate is composed of a III-V material, and the charge carrier dopant impurity atoms are atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0125] As described throughout this application, isolation regions, such as shallow trench isolation regions or sub-fin isolation regions, can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of a portion of a permanent gate structure from an underlying bulk substrate, or for isolating an active region formed within an underlying bulk substrate, such as an isolated fin active region. For example, in one embodiment, the isolation region is composed of one or more layers of dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof.

[0126] As described throughout this application, a gate line or gate structure may be comprised of a gate electrode stack including a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate, and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer is comprised of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Additionally, a portion of the gate dielectric layer may include a native oxide layer formed from the top layers of a semiconductor substrate. In an embodiment, the gate dielectric layer is comprised of a top high-k portion and a lower portion comprised of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is comprised of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a "U"-shaped structure comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0127] In one embodiment, the gate electrode is composed of a metal layer, such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting filler material formed above a metal work function setting layer. The gate electrode layer can be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor will be a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive filler layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode can be composed of a "U"-shaped structure, wherein the "U"-shaped structure includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode can be simply a planar layer substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In other embodiments of the present disclosure, the gate electrode can be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode can be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0128] As described throughout this application, spacers associated with gate lines or electrode stacks can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of a permanent gate structure from an adjacent conductive contact, such as a self-aligned contact. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0129] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0130] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. A common example is a structure using copper lines and a barrier layer that may or may not include copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of various metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack or alloy of different metals, and the like. Therefore, the interconnect may be a single material layer, or may be formed by several layers comprising a conductive liner and a filling layer. Any suitable deposition process such as electroplating, chemical vapor deposition, or physical vapor deposition may be used to form the interconnect. In an embodiment, the interconnect is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or its alloys. Interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects in the art.

[0131] In an embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etch selectivities relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a silicon nitride (e.g., silicon nitride) layer or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material comprises a metallic substance. For example, the hard mask or other overlying material may comprise a nitride (e.g., titanium nitride) layer of titanium or another metal. Other materials, such as oxygen, may be included in one or more of these layers in potentially smaller amounts. Alternatively, other hard mask layers known in the art may be used, depending on the particular embodiment. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

[0132] In an embodiment, as also used throughout this specification, lithography operations are performed using 193 nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography. Positive or negative resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0133] In an embodiment, the methods described herein can involve forming a contact pattern that is very well aligned with an existing gate pattern while eliminating the use of lithographic operations with very tight registration budgets. In one such embodiment, the method enables the use of a wet etch that is highly selective in nature (e.g., relative to a dry or plasma etch) to generate the contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithographic operation. In one such embodiment, the method enables the need for otherwise critical lithographic operations used in other methods to generate the contact pattern to be eliminated. In an embodiment, the trench contact grid is not patterned separately, but is formed between the polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0134] In addition, the gate stack structure can be manufactured by a replacement gate process. In such a scheme, the dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, rather than performing the formation of the permanent gate dielectric layer by an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including the use of NH4OH aqueous solution or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including an aqueous phosphoric acid solution.

[0135] In one embodiment, one or more methods described herein generally contemplate dummy and replacement gate processes in combination with dummy and replacement contact processes to obtain a structure. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high-temperature annealing of at least a portion of the permanent gate stack. For example, in certain such embodiments, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than approximately 600 degrees Celsius, for example, after forming the gate dielectric layer. The annealing is performed before forming the permanent contact.

[0136] In some embodiments, the arrangement of the semiconductor structure or device places the gate contact portion above the gate line or gate stack above the isolation region. However, such an arrangement may be considered an inefficient use of layout space. In another embodiment, the semiconductor device has a contact structure that contacts the portion of the gate electrode formed above the active area. Typically, before (e.g., in addition to) forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present disclosure include first using a gate alignment trench contact process. Such a process can be implemented to form a trench contact structure for semiconductor structure manufacturing (e.g., for integrated circuit manufacturing). In an embodiment, the trench contact pattern is formed to align with an existing gate pattern. In contrast, other methods typically involve an additional photolithography process in which the photolithographic contact pattern is closely aligned with the existing gate pattern in combination with selective contact etching. For example, another process may include patterning the polysilicon (gate) grid using separate patterning of contact features.

[0137] It should be understood that the pitch division process and patterning scheme can be implemented to achieve the embodiments described herein, or the pitch division process and patterning scheme can be included as part of the embodiments described herein. Pitch division patterning generally refers to pitch halving, pitch quartering, etc. The pitch division scheme can be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., strictly unidirectional or primarily unidirectional) at a predefined pitch. Pitch division processing is then implemented as a technique to increase line density.

[0138] In an embodiment, the term "grid structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a close-pitch grid structure. In one such embodiment, the close pitch cannot be directly achieved by selected lithography. For example, a pattern based on selected lithography can be formed first, but the pitch can be halved by patterning using a spacer mask, as is known in the art. Further, the original pitch can be quartered by a second round of spacer mask patterning. Thus, the grid-like pattern described herein can have metal lines, ILD lines, or hard mask lines that are spaced at substantially uniform pitches and have substantially uniform widths. For example, in some embodiments, the pitch variation will be within ten percent and the width variation will be within ten percent, and in some embodiments, the pitch variation will be within five percent and the width variation will be within five percent. The pattern can be manufactured by halving the pitch or quartering the pitch or other pitch division methods. In an embodiment, the grid is not necessarily a single pitch.

[0139] In an embodiment, the uniform thickness film is patterned using a lithography and etching process that may involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It will be understood that other pitch division methods may also be implemented. In any case, in an embodiment, a gridded layout may be manufactured by a selected lithography method such as 193nm immersion lithography (193i). Pitch division may be implemented to increase the density of lines in the gridded layout by a factor of n. A gridded layout formed using 193i lithography plus "n" times the pitch division may be designated as 193i+P / n pitch division. In one such embodiment, 193nm immersion scaling may be extended for many generations with cost-effective pitch division.

[0140] It should also be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, it is no longer necessary to form a dummy gate before fabricating a gate contact over the active portion of the gate stack. The above-described gate stack may actually be a permanent gate stack that is initially formed. In addition, the processes described herein may be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or the like. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for a logic cell or memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, a FIN-FET, a nanowire, or a nanoribbon. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) technology node or a sub-10 nanometer (10 nm) technology node.

[0141] Additional or intermediate operations for FEOL layer or structure fabrication may include standard microelectronics fabrication processes such as photolithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other process associated with microelectronic component fabrication. Furthermore, it should be understood that the process operations described with respect to the foregoing process flow may be practiced in an alternative order, not every operation need be performed, or additional process operations may be performed, or both.

[0142] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, the integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, and the like. The integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, and the like via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0143] Figure 13 A computing device 1300 is shown in accordance with one embodiment of the present disclosure. Computing device 1300 houses a board 1302. Board 1302 can include a number of components, including, but not limited to, a processor 1304 and at least one communication chip 1306. Processor 1304 is physically and electrically coupled to board 1302. In some embodiments, at least one communication chip 1306 is also physically and electrically coupled to board 1302. In further embodiments, communication chip 1306 is part of processor 1304.

[0144] Depending on its application, computing device 1300 may include other components that may or may not be physically and electrically coupled to board 1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and mass storage devices (such as hard drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0145] The communication chip 1306 implements wireless communications for transmitting data to and from the computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. The communication chip 1306 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 1300 may include multiple communication chips 1306. For example, the first communication chip 1306 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1306 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0146] The processor 1304 of the computing device 1300 includes an integrated circuit die packaged within the processor 1304. In some implementations of the embodiments of the present disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures constructed according to embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers or memory, or both, to transform the electronic data into other electronic data that can be stored in registers or memory, or both.

[0147] The communication chip 1306 also includes an integrated circuit die packaged within the communication chip 1306. According to another embodiment of the present disclosure, the integrated circuit die of the communication chip is constructed according to an embodiment of the present disclosure.

[0148] In further implementations, another component housed within computing device 1300 may include an integrated circuit die constructed according to implementations of embodiments of the present disclosure.

[0149] In various embodiments, computing device 1300 may be a laptop computer, a netbook, a notebook, an ultrabook, a smartphone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further embodiments, computing device 1300 may be any other electronic device that processes data.

[0150] Figure 14 An interposer 1400 is shown that includes one or more embodiments of the present disclosure. Interposer 1400 is an intermediate substrate used to bridge a first substrate 1402 to a second substrate 1404. First substrate 1402 can be, for example, an integrated circuit die. Second substrate 1404 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 1400 is to extend connections to a wider spacing or to reroute connections to different connections. For example, interposer 1400 can couple an integrated circuit die to a ball grid array (BGA) 1406, which can then be coupled to second substrate 1404. In some embodiments, first substrate 1402 and second substrate 1404 are attached to opposite sides of interposer 1400. In other embodiments, first substrate 1402 and second substrate 1404 are attached to the same side of interposer 1400. And in further embodiments, three or more substrates are interconnected through interposer 1400.

[0151] Interposer 1400 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In other embodiments, interposer 1400 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0152] Interposer 1400 may include metal interconnects 1408 and vias 1410, including but not limited to through-silicon vias (TSVs) 1412. Interposer 1400 may also include embedded devices 1414, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 1400. According to embodiments of the present disclosure, the apparatus or process disclosed herein may be used to manufacture interposer 1400 or components included in interposer 1400.

[0153] Figure 15is an isometric view of a mobile computing platform 1500 employing an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, according to an embodiment of the present disclosure.

[0154] The mobile computing platform 1500 can be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1500 can be any one of a tablet computer, a smart phone, a laptop computer, etc., and includes a display screen 1505, a chip-level (SoC) or package-level integrated system 1510, and a battery 1513. The display screen 1505 is a touch screen (capacitive, inductive, resistive, etc.) in an exemplary embodiment. As shown in the figure, the greater the integration in the system 1510 achieved by a higher transistor packaging density, the larger the portion of the mobile computing platform 1500 that can be occupied by the battery 1513 or a non-volatile storage device (such as a solid-state drive), or the larger the transistor gate count for improved platform functionality. Similarly, the greater the carrier mobility of each transistor in the system 1510, the stronger the functionality. Therefore, the technology described herein can achieve performance and form factor improvements in the mobile computing platform 1500.

[0155] Integrated system 1510 is further shown in expanded view 1520. In an exemplary embodiment, packaged device 1577 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or graphics processor) manufactured according to one or more processes described herein or including one or more features described herein. Packaged device 1577 is further coupled to board 1560 along with one or more of a power management integrated circuit (PMIC) 1515, an RF (wireless) integrated circuit (RFIC) 1525 including a broadband RF (wireless) transmitter and / or receiver (e.g., including a digital baseband and analog front-end module, as well as a power amplifier in the transmit path and a low-noise amplifier in the receive path), and its controller 1511. Functionally, PMIC 1515 performs battery power regulation, DC-to-DC conversion, etc., and therefore has an input coupled to battery 1513 and an output that provides current supply to all other functional modules. As further shown, in an exemplary embodiment, RFIC 1525 has an output coupled to an antenna to provide for implementing any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. In alternative embodiments, each of these board-level modules can be integrated onto a separate IC coupled to the packaging substrate of packaged device 1577 or within a single IC (SoC) coupled to the packaging substrate of packaged device 1577.

[0156] On the other hand, semiconductor packages are used to protect integrated circuit (IC) chips or dies and also provide the die with an electrical interface to external circuitry. As the demand for smaller electronic devices increases, semiconductor packages are being designed to be even more compact and must support greater circuit density. Furthermore, the demand for higher performance devices has led to a need for improved semiconductor packages that can achieve a thin package profile and low overall warpage compatible with subsequent assembly processes.

[0157] In an embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, the die is mounted to the ceramic or organic package substrate using a C4 process. In particular, a C4 solder ball connection can be implemented to provide a flip chip interconnect between the semiconductor device and the substrate. Flip chip or controlled collapse chip connection (C4) is a type of mounting for semiconductor devices (such as integrated circuit (IC) chips, MEMS or components) that utilizes solder bumps instead of wire bonding. The solder bumps are deposited on the C4 pads located on the top side of the substrate package. In order to mount the semiconductor device to the substrate, the semiconductor device is flipped over with the active side facing down towards the mounting area. Solder bumps are used to connect the semiconductor device directly to the substrate.

[0158] Figure 16 A cross-sectional view of a flip-chip mounted die is shown according to an embodiment of the present disclosure.

[0159] refer to Figure 16 According to an embodiment of the present disclosure, device 1600 includes a die 1602, such as an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein. Die 1602 includes metallization pads 1604 thereon. A package substrate 1606, such as a ceramic or organic substrate, includes connections 1608 thereon. Die 1602 and package substrate 1606 are electrically connected via solder balls 1610 coupled to metallization pads 1604 and connections 1608. An underfill material 1612 surrounds solder balls 1610.

[0160] Processing a flip chip can be similar to conventional IC manufacturing, with a few additional operations. At the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically involves several steps. Small dots of solder are then deposited on each metallized pad. The chips are then cut from the wafer as usual. To attach the flip chip to the circuit, the chip is inverted to bring the solder dots down to the underlying electronics or connectors on the circuit board. The solder is then remelted, typically using ultrasound or, alternatively, a reflow soldering process, to create the electrical connection. This also leaves a small space between the chip's circuitry and the underlying mounting. In most cases, an electrically insulating adhesive is then "underfilled" to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0161] In other embodiments, newer packaging and die-to-die interconnect methods (such as through-silicon vias (TSVs) and silicon interposers) are implemented in accordance with embodiments of the present disclosure to fabricate high-performance multi-chip modules (MCMs) and system-in-packages (SiPs) that incorporate integrated circuits (ICs) fabricated according to one or more processes described herein or that include one or more features described herein.

[0162] Thus, embodiments of the present disclosure include integrated circuit structures having direct backside source or drain contacts.

[0163] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even in cases where a single embodiment has been described with respect to specific features. Unless otherwise stated, the examples of features provided in the present disclosure are intended to be illustrative rather than restrictive. The above description is intended to encompass such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art having the benefit of this disclosure.

[0164] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly) or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be filed during the prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of the independent claims, and features from respective independent claims may be combined in any appropriate manner, not merely in the specific combinations recited in the appended claims.

[0165] The following examples relate to further embodiments.The various features of the different embodiments can be combined in different ways, including some features and excluding others to suit a variety of different applications.

[0166] Example embodiment 1: An integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. A first gate stack is above the first plurality of horizontally stacked nanowires, and a second gate stack is above the second plurality of horizontally stacked nanowires. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the epitaxial source or drain structure being above and electrically coupled to a corresponding conductive back contact, the conductive back contact extending laterally beyond the first epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

[0167] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein bottommost surfaces of the first gate stack and the second gate stack are above a bottommost surface of the epitaxial source or drain structure.

[0168] Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the conductive back contact extends laterally below the first gate stack and the second gate stack.

[0169] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2, or 3, wherein the epitaxial source or drain structure comprises silicon, germanium, and boron.

[0170] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, or 3, wherein the epitaxial source or drain structure comprises silicon and phosphorus.

[0171] Example 6: An integrated circuit structure includes a first fin laterally spaced apart from a second fin. A first gate stack is above the first fin, and a second gate stack is above the second fin. An epitaxial source or drain structure is between the first fin and the second fin, the epitaxial source or drain structure being above and electrically coupled to a corresponding conductive back contact, the conductive back contact extending laterally beyond the first epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

[0172] Example Embodiment 7: The integrated circuit structure of Example Embodiment 6, wherein the bottommost surfaces of the first gate stack and the second gate stack are above the bottommost surface of the epitaxial source or drain structure.

[0173] Example Embodiment 8: The integrated circuit structure of Example Embodiment 6 or 7, wherein the conductive back contact extends laterally below the first gate stack and the second gate stack.

[0174] Example Embodiment 9: The integrated circuit structure of Example Embodiment 6, 7, or 8, wherein the epitaxial source or drain structure comprises silicon, germanium, and boron.

[0175] Example Embodiment 10: The integrated circuit structure of Example Embodiment 6, 7, or 8, wherein the epitaxial source or drain structure comprises silicon and phosphorus.

[0176] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including a first plurality of horizontally stacked nanowires or fins laterally spaced apart from a second plurality of horizontally stacked nanowires or fins. A first gate stack is above the first plurality of horizontally stacked nanowires or fins, and a second gate stack is above the second plurality of horizontally stacked nanowires or fins. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fins and the second plurality of horizontally stacked nanowires or fins, the epitaxial source or drain structure being above and electrically coupled to a corresponding conductive back contact, the conductive back contact extending laterally beyond the first epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

[0177] Example Embodiment 12: The computing device of Example Embodiment 11, comprising the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires.

[0178] Example Embodiment 13: The computing device of Example Embodiment 11, comprising the first fin and the second fin.

[0179] Example Embodiment 14: The computing device of Example Embodiment 11, 12, or 13, further comprising a memory coupled to the board.

[0180] Example Embodiment 15: The computing device of Example Embodiment 11, 12, 13, or 14, further comprising a communication chip coupled to the board.

[0181] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14, or 15, further comprising a battery coupled to the board.

[0182] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15, or 16, further comprising a camera coupled to the board.

[0183] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, or 17, further comprising a display coupled to the board.

[0184] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, or 18, wherein the component is a packaged integrated circuit die.

[0185] Example Embodiment 20: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. An integrated circuit structure comprising: a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires; a first gate stack over the first plurality of horizontally stacked nanowires, and a second gate stack over the second plurality of horizontally stacked nanowires; as well as An epitaxial source or drain structure is located between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the epitaxial source or drain structure being above and electrically coupled to a corresponding conductive back contact, the conductive back contact extending laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

2. The integrated circuit structure according to claim 1, wherein: The bottommost surfaces of the first gate stack and the second gate stack are located above the bottommost surface of the epitaxial source or drain structure.

3. The integrated circuit structure according to claim 1 or 2, wherein: The conductive back contact extends laterally beneath the first gate stack and the second gate stack.

4. The integrated circuit structure according to claim 1 or 2, wherein: The epitaxial source or drain structure includes silicon, germanium and boron.

5. The integrated circuit structure according to claim 1 or 2, wherein: The epitaxial source or drain structure includes silicon and phosphorus.

6. An integrated circuit structure comprising: a first fin laterally spaced apart from a second fin; a first gate stack on the first fin, and a second gate stack on the second fin; as well as an epitaxial source or drain structure between the first fin and the second fin, the epitaxial source or drain structure being above and electrically coupled to a corresponding conductive back contact, the conductive back contact extending laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

7. The integrated circuit structure according to claim 6, wherein: The bottommost surfaces of the first gate stack and the second gate stack are located above the bottommost surface of the epitaxial source or drain structure.

8. The integrated circuit structure according to claim 6 or 7, wherein: The conductive back contact extends laterally beneath the first gate stack and the second gate stack.

9. The integrated circuit structure according to claim 6 or 7, wherein: The epitaxial source or drain structure includes silicon, germanium and boron.

10. The integrated circuit structure according to claim 6 or 7, wherein: The epitaxial source or drain structure includes silicon and phosphorus.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: a first plurality of horizontally stacked nanowires or first fins laterally spaced apart from a second plurality of horizontally stacked nanowires or second fins; a first gate stack over the first plurality of horizontally stacked nanowires or first fins, and a second gate stack over the second plurality of horizontally stacked nanowires or second fins; and An epitaxial source or drain structure is located between the first plurality of horizontally stacked nanowires or first fins and the second plurality of horizontally stacked nanowires or second fins, the epitaxial source or drain structure being above and electrically coupled to a corresponding conductive back contact, the conductive back contact extending laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

12. The computing device of claim 11, comprising the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires. The computing device of claim 11 , comprising the first fin and the second fin.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12, or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12, or 13, further comprising: A battery coupled to the board.

17. The computing device of claim 11, 12, or 13, further comprising: A camera is coupled to the board.

18. The computing device of claim 11, 12, or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12 or 13, wherein: The component is a packaged integrated circuit die.

20. The computing device of claim 11, 12, or 13, wherein: The component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

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