Memory management unit, processor and page table caching method

Abstract

The invention discloses a memory management unit, a processor and a page table caching method, and belongs to the technical field of computers. The memory management unit comprises a cache management module, a conversion backup buffer TLB module and a page table traversal PTW module; the TLB module is configured to cache a page table item; the PTW module is configured to query the page table according to the first virtual address under the condition that the TLB module is queried through the first virtual address and the TLB module is not hit; the cache management module is configured to merge 2n page table entries including a target page table entry to obtain a merged page table entry if the target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is smaller than or equal to a merging threshold value; and caching the merged page table entry into a TLB module. The memory management unit provided by the invention can merge the effective page table entries corresponding to the pages smaller than or equal to the merge threshold, so that the utilization rate and hit rate of the TLB module are improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory management unit, a processor, and a method for caching a page table. Background Art

[0002] In a virtual memory system, the mapping between virtual addresses and physical addresses is indicated by page table entries in the page table. The MMU (Memory Management Unit) converts virtual addresses into physical addresses based on the page table entries, and then accesses physical memory based on the physical addresses. The page table is located in the physical memory.

[0003] In the related art, in order to speed up address translation and improve memory access efficiency, a TLB (Translation Lookaside Buffer) outside the memory is usually used to cache some page table entries with high access frequency in the page table.

[0004] However, in the above method, since the TLB usually caches the page table entries of the page where the current virtual address is located regardless of the page size, in the virtual storage system of the RISC-V (Reduced Instruction Set Computer-Five) architecture, the virtual address space that can be covered by the page table entries cached in the TLB may be small, the cached entries in the TLB need to be replaced frequently, and the utilization rate is low. Summary of the Invention

[0005] The present application provides a memory management unit, a processor, and a method for caching page tables to solve the technical problems existing in the related art. Specifically, it includes the following technical solutions.

[0006] In a first aspect, the present application provides a memory management unit, the memory management unit comprising: a cache management module, a translation lookaside buffer (TLB) module, and a PTW (Page Table Walk) module; the TLB module being configured to cache page table entries; the PTW module being configured to query a page table according to a first virtual address when the TLB module is queried through the first virtual address and a hit is missed; the cache management module being configured to merge two pages including the target page table entry if a target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is less than or equal to a merge threshold. n Merge the page table entries to obtain a merged page table entry; cache the merged page table entry in the TLB module; wherein n is an integer greater than or equal to 1, and 2 n The attribute status information of the two page table entries is the same, and the twon The physical pages indicated by the two page table entries are continuous, and the physical pages indicated by the merged page table entry are n The order of the physical pages indicated by the page table entries is the same as the 2 n The location index of each page table entry is consistent.

[0007] In some possible implementations, the 2 n The page table entry includes a physical page number (PPN), and the cache management module includes the target page table entry. n When the page table entries are merged and the merged page table entry is obtained, it is configured as follows: n The page size indicated by the two page table entries determines the page size indicated by the merged page table entry; n The number of page table entries determines the PPN of the merged page table entry.

[0008] In some possible implementations, the PPN of the target page table entry includes a target high bit and a target low bit, the number of bits of the target low bit is n, and the cache management module calculates the target page table entry according to the PPN of the target page table entry and the 2 n When the number of page table entries is used to determine the PPN of the merged page table entry, the method is configured to: determine the target high bit as the PPN of the merged page table entry.

[0009] In some possible implementations, the attribute status information includes at least: validity information, access permission information, global information, modification status information, memory type information, access mode information, and continuous page table information.

[0010] In some possible implementations, the 2 n The page table entry includes the physical page number PPN, the 2 n The PPN of a page table entry includes a high bit and a low bit, the number of the low bits is n, and the position index includes the low bit.

[0011] In some possible embodiments, the cache management module is further configured to determine the target physical address corresponding to the target merged page table entry based on the second virtual address when querying the TLB module through the second virtual address and hitting the target merged page table entry in the merged page table entry, and the target physical address is used to access the memory.

[0012] In a second aspect, the present application provides a method for caching a page table, the method comprising: in a case where a translation lookaside buffer (TLB) module of a memory management unit is queried through a first virtual address and a hit is not hit, querying a page table according to the first virtual address, the TLB module being used to cache a page table entry; if a target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is less than or equal to a merge threshold, merging the 2 pages including the target page table entry. n Merge the page table entries to obtain a merged page table entry; cache the merged page table entry in the TLB module; wherein n is an integer greater than or equal to 1, and 2 n The attribute status information of the two page table entries is the same. n The physical pages indicated by the two page table entries are continuous, and the physical pages indicated by the merged page table entry are n The order of the physical pages indicated by the page table entries is the same as the 2 n The location index of each page table entry is consistent.

[0013] In some possible implementations, the 2 n The page table entry includes the physical page number PPN, and the 2 n Merge the page table entries to obtain the merged page table entry, including: n The page size indicated by the two page table entries determines the page size indicated by the merged page table entry; n The number of page table entries determines the PPN of the merged page table entry.

[0014] In some possible implementations, the PPN of the target page table entry includes a target high bit and a target low bit, the number of bits of the target low bit is n, and the PPN of the target page table entry and the 2 n The method of determining the PPN of the merged page table entry based on the number of the merged page table entries includes: determining the target high bit as the PPN of the merged page table entry.

[0015] In some possible implementations, the attribute status information includes at least: validity information, access permission information, global information, modification status information, memory type information, access mode information, and continuous page table information.

[0016] In some possible implementations, the 2 n The page table entry includes the physical page number PPN, the 2 n The PPN of a page table entry includes a high bit and a low bit, the number of the low bits is n, and the position index includes the low bit.

[0017] In some possible embodiments, the method includes: when querying the TLB module through a second virtual address and hitting a target merged page table entry in the merged page table entry, determining a target physical address corresponding to the target merged page table entry based on the second virtual address and the target merged page table entry, and the target physical address is used to access memory.

[0018] In a third aspect, the present application provides a processor, wherein the instruction processing unit is used to send an access instruction to the memory management unit, the access instruction carries a virtual address, and the processor includes an instruction processing unit and the memory management unit described in any one of the first aspects of the present application.

[0019] In a fourth aspect, the present application provides a computer-readable storage medium on which program instructions for caching page tables are stored. When the program instructions are executed by one or more processors, the memory management unit implements the method for caching page tables described in any one of the second aspects of the present application.

[0020] The beneficial effects of the technical solution provided by this application include at least:

[0021] The technical solution provided by the present application is that, when a TLB module misses, when querying the page table according to the virtual address, by setting a merge threshold, the target page table entries corresponding to the first virtual address can be selectively merged, so that page table entries with a partial page size less than or equal to the merge threshold are merged, so as to ensure that each page table entry cached in the TLB module can cover a larger virtual address space, which is conducive to improving the utilization rate and hit rate of the TLB module. In addition, when merging page table entries, by setting the number of merged page table entries, and ensuring that the attribute status information of the page table entries is the same, the physical pages indicated by the page table entries are continuous, and the position in the physical page corresponding to the merged page table entry is consistent with the position index of the page table entry, it is conducive to reducing the consumption of hardware resources in the page table entry merging process and reducing the hardware complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 It is a schematic diagram of an implementation scenario provided by an embodiment of the present application;

[0024] Figure 2 This is a flow chart of a method for caching page tables provided in an embodiment of the present application;

[0025] Figure 3Schematic diagram of page table entries in a virtual system of the RISC-V64 architecture provided in an embodiment of the present application;

[0026] Figure 4 This is a schematic diagram of the structure of the memory management unit provided in an embodiment of the present application;

[0027] Figure 5 It is a structural diagram of the processor provided in this application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0030] In a virtual storage system, an operating system or an application running within the operating system accesses the device's physical memory (i.e., the actual physical storage resources within the device) through virtual addresses. When the operating system or an application running within the operating system needs to access physical memory, the virtual address carried in the memory access instruction from the operating system or the application running within the operating system needs to be converted into a physical address based on the mapping relationship between the virtual address and the physical address indicated by the page table entry in the page table (stored within the physical memory). In related art, to improve the efficiency of address translation, some page table entries with higher access frequencies can be cached in the TLB.

[0031] However, because the RISC-V architecture's virtual memory system supports four different page sizes: 4KB (kilobyte), 2MB (megabyte), 1GB (gigabyte), and 512GB, the mapping relationships between virtual addresses and physical addresses stored in the page table also include mapping relationships for different page sizes, such as 4KB, 2MB, 1GB, and 512GB. When some frequently accessed page table entries in the page table are directly cached in the TLB module, the page table entries cached in the TLB module may include mapping relationships for pages with smaller page sizes, resulting in the technical problem that the page table entries cached in the TLB module may need to be frequently replaced and have low utilization rates.

[0032] In response to the above technical problems, the present application proposes a method for caching page tables, which can merge some page table entries in the page table that are less than or equal to the merge threshold and cache them in the TLB module, so that the page table entries cached in the TLB module can cover a larger virtual address space, thereby improving the hit rate and utilization rate of the TLB module.

[0033] Figure 1 This is a schematic diagram of the implementation scenario provided by the embodiment of this application. Figure 1 The implementation scenario provided by the embodiment of the present application includes a processor 110 and a memory 120. The processor 110 includes, for example, an instruction processing unit 111, a memory management unit 112, and a bus interface unit 113.

[0034] As an example, Figure 1 The implementation scenario shown in the figure can be, for example, a scenario in which an operating system of any computing device, such as a server, host, or personal computer, or an application running in the operating system, accesses the memory 120 of the computing device to read and write data. The memory access instruction includes, for example, program code generated by the operating system of the computing device or the application running in the operating system for accessing the memory 120.

[0035] Optionally, the instruction processing unit 111 may be used for, but not limited to, parsing a received memory access instruction and generating a virtual address corresponding to the memory access instruction. The memory management unit 112 may be used for, but not limited to, performing address translation on the virtual address generated by the instruction processing unit 111, converting the virtual address corresponding to the memory access instruction into a physical address, and then sending the physical address to the bus interface unit 113. The bus interface unit 113 may be used for, but not limited to, accessing the memory 120 based on the received physical address.

[0036] As an example, the processor 110 includes a central processing unit (CPU), a network processor (NP), a microprocessor, or may be one or more integrated circuits for implementing the solution of the present application.

[0037] As an example, the memory 120 can be a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disc (including a compact disc read-only memory (CD-ROM), a compact disc, a laser disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0038] It should be noted that Figure 1 In the implementation scenario shown in the figure, the way in which the memory management unit 112 is integrated with the processor 110 is illustrative and not restrictive. In other implementation scenarios, the memory management unit 112 may also exist independently, and this application does not impose any restrictions in this regard.

[0039] Figure 2 This is a flow chart of a method for caching page tables provided in an embodiment of the present application. This method can be executed by a memory management unit in a computing device, for example. The memory management unit can be integrated into the processor of the computing device or can exist in the computing device independently of the processor. This application does not impose any restrictions in this regard. Figure 2 The method for caching page tables provided in an embodiment of the present application may include the following steps.

[0040] Step S210: When a translation lookaside buffer (TLB) module of a memory management unit is queried through the first virtual address and a hit is not found, a page table is queried according to the first virtual address.

[0041] Among them, the TLB module is used to cache page table entries. The translation lookaside buffer can also be called the address translation lookaside buffer, page table cache, fast table, etc. For ease of understanding, this application collectively refers to it as the translation lookaside buffer or TLB module.

[0042] Exemplarily, a page table (stored in the physical memory of a computing device) may be, for example, a collection of page table entries, which are used to, but not limited to, indicate a mapping relationship between a virtual address and a physical address. In some embodiments, a page table entry includes, for example, a field (an array of different bits) for indicating the location of a physical page corresponding to the page table entry and attribute status information of the physical page. For example, a field including a physical page number (PPN) for indicating the location of a physical page corresponding to the page table entry may be included. This application does not impose any limitations in this regard.

[0043] The translation lookaside buffer (TLB) module is used for, but not limited to, caching frequently accessed page table entries in a page table. The first virtual address, for example, includes the virtual address currently being translated by the memory management unit. A TLB module miss scenario includes, for example, when the page table entry cached in the TLB module does not include the target page table entry corresponding to the first virtual address.

[0044] In some embodiments, the memory management unit includes, for example, a page table traversal PTW module, and the operation of querying the page table according to the first virtual address is, for example, performed by the PTW module of the memory management unit.

[0045] Considering that direct access to physical memory is slow, in order to reduce the number of direct accesses to physical memory and improve the speed of querying the page table, the process of querying the page table by the PTW module can be optimized through a cache mechanism.

[0046] In some embodiments, a cache module is provided between the PTW module and the physical memory. The method for querying a page table based on a first virtual address includes, for example, reading a page table stored in the physical memory into the cache module in units of cache lines, and the PTW module querying, based on the first virtual address, page table entries in the cache lines read into the cache module. The size of the cache lines can be adjusted based on actual application circumstances, and this application does not impose any limitations in this regard.

[0047] As mentioned above, when the operating system or an application running within the operating system needs to access physical memory, the MMU needs to convert the virtual address carried in the memory access instruction of the operating system or the application running within the operating system into a physical address. Given this, when the TLB module misses, the MMU needs to access physical memory, query the page table stored in physical memory, and complete the first virtual address conversion process based on the mapping relationship between the virtual address and the physical address indicated by the page table entry in the page table.

[0048] Step S220: If the target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is less than or equal to the merge threshold, the two pages including the target page table entry are merged. n Merge the page table entries to obtain a merged page table entry.

[0049] Where n is an integer greater than or equal to 1, 2 n The attribute status information of the page table entries is the same, 2 n The physical pages indicated by the page table entries are continuous, and the physical pages indicated by the merged page table entries are 2 n The order of the physical pages indicated by the page table entries is the same as 2 n The location index of each page table entry is consistent.

[0050] Exemplarily, the valid bit of the target page table entry is used to indicate that the mapping relationship between the virtual address indicated by the target page table entry and the physical address is valid. In some embodiments, the field for indicating the attribute status information of the page table entry in the target page table entry includes, for example, a valid bit for indicating whether the target page table entry is valid, and the method for the MMU to determine whether the target page table entry is valid includes, for example: determining whether the target page table entry is valid based on the valid bit of the target page table entry. For example, the valid bit includes one bit, and when the valid bit is 1, it indicates that the target page table entry is valid, that is, the mapping relationship between the virtual address indicated by the target page table entry and the physical address is valid; when the valid bit is 0, it indicates that the target page table entry is invalid, that is, the mapping relationship between the virtual address indicated by the target page table entry and the physical address is invalid.

[0051] As mentioned above, when the page size indicated by the page table entry cached in the TLB module is small, the virtual address space covered by the page table entry will also be small, resulting in an increased possibility of TLB module misses when querying the TLB module based on the virtual address, which in turn leads to a low utilization rate of the TLB module and frequent replacement of the page table entries cached in the TLB module. In view of this, the embodiment of the present application can set a merge threshold. When the target page table entry queried is less than or equal to the merge threshold, the 2 pages including the target page table entry can be merged. n The page table entries are merged so that the target physical page corresponding to the target page table entry and the two consecutive pages of the target physical page are n The physical pages corresponding to the page table entries are merged into a larger physical page, thereby covering a larger virtual space. The value of the merge threshold can be adjusted according to the actual application situation, and this application does not impose any restrictions in this regard.

[0052] As mentioned above, the page table entry includes, for example, a field for indicating the location of the physical page corresponding to the page table entry and the attribute status information of the page table entry. In order to ensure that the merged page table entry can be used normally in subsequent address conversion work, after merging multiple page table entries including the target page table entry, it is necessary to calculate the fields in the merged page table entry to determine the location of the merged physical page corresponding to the merged page table entry and the attribute status information of the merged page table entry. In view of this, in order to reduce the resource overhead required when calculating the merged page table entry after the merger, and to reduce the complexity of the hardware design, the method provided in the embodiment of the present application also sets multiple conditions so that the page table entries that meet the conditions are merged.

[0053] In some embodiments, the fields in the merged page table entry include a PPN for indicating the location of a physical page corresponding to the merged page table entry and a field for indicating attribute status information of the merged page table entry.

[0054] When the number of page table entries merged by the merged page table entry, including the target page table entry, is 2 n When merging page table entries, the conversion logic of the PPN of the merged page table entries can be simplified, and the resource overhead when calculating the PPN of the merged page table entries can be reduced.

[0055] When the attribute status information of multiple page table entries merged by the merged page table entry, including the target page table entry, is the same, the attribute status information of the merged page table entry can be directly determined based on the attribute status information of the multiple page table entries merged, and the generation of additional fields for distinguishing the attribute status information of multiple page table entries in the merged page table entry can be avoided, thereby ensuring that the array structure of the merged page table entry does not change, such as the array length, the type and number of fields, etc.

[0056] In some embodiments, the attribute status information of the page table entry includes, for example, validity information, access permission information, global information, modification status information, memory type information, access mode information, and continuous page table information.

[0057] The fields in the page table entry used to indicate the attribute status information of the physical page corresponding to the page table entry include, for example: a valid bit corresponding to the validity information corresponding to the page table entry, used to indicate whether the page table entry is valid; a permission bit corresponding to the access permission information of the page table entry, used to indicate the access permission of the page table entry, and the access permission of the page table entry includes, for example, read permission, write permission, execute permission, etc.; a global bit corresponding to the global information of the page table entry, used to indicate whether the page table entry is visible to all applications in the operating system; a dirty bit corresponding to the modification status information of the page table entry, used to indicate whether the page table entry has been modified; a memory type bit corresponding to the memory type information of the page table entry, used to indicate the memory type of the physical page corresponding to the page table entry, and the memory type of the physical page includes, for example, ordinary memory, strongly ordered memory, etc.; an access mode bit corresponding to the access mode information of the page table entry, used to indicate the access mode of the page table entry, and the access mode of the page table entry includes, for example, user mode; a continuous page table bit corresponding to the continuous page table information of the page table entry, used to indicate whether the page table entry belongs to part of a continuous page table.

[0058] 2 n The location index of the page table entry can be used to indicate but is not limited to 2 n For example, when the page table stored in the physical memory is read into the cache module in units of cache lines, 2 n The location index of the page table entry can be used to indicate 2 nThe order of the page table entries in the cache line. When the physical page indicated by the merged page table entry is 2 n The order of the physical pages indicated by the page table entries is the same as 2 n When the position indexes of the two page table entries are consistent, the logic of subsequent address conversion based on the merged page table entries can be simplified, and the resource overhead of address conversion based on the merged page table entries can be reduced.

[0059] In some embodiments, the page table entry includes, for example, a PPN, and the PPN includes, for example, a high bit and a low bit, and the number of bits of the low bit is n, 2 n The location index of each page table entry includes, for example, an array of low bits.

[0060] In some embodiments, the 2 including the target page table entry n The method for merging the page table entries to obtain the merged page table entries includes, for example: n The page size indicated by the two page table entries determines the page size indicated by the merged page table entry. n The sum of the page sizes indicated by the merged page table entries is determined as the merged page size indicated by the merged page table entry.

[0061] In other embodiments, the 2 including the target page table entry n The method for merging the target page table entry and obtaining the merged page table entry includes: n The number of page table entries determines the PPN of the merged page table entry. For example, the PPN of the target page table entry includes a target high bit and a target low bit, the number of target low bits is n, and the target high bit of the target page table entry is determined as the PPN of the merged page table entry.

[0062] The following will take the RISC-V64 architecture virtual system as an example to analyze the above two including the target page table entry. n The process of merging multiple page table entries to obtain the merged page table entry and the conditions for merging multiple page table entries are described. Among them, the virtual system of the RISC-V64 architecture supports a 64-bit address space.

[0063] Figure 3 Schematic diagram of page table entries in a virtual system of the RISC-V64 architecture provided in an embodiment of the present application. Figure 3 , a page table entry in a virtual system of the RISC-V64 architecture includes, for example, 64 bits.

[0064] Among them, field V is the valid bit of the page table entry, field R is the read permission bit in the permission bits of the page table entry, field W is the write permission bit in the permission bits of the page table entry, field X is the execute permission bit in the permission bits of the page table entry, U is the access mode bit of the page table entry, G is the global bit of the page table entry, A is the access status bit of the page table entry (used to indicate whether the page table entry has been accessed), D is the dirty bit of the page table entry, the RSW field and the Reserved field are undefined reserved bits for the page table entry, the PPN field is the physical page number of the page table entry, PBMT is the memory type bit of the page table entry, and N is the continuous page table bit of the page table entry.

[0065] As mentioned above, the page table stored in the physical memory is read in units of cache lines, for example. The PTW module can query the page table entry in the cache line according to the first virtual address to obtain the target page table entry. When the number of bits in the cache line is greater than the number of bits in the page table entry, a cache line may include multiple page table entries (including the target page table entry), that is, the PTW module can simultaneously obtain multiple page table entries in the cache line (including the target page table entry). When the target page table entry is valid, and the page size indicated by the target page table entry is less than or equal to the merge threshold, and the multiple page table entries in the cache line meet the following conditions, the multiple page table entries in the cache line can be merged: (1) The number of multiple page table entries in the cache line is 2 n (n is an integer greater than or equal to 1); (2) the attribute status information of multiple page table entries in the cache line is the same; (3) the physical pages indicated by the multiple page table entries in the cache line are continuous; (4) the order of the physical pages corresponding to the multiple page table entries in the cache line after merging is consistent with the position index of the multiple page table entries in the cache line.

[0066] In some embodiments, the size of a cache line is, for example, 256 bits. When the PTW module queries the page table entry in the cache line according to the first virtual address, it can simultaneously obtain 2 bits in a cache line. 2 4KB page table entries, 2 2 The page table entries are arranged in sequence in the cache line, including: PTE0, PTE1, PTE2 and PTE3.

[0067] When the merge threshold is 4 KB, if the target page table entry PTE0 is valid, it can be further determined whether to merge PTE0, PTE1, PTE2, and PTE3 in the cache line according to the above conditions.

[0068] For example, if the value of the field V of PTE0, PTE1, PTE2, and PTE3 is the same and is 1, it means that PTE0, PTE1, PTE2, and PTE3 are all valid.

[0069] If bits [43:2] in the PPN field of PTE0, PTE1, PTE2, and PTE3 are ( Figure 3 If the values ​​of the PPN field (an array of 42 bits from the 3rd bit to the 44th bit from right to left) are the same, it means that PTE0, PTE1, PTE2 and PTE3 are in the same 16KB page, that is, the physical pages corresponding to PTE0, PTE1, PTE2 and PTE3 are continuous.

[0070] If the values ​​of the fields N, PBMT, D, G, U, X, W, and R of PTE0, PTE1, PTE2, and PTE3 are the same, it means that the continuous page table information, memory type information, modification status information, global information, access mode information, and access permission information of PTE0, PTE1, PTE2, and PTE3 are the same.

[0071] If bits [1:0] of the PPN field of PTE0 ( Figure 3 The decimal value of the [1:0] bits of the PPN field of PTE1 is 1, the decimal value of the [1:0] bits of the PPN field of PTE2 is 2, and the decimal value of the [1:0] bits of the PPN field of PTE3 is 3, which means that the order of the physical pages corresponding to PTE0, PTE1, PTE2 and PTE3 in the merged 16KB page is consistent with the position index of PTE0, PTE1, PTE2 and PTE3. Among them, the array composed of the low bits in the PPN fields of PTE0, PTE1, PTE2 and PTE3, that is, the [1:0] bits in the PPN field are the position indexes of PTE0, PTE1, PTE2 and PTE3, which are used to indicate the order of PTE0, PTE1, PTE2 and PTE3 in the cache line.

[0072] At this point, PTE0, PTE1, PTE2, and PTE3 in the cache line may be merged.

[0073] In the above method, since the multiple page table entries including the target page table entry to be merged meet the following conditions: the number of the multiple page table entries is 2 n (n is an integer greater than or equal to 1); (2) the attribute status information of multiple page table entries is the same; (3) the physical pages indicated by multiple page table entries are continuous; (4) the order of the physical pages corresponding to the multiple page table entries after merging is consistent with the position index of the multiple page table entries. Therefore, the array structure of the merged page table entries after merging remains unchanged, which is the same as Figure 3At the same time, the values ​​of the fields N, PBMT, D, U, G, X, W, R, V, and the high bits in the field PPN (i.e., the [43:2] bits in the field PPN) in the merged page table entry are consistent with those of the target page table entry. The values ​​of the remaining fields in the merged page table entry can be adjusted according to actual application conditions, and this application does not impose any restrictions in this regard.

[0074] It should be noted that Figure 3 The contents and descriptions shown in are only illustrative and not restrictive. Other existing or future page table entries that are applicable to this application should also be included in the scope of protection of this application and are incorporated herein by reference.

[0075] Step S230: Cache the merged page table entry into the TLB module.

[0076] Optionally, the TLB module can also be used to cache merged page table entries. When the TLB module is queried using the second virtual address and a target merged page table entry in the merged page table entries is hit, a target physical address corresponding to the target merged page table entry is determined based on the second virtual address and the target merged page table entry; and memory is accessed based on the target physical address. The target physical address is used for, but not limited to, accessing memory.

[0077] Since the merged page table entry cached in the TLB module is 2 n The physical page indicated by the merged page table entry is 2 n In view of this, after the merged page table entry hits, it is necessary to determine the physical page corresponding to the merged page table entry according to the merged page table entry, and then determine the target physical address according to the target page offset in the second virtual address and the low bit of the PPN of the target page table entry.

[0078] In some embodiments, the PPN of the target merge page table entry includes a target merge high bit and a target merge low bit, the number of bits of the target merge low bit is n, the second virtual address includes an offset within the target page, the virtual page number VPN of the second virtual address includes a displacement bit, the number of bits of the displacement bit is n, and the target physical address is determined based on the second virtual address and the target merge page table entry, for example, including: determining the target physical address based on the target merge page table entry, the offset within the target page and the displacement bit.

[0079] The method for determining the target physical address according to the target merged page table entry, the target page offset and the shift bit can refer to the following formula (1):

[0080] PA={PPN[target combined high bit],

[0081] VPN[bit shift, offset in target page]}(1)

[0082] Wherein, PA is the target physical address, PPN is the PPN of the target merged page table entry, and VPN is the virtual page number of the second virtual address.

[0083] The technical solution provided by the present application is that, when a TLB module misses, when querying the page table according to the virtual address, by setting a merge threshold, the target page table entries corresponding to the first virtual address can be selectively merged, so that page table entries with a partial page size less than or equal to the merge threshold are merged, so as to ensure that each page table entry cached in the cache module can cover a larger virtual address space, which is conducive to improving the utilization rate and hit rate of the TLB module. In addition, when merging page table entries, by setting the number of merged page table entries, and ensuring that the attribute status information of the page table entries is the same, the physical pages indicated by the page table entries are continuous, and the position in the physical page corresponding to the merged page table entry is consistent with the position index of the page table entry, it is conducive to reducing the consumption of hardware resources in the page table entry merging process and reducing the hardware complexity.

[0084] In some other possible implementations, the present application also provides a memory management unit. Figure 4 This is a schematic diagram of the structure of the memory management unit provided in the embodiment of the present application. Figure 4 The memory management unit provided in the embodiment of the present application includes a cache management module 310, a TLB module 320 and a PTW module 330.

[0085] The TLB module 320 is configured to cache page table entries.

[0086] The PTW module 330 is configured to query the page table according to the first virtual address if the TLB module 320 is queried through the first virtual address and a hit is not found.

[0087] The cache management module 310 is configured to merge the 2 pages including the target page table entry if the target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is less than or equal to the merge threshold. n The page table entries are merged to obtain a merged page table entry, and the merged page table entry is cached in the TLB module 320.

[0088] Where n is an integer greater than or equal to 1, 2 n The attribute status information of the page table entries is the same, and 2 n The physical pages indicated by the page table entries are continuous, and the physical pages indicated by the merged page table entries are 2 n The order of the physical pages indicated by the page table entries is the same as 2 n The location index of each page table entry is consistent.

[0089] In some embodiments, 2n The page table entry includes the physical page number PPN, and the cache management module 310 converts the 2 pages including the target page table entry into n When the merged page table entries are merged, the merged page table entry is configured as follows: n The page size indicated by the two page table entries determines the page size indicated by the merged page table entry; according to the PPN of the target page table entry and 2 n The number of page table entries determines the PPN of the merged page table entry.

[0090] In some embodiments, the PPN of the target page table entry includes a target high bit and a target low bit, and the number of the target low bit is n. The cache management module 310 selects the target page table entry according to the PPN and 2 n When the number of page table entries determines the PPN of the merged page table entry, it is configured to determine the target high bit as the PPN of the merged page table entry.

[0091] In some embodiments, the attribute status information includes at least: validity information, access permission information, global information, modification status information, memory type information, access mode information, and continuous page table information.

[0092] In some embodiments, 2 n The page table entry includes the physical page number PPN, 2 n The PPN of a page table entry includes a high bit and a low bit, the number of bits of the low bit is n, and the position index includes the low bit.

[0093] In some embodiments, the cache management module 310 is further configured to determine the target physical address corresponding to the target merged page table entry based on the second virtual address when querying the TLB module 320 through the second virtual address and hitting the target merged page table entry in the merged page table entry, and the target physical address is used to access the memory.

[0094] above Figure 4 The principles of the various modules of the memory management unit shown above can be referred to. Figure 2 The memory management unit embodiment provided in the above embodiment and the embodiment of the method for caching page tables belong to the same concept, and their specific implementation process can be found in the embodiment of the method for caching page tables.

[0095] In some other possible implementations, the present application also provides a processor. Figure 5 This is a schematic diagram of the structure of the processor provided by this application. Figure 5 The processor includes an instruction processing unit 410 and a memory management unit 420. The instruction processing unit 410 is used to send an access instruction to the memory management unit 420. The access instruction carries a virtual address. The memory management unit 420 can be the above Figure 4 Of course, the processor may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output, and the processor may also include other components for realizing device functions, which will not be described in detail here.

[0096] In some other possible implementations, the present application further provides a computer-readable storage medium having stored thereon program instructions for caching a page table, which, when executed by one or more processors, enables the processor to implement the above-mentioned combination of Figure 2 The described method and steps of its multiple embodiments. The computer-readable storage medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0097] It should also be noted that the terms "first," "second," etc. (if any) in the specification and claims of the present application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0098] The term "and / or" in the embodiments of the present application is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0099] The above description is only for the purpose of facilitating the understanding of the technical solution of this application by those skilled in the art and is not intended to limit this application. Any modification, equivalent replacement, improvement, etc. made within the principles of this application shall be included in the scope of protection of this application.

Claims

1. A memory management unit, characterized in that: The memory management unit includes: a cache management module, a translation lookaside buffer (TLB) module and a page table traversal (PTW) module; The TLB module is configured to cache page table entries; The PTW module is configured to query the page table according to the first virtual address when the TLB module is queried through the first virtual address and a hit is not found; The cache management module is configured to merge the two pages including the target page table entry if the target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is less than or equal to the merge threshold. n Merging the page table entries to obtain a merged page table entry; caching the merged page table entry into the TLB module; Wherein, n is an integer greater than or equal to 1, and 2 n The attribute status information of the two page table entries is the same, and the two n The physical pages indicated by the two page table entries are continuous, and the physical pages indicated by the merged page table entry are n The order of the physical pages indicated by the page table entries is the same as the 2 n The location index of each page table entry is consistent.

2. The memory management unit according to claim 1, wherein: Said 2 n The page table entry includes a physical page number PPN, and the cache management module includes the target page table entry. n When the page table entries are merged, the merged page table entry is configured as follows: According to the 2 n determining the page size indicated by the merged page table entry based on the page sizes indicated by the two page table entries; According to the PPN of the target page table entry and the 2 n The number of page table entries determines the PPN of the merged page table entry.

3. The memory management unit according to claim 2, wherein: The PPN of the target page table entry includes a target high bit and a target low bit, the number of bits of the target low bit is n, and the cache management module calculates the target page table entry according to the PPN of the target page table entry and the target low bit. n When the number of page table entries determines the PPN of the merged page table entry, it is configured as follows: The target high bit is determined as the PPN of the merged page table entry.

4. The memory management unit according to claim 1, wherein: The attribute status information at least includes: validity information, access permission information, global information, modification status information, memory type information, access mode information and continuous page table information.

5. The memory management unit according to claim 1, wherein: Said 2 n The page table entry includes the physical page number PPN, the 2 n The PPN of a page table entry includes a high bit and a low bit, the number of the low bits is n, and the position index includes the low bit.

6. The memory management unit according to claim 1, characterized in that: The cache management module is also configured to determine the target physical address corresponding to the target merged page table entry according to the second virtual address when querying the TLB module through the second virtual address and hitting the target merged page table entry in the merged page table entry, and the target physical address is used to access the memory.

7. A processor, characterized in that: The processor includes an instruction processing unit and a memory management unit, the instruction processing unit is used to send an access instruction to the memory management unit, the access instruction carries a virtual address, and the memory management unit is the memory management unit according to any one of claims 1-6.

8. A method for caching a page table, characterized in that: The method comprises: In a case where a translation lookaside buffer (TLB) module of a memory management unit is queried through the first virtual address and a hit is not found, querying a page table according to the first virtual address, the TLB module being used to cache page table entries; If the target page table entry corresponding to the first virtual address in the page table is valid, and the page size indicated by the target page table entry is less than or equal to the merge threshold, the two pages including the target page table entry are merged. n Merge the page table entries to obtain a merged page table entry; Cache the merged page table entry in the TLB module; Wherein, n is an integer greater than or equal to 1, and 2 n The attribute status information of the two page table entries is the same. n The physical pages indicated by the two page table entries are continuous, and the physical pages indicated by the merged page table entry are n The order of the physical pages indicated by the page table entries is the same as the 2 n The location index of each page table entry is consistent.

9. The method according to claim 8, characterized in that Said 2 n The page table entry includes the physical page number PPN, and the 2 n Merging the page table entries to obtain the merged page table entry includes: According to the 2 n determining the page size indicated by the merged page table entry based on the page sizes indicated by the two page table entries; According to the PPN of the target page table entry and the 2 n The number of page table entries determines the PPN of the merged page table entry.

10. The method according to claim 9, characterized in that The PPN of the target page table entry includes a target high bit and a target low bit, the number of bits of the target low bit is n, and the PPN of the target page table entry and the 2 n The number of page table entries determines the PPN of the merged page table entry, including: The target high bit is determined as the PPN of the merged page table entry.

11. The method according to claim 8, characterized in that The attribute status information includes at least: validity information, access permission information, global information, modification status information, memory type information, access mode information and continuous page table information.

12. The method according to claim 8, characterized in that Said 2 n The page table entry includes the physical page number PPN, the 2 n The PPN of a page table entry includes a high bit and a low bit, the number of the low bits is n, and the position index includes the low bit.

13. The method according to claim 8, characterized in that The method comprises: When the TLB module is queried through the second virtual address and a target merged page table entry in the merged page table entry is hit, a target physical address corresponding to the target merged page table entry is determined according to the second virtual address and the target merged page table entry, and the target physical address is used to access the memory.

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