Front-end low-power-consumption verification environment generation method, electronic equipment and medium

Abstract

The invention relates to the technical field of chip verification, in particular to a front-end low-power-consumption verification environment generation method, electronic equipment and a medium, and the method comprises the steps: S1, obtaining register transfer level code information An and unified power consumption format information Bn of a chip; s2, acquiring a target configuration file; s3, analyzing the target configuration file, if Cn is set as a first identifier, adding A1n and B1n into a target compiling file list, and if Cn is set as a second identifier, adding A2n and B2n into the target compiling file list; s4, screening the standard cell library information file corresponding to at least one process corner from each standard cell library information file, and adding the standard cell library information file into a target compiling file list; and S5, compiling and generating a front-end low-power-consumption verification environment based on the target compiling file list. According to the invention, the generation efficiency and accuracy of the front-end low-power-consumption verification environment are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a front-end low-power verification environment generation method, electronic equipment, and medium. Background Art

[0002] Front-end low-power verification is an essential and critical step in chip verification. During the construction of the front-end low-power verification environment, the chip's Register-Transfer Level (RTL) code may be adjusted. In existing technologies, when chip RTL code is adjusted, the Unified Power Format (UPF) file must be manually adjusted, which is labor-intensive and error-prone, resulting in low efficiency in generating the front-end low-power verification environment. Furthermore, the existing front-end low-power verification environment generation process requires compilation based on all standard cell library information files. However, the number of standard cell library information files is enormous, and the front-end low-power verification environment does not require a real voltage simulator or real sensors, thus not requiring all standard cell library information files. However, in existing technologies, the front-end low-power verification environment is compiled based on all standard cell library information files, further reducing its generation efficiency. Therefore, improving the generation efficiency and accuracy of the front-end low-power verification environment has become a pressing technical issue to be addressed. Summary of the Invention

[0003] The present invention aims to provide a method for generating a front-end low-power consumption verification environment, an electronic device and a medium, thereby improving the generation efficiency and accuracy of the front-end low-power consumption verification environment.

[0004] According to a first aspect of the present invention, a method for generating a front-end low-power consumption verification environment is provided, comprising: Step S1: Obtain the register transfer level code information set {A1, A2, ..., A n ,...,A N} and unified power consumption format information set {B1,B2,...,B n ,...,B N}, A n B is the register transfer level code information corresponding to the nth chip component module, n The power consumption information corresponding to the nth group of chip components, n ranges from 1 to N, N is the total number of chip components, A n =(A1 n ,A2 n ), A1 n Register transfer level code file for the nth chip module, A2 n The interface code file for the nth chip module, Bn =(B1 n ,B2 n ), B1 n The unified power consumption format file corresponding to the nth chip component module, B2 n The interface power connection information corresponding to the nth chip component module, where the chip component module is composed of interconnected standard cells; Step S2: Get the target configuration file {C1, C2, ..., C n ,...,C N}, C n The configuration information of the nth chip module, C n Configured as a first identifier or a second identifier; Step S3: parse the target configuration file. If C n Set as the first identifier, then A1 n and B1 n Add to the target compilation file list, if C n Set as the second identifier, then A2 n and B2 n Add target compilation file list; Step S4: selecting at least one standard cell library information file corresponding to a process corner from each standard cell library information file and adding the file to the target compilation file list; Step S5: compile and generate a front-end low-power verification environment based on the target compilation file list.

[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0007] The present invention has significant advantages and beneficial effects compared to existing technologies. Through the above technical solution, the present invention provides a front-end low-power verification environment generation method, electronic device, and medium that can achieve considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects: The present invention can automatically acquire a register transfer level code information set and a unified power consumption format information set, and then generate a target compilation file list based on a target configuration file. Furthermore, the present invention can filter at least one standard cell library information file corresponding to a process corner from each standard cell library information file and add it to the target compilation file list. Ultimately, the front-end low-power verification environment is compiled based on the target compilation file list. This invention improves the efficiency and accuracy of generating the front-end low-power verification environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A flow chart of a method for generating a front-end low-power verification environment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0011] The embodiment of the present invention provides a method for generating a front-end low-power verification environment, such as Figure 1 As shown, including: Step S1: Obtain the register transfer level code information set {A1, A2, ..., A n ,...,A N} and unified power consumption format information set {B1,B2,...,B n ,...,B N}, A n B is the register transfer level code information corresponding to the nth chip component module, n The power consumption information corresponding to the nth group of chip components, n ranges from 1 to N, N is the total number of chip components, A n =(A1 n ,A2 n ), A1 n Register transfer level code file for the nth chip module, A2 n The interface code file for the nth chip module, B n =(B1n ,B2 n ), B1 n The unified power consumption format file corresponding to the nth chip component module, B2 n The interface power connection information corresponding to the nth chip component module is composed of interconnected standard units.

[0012] Among them, the chip design register transfer level code file is a key abstract level in the chip design process, which is used to describe the interconnection relationship between chip component modules and chip component modules, specifically the data flow and logical operations between registers in digital circuits. The chip power management strategy information defined by the unified power consumption format file includes information such as power domain, power consumption mode, isolation logic, and retention logic. The standard unit hierarchical setting in the chip component module, that is, the standard unit interconnection can form a unit, the chip component unit and the standard unit can be further interconnected to form a chip component unit, and the chip component unit and the standard unit can be hierarchically set, that is, the standard unit has no sub-module, the sub-module of the chip component unit can be a chip component unit or a standard unit, and the sub-module of the chip component module can be a chip component unit and a standard unit. The chip can specifically be a GPU (Graphics Processing Unit) chip.

[0013] Step S2: Get the target configuration file {C1, C2, ..., C n ,...,C N}, C n The configuration information of the nth chip module, C n Configured as the first identifier or the second identifier.

[0014] It should be noted that during the front-end low-power verification process, it is not necessary to pay attention to all chip component modules. In order to improve the efficiency of the front-end low-power verification and save resources, different chip component modules can be set with different identifiers through the target configuration file. If the first identifier is configured, it means that the corresponding chip component module is the module that needs to be paid attention to during the front-end low-power verification process. If the second identifier is configured, it means that the corresponding chip component module is the module that does not need to be paid attention to during the front-end low-power verification process.

[0015] Step S3: parse the target configuration file. If C n Set as the first identifier, then A1 n and B1 n Add to the target compilation file list, if C n Set as the second identifier, then A2 n and B2 n Add to the target compilation file list.

[0016] Modules that require attention need to completely load the corresponding code information, while modules that do not require attention only need to load the corresponding interface code files and the corresponding interface power connection information to ensure that the normal operation of the modules that require attention is not affected.

[0017] Step S4: Filter at least one standard cell library information file corresponding to a process corner from each standard cell library information file and add it to the target compilation file list.

[0018] In the field of low-power chips, Corner (process corner) is a way to describe the range of device parameter variations in the manufacturing process. It represents the extreme combination of process, voltage, and temperature and is used to verify the performance and power consumption of the chip under various conditions.

[0019] Step S5: compile and generate a front-end low-power verification environment based on the target compilation file list.

[0020] It should be noted that the generated front-end low-power verification environment is the design under test (DUT) for front-end low-power verification.

[0021] As an embodiment, step S1 further includes: Step S10: If the code information of the nth chip component module needs to be updated, then update A synchronously. n and B n , based on the updated {A1,A2,...,A n ,...,A N} and {B1,B2,...,B n ,...,B N}Execute step S2.

[0022] It should be noted that, through the above solution, when the chip RTL code is adjusted, there is no need to manually adjust the unified power consumption format, but automatically adjust the corresponding A n and B n , then based on the updated {A1,A2,...,A n ,...,A N} and {B1,B2,...,B n ,...,B N} to automate subsequent steps and generate a front-end low-power verification environment.

[0023] In one embodiment, the process corner includes identification information, a temperature value, and a voltage value. The name of each standard cell library information file includes the identification information, temperature value, and voltage value corresponding to the process corner. The identification information includes a typical process corner identifier and an atypical process corner identifier. It should be noted that the typical process corner identifier refers to a designated typical process corner, while the atypical process corner refers to an ordinary process corner. When screening standard cell library information files, the standard cell library information files corresponding to the typical process corners are preferentially selected.

[0024] A front-end low-power verification environment doesn't require a real voltage simulator or sensors, so not all standard cell library information files are required. Loading all standard cell library information files would increase compilation time. However, each standard cell requires at least one process corner to have all the corresponding standard cell library information files. The following two examples further illustrate the screening method.

[0025] Example 1 The step S4 comprises: Step S41, obtain the standard cell library information file set {D1, D2, ..., D m ,...,D M}, D m is the library file set of the mth standard unit, the value range of m is 1 to M, M is the total number of standard units, D m ={D1 m ,D2 m ,...,D i m ,...,D f(m) m}, D i m D m The i-th standard cell library information file, i ranges from 1 to f(m), and f(m) is the total number of library files for the m-th standard cell.

[0026] It is understandable that when m takes different values, f(m) may be different. Different when m takes the same value and i takes different values, different D i m They may belong to the same process corner or different process corners.

[0027] Step S42, traverse each D i m The name will include the D of the typical process angle identification i m As candidate D i m Added to the first candidate standard cell library information file set.

[0028] It should be noted that, although a portion of standard cell library information files can be filtered out through typical process corner identification, the number of standard cell library information files can still be further reduced.

[0029] Step S43, traverse each candidate D in the first candidate standard cell library information file set i m , the candidate D whose temperature value is the preset temperature value and whose voltage value is the preset voltage value i m Determined as target D i m .

[0030] It can be understood that in step S43, the combination of the preset temperature value and the preset voltage value is used as the screening condition, the preset temperature value is the temperature contained in the library file corresponding to each standard cell, and the preset voltage value is the voltage value contained in the library file corresponding to each standard cell. By screening the combination of the preset temperature value and the preset voltage value, the number of standard cell library information files can be further reduced, and it can also be ensured that each standard cell requires at least one process corner to have corresponding all standard cell library information files.

[0031] Step S44: All targets D i m Add to the target compilation file list.

[0032] Example 2 The step S4 comprises: Step C41, obtain the standard cell library information file set {D1, D2, ..., D m ,...,D M}, D m is the library file set of the mth standard unit, the value range of m is 1 to M, M is the total number of standard units, D m ={D1 m ,D2 m ,...,D i m ,...,D f(m) m}, D i m D m The i-th standard cell library information file, i ranges from 1 to f(m), and f(m) is the total number of library files for the m-th standard cell.

[0033] It is understandable that when m takes different values, f(m) may be different. Different when m takes the same value and i takes different values, different D i mThey may belong to the same process corner or different process corners.

[0034] Step C42, traverse each D i m The name will include the D of the typical process angle identification i m As candidate D i m Added to the candidate standard cell library information file collection.

[0035] It should be noted that, although a portion of standard cell library information files can be filtered out through typical process corner identification, the number of standard cell library information files can still be further reduced.

[0036] Step C43, traverse each candidate D in the first selected standard cell library information file set i m , set the temperature value to the candidate D of the preset temperature value i m Determined as the second candidate D i m .

[0037] It should be noted that a portion of the standard cell library information files can be further filtered out by presetting the temperature value. At this time, there may be a portion of the second candidate D corresponding to the standard cells. i m The number of standard cells has met the requirements, and the second candidate D i m The number still needs to be further reduced.

[0038] Step C44: If the second candidate D corresponding to the i-th standard cell i m The number of is less than the preset threshold, then the second candidate D corresponding to the i-th standard unit is i m Determined as target D i m Add it to the target compilation file list, otherwise, execute step C45.

[0039] It should be noted that the preset threshold value is set according to specific application requirements.

[0040] Step C45, traverse the second candidate D corresponding to the i-th standard cell i m , the second candidate whose voltage value is the preset voltage value is determined as the target D i m Add to the target compilation file list.

[0041] As an embodiment, step S5 includes: Step S51: If the file corresponding to the nth chip component module in the target compilation file list is A1 n and B1 n , then B1 n Added low power information to A1 n In the middle, A1 n The corresponding standard cell in the target compilation file list is added to the low power consumption information of the standard cell library information file in A1 n middle.

[0042] Step S52: If the file corresponding to the nth chip component module in the target compilation file list is A2 n and B2 n , then B2 n Added low power information to A2 n In the front-end low-power verification environment, generate

[0043] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0044] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0045] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0046] Embodiments of the present invention can automatically acquire a register transfer level code information set and a unified power consumption format information set, and then generate a target compilation file list based on a target configuration file. Furthermore, the present invention can filter at least one standard cell library information file corresponding to a process corner from each standard cell library information file and add it to the target compilation file list. Ultimately, the front-end low-power verification environment is compiled and generated based on the target compilation file list. This invention improves the efficiency and accuracy of generating the front-end low-power verification environment.

[0047] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for generating a front-end low-power verification environment, characterized in that: include: Step S1: Obtain the register transfer level code information set {A1, A2, ..., A n ,...,A N } and unified power consumption format information set {B1,B2,...,B n ,...,B N }, A n is the register transfer level code information corresponding to the nth chip component module, B n The power consumption information corresponding to the nth group of chip components, n ranges from 1 to N, N is the total number of chip components, A n =(A1 n ,A2 n ), A1 n Register transfer level code file for the nth chip module, A2 n The interface code file for the nth chip module, B n =(B1 n ,B2 n ), B1 n The unified power consumption format file corresponding to the nth chip component module, B2 n The interface power connection information corresponding to the nth chip component module, where the chip component module is composed of interconnected standard cells; Step S2: Get the target configuration file {C1, C2, ..., C n ,...,C N }, C n The configuration information of the nth chip module, C n Configured as a first identifier or a second identifier; Step S3: parse the target configuration file. If C n Set as the first identifier, then A1 n and B1 n Add to the target compilation file list, if C n Set as the second identifier, then A2 n and B2 n Add target compilation file list; Step S4: selecting at least one standard cell library information file corresponding to a process corner from each standard cell library information file and adding the file to the target compilation file list; Step S5: compile and generate a front-end low-power verification environment based on the target compilation file list.

2. The method according to claim 1, characterized in that After step S1, the following steps are also included: Step S10: If the code information of the nth chip component module needs to be updated, then update A synchronously. n and B n , based on the updated {A1,A2,...,A n ,...,A N } and {B1,B2,...,B n ,...,B N }Execute step S2.

3. The method according to claim 1, characterized in that The process corner includes identification information, temperature value and voltage value. The name of each standard cell library information file includes identification information, temperature value and voltage value corresponding to the process corner. The identification information includes a typical process corner identification and an atypical process corner identification.

4. The method according to claim 3, characterized in that The step S4 comprises: Step S41, obtain the standard cell library information file set {D1, D2, ..., D m ,...,D M }, D m is the library file set of the mth standard unit, the value range of m is 1 to M, M is the total number of standard units, D m ={D1 m ,D2 m ,...,D i m ,...,D f(m) m }, D i m D m The i-th standard cell library information file, where i ranges from 1 to f(m), and f(m) is the total number of library files for the m-th standard cell; Step S42, traverse each D i m The name will include the D of the typical process angle identification i m As candidate D i m Adding to the first candidate standard cell library information file set; Step S43, traverse each candidate D in the first candidate standard cell library information file set i m , the candidate D whose temperature value is the preset temperature value and whose voltage value is the preset voltage value i m Determined as target D i m ; Step S44: All targets D i m Add to the target compilation file list.

5. The method according to claim 3, characterized in that The step S4 comprises: Step C41, obtain the standard cell library information file set {D1, D2, ..., D m ,...,D M }, D m is the library file set of the mth standard unit, the value range of m is 1 to M, M is the total number of standard units, D m ={D1 m ,D2 m ,...,D i m ,...,D f(m) m }, D i m D m The i-th standard cell library information file, where i ranges from 1 to f(m), and f(m) is the total number of library files for the m-th standard cell; Step C42, traverse each D i m The name will include the D of the typical process angle identification i m As candidate D i m Add to the candidate standard cell library information file collection; Step C43, traverse each candidate D in the first selected standard cell library information file set i m , set the temperature value to the candidate D of the preset temperature value i m Determined as the second candidate D i m ; Step C44: If the second candidate D corresponding to the i-th standard cell i m The number of is less than the preset threshold, then the second candidate D corresponding to the i-th standard unit is i m Determined as target D i m Add it to the target compilation file list, otherwise, execute step C45; Step C45, traverse the second candidate D corresponding to the i-th standard cell i m , the second candidate whose voltage value is the preset voltage value is determined as the target D i m Add to the target compilation file list.

6. The method according to claim 1, wherein The step S5 comprises: Step S51: If the file corresponding to the nth chip component module in the target compilation file list is A1 n and B1 n , then B1 n Added low power information to A1 n In the middle, A1 n The corresponding standard cell in the target compilation file list is added to the low power consumption information of the standard cell library information file in A1 n middle; Step S52: If the file corresponding to the nth chip component module in the target compilation file list is A2 n and B2 n , then B2 n Added low power information to A2 n In the front-end low-power verification environment, generate 7. The method according to claim 1, characterized in that The chip is composed of standard cell level settings in the module.

8. The method according to claim 1, characterized in that The chip is a GPU chip.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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