Light emitting diode packages with real-time processing and related methods

Abstract

Light emitting diode (LED) packages are disclosed, and more particularly, real-time digital communications for LED packages and related methods. The discrete LED packages are arranged for cascade communication. Each LED package is capable of individually receiving communications from the data stream, controlling operation of one or more LED chips, and performing real-time processing on at least one variable data value of the data stream. The LED package may include a real-time processor capable of processing data from the data values of the data stream and introducing the processed or altered data into the data stream at the same data value. LED packages are disclosed that can be assembled together to form an array, where each LED package can individually process data and send the processed data to the next downstream LED package. This real-time processing may be performed while providing various bit delays within each LED package.

Description

Technical Field

[0001] The present disclosure relates to light emitting diode (LED) packages, and more particularly to real-time processing and related methods for LED packages. Background Art

[0002] A light emitting diode (LED) is a solid-state device that converts electrical energy into light and generally includes one or more active layers (or active regions) of semiconductor material disposed between oppositely doped n-type and p-type layers. When a bias is applied across the doped layers, holes and electrons are injected into the active layer(s), where they recombine to generate emission, such as visible or ultraviolet light.

[0003] LEDs have been widely adopted in various lighting environments, including backlighting for liquid crystal display (LCD) systems (e.g., as a replacement for cold cathode fluorescent lamps) and direct-view LED displays. Applications utilizing LED arrays include vehicle headlamps, roadway lighting, lamps, and various indoor, outdoor, and specialty environments. Desirable characteristics of LED devices include high luminous efficacy and long life.

[0004] Large, multicolor, direct-view LED displays (including full-color LED video screens) typically consist of many individual LED panels, packages, and / or assemblies, providing an image resolution determined by the distance between adjacent pixels, or "pixel pitch." Direct-view LED displays typically include three-color displays with arrays of red, green, and blue (RGB) LEDs, and two-color displays with arrays of red and green (RG) LEDs. Other colors and color combinations may be used. For many LED display systems, it is desirable to form a set of LED colors for each pixel, such as the primary colors red, green, and blue (RGB), defining the vertices of a triangle (or polygon) on a chromaticity diagram. This polygon defines the so-called color gamut of the display device, whose area describes all possible colors the display device can produce. Driver printed circuit boards used to control LED displays are typically densely populated with the electrical devices used to drive the display pixels, including capacitors, field-effect transistors (FETs), decoders, microcontrollers, and more. As the pixel pitch of higher-resolution displays continues to decrease, the density of this electronics increases in response to the increasing number of pixels in a given panel area. This tends to increase the complexity and cost of LED panels used in display applications.

[0005] The art continues to seek improved LED array devices having small pixel pitches while overcoming limitations associated with conventional devices and production methods. Summary of the Invention

[0006] The present disclosure relates to light emitting diode (LED) packages, and more particularly to real-time digital communications for LED packages and related methods. Discrete LED packages are arranged for cascaded communications. Each LED package includes one or more LED chips, and each LED package is capable of individually receiving communications from a data stream, controlling the operation of the one or more LED chips, and performing real-time processing on at least one variable data value of the data stream. The LED package may include a real-time processor capable of processing data from a data value of the data stream and introducing the processed or altered data into the data stream as the same data value. Disclosed are LED packages that can be assembled together to form an array, wherein each LED package can individually process data and send the processed data to the next downstream LED package. Such real-time processing can be performed while providing various bit delays within each LED package.

[0007] In one aspect, a digital communication method includes: transmitting a digital communication from at least one light emitting diode (LED) package to at least one other component, the digital communication comprising a bit pattern, the bit pattern comprising at least one variable data value; and performing real-time processing on the at least one variable data value within the at least one LED package. In some embodiments, the at least one variable data value comprises at least 2 bits and up to 64 bits. In some embodiments, the at least one variable data value is a data position value within a data stream, the data position value relating to a position of a data value within a data stream segment of the data stream, the data value being specific to the at least one LED package. In some embodiments, at least one LED package is a first LED package among a plurality of LED packages connected in series to receive digital communications from a data stream, the first LED package being arranged to receive the digital communications before other LED packages among the plurality of LED packages; the data value precedes a first data segment among a plurality of data segments of the data stream segment, wherein each data segment among the plurality of data segments is for a different LED package among the plurality of LED packages; and the data stream segments are arranged in reverse order such that the first data segment for the first LED package is received after the other data segments among the plurality of data segments for the other LED packages are received by the first LED package. In some embodiments, the at least one variable data value is a delay value associated with a delay time when the at least one LED package performs one or more events. In some embodiments, the at least one LED package is a first LED package among the plurality of LED packages connected in series to receive digital communications; and the delay value is varied such that two or more other LED packages among the plurality of LED packages have events synchronized with one or more events of the first LED package. In some embodiments, the real-time processing includes at least one of adding, subtracting, multiplying, dividing, incrementing, or decrementing a received value of the at least one variable data value.

[0008] In another aspect, a method for timing operation of at least one light emitting diode (LED) package for cascaded serial communication includes: receiving one or more synchronization values ​​at the at least one LED package; providing a delayed response associated with the one or more synchronization values; and operating the at least one LED package based on the delayed response. In certain embodiments, the one or more synchronization values ​​are modified for use by subsequent LED packages through real-time processing within the at least one LED package. In certain embodiments, the delayed response is synchronized with another delayed response of at least one other LED package that is arranged to receive the cascaded serial communication. In certain embodiments, the start of the delayed response is controlled by an initial timing value of a counter that is the result of a calculation, wherein the counter rate of the counter is at least partially synchronized with the data rate of the cascaded serial communication. In certain embodiments, the one or more synchronization values ​​are part of a variable data value, and the calculation is performed in real time such that one or more of the variable data values ​​are changed and transmitted in the same time slot as the variable data value. In certain embodiments, the calculation is based at least in part on other values ​​or states stored within the at least one LED package. In some embodiments, the delayed response includes at least one event; the at least one event is controlled by at least one event value; the at least one event value is an event type; and the event type includes one or more of: turning on, turning off, and setting one or more LED chips residing in at least one LED package to a predetermined value. In some embodiments, the at least one event is a series of synchronized events, including a first event in which all of the one or more LED chips are turned off for a specified amount of time, followed by a second event in which all of the one or more LED chips are turned on to achieve a desired brightness for the associated data frame. In some embodiments, the series of synchronized events further includes a third event and a fourth event occurring between the first and second events, wherein the third event includes turning on the one or more LED chips, and the fourth event includes turning off the one or more LED chips.

[0009] In another aspect, a digital communication method includes serially transmitting digital communications along a plurality of light emitting diode (LED) packages, the digital communications including data values ​​defined by a controller external to the plurality of LED packages, the data values ​​being directed to the plurality of LED packages and corresponding to variable-length data blocks of the digital communications. In some embodiments, the data values ​​are transmitted to the plurality of LED packages in the form of variable data values ​​of the digital communications, wherein the variable data values ​​are part of a bit pattern of the digital communications, the bit pattern also including at least a portion of a preamble for each data block, the preamble including at least one of the data values ​​initially defined by the controller and sequentially modified by each of the plurality of LED packages. In some embodiments, at least one of the data values ​​corresponds to a data position within the variable-length data block, the data position representing a plurality of data segments within the variable-length data block, and each data segment being directed to a different LED package from the plurality of LED packages. In some embodiments, a first LED package among a plurality of LED packages is arranged to receive digital communications before other LED packages among the plurality of LED packages; and a last data segment among the plurality of data segments is targeted at the first LED package, such that the plurality of data segments are arranged in a reverse order, and the last data segment is received by the first LED package after the other data segments among the plurality of data segments for the other LED packages are received by the first LED package.

[0010] In another aspect, an LED package includes: at least one LED chip; a digital communication receiving device configured to receive a communication signal from another LED package; and a real-time processor configured to modify a variable data value of at least two consecutive bits of the communication signal received by the digital communication receiving device. In some embodiments, the variable data value is transmitted to a counter to provide a delayed response, and wherein the delayed response is related to at least one of the data rate of the communication signal, the internal clock of the LED package, or an external clock. In some embodiments, the real-time processor is configured to process and modify the variable data value so that the delayed response is synchronized with other LED chips in other LED packages arranged to receive the communication signal. The LED package may also include an event processor configured to activate a series of responses as delayed responses. In some embodiments, the real-time processor includes a data selector and a counter configured to associate the position of target data to be followed within the communication signal, and select the target data to input the data into the control logic within the LED package.

[0011] In another aspect, any of the aforementioned aspects (alone or together) and / or the individual aspects and features described herein can be combined to achieve additional advantages. Unless otherwise indicated herein, any of the disclosed features and elements can be combined with one or more other disclosed features and elements.

[0012] Those skilled in the art will understand the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0014] Figure 1 is a block diagram illustrating a system-level control scheme for a lighting device using cascade communication for series-connected light emitting diode (LED) packages.

[0015] Figure 2 Certain details of active electrical components according to the principles of the present disclosure Figure 1 Block diagram of an LED package.

[0016] Figure 3 Includes real-time logic Figure 2 Block diagram of a portion of the control logic.

[0017] Figure 4 is with Figure 3 A block diagram of a portion of similar control logic is provided for an embodiment where real-time logic performs the operation of a decrementing counter or decrementer.

[0018] Figure 5A is a block diagram illustrating cascaded communication and data bit processing for multiple LED packages according to the principles of the present disclosure.

[0019] Figure 5B is with Figure 5A The schematic diagram is similar to the schematic diagram and further illustrates the progression of the data bits through the LED package.

[0020] Figure 6 It shows that Figure 4 Schematic diagram of an embodiment of the control logic and the bit patterns received and processed by the real-time processor.

[0021] Figure 7 is with Figure 6 Same schematic, except that the data for each pixel is delayed in time by two bits so that each pixel is aligned when receiving its corresponding data along a common time axis.

[0022] Figure 8 is with Figure 7 Similar diagram, except that the data for each pixel is delayed in time by four bits so that each pixel is aligned when receiving its corresponding data along a common time axis. DETAILED DESCRIPTION

[0023] The embodiments described below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode for practicing these embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0024] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0025] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “on” another element, it may be directly on the other element, or directly extend onto the other element, or there may be intervening elements. Conversely, when an element is referred to as being “directly on” or extending “directly” “on” another element, there are no intervening elements. Similarly, it will be understood that when an element such as a layer, region, or substrate is referred to as being “on” another element or extending “on” another element, it may be directly on the other element or extend directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being “directly on” or extending “directly on” another element, there are no intervening elements. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements.

[0026] Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical", may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0027] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise," "comprising," "include," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It will also be understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted as idealized or overly formal unless expressly defined as such herein.

[0029] Embodiments are described herein with reference to schematic illustrations of embodiments of the present disclosure. Therefore, the actual sizes of layers and elements may be different, and due to, for example, manufacturing technology and / or tolerances, variations in the shapes of the illustrations are expected. For example, a region shown or described as a square or rectangle may have circular or curved features, and a region shown as a straight line may have some irregularities. Therefore, the regions shown in the figures are schematic, and their shapes are not intended to illustrate the precise shape of the region of the device, and are not intended to limit the scope of the present disclosure. In addition, for illustrative purposes, the size of a structure or region may be exaggerated relative to other structures or regions, and the size of the structure or region is therefore provided to illustrate the general structure of this theme, and the size of the structure or region may or may not be drawn to scale. Common elements between figures may be illustrated herein using common element numbers, and may not be repeatedly described subsequently.

[0030] The present disclosure relates to light emitting diode (LED) packages, and more particularly to real-time digital communications for LED packages and related methods. Discrete LED packages are arranged for cascaded communications. Each LED package includes one or more LED chips, and each LED package is capable of individually receiving communications from a data stream, controlling the operation of the one or more LED chips, and performing real-time processing on at least one variable data value of the data stream. The LED package may include a real-time processor capable of processing data from a data value of the data stream and introducing the processed or altered data into the data stream as the same data value. Disclosed are LED packages that can be assembled together to form an array, wherein each LED package can individually process data and send the processed data to the next downstream LED package. Such real-time processing can be performed while providing various bit delays within each LED package.

[0031] In cascaded digital communication, multiple electronic devices are arranged as repeaters to sequentially receive serial communications for operation. In the context of fine-pitch video displays, multiple LED packages are arranged in series as LED pixels to receive cascaded communication. The incoming signal for each LED pixel is generated by another component (such as a master controller or the previous LED pixel), and the bit stream of the incoming signal comes from the clock domain of one or more previous devices. Properly distributing communication signals to thousands of LED pixels presents challenges. LED packages need to be small to form pixels for high-resolution video displays, and these size limitations create further challenges.

[0032] All LED pixels in a video display need to be updated synchronously. One example is that screen updates can be synchronized with video recording or photography equipment to eliminate undesirable effects, such as uneven exposure of the captured display. Another example is that three-dimensional (3D) shutter glasses need to synchronize with the display frames for the left and right eyes. Common 3D display methods often include a so-called "blanking period," in which all LED pixels on the screen are simultaneously turned off for a period of time, such as 2 milliseconds (ms), at the beginning and / or end of each video frame. Some 3D display methods also require a brief flash of light during the blanking period. The flash of light during the blanking period serves as a signal to devices, such as 3D shutter glasses, to distinguish between left and right frames. Other 3D display methods use other communication media, such as radio between a controller and headphones, but still require synchronization and blanking between pixels when the shutter glasses switch from one side to the other. For the purposes of this discussion, synchronization means that the LED packages or LED pixels coordinate their actions at the same time or within 1 ms of each other. Synchronization can also include the coordinated action of individual LED pixels, so that individual or groups of LED pixels respond to their corresponding data with different delays. The above statement includes many other possibilities besides all LED pixels operating in the same way at the same time. For example, the flashing could be a vertical line that flashes rapidly from left to right on the screen, or any other timed pattern that involves a series of actions instead of flashing the screen.

[0033] As used herein, the terms "data stream" and "communication channel" are sometimes used interchangeably. However, a "data stream" generally refers to the non-physical representation of data flowing over time through a set of at least one communication channel, as well as the internal wiring and storage registers within various components, such as controllers and active electrical components. A data stream can also be referred to as digital communication between two components, such as a controller component sending digital communication and a receiver component receiving digital communication. A "communication channel" generally refers to the physical medium that carries the data stream. For example, a communication channel can include wires with associated electrical components, optical fibers, or even air, as in the case of radio, light, or sound waves. A given physical channel can also be divided in time or frequency to allow multiple "communication channels" to be used simultaneously within a single medium, such as by switching to different frequency bands. In some aspects, a communication channel can be embodied as a serial digital communication channel. Some aspects relate to a binary communication channel, which refers to a single wire with a common conductor (such as ground) that can typically only hold a high or low voltage value (e.g., a digital "0" or "1") at a time and is controlled by the output register of the preceding device. A two-wire differential signaling approach is also contemplated, but the preferred embodiment shown here primarily refers to a single-wire approach due to the increased complexity of providing more traces with a fine pitch display.

[0034] In certain aspects, the present disclosure relates to light-emitting devices including LEDs, LED packages, and related LED displays, and more specifically, to active control of LEDs within LED displays. An LED display may include rows and columns of LEDs forming an array of LED pixels. A particular LED pixel may include a cluster of LED chips of the same color or multiple colors, with exemplary LED pixels including a red LED chip, a green LED chip, and a blue LED chip. In certain embodiments, an LED package includes multiple LED chips forming at least one LED pixel, and multiple such LED packages may be arranged to form an array of LED pixels for an LED display. Each LED package may include its own active electrical component configured to receive control signals, such as brightness or grayscale levels or color selection signals, for the LED chips of the LED devices, and actively maintain an operational state when addressing other LED devices. In certain embodiments, the active electrical component may include active circuitry including one or more of a driver device, a signal conditioning or conversion device, a memory device, a decoder device, an electrostatic discharge (ESD) protection device, a thermal management device, and a detection device. The active electrical element also includes circuitry for facilitating communication with multiple unrelated clock domains, including the original clock domain from the controller and a local clock domain derived within the active electrical element. In this regard, each LED pixel of the LED display can be configured to operate using active matrix addressing with mixed clock domain communication. The active electrical element can be configured to receive one or more of an analog control signal, an encoded analog control signal, a digital control signal, and an encoded digital control signal. In this arrangement, a string of LED packages (each having its own active electrical element) can be arranged for serial communication, wherein each active electrical element receives data from a data stream and sends the data to the next active electrical element in the string of LED packages.

[0035] With active-matrix addressing, each LED pixel is configured to actively maintain an operating state or otherwise control a drive state, such as brightness, grayscale, or color selection, while addressing other LED pixels. This allows each LED pixel to maintain or otherwise independently control its drive state, providing improved viewing and / or image recording by reducing or eliminating the effects of low-frequency pulse beating from devices such as illumination sources, other pulsed displays, or image capture devices. Thus, each LED pixel can be configured to maintain its respective operating state via a continuous drive signal, including pulse-width modulation (PWM), rather than via conventional methods that use time-division multiplexing signal scanning between groups of pixels, which typically results in the addition of low-frequency components to the drive signal associated with passive-matrix addressing. In this regard, each LED pixel can include an active electrical chip or active electrical component, which may include a memory device and the ability to change the drive condition of the LED pixel based on the state stored in the memory of the active electrical component. In some embodiments, the continuous drive signal is a constant analog drive current, and in other embodiments where the brightness level can be controlled by a pulsed method (such as PWM), the continuous drive signal can refer to a PWM signal that is not interrupted by the time-division multiplexed scanning of other LED pixels within the array or sub-array. In some embodiments, the active electrical component can include active circuitry including one or more of a driver device, a signal conditioning or conversion device, a memory device, a decoder device, an ESD protection device, a thermal management device, a detection device, a voltage and / or current sensing device, a command processing device and circuitry, and the like. In various embodiments, the active electrical component comprises an integrated circuit chip, an application-specific integrated circuit (ASIC), a microcontroller, or a field-programmable gate array (FPGA). In some embodiments, the active electrical component can be configured to be programmable or reprogrammable after fabrication using various memory elements and logic incorporated within the active electrical component.

[0036] As used herein, the terms "active electrical chip," "active electrical element," or "active electrical component" include any chip or component that is capable of changing the driving conditions of an LED based on memory or other information that may be stored within the chip or component. As used herein, the terms "active LED pixel" and "smart LED pixel" may be used interchangeably and may refer to a device that includes one or more LED devices or chips that form a pixel and an active electrical element or chip as described above. In some embodiments, each LED pixel may include a single LED package that is configured as an active LED package, including multiple LED chips and active electrical elements as described above. In this way, the number of separate electrical devices required for an LED display, such as the separate electrical devices located on the back side of the LED panel of the LED display as previously described, may be reduced. In addition, the overall operating power required for operation of the LED panel may be reduced.

[0037] As used herein, in the context of real-time processing, the term "real-time" generally refers to processing performed within time constraints that allow uninterrupted processing of a data stream flowing through an LED package. For cascaded serial communication of LED packages, the data stream flows continuously through a group of serially connected LED packages. As used herein, real-time processing can be defined as data in a given block, or time slot, of a data stream being processed by an LED package, and as the data stream flows through the LED package, new data can be introduced into the same block by replacing or modifying the original data. By modifying the same data value in the data stream, real-time processing within the LED package occurs within given time constraints and without interrupting the data flow. This real-time processing can be performed within time constraints, typically less than 10 microseconds (μs). This provides real-time processing within the same time constraints for unprocessed data flowing through the LED package. In certain aspects disclosed herein, the LED package can be configured to perform real-time processing with certain bit delays (such as a 2-bit delay or a 4-bit delay), where certain data values ​​are processed within the same time delay as unprocessed blocks flowing through the LED package.

[0038] Figure 1 1 is a block diagram illustrating a system-level control scheme for a lighting device using cascade communication for series-connected LED packages 12. The lighting device may be embodied as an LED display, and each LED package 12 may form an LED pixel of the display. For such applications, the terms LED package and LED pixel may be used interchangeably, although it is recognized that an LED package may be composed of several LED pixels formed together in one assembly. Figure 1The dashed box in indicates an exemplary LED string 14 for serial communication. Although only a single LED string 14 is provided in detail, one or more other LED strings may also be coupled to the controller 16. As shown, the controller 16 is arranged to control one or more LED strings 14. The controller 16 may include an integrated circuit, such as one or more of an ASIC, a microcontroller, a programmable control element, and an FPGA. In some embodiments, the controller 16 may be referred to as a master controller for the LED strings 14. In other embodiments, the controller 16 may be a sub-controller to which another master controller (not shown) delegates a set of tasks as it belongs to a larger system. The data signal out (DOUT) of the controller 16 may be passed serially along the LED string 14, and a return data signal in (DIN) may be received back by the controller 16. This signal includes the original clock domain provided by the controller 16 or another master controller as described above. In Figure 1 In the embodiment, each LED package 12 or LED pixel is provided with a label such as "Px 1,1", where the first number represents a row and the second number represents a column. Each LED package 12 includes its own active electrical components 18 that are registered and housed therein so that each LED package 12 includes logic for responding to received data signals.

[0039] For cascaded serial communication of LED packages 12, important features include addressing data to a specific LED package 12, making the specific LED package 12 aware of its position in the LED string 14, and synchronizing the LED output with the other LED packages 1 of the display in a coordinated manner. One prior technique for addressing data to a specific LED package 12 involves having each LED package 12 strip off a data set and retransmit the remaining data along the LED string 14. However, this does not allow data to be returned in the data stream. Another prior technique for addressing data to a specific LED package 12 involves providing a command protocol in which an executed bit is marked by the LED package 12 for signaling to downstream LED packages 12 to ignore the corresponding data. As will be further described in more detail below, the present disclosure provides the above-mentioned important features with improved efficiency while effectively synchronizing the output of the LED packages 12 connected in series. Enhanced intercommunication is provided between LED packages 12 arranged as LED pixels, including communication of position and delay factors for directing specific data and synchronization for each LED pixel.

[0040] Figure 2 Certain details of an active electrical element 18 according to the principles of the present disclosure are provided. Figure 11 and 2. Block diagram of an LED package 12. According to embodiments disclosed herein, the active electrical component 18 may include a plurality of ports represented by a power supply voltage (Vdd), a ground (GND or Vss), and a bidirectional communication port or digital input / output port (DIO1 and DIO2). By having the DIO1 port and the DIO2 port as bidirectional communication ports, the active electrical component 18 may advantageously be able to detect an input signal from a communication channel and then assign one of the DIO1 port and the DIO2 port as an input port, and the other of the DIO1 port or the DIO2 port as an output port. This provides flexibility in the layout of a display where multiple LED packages 12 are connected together for cascade communication. For example, as Figure 1 As shown, multiple LED packages 12 can be arranged in multiple rows, wherein data is cascaded between packages along each row and in a serpentine manner between rows. In this arrangement, the bidirectional communication port allows the LED packages 12 to be mounted in the same orientation and receive and send digital communications from left to right or from right to left depending on the row position. In addition to the four ports of Vdd, GND, DIO1 and DIO2 on the left side of the block diagram, the active electrical component 18 also includes four ports on the right side, which are coupled to the LEDs 20-1 to 20-3 of the LED package 12. In this regard, the LEDs 20-1 to 20-3 are packaged together with the active electrical component 18 in a common LED package 12 to form a single pixel of a larger display. As used herein, the LEDs 20-1 to 20-3 may also be referred to as LED chips.

[0041] Certain elements of the active electrical components 18 are described below; however, it should be understood that the active electrical components 18 may include many other components, including memory components, signal conditioning components, thermal management, electrostatic discharge components, clock components and oscillators, etc. Figure 2 In the embodiment, the control logic 22 is arranged to receive input data, execute commands according to the command protocol, provide control signals for the operation of the LEDs 20-1 to 20-3, report various voltage levels and / or temperature levels included in the output data, and transmit the output data to the next adjacent LED package via the DIO1 port and the DIO2 port. The control logic 22 can operate in the digital domain and can include input / output buffers electrically coupled to the DIO1 port and the DIO2 port. These buffers assign input and output configurations to the bidirectional DIO1 port and the DIO2 port.

[0042] In some embodiments, the active electrical components 18 can be configured to provide forward and reverse bias conditions to the LEDs 20-1 to 20-3. In this regard, the control logic 22 can include a reverse bias control output signal that, through appropriate active components, can be configured to provide a voltage level close to Vdd or close to GND to the LEDs 20-1 to 20-3. Since the term "reverse bias" implies that a high level at the output of the control logic 22 creates a reverse bias condition, the output signal can simply be coupled to the inverter 24 provided in the driver 26 of the active electrical components 18. Thus, the LEDs 20-1 to 20-3 can be forward biased or reverse biased depending on the particular operating state and / or commands received by the control logic 22. The inverter 24 or inverter logic element can have sufficient output characteristics to drive the LEDs 20-1 to 20-3. The driver 26 can essentially be an analog interface for the active electrical components 18 electrically coupled to the control logic 22. Driver 26 may include controllable current sources 28-1 through 28-3, which may also be configured as LED sink drivers. Pull-up resistors R1 through R3 may be incorporated to provide each of LEDs 20-1 through 20-3 with a path to Vdd, which facilitates voltage measurement when configured for reverse bias. Each of current sources 28-1 through 28-3 may be electrically coupled to digital output signals LED1 through LED3 of control logic 22. Output signals LED1 through LED3 may be provided along multiple lines coupled to each of current sources 28-1 through 28-3 for current selection purposes. Output signals LED1 through LED3 may represent PWM outputs from control logic 22 for controlling the operation of LEDs 20-1 through 20-3. Driver 26 may also include a multiplexer 30 electrically coupled to an analog-to-digital (ADC) converter and ADC selector of control logic 22. Additionally, driver 26 may include an on-chip temperature sensor provided via multiplexer 30. In certain embodiments, temperature sensors provide thermal compensation for LEDs 20 - 1 to 20 - 3 through thermal compensation curves and / or thermal shutdown.

[0043] The active electrical element 18 also includes a serial interface 32, which embodies a module having circuitry configured to decode and convert the incoming signal of the data stream into a bit stream in the local clock domain, which can be further processed by the control logic 22. In this manner, the serial interface 32 can also be referred to as a digital communication receiving device. Digital communications can be received from a controller (e.g., Figure 116) and / or another LED package in the serial string. The serial interface 32 is also configured to retransmit the decoded and converted bit stream along with the modified data to another LED package or a communication channel to which another external component is connected in a manner compatible with the entire LED display system. In some embodiments, the control logic 22 may include circuitry in the form of real-time logic 34 that, when enabled by other logic within the active electrical component 18, performs operations, such as mathematical operations, on the data values ​​received from the serial interface 32. The real-time logic 34 immediately returns the processed results to the serial interface 32 in real time as described above for transmission as replacement data for the same data value. As used herein, the real-time logic 34 may also be referred to as a real-time processor. The control logic 22 may also include other circuitry, such as a finite state machine, which goes through a series of states or steps to perform a set of required tasks. In this way, one or more portions of the control logic 22 may form an event processor configured to activate a series of responses, such as delayed responses based on real-time processing.

[0044] Figure 3 It includes real-time logic 34 Figure 2 A block diagram of a portion of the control logic 22. Figure 3 The hash marks across the various conductors indicate that multiple lines or multiple signals may also be provided. The real-time logic 34 is configured to receive data from the data stream as a Figure 2 32 serial interface input for real-time processing. Figure 2 Unlike the multiplexer 30, the processed results or processed data can be enabled or disabled by the multiplexer 36. The multiplexer 36 is configured to select the desired signal to output back to the serial interface 32 and continue to output to the exit Figure 2 The desired signal for output can be selected from several possible signals received by the multiplexer 36, including processed data from the real-time logic 34, other internal signals from the control logic 22, or unprocessed input data that bypasses the real-time logic 34 for retransmission unchanged. Other internal signals from the control logic 22 can include cyclic redundancy check (ORC) codes and internal status values, among others.

[0045] Real-time logic 34 can be configured to perform any number of operations on input data for processing. Such operations include addition, subtraction, up-counting, down-counting, incrementing, decrementing, multiplication and division calculations, as well as simpler logical operations. As shown, real-time logic 34 can also be configured to receive one or more control signals. Such control signals can include a reset signal, a clock signal, and various function selection signals. Various function selection signals can include signals for turning real-time logic 34 on and off, signals for performing calculations, or signals for implementing other mathematical operations or processes. As further shown, a selection control signal can be provided to multiplexer 36 along one or more selection lines.

[0046] Figure 4 is with Figure 3 A similar block diagram of a portion of the control logic 22 is provided for an embodiment in which the real-time logic 34 performs the operation of a counter, such as a down counter or decrementer. In this configuration, Figure 4 Shown in Figure 3 The control signal line of the is used as a reset line and a clock line. By counting down to zero, an event is triggered that tells the control logic 22 to copy the next data value into the memory because this is the data value targeted for a particular LED package or pixel in the serial string. All other data values ​​can be ignored and repeated for consecutive LED packages. In this way, the real-time logic 34 can include a data selector configured with the counter to associate the location of the target data to be followed within the communication signal, and select the target data for input to the control logic 22 within the corresponding LED package.

[0047] exist Figure 4In the example, real-time logic 34 includes a register element 38, such as a flip-flop circuit, a data (D) flip-flop circuit, or a latch element, which can receive input from serial interface 32 via an AND gate 40 and an inverter 42. By way of example, the following operational discussion will be provided in the context of a D flip-flop circuit in register element 38. For proper operation, a reset signal is applied to register element 38 via the reset line prior to operation, setting register element 38 to a logic level of 1. This flip-flop maintains the borrow state of register element 38 as it subtracts a value of 1 from the input value, performing a subtractor function. Input data is introduced least significant bit (LSB) first. Exclusive OR (XOR) gate 44 performs the operation between the input data value and the borrow. Once the first value of 1 is introduced to the input, the borrow is no longer needed, and the borrow state becomes zero until it is reset for another decrement operation. In this case, the calculation performed by the countdown can be based at least in part on the data rate of the cascaded serial communication, allowing the counter to be synchronized with the data rate. The calculation can be based at least in part on a clock internal to the LED package or external to the LED package such that the counter is synchronized with the clock. In some embodiments, the start of the delayed response as described above can be controlled by an initial timing value of the counter as a result of the calculation, and the counter rate of the counter is at least partially synchronized with the data rate of the cascaded serial communication. Other values ​​or states stored within the LED package can also be taken into account in the calculation. For example, a received control signal can instruct the real-time logic 34 to select from incrementing or decrementing. In another example, a separately stored value can be used such that the value is subtracted from the incoming data, such as some other value in addition to one value. As Figure 4 As shown, the real-time logic 34 configured as a decrementer can be used to associate the location of the target data to be followed within the communication signal so that the target data can be selected as data input to the control logic within the LED package (e.g., Figure 2 22). An example of this process is detailed below.

[0048] Figure 5A is a block diagram 46 illustrating cascade communication and data bit processing for multiple LED packages 12-1 to 12-3 according to the principles of the present disclosure. The LED packages 12-1 to 12-3 may be arranged as Figure 11 to 12-3. The LED package 12-1 receives an input communication of a data stream 48 from the communication channel and transmits it from an input register 50 to an output register 52, which is graphically shown as a box within the LED package 12-1. The input register 50 and the output register 52 represent memory locations within the active electrical components 18. The data stream may include a bit pattern of data blocks of any length, where the bits are numbered 1, 2, 3, 4, ... n. The data blocks may include command codes that are processed by the active electrical components 18 of each LED package 12-1 to 12-3 to control the action of the corresponding active electrical component 18 and / or control the operation of the corresponding LED within the LED packages 12-1 to 12-3.

[0049] During operation, each data bit of a data block is sequentially received and held by input register 50 during one clock count, and then transferred to output register 52 on the next clock count. In this way, data stream 48 may be subject to a two-bit delay during processing. In other cases, other delays (such as a four-bit delay) may be provided by other registers within active electrical element 18. In some cases, according to Figure 2 The real-time logic 34 changes or modifies the bit data transmitted to the output register 52.

[0050] Figure 5B is with Figure 5A Schematic diagram 54 is similar to schematic diagram 46 and further illustrates the progression of data bits through the LED packages 12-1 to 12-3. As shown, the bit positions of a data block may be sequentially shifted from left to right through the input register 50 and the output register 52 of the plurality of LED packages 12-1 to 12-3 according to a clock cycle. In this manner, the first bit position (i.e., "1") of the data block may already be held in the input register 50 of the third LED package 12-3, while bit positions "2" and "3" are in the second LED package 12-2, bit positions "4" and "5" are in the first LED package 12-1, and the remaining bit positions have not yet been received by the LED packages 12-1 to 12-3. Figure 5B In FIG, an overlay box is shown above the input register 50 and the output register 52 to represent a block of data, wherein the corresponding bit positions are now distributed among the plurality of LED packages 12-1 to 12-3. The internal logic of the active electrical element 18 may include the above-mentioned Figure 2 3. The real-time logic 34 described above performs real-time processing during the flow of the data stream 48. Thus, the next value of each output register 52 may be based on the internal state of the logic and the value of the input register 50. This real-time processing involves manipulating bits or data values ​​of a block of data and altering the data stream at the same time slot as the processed bits or processed data values.

[0051] Figure 6 It shows that Figure 4 Schematic diagram 56 of an embodiment of a bit pattern received and processed by the control logic 22 and the real-time logic 34. For simplicity, the data element or pixel data size is shown as an 8-bit byte, but in an actual system, the corresponding element may require more bits, such as the number of bytes and individual pixel data blocks. The pixel 1, pixel 2 and pixel 3 input rows represent the pixel data of the pixel 1, pixel 2 and pixel 3 input rows. Figure 5A and Figure 5B The inputs to each of the three LED packages 12-1 to 12-3 shown in FIG. The row alignment of the pixel 1, pixel 2, and pixel 3 inputs does not mean that the timing of each vertical column is the same.

[0052] During the flow of data, pixel 1 receives its input and produces an output, which becomes the input of pixel 2, and so on. The pixel 3 output row represents the output data from pixel 3, which can be the input of another downstream pixel or returned to a main controller such as Figure 1 This is part of a data stream from a controller 16 (e.g., a controller 16). For simplicity, various "x" values ​​are shown to represent values ​​in the data stream that may not be relevant to the real-time processing principles discussed herein. The bit pattern of the data or data block represented includes a command byte, which, along with other information, tells pixels 1-3 what type of data set to follow. This is followed by a 3-byte preamble, labeled Digital Byte-1, Synchronization Value, and Digital Data Unit-1, representing one or more data values ​​of the bit pattern.

[0053] Digital Byte-1 provides information to pixels 1-3 about how many bytes follow the preamble so that pixels 1-3 know when to expect the end of the bit pattern and perhaps another command. Figure 6In the example, for a 3-byte zero count, the value is set to "2" and does not change between pixels. The synchronization value is a timing value used to provide pixels 1-3 with information about when to initiate an event or series of events. Pixel 1 receives the command first, but its corresponding data segment (i.e., pixel 1 data) is received last, after the pixel 3 data and pixel 2 data segments have flowed through. This arrangement of the bit pattern can be described as a reverse ordering of the data segments (i.e., pixel 3 data, pixel 2 data, then pixel 1 data) relative to the order of the pixels in the string (e.g., pixel 1, pixel 2, and then pixel 3). Therefore, pixel 1 requires a longer delay after receiving the command than the subsequent downstream pixels 2 and 3. Therefore, pixel 1 receives a higher synchronization value, which is implemented by pixel 1 to set the timer to trigger the start event signal. In many cases, this delay can be calculated locally by pixel 1 based on digital byte-1 and digital data unit-1, or vice versa. Therefore, the synchronization value can be considered redundant. However, this data redundancy can be advantageous because it requires less computational resources within pixels 1-3. During the processing of pixel 1, the synchronization value is decremented by one for the input of pixel 2, and so on for each additional pixel. In this example, digital data unit -1 is another zero-based number indicating the number of pixel data units to ignore before accepting the target data sub-block for the pixel. That is, digital data unit -1 is implemented to inform each of pixels 1-3 of its expected data. Figure 6 In this example, pixel 3 is the last pixel in the serial string, and therefore, the pixel 3 output of digital data unit -1 is sent back to the host controller with a value of all 1s. This is because during real-time processing, synchronization values ​​are processed, and the value of digital data unit -1 is decremented as the data flows through each pixel. Once this value reaches zero, the next value (-1) will be represented as all ones in binary as the counter rolls over.

[0054] The synchronization value portion and / or the digital data unit-1 portion of the bit pattern can collectively form a variable data value on which real-time processing is performed. The synchronization value portion and / or the digital data unit-1 portion can also be referred to as two variable data values ​​on which real-time processing is performed. In some embodiments, the variable data value can include at least two data bits. In further embodiments, the variable data value can include any number of bits, for example, up to about 64 bits, which corresponds to the standard width of a double-precision floating point number. Further embodiments can include a set of these numbers manipulated via the real-time logic 34. The variable data value (digital data unit-1) refers to a data position value within a data stream that is related to the position of a data value within a data stream segment of the data stream, which data value is for a particular pixel 1-3. As the variable data value flows through each of the pixels 1-3, it can be processed and modified. Depending on the application, the length of the variable data value may be variable during the cascade communication. That is, the length of the synchronization value portion and / or the digital data unit-1 portion can be modified during real-time processing based on a value specified by an external controller (e.g., Figure 1 16) The bit pattern provided varies as part of the preamble.

[0055] Through this real-time processing, variable data values ​​(synchronization values) form delay values ​​for pixels 1-3, synchronizing and responding to data stream commands in a coordinated manner. In this way, the delay values ​​provide a relative delay time or delayed response when each pixel 1-3 performs one or more events, such as turning on, off, or setting one or more LED chips within each pixel 1-3 to a predetermined value. The delay values ​​are varied as they flow through each pixel 1-3, allowing each downstream pixel to substantially synchronize corresponding events.

[0056] To further illustrate how to use synchronized values, Figure 7 is with Figure 6 The same schematic 58, except that the data for each pixel 1-3 is delayed in time by two bits so that each pixel 1-3 is aligned when receiving its corresponding data along a common time axis. Thus, the row alignment of the pixel 1, pixel 2, and pixel 3 inputs represents the same time position for each vertical column of all pixels 1-3. Figure 7 As the data shifts to the right, time increases to the left. As previously mentioned, the synchronization value is introduced with an initial value and is decremented by one by each pixel 1-3. The decremented value is passed to the next pixel 1-3, but the input value is loaded into the internal down counter with only one bit shift, resulting in the loaded value being twice the original value (i.e., 12 loaded into the down counter of pixel 1 becomes 24). Each pixel 1-3 counts down from that number every clock cycle based on the reception or association of each bit. When the counter reaches zero, as Figure 7The synchronization event trigger shown is triggered. The internal logic within the active electrical elements of each pixel 1-3 can use this event trigger to further delay and trigger a series of events, such as blanking, blinking, and starting a new brightness level for the corresponding LED chip. In one example, a series of synchronization events provides blanking, wherein a first event turns off all pixels 1-3 for a specified amount of time, followed by a second event that turns all pixels 1-3 on to the desired brightness of the associated data frame. In another example, the series of events may also include a third event and a fourth event occurring between the first and second events, wherein the third event includes turning on the pixels 1-3, and the fourth event includes turning off the pixels 1-3 to provide a light pulse during the blanking period that can be used for left-right synchronization of 3D glasses. Figure 7 The two-bit shift shown corresponds to a two-bit delay as previously described.

[0057] The time series for each of pixels 1-3 has vertical tick marks indicating the start count position 60-1 to 60-3, the 1x count 62-1 to 62-3, and the 2x count 64-1 to 64-3. As shown, the 2x count 64-1 to 64-3 occurs simultaneously for all three pixels. Specifically, the count position 64-1 to 64-3 triggers the synchronization event trigger. At this point, all three pixels 1-3 have also received their target data segment because pixel 1 received its data last. The triggering event at this point may initiate internal processes in each pixel 1-3 to execute synchronously. This can include outputting a new LED brightness value, as well as other actions. Each event type is associated with one of several possible actions, such as turning one or more LED chips on, off, or setting them to a predetermined value.

[0058] Figure 7 An exemplary embodiment is shown to illustrate various aspects of the present disclosure. Actual implementations may require wider word widths for the three values ​​in the pixel data and preamble. The preamble values ​​typically require two bytes each. For color depths between 24 and 48 bits, each pixel 1-3 requires three, four, five, or six bytes. Many other embodiments are contemplated. If the delay between pixels is Figure 7 If the two-bit delay shown is different, the calculations and / or values ​​will change. Instead of loading 4x the data byte length in the initial synchronization value, 8x the data byte length can be loaded, and the countdown is performed twice for each pixel, and this value can be used without shifting (e.g., a 2x multiplication). As previously mentioned, the synchronization value can be omitted from the preamble and calculated internally based on the other two values. As shown, many modifications to this method are contemplated within the scope of the present disclosure.

[0059] Figure 8 is with Figure 7Similar to diagram 66, except that the data segments for each pixel 1-3 are delayed in time by four bits so that each pixel 1-3 is aligned when receiving its corresponding data along a common time axis. Figure 7 Likewise, the row alignment of the pixel 1, pixel 2, and pixel 3 inputs represents the same temporal position for each vertical column of all pixels 1-3. Figure 8 The four-bit shift shown corresponds to real-time processing with a four-bit delay as previously described. Figure 8 , the synchronization value is changed so that the synchronization event triggering of the counting positions 64-1 to 64-3 occurs simultaneously for all pixels 1-3. Figure 7 The 2-bit delay example receives its data segment in a similar manner. In this example, the value 6 (i.e., 00000110) for pixel 1 is loaded into the counter with a 2-bit shift (4x multiplication). In this manner, pixel 1 still counts down 24 clock cycles to trigger the synchronization event, while pixel 2 counts down 20 cycles, and pixel 3 counts down 16 cycles.

[0060] In some aspects, Figures 6 to 8 The sequence shown in represents a synchronization configuration and method that will use a real-time processor (e.g., Figure 2 34) is combined with a technique for counting from a given position (such as a command) to a synchronous trigger event. In this way, the real-time processor is configured to perform real-time processing on the same variable data value during the serial communication. In other aspects, the above sequence can be performed without having a real-time processor within each pixel 1-3. Instead, the value can be loaded into the pixel 1-3 in any number of other ways, such as through the same command as the brightness value. In other embodiments, the data stream command can be combined with the real-time processor within each pixel 1-3 (for example, Figure 2 The real-time processing of 34) loads the values ​​into pixels 1-3.

[0061] In some aspects, Figures 6 to 8 The sequence shown in can represent a synchronization configuration and method for data without the digital byte-1, synchronization value and preamble of the digital data unit-1. Instead, separate commands and / or data can provide parameters for pixels 1-3, such as the data length and its corresponding data offset. In other words, the method for synchronization and corresponding data offset proposed herein can be adopted without the use of real-time processing by storing the value of each pixel 1-3 so that it can be pre-counted by other means. In turn, pixels 1-3 can count data using the digital byte-1, synchronization value and preamble of the digital data unit-1 as described above. In some embodiments, an external data source (such as Figure 1The controller 16 can define the variable length data segments and the number of data segments to be provided to each pixel 1-3. In some embodiments, the variable length data segments and the variable number of data segments can be processed by a real-time processor within each pixel 1-3 (e.g., Figure 2 34) is combined with real-time processing to achieve this.

[0062] According to the above-described embodiments, discrete LED packages can be assembled together for cascaded communication within LED arrays for various applications. In one such application, the discrete LED packages form LED pixels in an LED display. Each LED package may include one or more LED chips, which together with active electrical components form at least one individual pixel. The active electrical components are capable of receiving serial communications from a data stream, controlling the operation of the one or more LED chips based on commands received in the data stream, and performing real-time processing on various data values ​​in the data stream. The active electrical components within each LED package may include circuitry in the form of a real-time processor capable of processing data from a data value or time slot of the data stream and introducing the processed or modified data into the data stream within the same data value or time slot. In this way, each LED package in an LED display can independently process data and transmit the processed data to the next downstream LED package. In some embodiments, this real-time processing can be performed while providing various bit delays within each active electrical component, such as a two-bit delay or a four-bit delay. Performing real-time processing individually at each LED package or LED pixel in a display offers various advantages, including the ability to synchronize and / or coordinate the actions of series-connected LED packages. Also according to the above embodiment, a method for directing certain segments of a larger data block to corresponding pixels is disclosed. In addition, a method for synchronizing the behavior of multiple pixels is also disclosed.

[0063] It is contemplated that any of the aforementioned aspects and / or the individual aspects and features described herein may be combined to achieve additional advantages. Any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments, unless otherwise indicated herein.

[0064] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A digital communication method, comprising: sending a digital communication from at least one light emitting diode (LED) package to at least one other component, the digital communication comprising a bit pattern, the bit pattern comprising at least one variable data value; as well as Real-time processing is performed on the at least one variable data value within at least one LED package.

2. The method according to claim 1, wherein The at least one variable data value includes at least 2 bits to 64 bits.

3. The method according to claim 1, wherein The at least one variable data value is a data position value within the data stream, the data position value relating to a position of a data value within a data stream segment of the data stream, the data value being for the at least one LED package.

4. The method according to claim 3, wherein: the at least one LED package being a first LED package of a plurality of LED packages connected in series to receive the digital communication from the data stream, the first LED package being arranged to receive the digital communication before other LED packages of the plurality of LED packages; The data value precedes a first data segment of a plurality of data segments of the data stream segment, wherein each data segment of the plurality of data segments is for a different LED package of the plurality of LED packages; and The data stream segments are arranged in reverse order such that the first data segment for the first LED package is received after the other data segments of the plurality of data segments for the other LED packages are received by the first LED package.

5. The method according to claim 1, wherein The at least one variable data value is a delay value associated with a delay time when the at least one LED package performs one or more events.

6. The method according to claim 5, wherein: The at least one LED package is a first LED package of a plurality of LED packages connected in series to receive the digital communication; and The delay value is varied such that two or more other LED packages of the plurality of LED packages have events that are synchronized with the one or more events of the first LED package.

7. The method according to claim 1, wherein The real-time processing includes at least one of adding, subtracting, multiplying, dividing, incrementing, or decrementing a received value of the at least one variable data value.

8. A method for timing operation of at least one light emitting diode (LED) package for cascade serial communication, the method comprising: receiving one or more synchronization values ​​at the at least one LED package; providing a delayed response associated with the one or more synchronization values; as well as The at least one LED package is operated according to the delayed response.

9. The method according to claim 8, wherein The one or more synchronization values ​​are modified by real-time processing within the at least one LED package for use by subsequent LED packages.

10. The method according to claim 8, wherein The delayed response is synchronized with another delayed response of at least one other LED package arranged to receive the cascaded serial communication.

11. The method according to claim 8, wherein The start of the delayed response is controlled by an initial timing value of a counter as a result of the calculation, wherein a counter rate of the counter is at least partially synchronized with a data rate of the cascaded serial communication.

12. The method according to claim 11, wherein The one or more synchronization values ​​are part of a variable data value, and the calculation is processed in real time such that one or more of the variable data values ​​are changed and transmitted in a same time slot as the variable data value.

13. The method according to claim 11, wherein The calculation is based at least in part on other values ​​or states stored within the at least one LED package.

14. The method according to claim 8, wherein: The delayed response includes at least one event; The at least one event is controlled by at least one event value; The at least one event value is an event type; and The event types include one or more of: turning on, turning off, and setting one or more LED chips residing within the at least one LED package to a predetermined value.

15. The method according to claim 14, wherein The at least one event is a series of synchronized events comprising a first event of turning off all of the one or more LED chips for a specified amount of time, followed by a second event of turning on all of the one or more LED chips to achieve a desired brightness for an associated data frame.

16. The method according to claim 15, wherein: The series of synchronous events further includes a third event and a fourth event occurring between the first event and the second event, wherein the third event includes turning on the one or more LED chips, and the fourth event includes turning off the one or more LED chips.

17. A digital communication method, the method comprising: Digital communications are serially transmitted along a plurality of light emitting diode (LED) packages, the digital communications including data values ​​defined by a controller external to the plurality of LED packages, the data values ​​being directed to the plurality of LED packages and corresponding to variable length data blocks of the digital communications.

18. The method according to claim 17, wherein The data value is transmitted to the multiple LED packages in the form of a variable data value of the digital communication, wherein the variable data value is part of the bit pattern of the digital communication, and the bit pattern also includes at least a part of the preamble code of each data block, and the preamble code includes at least one of the data values ​​initially defined by the controller, and the data value is modified in turn by each LED package of the multiple LED packages.

19. The method according to claim 17, wherein At least one of the data values ​​corresponds to a data position within the variable-length data block, the data position representing a plurality of data segments within the variable-length data block, and each data segment is for a different LED package of the plurality of LED packages.

20. The method of claim 19, wherein: A first LED package of the plurality of LED packages is arranged to receive the digital communication before other LED packages of the plurality of LED packages; and The last data segment of the multiple data segments is for the first LED package, so that the multiple data segments are arranged in reverse order, and the last data segment is received by the first LED package after the other data segments of the multiple data segments for the other LED packages are received by the first LED package.

21. A light emitting diode (LED) package, comprising: at least one LED chip; a digital communication receiving device configured to receive a communication signal from another LED package; as well as A real-time processor is configured to modify a variable data value of at least two consecutive bits of the communication signal received by the digital communication receiving device.

22. The LED package according to claim 21, wherein The variable data value is communicated to a counter to provide a delayed response, and wherein the delayed response is related to at least one of a data rate of the communication signal, an internal clock of the LED package, and an external clock.

23. The LED package according to claim 22, wherein: The real-time processor is configured to process and modify the variable data value such that the delayed response is synchronized with other LED chips in other LED packages arranged to receive the communication signal.

24. The LED package according to claim 22, further comprising: The event processor is configured to activate a series of responses as the delayed response.

25. The LED package according to claim 21, wherein The real-time processor includes a data selector and a counter configured to associate a location of target data to be followed within the communication signal and select the target data for inputting data into control logic within the LED package.

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