High real-time radio frequency simulation architecture and real-time synchronous control method

Abstract

The invention discloses a high real-time radio frequency simulation architecture and a real-time synchronous control method, an optical fiber reflection memory network based on star topology is composed of an optical fiber reflection memory card and a switch, and real-time data interaction between a digital simulation scene and hardware equipment is achieved; the transmission efficiency is optimized through an instruction and data partition transmission mechanism; the hard synchronization module generates a synchronization pulse signal by using a timer card, and cooperates with a reflection memory interrupt control device for synchronization; the real-time simulation deduction module adopts an ARM + FPGA hardware architecture to operate a real-time Linux system, and executes node parameter analysis, motion platform position / speed / angle / Doppler characteristic calculation and parameter updating; and the main control computer manages register clearing, data writing, instruction issuing and state verification of the equipment. Based on a reflective memory mechanism and a hard synchronization mechanism, high-real-time simulation of a large-scale radio frequency simulation system composed of a digital simulation scene and a hardware object is realized, so that a time-sensitive simulation test is supported.

Description

Technical Field

[0001] The present application relates to the field of microwave simulation technology, and in particular to a high-real-time radio frequency simulation architecture and a real-time synchronous control method. Background Art

[0002] With the advancement of high-precision simulation technology, simulation scenarios in the microwave and radio frequency field are increasingly characterized by the deep coupling of large-scale digital models with physical devices. This type of simulation not only requires accurate simulation of the dynamic characteristics of RF signals but also requires the simultaneous calculation of the motion platform's coordinate position in three-dimensional space, velocity components, acceleration components, motion-induced Doppler effects, and the real-time relative positional relationships between multiple platforms. In more refined simulations, a six-degree-of-freedom motion model is also required to characterize the dynamic changes in the platform's posture.

[0003] Such systems generally use a fixed simulation cycle to drive global state updates, and the accuracy of this cycle directly determines the real-time performance of the simulation. For scenarios involving high-speed motion platforms or transient RF signals, the cycle must be compressed to milliseconds or even microseconds to approximate the continuity of the physical world. This requires the system to complete numerical calculations, model state updates, and physical device control command interactions across a large number of nodes in an extremely short time, posing a severe challenge to computational real-time performance. Existing real-time solutions often rely on the priority task scheduling and hardware interrupt mechanisms of real-time operating systems. However, in ultra-large-scale RF simulation scenarios, conventional architectures face the following bottlenecks: First, multi-dimensional data streams such as motion states, RF parameters, and device controls must interact in real time across nodes, making traditional communication protocols unable to meet low-latency deterministic transmission requirements. Second, parallel execution of computationally intensive tasks such as 6-DoF kinematics, Doppler shift compensation, and RF field strength superposition can easily lead to cycle timeouts. Third, existing optimizations often focus on single-point technologies and lack a collaborative architecture that supports high-real-time simulation across the entire system.

[0004] Existing technology 1 proposes a real-time data interaction method based on a fiber-optic reflective memory network, which optimizes the underlying transmission efficiency by dividing the identification area and the data area, but does not solve the global scheduling and computing resource allocation problems in multi-node collaborative simulation. Existing technology 2 implements trajectory closed-loop synchronization for navigation signal simulation, but its lightweight data processing solution is difficult to expand to large-scale scenarios with hundreds of moving nodes and thousands of RF signals. Therefore, it is urgent to design a real-time computing architecture for ultra-large-scale RF simulation systems to achieve high-fidelity synchronous simulation of all elements of multi-degree-of-freedom motion models, RF characteristics, and physical equipment while ensuring microsecond-level beat accuracy. Summary of the Invention The purpose of this application is to provide a high-real-time RF simulation architecture and real-time synchronization control method in order to overcome the existing technical defects. Based on the reflective memory mechanism and the hard synchronization mechanism, high-real-time simulation of a large-scale RF simulation system composed of digital simulation scenes and physical hardware is achieved, thereby supporting time-sensitive simulation experiments.

[0005] The purpose of this application is achieved through the following technical solutions: In a first aspect, the present application proposes a high-real-time radio frequency simulation architecture, the architecture comprising: A fiber optic reflective memory network based on a star topology, consisting of fiber optic reflective memory cards and fiber optic reflective memory switches, is used to connect digital simulation scenarios with physical hardware devices, enabling real-time data interaction between multiple devices. The fiber optic reflective memory network adopts a partitioned transmission mechanism for instructions and data. Instruction transmission is triggered by interrupt events, and data transmission follows the four principles of partitioning, redundancy, integers, and continuity. The hard synchronization mechanism module generates a synchronization pulse signal through the timer card, and synchronizes the control device with the reflective memory interrupt through the synchronization pulse signal; The real-time simulation module uses an ARM+FPGA hardware architecture and runs a real-time Linux operating system to perform: Analyze the node parameters of the visual planning module; Calculate the position, velocity, angle information and Doppler characteristics of the motion platform in real time; Write the updated parameters to the reflective memory network interface cache; The main control computer is configured to clear the report registers of all devices, write data to the reflective memory network, send operation instructions to the devices, read the report registers and verify the operation execution status.

[0006] In a possible implementation, the instruction transmission rules include: Partitioning principle: instructions for different devices are stored in different continuous address areas of the reflective memory network; Redundancy principle: reserve expansion space in the instruction area; Integer principle: instruction addresses are aligned to 0x100 units; Continuity principle: The instruction words of the same device are stored in increasing order of address.

[0007] In one possible implementation, the hard synchronization mechanism module includes a central simulation machine and a subsystem hardware board; The central simulator sends synchronization pulse signals and reflective memory interrupts at a 1ms period; The subsystem hardware board updates the output parameters after receiving the synchronization pulse signal.

[0008] In one possible implementation, the calculation of the motion platform includes: The central node performs 9 multiplication and accumulation operations and 6 update operations; A single motion platform performs 9 multiplication and accumulation operations, 4 square operations, 2 square root operations, 2 floating-point division operations, 2 trigonometric functions, 6 addition operations, and 8 update operations.

[0009] In one possible implementation, the fiber reflective memory network has a transmission delay of 13 μs and a transmission rate of 128 MB / s.

[0010] In a possible implementation, the subsystem hardware boards include: a baseband board of a signal simulator, a switch board of an array feed system, and a control board of a turntable system.

[0011] In a second aspect, the present application proposes a real-time synchronization control method based on the first aspect, the method comprising: The central simulator completes the model solution within a preset period and sends down the parameters through the reflective memory network; The timer card sends synchronization pulse signals and reflective memory interrupts to each subsystem; The subsystem lower computer reads parameters through interruption and completes real-time calculation; The subsystem hardware board updates the output parameters after receiving the synchronization pulse signal.

[0012] The above-mentioned main solution of this application and its various further options can be freely combined to form multiple solutions, all of which are solutions that can be adopted and protected by this application. Moreover, in this application, (non-conflicting options) can also be freely combined with each other and with other options. After understanding the solution of this application, those skilled in the art will understand that there are many combinations based on existing technology and common knowledge, all of which are technical solutions to be protected by this application, and this is not an exhaustive list.

[0013] This application discloses a high-real-time radio frequency simulation architecture and real-time synchronization control method. The architecture utilizes a star-topology fiber-optic reflective memory network, comprised of fiber-optic reflective memory cards and switches, to achieve real-time data interaction between digital simulation scenarios and hardware devices. Transmission efficiency is optimized through a partitioned instruction and data transmission mechanism. A hard synchronization module utilizes a timer card to generate synchronization pulse signals, coordinating with reflective memory interrupts to control device synchronization. A real-time simulation deduction module utilizes an ARM+FPGA hardware architecture to run a real-time Linux system, performing node parameter analysis, motion platform position / velocity / angle / Doppler characteristic calculations, and parameter updates. A master control computer manages device register clearing, data writing, instruction issuance, and status verification. Based on the reflective memory and hard synchronization mechanisms, high-real-time simulation of large-scale radio frequency simulation systems consisting of digital simulation scenarios and physical hardware is achieved, thereby supporting time-sensitive simulation experiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A structural diagram of a high-real-time radio frequency simulation architecture proposed in an embodiment of the present application is shown.

[0016] Figure 2 A schematic diagram of the processing timing and real-time synchronization of the signal simulation system, position simulation system and central simulation machine is shown. DETAILED DESCRIPTION

[0017] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0018] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0019] In order to solve the problems existing in the prior art, the embodiments of the present application propose a high-real-time RF simulation architecture and a real-time synchronization control method. This architecture solves the high real-time requirements of multi-device collaborative simulation through hardware accelerated computing, dual-trigger synchronization mechanism and transmission protocol optimization, and achieves microsecond-level data synchronization accuracy and millisecond-level full-cycle closed-loop control. It is described in detail below.

[0020] Please refer to Figure 1 , Figure 1The present invention shows a structural diagram of a high-real-time radio frequency simulation architecture proposed in an embodiment of the present application, which illustrates the composition and connection relationship of the high-real-time radio frequency simulation architecture. The test control system includes a simulation main control computer, a situation display and evaluation system. The simulation main control computer is equipped with a visual planning module and a real-time simulation module, which is responsible for the control and data management of the entire simulation process. The system is connected to various hardware devices through a fiber optic reflection memory switch and an Ethernet switch. Among them, the fiber optic reflection memory switch is used to achieve high-real-time data interaction, and the Ethernet switch is used for conventional network communication. The hardware devices include a simulation turntable, a position simulation system and a signal simulator, etc. These devices receive simulation parameters and instructions through the fiber optic reflection memory network and update the output signal in real time. The simulation main control computer sends parameters through the fiber optic reflection memory switch, and each hardware device updates the parameters and outputs the signal after receiving the synchronization pulse signal to achieve system synchronization. The entire architecture ensures the real-time and synchronization of the simulation process through the collaborative work of the hard synchronization mechanism and the fiber optic reflection memory network.

[0021] A high real-time RF simulation architecture includes: A fiber optic reflective memory network based on a star topology, consisting of fiber optic reflective memory cards and fiber optic reflective memory switches, is used to connect digital simulation scenarios with physical hardware devices, enabling real-time data interaction between multiple devices. The fiber optic reflective memory network adopts a partitioned transmission mechanism for instructions and data. Instruction transmission is triggered by interrupt events, and data transmission follows the four principles of partitioning, redundancy, integers, and continuity. The hard synchronization mechanism module generates a synchronization pulse signal through the timer card, and synchronizes the control device with the reflective memory interrupt through the synchronization pulse signal; The real-time simulation module uses an ARM+FPGA hardware architecture and runs a real-time Linux operating system to perform: Analyze the node parameters of the visual planning module; Calculate the position, velocity, angle information and Doppler characteristics of the motion platform in real time; Write the updated parameters to the reflective memory network interface cache; The main control computer is configured to clear the report registers of all devices, write data to the reflective memory network, send operation instructions to the devices, read the report registers and verify the operation execution status.

[0022] This application utilizes a fiber-optic reflective memory network based on a star topology, consisting of fiber-optic reflective memory cards and fiber-optic reflective memory switches. This network structure is primarily used to connect digital simulation scenarios with various physical hardware devices, enabling real-time data exchange between multiple devices. Through the fiber-optic reflective memory network, the state parameters of digital models and physical hardware can be updated and synchronized in real time.

[0023] The fiber-optic reflective memory network utilizes a partitioned instruction and data transmission mechanism. Instruction transmission is triggered by interrupt events, and instructions for different devices are stored in different consecutive address areas within the reflective memory network. Furthermore, data transmission adheres to the four principles of partitioning, redundancy, integers, and continuity. The partitioning principle ensures that instructions and data from different devices do not interfere with each other; the redundancy principle reserves space for future expansion; the integer principle aligns instruction and data addresses in 0x100 units, facilitating fast device location and access; and the continuity principle ensures that instruction words for the same device are stored in ascending address order, facilitating management and access.

[0024] The hard synchronization mechanism module generates synchronization pulse signals using timer cards and uses these signals in conjunction with reflective memory interrupts to synchronize device operations. Specifically, the central simulation machine sends synchronization pulse signals and reflective memory interrupts at a 1ms period. Each subsystem's hardware board updates its output parameters only after receiving the synchronization pulse signals. This synchronization mechanism ensures that all components of the simulation system operate in an orderly manner based on the same time base.

[0025] The real-time simulation module is a core component of the entire architecture. It utilizes an ARM+FPGA hardware architecture and runs a real-time Linux operating system. It receives and interprets node and function parameters from the visual planning module. It also calculates the position, velocity, angle, and Doppler characteristics of each motion platform in real time. These calculations are crucial for simulating the motion platform's behavior in a real-world environment. The updated parameters generated by these real-time calculations are written to the reflective memory network interface cache, enabling other devices to access these updated parameters promptly.

[0026] The master computer serves as the command center for the entire simulation system. Before the simulation begins, it clears the report registers of all participating devices to ensure data accuracy. Simulation data is then written to the specified address in the reflective memory network to provide data support for subsequent simulations. The master computer then sends corresponding operation instructions to all participating devices, initiating and controlling their simulation tasks. After a period of waiting, the master computer reads the report registers of all participating devices to determine whether the operation was successful.

[0027] The entire system's application of the reflective memory network is divided into two categories: instructions and data. Instructions are implemented by a specific device interrupting the reflective memory card of the target device through the reflective memory network.

[0028] Instruction transmission rules include: Partitioning principle: instructions for different devices are stored in different continuous address areas of the reflective memory network; Redundancy principle: reserve expansion space in the instruction area; Integer principle: instruction addresses are aligned to 0x100 units; Continuity principle: The instruction words of the same device are stored in increasing order of address.

[0029] The instruction transmission rules of the reflective memory network are: Partitioning principle: Instructions from different devices are stored in independent continuous address areas in the reflective memory network to achieve effective distinction and management of instructions and avoid mutual interference between instructions from different devices.

[0030] Redundancy principle: Reserve a certain amount of expansion space for the instruction word distribution area of ​​each device. That is, the size of the instruction word distribution area of ​​each device exceeds the current actual demand, so that in subsequent system upgrades or function expansions, new instructions can be easily added without large-scale adjustments to the existing instruction area.

[0031] Integer principle: The areas where different devices write instruction words are aligned in units of 0x100. This helps maintain the neatness and standardization of memory addresses, facilitating quick location and read / write operations on devices, while also improving memory utilization and overall system performance.

[0032] Continuity principle: Instructions for the same device are stored in ascending order, starting from a specific starting address. When a new instruction is inserted, the value of the existing instruction is incremented to make room; when a new parameter is inserted, the addresses of the remaining parameters are shifted sequentially. This ensures that instructions and parameters for the same device are stored in a continuous and orderly manner in memory, facilitating unified management and efficient access to the device's own instructions and parameters.

[0033] The hard synchronization mechanism module includes a central simulation machine and subsystem hardware boards; The central simulator sends synchronization pulse signals and reflective memory interrupts at a 1ms period; The subsystem hardware board updates the output parameters after receiving the synchronization pulse signal.

[0034] After the simulation begins, the central simulator initiates model calculation and distributes simulation parameters via reflective memory. Subsequently, the synchronization pulse transmission model and the reflective memory interrupt transmission model are simultaneously activated. Under the precise timing of the timer card, synchronization pulse signals and reflective memory interrupts are transmitted in a strict 1ms cycle. Furthermore, the central simulator's real-time model calculation time is strictly controlled to within 1ms. After the calculation is completed, the timer waits for the next 1ms simulation cycle to arrive, at which point the real-time calculation for the next cycle is restarted and the reflective memory parameters are updated.

[0035] The subsystem hardware boards only update their output parameters after receiving a synchronization pulse signal. Upon receiving a reflective memory interrupt, each subsystem's software reads the real-time simulation data updated by the central simulator through the reflective memory. It then performs real-time calculations for the current simulation step and sends the calculated real-time parameter package to the corresponding board. However, upon receiving the real-time parameters from the lower-level software, the hardware board logic does not immediately update and output the parameters, but instead waits. Only when the control board receives a 1ms synchronization pulse signal from the simulator will it trigger the corresponding board to update its parameters and output signals.

[0036] Data exchange between subsystems occurs via the network and the fiber-optic reflective memory network. In networked mode, each system performs collaborative simulation under the control of the simulation master control system and the situation display system. The fiber-optic reflective memory network consists of fiber-optic reflective memory cards and fiber-optic radial memory switches. This system uses GE's PCI-5565 fiber-optic reflective memory card. Furthermore, a fiber-optic radial memory switch is used for data transmission and exchange within the fiber-optic network switch.

[0037] The calculation of the motion platform includes: The central node performs 9 multiplication and accumulation operations and 6 update operations; A single motion platform performs 9 multiplication and accumulation operations, 4 square operations, 2 square root operations, 2 floating-point division operations, 2 trigonometric functions, 6 addition operations, and 8 update operations.

[0038] This application is applied to a microwave darkroom simulation system. The length of the command word packet issued by the real-time simulation deduction module is approximately: 800 32-bit words, that is, 3200B. The interface between the real-time simulation deduction module and the visual planning module is Gigabit Ethernet, so the maximum transmission time of the command word is 80us. The time taken to parse the received command word is about 20us. Therefore, the time taken for step 1 is about 90us. Step 3: Summarize the calculation results of each thread, which is about 1600B, and update them into the interface cache. Based on previous engineering experience, this part takes about 80us. The calculation analysis of step 2 is as follows: The position and velocity of the central node and the position, velocity, and angle information of up to 48 other motion platforms need to be calculated. The carrier's computational workload includes 9 multiplication and addition operations and 6 update operations.

[0039] The computational load of a single node includes 9 multiplication and addition operations, 4 square operations, 2 square root operations, 2 single-precision floating-point division operations, 2 trigonometric functions, 6 addition operations, and 8 update operations. The computational load of a central node and 48 other nodes is shown in Table 1: Table 1

[0040] The real-time processor's main frequency is 800 MHz, and each clock cycle is 1.25 ns. Therefore, the calculation time for step 2) is approximately 137 μs. Based on the above analysis, the total time consumption is approximately: 90 + 137 + 80 = 307 μs.

[0041] The transmission delay of the fiber optic reflective memory network is 13μs and the transmission rate is 128MB / s.

[0042] The simulation parameters calculated and output by the simulation host computer are sent to other devices via the fiber optic reflective memory network. The parameter data packet size is 128MB / s. The average transmission rate of the fiber optic reflective memory is 128MB / s, so the transmission time is about 13us. The sub-devices that receive simulation parameters from the simulation main control computer include: signal simulator, position simulation system, and turntable system.

[0043] The real-time processing unit of the lower computer of the signal simulator receives the parameter word packet sent from the optical fiber reflection memory card through an interrupt, and then performs command word analysis, interpolation, control word calculation and packaging for sending.

[0044] Similarly, the array feed system's lower computer receives parameter packets from the fiber optic reflectance memory card via interrupts, then performs command word parsing, interpolation, control word calculation, and packet distribution. The turntable system also receives parameters from the simulation master computer via interrupts from the fiber optic reflectance memory card.

[0045] Figure 2 A schematic diagram shows the processing sequence and real-time synchronization of the signal simulation system, position simulation system, and central simulation machine. After the central simulation machine begins simulation, it first issues a command word, sending simulation parameters to each hardware device via the reflective memory network. The central simulation machine generates a 1ms fiber interrupt, which triggers a reflective memory interrupt, notifying each device to read the new simulation parameters. The central simulation machine generates a synchronization pulse signal to control the hardware boards to update their output parameters based on a unified time base. After receiving the command word from the central simulation machine, the signal simulation system receives, processes, and issues the command word, passing it to the slave computers. Upon receiving the synchronization pulse signal, the slave computers in the signal simulation system update their parameters, apply the update, and output the new signal. The position simulation system also receives, processes, and issues the command word from the central simulation machine. Upon receiving the synchronization pulse signal, the slave computers in the position simulation system update their parameters, apply the update, and output the new position information.

[0046] The subsystem hardware boards include: baseband board of signal simulator, switching board of array feed system, and control board of turntable system.

[0047] The subsystem hardware boards primarily include the baseband board for the signal simulator, the switching board for the array feed system, and the control board for the turntable system. After synchronously receiving a reflective memory interrupt, each subsystem software reads the real-time simulation data updated by the simulator through the reflective memory, begins real-time calculations for the current simulation step, and sends the calculated real-time parameter package to the corresponding board. This process is completed within 1ms, and after completion, it waits for the next reflective memory interrupt and begins the next cycle of real-time calculations. Upon receiving the real-time parameters sent by the lower-level software, the logic of each subsystem hardware board does not immediately update and output the parameters. Instead, it waits for the control board to receive the 1ms synchronization pulse signal sent by the simulator before controlling the corresponding board to update the parameters and output the signal, ultimately achieving synchronization of the outputs of each subsystem.

[0048] A possible implementation of the real-time synchronization control method based on the first aspect is provided below, which is used to execute the high real-time radio frequency simulation architecture shown in the above embodiment and possible implementation. The method includes: The central simulator completes the model solution within a preset period and sends down the parameters through the reflective memory network; The timer card sends synchronization pulse signals and reflective memory interrupts to each subsystem; The subsystem lower computer reads parameters through interruption and completes real-time calculation; The subsystem hardware board updates the output parameters after receiving the synchronization pulse signal.

[0049] After simulation begins, the central simulator initiates the model solution process, calculates the parameters for the current simulation step, and distributes these parameters to each subsystem via the reflective memory network. The central simulator activates the synchronization pulse transmission model and the reflective memory interrupt transmission model. Under the precise timing of the timer card, synchronization pulse signals and reflective memory interrupts are transmitted at a 1ms period. Upon synchronous receipt of the reflective memory interrupt, the software in each subsystem reads the real-time simulation data updated by the simulator through the reflective memory. The subsystem's lower-level software begins real-time calculation for the current simulation step and distributes the calculated real-time parameter package to the corresponding board. This process completes within 1ms, after which it waits for the next reflective memory interrupt to begin the next cycle of real-time calculation. Upon receiving the real-time parameters from the lower-level software, the hardware logic of each subsystem board does not immediately update and output the parameters. Instead, it waits for the control board to receive the 1ms synchronization pulse signal from the simulator before controlling the corresponding board to update the parameters and output the signal, ultimately achieving synchronization of the subsystem's outputs.

[0050] Compared with the prior art, the embodiments of the present application have the following beneficial effects: First, the central simulation machine completes the model solution and sends the parameters within the preset cycle, and the subsystem lower computer reads the parameters and completes the calculation within 1ms. The entire simulation system has a short step time and high simulation efficiency.

[0051] Second, the fiber optic reflective memory network is used to ensure fast and accurate data transmission; the star connection method improves network reliability, and the hard synchronization mechanism ensures synchronous operation of devices, reducing simulation errors and failure risks.

[0052] Third, each subsystem hardware board updates its parameters after receiving the synchronization pulse signal to achieve precise synchronization; instruction and data transmission follow four principles to avoid data conflicts and ensure that equipment works together.

[0053] Fourth, the star topology makes it easy to add new equipment, and the principles of partitioning and redundancy reserve space for system upgrades, facilitating system optimization and improvement.

[0054] Fifth, the star connection method simplifies network wiring, reduces the complexity of network construction and maintenance, reduces the risk of failure, and at the same time reduces dependence on high-performance hardware and reduces hardware costs.

[0055] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A high real-time radio frequency simulation architecture, characterized in that: The architecture includes: A fiber optic reflective memory network based on a star topology, consisting of fiber optic reflective memory cards and fiber optic reflective memory switches, is used to connect digital simulation scenarios with physical hardware devices, enabling real-time data interaction between multiple devices. The fiber optic reflective memory network adopts a partitioned transmission mechanism for instructions and data. Instruction transmission is triggered by interrupt events, and data transmission follows the four principles of partitioning, redundancy, integers, and continuity. The hard synchronization mechanism module generates a synchronization pulse signal through the timer card, and synchronizes the control device with the reflective memory interrupt through the synchronization pulse signal; The real-time simulation module uses an ARM+FPGA hardware architecture and runs a real-time Linux operating system to perform: Analyze the node parameters of the visual planning module; Calculate the position, velocity, angle information and Doppler characteristics of the motion platform in real time; Write the updated parameters to the reflective memory network interface cache; The main control computer is configured to clear the report registers of all devices, write data to the reflective memory network, send operation instructions to the devices, read the report registers and verify the operation execution status.

2. The high real-time radio frequency simulation architecture according to claim 1, wherein: Instruction transmission rules include: Partitioning principle: instructions for different devices are stored in different continuous address areas of the reflective memory network; Redundancy principle: reserve expansion space in the instruction area; Integer principle: instruction addresses are aligned to 0x100 units; Continuity principle: The instruction words of the same device are stored in increasing order of address.

3. The high real-time radio frequency simulation architecture according to claim 1, wherein: The hard synchronization mechanism module includes a central simulation machine and subsystem hardware boards; The central simulator sends synchronization pulse signals and reflective memory interrupts at a 1ms period; The subsystem hardware board updates the output parameters after receiving the synchronization pulse signal.

4. The high real-time radio frequency simulation architecture according to claim 1, wherein: The calculation of the motion platform includes: The central node performs 9 multiplication and accumulation operations and 6 update operations; A single motion platform performs 9 multiplication and accumulation operations, 4 square operations, 2 square root operations, 2 floating-point division operations, 2 trigonometric functions, 6 addition operations, and 8 update operations.

5. The high real-time radio frequency simulation architecture according to claim 1, wherein: The transmission delay of the fiber optic reflective memory network is 13μs and the transmission rate is 128MB / s.

6. The high real-time radio frequency simulation architecture according to claim 3, wherein: The subsystem hardware boards include: baseband board of signal simulator, switching board of array feed system, and control board of turntable system.

7. A real-time synchronization control method based on the architecture of any one of claims 1 to 6, characterized in that: The method comprises: The central simulator completes the model solution within a preset period and sends down the parameters through the reflective memory network; The timer card sends synchronization pulse signals and reflective memory interrupts to each subsystem; The subsystem lower computer reads parameters through interruption and completes real-time calculation; The subsystem hardware board updates the output parameters after receiving the synchronization pulse signal.

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