Data packet sending method, data processing unit, host and network card

Abstract

The invention relates to a data packet sending method, a data processing unit, a host and a network card, and the method comprises the steps: the host writes an aggregated data packet into a cache unit at a host side, and the data processing unit receives a packet sending notification sent by the host, and obtains a first cache descriptor and a second cache descriptor; the first cache descriptor comprises an address and an aggregation identifier of a cache unit at a host side, and the second cache descriptor comprises the length of each data packet contained in the aggregated data packet; reading the aggregated data packet from the cache unit on the corresponding host side according to the address of the cache unit; extracting each data packet from the aggregated data packet according to the length of each data packet; and sending the extracted data packets to opposite terminal equipment in sequence. According to the method and the device, the bandwidth utilization rate of the PCIe for sending the network packet based on the virtio virtualization protocol can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of network data transmission, and in particular to a data packet sending method, a data processing unit, a host, a network card, and a computer program product. Background Art

[0002] Network packets are data packets with relatively small data volumes during network transmission. Traditionally, when receiving network packets based on the Virtio virtualization protocol, each time a Virtio network device sends a network packet, it needs to read a cache descriptor from the host-side descriptor table through PCIe (Peripheral Component Interconnect Express). Based on the read cache descriptor, a network packet is read from the host-side descriptor table cache unit (buffer) and notified to the host software. However, due to the relatively small data volume of network packets, only a small amount of data is read each time, resulting in very low PCIe bandwidth utilization. Summary of the Invention

[0003] The purpose of this application is to propose a data packet sending method, a data processing unit, a host, a network card and a computer program product to improve the bandwidth utilization of PCIe for sending network packets based on the Virtio virtualization protocol.

[0004] To achieve the above-mentioned object, according to a first aspect of the present application, a method for sending a data packet is provided, the method comprising:

[0005] Receive a packet sending notification sent by the host, and obtain a first cache descriptor and a second cache descriptor; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier, the aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet, and the second cache descriptor includes the length of each data packet in the aggregated data packet;

[0006] Reading the aggregated data packet from the cache unit on the host side according to the address of the cache unit;

[0007] extracting the individual data packets from the aggregated data packet according to the length of the individual data packets;

[0008] The extracted data packet is sent to the opposite device.

[0009] Optionally, obtaining the first cache descriptor and the second cache descriptor includes:

[0010] The first cache descriptor and the second cache descriptor are read from the host side using a single PCIe read operation.

[0011] Optionally, extracting the individual data packets from the aggregated data packet according to the lengths of the individual data packets includes:

[0012] Based on a cache line alignment principle, the individual data packets are extracted from the aggregated data packet according to the lengths of the individual data packets.

[0013] Optionally, the second cache descriptor includes a mode field and multiple length fields of the same bit width, the mode field is used to describe the bit width corresponding to the actual length of each network packet, and the multiple length fields of the same bit width are respectively used to describe the actual length of each data packet.

[0014] In the above method, when a network packet needs to be sent, the data processing unit receives a packet sending notification sent by the host, obtains a first cache descriptor and a second cache descriptor, reads an aggregated data packet according to the first cache descriptor, and parses the aggregated data packet according to the second cache descriptor to obtain each original network packet. On the basis of compatibility with the existing Virtio protocol, the amount of network packet data that the data processing unit can read each time is increased, the number of times the descriptors and data packets are read is reduced, and the PCIe bus can transmit data more efficiently, thereby improving the bandwidth utilization of PCIe. The data processing unit does not need to frequently read the cache descriptor from the descriptor table on the host side through PCIe, thereby reducing the access frequency of PCIe and reducing the access overhead of PCIe. The transmission method of the aggregated data packet reduces the fragmentation of data transmission, so that the data processing unit can process and send data packets more efficiently, thereby improving the overall data transmission efficiency.

[0015] According to a second aspect of the present application, a method for sending a data packet is provided, the method comprising:

[0016] Writing each data packet to be sent into the cache unit on the host side in sequence according to the cache line alignment principle to form an aggregated data packet;

[0017] Generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into a descriptor table on the host side; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet, and the second cache descriptor includes the length of each data packet in the aggregated data packet;

[0018] A packet sending notification is sent to a data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process the aggregated data packet according to the first cache descriptor and the second cache descriptor.

[0019] Optionally, the first cache descriptor further includes a next cache descriptor index; the next cache descriptor index is a storage location of the second cache descriptor in a descriptor table on the host side.

[0020] Optionally, the second cache descriptor includes a mode field and multiple length fields of the same bit width, the mode field is used to describe the bit width corresponding to the actual length of each network packet in the current mode, and the multiple length fields of the same bit width are respectively used to describe the actual length of each data packet.

[0021] In the above method, the host aggregates multiple network packets into an aggregated data packet and stores it in a cache unit on the host side, and stores the length of each network packet in a second cache descriptor, so that the data processing unit can read the aggregated data packet according to the first cache descriptor, and parse the aggregated data packet according to the second cache descriptor to obtain each original network packet. On the basis of being compatible with the existing Virtio protocol, this method increases the number of descriptors and the amount of network packet data that the data processing unit can read each time, reduces the number of times descriptors and data packets are read, and enables the PCIe bus to transmit data more efficiently, thereby improving the bandwidth utilization of PCIe. The data processing unit does not need to frequently read cache descriptors from the descriptor table on the host side through PCIe, thereby reducing the access frequency of PCIe and reducing the access overhead of PCIe. In addition, the transmission method of the aggregated data packet reduces the fragmentation of data transmission, enables the data processing unit to process and send data packets more efficiently, and improves the overall data transmission efficiency.

[0022] According to a third aspect of the present application, a data processing unit is provided, including:

[0023] a descriptor acquisition module, configured to receive a packet sending notification sent by the host and acquire a first cache descriptor and a second cache descriptor; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier, the aggregation identifier indicating that the data packet stored in the cache unit is an aggregated data packet; and the second cache descriptor includes the length of each data packet in the aggregated data packet;

[0024] a data reading module, configured to read the aggregated data packet from the corresponding cache unit on the host side according to the address of the cache unit;

[0025] a data packet parsing module, configured to extract the individual data packets from the aggregated data packet according to the length of the individual data packets;

[0026] The data packet sending module is used to send the extracted data packets to the opposite end device.

[0027] Optionally, the descriptor acquisition module is specifically used to:

[0028] The first cache descriptor and the second cache descriptor are read from the host side using a single PCIe read operation.

[0029] Optionally, the data packet parsing module is specifically configured to:

[0030] Based on a cache line alignment principle, the individual data packets are extracted from the aggregated data packet according to the lengths of the individual data packets.

[0031] According to a fourth aspect of the present application, a host is provided, including:

[0032] A data writing module is used to write the data packets to be sent into the cache unit on the host side in sequence according to the cache line alignment principle to form an aggregated data packet;

[0033] a write descriptor module, configured to generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into a descriptor table on the host side; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet; and the second cache descriptor includes the length of each data packet included in the aggregated data packet;

[0034] The notification module is used to send a packet sending notification to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.

[0035] According to a fifth aspect of the present application, a network card is provided, comprising the data processing unit as described above and / or the host as described above.

[0036] According to a sixth aspect of the present application, a computer program product is provided, comprising computer program instructions, wherein the computer program instructions instruct a computer device to perform operations corresponding to the method described in the first aspect or the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 This is a flowchart of a data packet sending method in Example 1 of the present application.

[0039] Figure 2A schematic diagram of a Virtio system framework in an embodiment of the present application.

[0040] Figure 3 This is a flowchart of network data transmission between the DPU and the host in the Split mode of the Virtio 1.0 protocol in an embodiment of the present application.

[0041] Figure 4 This is a flowchart of network data transmission between the DPU and the host in the Virtio 1.0 protocol Packed mode in an embodiment of the present application.

[0042] Figure 5 This is a simplified model diagram of the Virtio system in an embodiment of the present application.

[0043] Figure 6 Schematic diagram of the data packet sending direction delay model in the embodiment of the present application.

[0044] Figure 7 This is a schematic diagram of the data packet sending principle using the Split mode as an example in an embodiment of the present application.

[0045] Figure 8 This is a schematic diagram of the field structure of the second cache descriptor in Example 1 of the present application.

[0046] Figure 9 This is a flowchart of a data packet sending method in Example 2 of the present application. DETAILED DESCRIPTION

[0047] The detailed description of the accompanying drawings is intended to serve as an illustration of the current embodiment of the present application and is not intended to represent the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included in the spirit and scope of the present application.

[0048] See Figure 1 Embodiment 1 of the present application provides a data packet sending method, which is applied to a data processing unit (DPU) for data transmission between the data processing unit (DPU) and a host (Host). The method includes:

[0049] Step S11, receive the packet sending notification sent by the host, and obtain a first cache descriptor and a second cache descriptor; the first cache descriptor includes the address and aggregation identifier of the cache unit on the host side, the aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet, and the second cache descriptor includes the length of each data packet in the aggregated data packet.

[0050] Specifically, for example, Figure 2The figure shows a system diagram of a Virtio backend device based on DPU. A DPU (data processing unit) chip can support multiple virtual machines (VMs). Each virtual machine can run multiple Guest OS (client operating systems). The Virtio front-end driver runs in the Guest OS. At the same time, a single virtual machine can load multiple Virtio front-end drivers. Virtio uses Virt-queue to implement the I / O mechanism. Each Virt-queue is a queue that carries a large amount of data. Virtio-net is generally used in pairs, one queue for sending and one queue for receiving. The host in step S11 refers to the virtual machine (VM), which can also be understood as Figure 2 Guest OS 0~n in the backend device refers to Figure 2 Specifically, assuming the host wants to send network data to the DPU, the host can first add the buffer containing the data to the Virt-queue through the Virt-queue_add_buf function, then call the Virt-queue_kick function. Virt-queue_kick calls the Virt-queue_notify function to notify the DPU by writing to the register. The DPU then calls Virt-queue_get_buf to get the data received in the Virt-queue.

[0051] The following describes the network data transmission process between the hardware DPU and the host using the Virtio protocol in the traditional packed and split modes.

[0052] In Split mode, the host and DPU implement the network data transmission process through Virt-queue as follows Figure 3 The specific steps are as follows:

[0053] Step 1: The host driver writes the data packet into the host buffer, assembles the buffer base address, length and other information into a cache descriptor entry, and then fills it into the descriptor table. The header descriptor ID is filled in the entry of the available ring (avring), and the available ring index is updated.

[0054] Step 2: The host initiates a send notification to the DPU;

[0055] Step 3: The DPU parses the send notification, searches for queue-related configuration information stored locally, obtains the addresses of each ring, and initiates a request to read the avring index and avring entry.

[0056] Step 4: The DPU parses the descriptor table entry based on the read-back avring entry and initiates a Descriptor Table request (reading the cache descriptor) based on the relevant information.

[0057] Step 5: The DPU parses the entire buffer data based on the read-back Descriptor Table entry information, initiates a buffer read request, and processes the returned data before sending it to the destination port.

[0058] Step 6: The DPU updates the host-side used ring entry, including the buffer ID and buffer length.

[0059] Step 7: The DPU updates the used ring index on the host side;

[0060] Step 8: The DPU sends an MSI-X interrupt to the host to inform the host that data transmission is completed.

[0061] In Packed mode, the host and DPU implement the network data transmission process through Virt-queue as follows Figure 4 The specific steps are as follows:

[0062] Step 1: The host driver writes the data into the host buffer, assembles the buffer information into an entry, and then fills it into the entry of the descriptor table, and updates the local avring (available ring) wrap cnt;

[0063] Step 2: The host initiates a send notification to the DPU;

[0064] Step 3: The DPU parses the send notification, searches for queue-related configuration information stored locally, obtains the ring base addresses, and initiates a request to read the Descriptor Table entry.

[0065] Step 4: The DPU parses the buffer address, length, and other information based on the read Descriptor Table entry, initiates a request to read the buffer data, and sends the read data to the destination port;

[0066] Step 5: The DPU updates the host-side Descriptor Table, including the buffer ID and wrap cnt.

[0067] Step 6: The DPU sends an MSI-X interrupt to the host to inform the host that the data transmission is completed.

[0068] Based on the above process analysis, we can see that packed mode simplifies the ring structure compared to split mode, reducing the original three rings (avring, descriptor table, and usedring) to a single descriptortable. The avring wrap_cnt replaces the avring's function of indicating the producer index, while the ushering wrap_cnt replaces the usedring's function of indicating the consumer index. Packed mode operates two fewer rings than split mode, effectively reducing the number of PCIe operations per I / O. Generally, PCIe physical bandwidth is the determining factor in performance, so packed mode offers significantly higher performance than split mode in terms of packet transmission.

[0069] exist Figure 2 In a system, the performance of small packets in the sending direction is an important indicator to measure the DPU capability. Limited by the Virtio virtualization protocol, the performance of small packets in the sending direction in the packed mode can only reach 250Mpps at most, and the split mode is even lower, which can only reach less than 200Mpps. In addition, when processing I / O, the software needs to process complex protocol processes for both large and small packets. Therefore, the efficiency of small packet processing is very low. In view of this, the method of this embodiment is used to improve the processing efficiency of network small packets.

[0070] The method of this embodiment is applicable to Split mode and Packed mode. When the data processing unit receives a packet sending notification sent by the host (informing that a new data packet needs to be sent), it obtains the first cache descriptor and the second cache descriptor from the host side. The first cache descriptor and the second cache descriptor are written into the descriptor table by the host.

[0071] The address of the cache unit on the host side points to a cache unit in the host memory for storing aggregated data packets, and the data processing unit reads the aggregated data packets from the cache unit at this address.

[0072] The aggregation identifier indicates that the cache unit stores an aggregated data packet, that is, a data packet composed of multiple small packets. The data processing unit needs to extract each network small packet from the aggregated data packet after reading the aggregated data packet.

[0073] Step S12, reading the aggregated data packet from the corresponding cache unit on the host side according to the address of the cache unit;

[0074] Specifically, when the host prepares data, it writes multiple network packets into the cache unit in sequence according to the cache line alignment principle to form an aggregated data packet. When the data processing unit reads the data packet, it reads the cache unit aggregated data packet through a single PCIe read operation, thereby realizing the reading of multiple small packet data through a single PCIe.

[0075] Step S13: extracting each data packet from the aggregated data packet according to the length of each data packet.

[0076] Specifically, when the host writes each data packet into the cache unit, it writes each data packet into the cache unit in sequence according to the cache line alignment principle. Therefore, after knowing the length of each data packet, the data processing unit can extract each data packet from the aggregated data packet in sequence.

[0077] Step S14: Send the extracted data packet to the opposite device.

[0078] This embodiment method considers the Virtio-net hardware offload scenario. Virtio-net sends network data. The simplified model is as follows: Figure 5 As shown, the host is responsible for preparing data packets and filling each ring with data. The data is forwarded by the DPU and sent out via Ethernet. The following explains in detail how the method of this embodiment analyzes the delay of each major module in the path and analyzes potential improvements to improve performance.

[0079] The TX direction delay model is as follows Figure 6 As shown:

[0080] T1: The latency for the host to send a notification, which is the PCIe write latency, typically 1000ns.

[0081] T2: DPU single read available ring index latency. Assuming the PCIe link latency is symmetric, the latency from request initiation to response reception is 2000ns. (Split mode only)

[0082] T3: DPU single read available ring entry latency, latency is 1000ns; (split mode only)

[0083] T4: DPU single read buffer descriptor latency, latency is 1000ns;

[0084] T5: DPU single read TX packet (data packet in the sending direction) delay, the delay value is 1000ns;

[0085] T6: The delay between the DPE processing the TX data and sending it to the MAC port. The delay value is the delay inside the DPU.

[0086] t0: DPE internal queue scheduling delay, which is an uncertain delay;

[0087] t1: The uncertain delay between T4 and T5. Different buffer descriptor structures correspond to different delay values. This delay value is introduced because the DPU cannot interleave data from different queues on the same port. For example, with a chained buffer descriptor structure, the DPU must cache all data blocks before initiating a read request.

[0088] From the above analysis, we can see that the total time to process a piece of I / O data (i.e., a data packet) is:

[0089] T1+T2+T3+T4+T5+T6+t0+t1, the concept of the method in this embodiment is to reduce the total time of data processing, thereby improving data transmission performance.

[0090] in:

[0091] The T1 time can be reduced by aggregating the number of notify times by the host.

[0092] T2 is the same as T1, and the latency is reduced by aggregating the host index.

[0093] The reduction of T3 time can improve the PCIe read bandwidth utilization by reading more avring entries in a single PCIe read operation.

[0094] T4 is the latency for reading the host's descriptor entry. A single entry is 16 bytes, but the maximum byte length of a PCIe read word is 1024 bytes. If a PCIe operation reads only one entry, the bandwidth utilization is very low at 1.5% (16 ÷ 1024). This latency can be reduced by aggregating entries and reducing the number of PCIe reads.

[0095] T5 is the latency for reading data from the host's buffer, which accounts for a significant portion of the entire data flow. When processing large packets, PCIe read bandwidth is already saturated and cannot be improved, resulting in the highest performance at this time. However, when processing small packets, the number of valid bytes read per PCIe transaction is relatively low, and PCIe bandwidth is also relatively low.

[0096] The three times T6, t0, and t1 are the processing delays within the DPU. The delay of a high-performance DPU can already be very low, so the improvement is limited.

[0097] It should be noted that T4 and T5 are the time required to read entry and buffer data, which account for a large proportion of the time in the I / O processing process. Especially when processing I / O data of chained descriptors, if the time of T4 and T5 can be effectively reduced, the benefits will be enormous.

[0098] Therefore, the method of this embodiment aims to reduce T4 and T5 delays. Reducing T4 delay mainly reduces the number of times the DPU reads entries. That is, when the driver software prepares a single entry, it needs to carry information about multiple small I / O packets. When the DPU reads such an entry, it reads many small packets of data to the DPU through a PCIe read operation, thereby increasing the valid data returned for each read request. This can significantly reduce the number of PCIe reads, thereby reducing T5 time. Based on the above ideas, for the processing of network packets, the method of this embodiment reduces the number of PCIe reads of the DPU by increasing the number of corresponding information of multiple data packets carried by a single entry, thereby reducing I / O processing delay and improving performance.

[0099] In the method of this embodiment, when a network packet needs to be sent, the data processing unit receives a packet sending notification sent by the host, obtains a first cache descriptor and a second cache descriptor, and parses the aggregated data packet according to the first cache descriptor and the second cache descriptor to obtain each original network packet. Based on compatibility with the existing Virtio protocol, this method increases the number of descriptors and the amount of network packet data that the data processing unit can read each time, reduces the number of times descriptors and data packets are read, and thus improves the bandwidth utilization of PCIe. In addition, the transmission method of the aggregated data packet reduces the fragmentation of data transmission, allowing the data processing unit to process and send data packets more efficiently, thereby improving the overall data transmission efficiency.

[0100] In some embodiments, obtaining the first cache descriptor and the second cache descriptor in step S10 includes: reading the first cache descriptor and the second cache descriptor from the host side through a single PCIe read.

[0101] Specifically, the first cache descriptor includes:

[0102] Buffer Address: points to the starting location of the actual data (aggregate data packet) in the host memory;

[0103] Buffer Length: Indicates the length of the buffer pointed to by the descriptor. This length can be the valid data length of the entire aggregated data packet or the maximum data length of the buffer, depending on the design requirements of the descriptor.

[0104] Aggregation Flag: Contains a flag bit that indicates whether the data packet pointed to by the descriptor is an aggregated data packet;

[0105] Next Buffer Descriptor Index: This field stores the index of the next descriptor in the descriptor chain. If the Next Buffer Descriptor Index is 0, it indicates that this is the last descriptor in the chain. In this embodiment, the Next Buffer Descriptor Index of the first buffer descriptor is the index of the second buffer descriptor. In a specific embodiment, the addresses of the first and second buffer descriptors are consecutive, so multiple buffer descriptors, including the first and second buffer descriptors, can be read through a single PCIe read operation.

[0106] It should be noted that the first cache descriptor in this embodiment includes fields such as cache unit address, cache unit length, flag and next cache descriptor index, which are the same as the field structure of the cache descriptor of the existing Virtio protocol, and is therefore compatible with the existing Virtio protocol.

[0107] In some embodiments, the second cache descriptor includes a mode field and multiple length fields of the same bit width, wherein the mode field is used to describe the bit width corresponding to the actual length of each network packet under the mode, and the multiple length fields of the same bit width are respectively used to describe the actual length of each data packet.

[0108] Specifically, the host side needs to ensure that the actual length of each data packet filled into the second cache descriptor in the same mode must be consistent in bit width. Only in this way can the data processing unit identify where the next network packet length (Packet_len) is. In order to improve the utilization of the 16Byte (128bit) length entry, bit [1:0] is used to represent the maximum value of a single Packet_len, that is, the occupied bit width, and it is named the mode field (mode). For example:

[0109] Mode = 0: Packet_len is a maximum of 64 bytes, occupying 6 bits. Lenn = 0 represents a 1-byte length, lenn = 1 represents a 2-byte length, and so on. Lenn = 63 represents a 64-byte length. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of a maximum of 21 (126 ÷ 6) packets smaller than 64 bytes.

[0110] Mode = 1: Packet_len is a maximum of 128 bytes, occupying 7 bits. Lenn = 0 represents a 1-byte length, lenn = 1 represents a 2-byte length, and so on. Lenn = 127 represents a 128-byte length. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of a maximum of 18 (126 ÷ 7) packets smaller than 128 bytes.

[0111] Mode = 2: Packet_len is a maximum of 256 bytes, occupying 8 bits. lenn = 0 represents a 1-byte length, lenn = 1 represents a 2-byte length, and so on. lenn = 255 represents a 256-byte length. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of a maximum of 15 (126 ÷ 8) packets smaller than 256 bytes.

[0112] Mode = 3: Packet_len is a maximum of 512 bytes, occupying 9 bits. Lenn = 0 represents a 1-byte length, lenn = 1 represents a 2-byte length, and so on. Lenn = 511 represents a 512-byte length. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of a maximum of 14 (126 ÷ 9) packets smaller than 512 bytes.

[0113] Take mode=0 as an example to show the field arrangement. Figure 8 The meaning of each field is shown in the following table:

[0114]

[0115]

[0116] Other modes are similar to mode=0 and are not shown here one by one.

[0117] The data processing unit checks the aggregation flag in the read first cache descriptor. If the aggregation flag is set to 1 (ie, indicating that this is an aggregate data packet), the data processing unit obtains the length of each network packet of the aggregate data packet according to the second cache descriptor.

[0118] The first cache descriptor of the method of this embodiment is compatible with the existing Virtio protocol. In addition, multiple cache descriptors are read through a single PCIe read operation. Compared with the traditional method of performing a PCIe read descriptor operation for each packet, this significantly reduces the PCIe overhead for descriptor reading. Especially when multiple network packets are aggregated, the method of this embodiment has a significant performance advantage. On the basis of being compatible with the existing Virtio protocol, the method of the embodiment of the present application reduces PCIe overhead and improves system performance.

[0119] In some embodiments, each data packet included in the aggregated data packet is written into a cache unit on the host side according to a cache line alignment principle, and each data packet occupies an integer number of cache lines;

[0120] Specifically, the cache line alignment principle refers to storing data on specific boundaries (usually multiples of the cache line size) to optimize data access efficiency. For example, if the free buffer allocated on the host side is 4Kbyte, when all the packets sent are small network packets, such as Figure 2As shown, the host will write the network packets such as Tx_small_packet_0, Tx_small_packet_1, Tx_small_packet_2, ..., Tx_small_packet_n-1 of the target queue into the cache unit (buffer) on the host side according to the cache line (cache_line) alignment principle. Taking the cache line (cache_line) of 64 bytes as an example, the length of the network packet is not an integer multiple of 64 bytes. The part of the tail beat that is less than 64 bytes will be written with 0 to supplement the entire network packet to an integer multiple of 64 bytes. Therefore, each network packet will occupy an integer multiple of the cache line (cache_line), and each buffer contains storage space for multiple cache lines.

[0121] The extracting the individual data packets from the aggregated data packet according to the lengths of the individual data packets comprises:

[0122] Based on a cache line alignment principle, the individual data packets are extracted from the aggregated data packet according to the lengths of the individual data packets.

[0123] Specifically, since the host writes each data packet into the cache unit according to the cache line alignment principle, the data processing unit can also extract the individual data packets from the aggregate data packet according to the cache line alignment principle and the length of each data packet after reading the aggregate data packet; Figure 7 As shown, Descriptor Entry0 is the storage location of the first cache descriptor, and Descriptor Entry1 is the storage location of the second cache descriptor. The data processing unit assembles the data of the first pkt_len0 length of buffer0 into tx_small_packet0 according to pkt_len0 and sends it out. Then, according to the cache_line alignment principle, after filtering out the corresponding length, similarly, parse the tx_small_packet1 message according to pkt_len1, and then send it out through Ethernet. All n small packets are parsed in turn and sent out through Ethernet.

[0124] In the method of this embodiment, when a network packet needs to be sent, the data processing unit receives a packet sending notification sent by the host, obtains a first cache descriptor and a second cache descriptor, reads an aggregated data packet according to the first cache descriptor, and parses the aggregated data packet according to the second cache descriptor to obtain each original network packet. On the basis of compatibility with the existing Virtio protocol, the number of times the data processing unit reads descriptors and data packets through PCIe is reduced, the access overhead of PCIe is reduced, and thus the bandwidth utilization of PCIe is improved. In addition, the transmission method of the aggregated data packet reduces the fragmentation of data transmission, so that the data processing unit can process and send data packets more efficiently, thereby improving the overall data transmission efficiency.

[0125] Corresponding to the method of embodiment 1, embodiment 2 of the present application provides a data packet sending method, which is applied to the host side, see Figure 9 , the method of embodiment 2 includes:

[0126] Step S21, writing each data packet to be sent into the cache unit on the host side in order according to the cache line alignment principle to form an aggregated data packet;

[0127] Step S22: Generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into a descriptor table on the host side; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet, and the second cache descriptor includes the length of each data packet included in the aggregated data packet;

[0128] Step S23: Send a packet sending notification to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.

[0129] In some embodiments, the first cache descriptor further includes a next cache descriptor index; the next cache descriptor index is a storage location of the second cache descriptor in a descriptor table on the host side.

[0130] In some embodiments, the second cache descriptor includes a mode field and multiple length fields of the same bit width, the mode field is used to describe the bit width corresponding to the actual length of each network packet, and the multiple length fields of the same bit width are respectively used to describe the length of each data packet.

[0131] It should be noted that the method of the second embodiment corresponds to the method of the first embodiment. The contents not described in detail in the second embodiment can be obtained by referring to the contents of the first embodiment. Therefore, they are not described in detail in the second embodiment.

[0132] A third embodiment of the present application provides a data processing unit, including:

[0133] a descriptor acquisition module, configured to receive a packet sending notification sent by the host and acquire a first cache descriptor and a second cache descriptor; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier, the aggregation identifier indicating that the data packet stored in the cache unit is an aggregated data packet; and the second cache descriptor includes the length of each data packet in the aggregated data packet;

[0134] a data reading module, configured to read the aggregated data packet from the corresponding cache unit on the host side according to the address of the cache unit;

[0135] a data packet parsing module, configured to extract the individual data packets from the aggregated data packet according to the length of the individual data packets;

[0136] The data packet sending module is used to send the extracted data packets to the opposite end device.

[0137] It should be noted that the data processing unit of this embodiment corresponds to the method described in Example 1. The contents not described in detail in the data processing unit of this embodiment can be obtained by referring to the contents of the method described in Example 1, and will not be repeated in this embodiment.

[0138] A fourth embodiment of the present application provides a host, including:

[0139] A data writing module is used to write the data packets to be sent into the cache unit on the host side in sequence according to the cache line alignment principle to form an aggregated data packet;

[0140] a write descriptor module, configured to generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into a descriptor table on the host side; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet; and the second cache descriptor includes the length of each data packet included in the aggregated data packet;

[0141] The notification module is used to send a packet sending notification to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.

[0142] It should be noted that the host in this embodiment corresponds to the method described in Example 2. The contents not described in detail in the host in this embodiment can be obtained by referring to the contents of the method described in Example 2, and will not be repeated in this embodiment.

[0143] Embodiment 5 of the present application provides a network card, comprising the data processing unit described in embodiment 3 and / or the host described in embodiment 4.

[0144] Embodiment 6 of the present application provides a computer program product, including computer program instructions, which instruct a computer device to perform operations corresponding to the method described in embodiment 1.

[0145] Specifically, the computer program product includes a series of computer program instructions. These computer program instructions are codes written in a computer program that define how to perform specific operations. These computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which are the steps in the method described in Example 1 above. In this way, the computer program product of this embodiment provides a complete software solution that can be run on various computer devices to implement the method described in Example 1 above.

[0146] Embodiment 7 of the present application provides a computer program product, including computer program instructions, which instruct a computer device to perform operations corresponding to the method described in embodiment 2.

[0147] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program and define how to perform specific operations. These computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which are the steps in the method described in Example 2 above. In this way, the computer program product of this embodiment provides a complete software solution that can be run on various computer devices to implement the method of Example 2 above.

[0148] While various embodiments of the present application have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data packet sending method, characterized in that: The method comprises: Receive a packet sending notification sent by the host, and obtain a first cache descriptor and a second cache descriptor; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier, the aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet, and the second cache descriptor includes the length of each data packet in the aggregated data packet; Reading the aggregated data packet from the cache unit on the host side according to the address of the cache unit; extracting the individual data packets from the aggregated data packet according to the length of the individual data packets; The extracted data packet is sent to the opposite device.

2. The method according to claim 1, characterized in that The obtaining of the first cache descriptor and the second cache descriptor includes: The first cache descriptor and the second cache descriptor are read from the host side using a single PCIe read operation.

3. The method according to claim 1, characterized in that The extracting the individual data packets from the aggregated data packet according to the lengths of the individual data packets comprises: Based on a cache line alignment principle, the individual data packets are extracted from the aggregated data packet according to the lengths of the individual data packets.

4. The method according to any one of claims 1 to 3, characterized in that The second cache descriptor includes a mode field and multiple length fields of the same bit width. The mode field is used to describe the bit width corresponding to the actual length of each network packet under the mode, and the multiple length fields of the same bit width are respectively used to describe the actual length of each data packet.

5. A data packet sending method, characterized in that: The method comprises: Writing each data packet to be sent into the cache unit on the host side in sequence according to the cache line alignment principle to form an aggregated data packet; Generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into a descriptor table on the host side; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet, and the second cache descriptor includes the length of each data packet in the aggregated data packet; A packet sending notification is sent to a data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process the aggregated data packet according to the first cache descriptor and the second cache descriptor.

6. The method according to claim 5, characterized in that The first cache descriptor further includes a next cache descriptor index; the next cache descriptor index is a storage location of the second cache descriptor in a descriptor table on the host side.

7. The method according to claim 5 or 6, characterized in that The second cache descriptor includes a mode field and multiple length fields of the same bit width. The mode field is used to describe the bit width corresponding to the actual length of each network packet in the current mode, and the multiple length fields of the same bit width are respectively used to describe the actual length of each data packet.

8. A data processing unit, characterized in that: include: a descriptor acquisition module, configured to receive a packet sending notification sent by the host and acquire a first cache descriptor and a second cache descriptor; the first cache descriptor includes an address of a cache unit on the host side and an aggregation identifier, the aggregation identifier indicating that the data packet stored in the cache unit is an aggregated data packet; and the second cache descriptor includes the length of each data packet in the aggregated data packet; a data reading module, configured to read the aggregated data packet from the corresponding cache unit on the host side according to the address of the cache unit; a data packet parsing module, configured to extract the individual data packets from the aggregated data packet according to the length of the individual data packets; The data packet sending module is used to send the extracted data packet to the opposite end device.

9. The data processing unit according to claim 8, characterized in that The descriptor acquisition module is specifically used for: The first cache descriptor and the second cache descriptor are read from the host side using a single PCIe read operation.

10. The data processing unit according to claim 8, characterized in that The data packet parsing module is specifically used for: Based on a cache line alignment principle, the individual data packets are extracted from the aggregated data packet according to the lengths of the individual data packets.

11. A host, characterized in that: include: A data writing module is used to write the data packets to be sent into the cache unit on the host side in sequence according to the cache line alignment principle to form an aggregated data packet; A write descriptor module, configured to generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into a descriptor table on a host side; The first cache descriptor includes an address and an aggregation identifier of a cache unit on the host side; The aggregation identifier indicates that the data packet stored in the cache unit is an aggregated data packet, and the second cache descriptor includes the length of each data packet included in the aggregated data packet; The notification module is used to send a packet sending notification to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.

12. A network card, characterized in that: The device comprises the data processing unit according to any one of claims 8 to 10 and / or the host according to claim 11.

13. A computer program product, characterized in that The method comprises computer program instructions, wherein the computer program instructions instruct a computer device to execute operations corresponding to the method according to any one of claims 1 to 7.

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