Performance test method, device and equipment for graphics card

Abstract

The invention relates to the technical field of performance testing, and discloses a performance testing method, device and equipment for a graphics card, and the method comprises the steps: carrying out the quaternion stage decoupling of a rendering pipeline of the graphics card, and obtaining a vertex shader decoupling unit, a geometric shader decoupling unit, a rasterization unit decoupling unit and a pixel shader decoupling unit; stage isolation performance tests are respectively carried out to obtain first performance test data of the vertex shader, second performance test data of the geometric shader, third performance test data of the rasterization unit and fourth performance test data of the pixel shader; the first performance test data, the second performance test data, the third performance test data and the fourth performance test data are comprehensively analyzed to obtain performance bottleneck positioning results of all stages of the rendering pipeline, the coupling states of all the stages of the rendering pipeline can be effectively separated, and accurate adjustment and control over the running states of all the stages are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of performance testing, and in particular to a performance testing method, device and equipment for a graphics card. Background Art

[0002] With the rapid development of graphics processing technology, the rendering pipeline structure of modern graphics cards has become increasingly complex, consisting of multiple tightly coupled processing stages, including vertex shaders, geometry shaders, rasterizers, and pixel shaders. Traditional graphics card performance testing methods mainly rely on overall performance evaluation, which cannot effectively identify and locate performance bottlenecks in specific stages of the rendering pipeline, resulting in a lack of targeted and precise performance optimization.

[0003] In existing technologies, severe data dependencies and resource competition exist between various stages, significantly affecting the performance of a single stage due to the operational status of upstream and downstream stages. This makes it difficult to obtain performance data that truly reflects the independent processing capabilities of that stage. This coupling not only affects the accuracy of performance test results, but also makes it difficult for developers to accurately identify the root cause of performance issues, thus hindering the effectiveness of graphics card architecture design and performance tuning. Summary of the Invention

[0004] The present invention provides a performance testing method, device and equipment for a graphics card. The present invention can effectively separate the coupling states of various stages of a rendering pipeline, thereby achieving precise adjustment and control of the operating states of various stages.

[0005] A first aspect of the present invention provides a performance testing method for a graphics card, the performance testing method for a graphics card comprising: Decouple the graphics card's rendering pipeline at the quaternion stage to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit, and a pixel shader decoupling unit; Performing stage-isolated performance tests based on the vertex shader decoupling unit, the geometry shader decoupling unit, the rasterization unit decoupling unit, and the pixel shader decoupling unit, respectively, to obtain first performance test data of the vertex shader, second performance test data of the geometry shader, third performance test data of the rasterization unit, and fourth performance test data of the pixel shader; A comprehensive analysis is performed on the first performance test data, the second performance test data, the third performance test data, and the fourth performance test data to obtain performance bottleneck positioning results at each stage of the rendering pipeline.

[0006] In combination with the first aspect, in a first implementation of the first aspect of the present invention, the quaternion stage decoupling of the rendering pipeline of the graphics card is performed to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit, and a pixel shader decoupling unit, including: Obtaining coupling state information of a rendering pipeline in a graphics card, and performing quaternion encoding conversion on the coupling state information to obtain a pipeline state quaternion; Constructing a quaternion rotation transformation matrix and a phase state selection function, and generating a quaternion decoupling operator based on the quaternion rotation transformation matrix and the phase state selection function; Inputting the pipeline state quaternion into the quaternion decoupling operator to perform stage state separation operation processing to obtain a vertex shader separation state component, a geometry shader separation state component, a rasterization unit separation state component, and a pixel shader separation state component; The vertex shader separation state component, the geometry shader separation state component, the rasterization unit separation state component and the pixel shader separation state component are respectively encapsulated into independent units to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit and a pixel shader decoupling unit.

[0007] In combination with the first aspect, in a second implementation of the first aspect of the present invention, performing stage-isolated performance tests based on the vertex shader decoupling unit, the geometry shader decoupling unit, the rasterization unit decoupling unit, and the pixel shader decoupling unit, respectively, to obtain first performance test data of the vertex shader, second performance test data of the geometry shader, third performance test data of the rasterization unit, and fourth performance test data of the pixel shader, includes: Inputting the vertex test load into the vertex shader decoupling unit to perform a stage isolation performance test to obtain first performance test data of the vertex shader; Inputting the geometry test load into the geometry shader decoupling unit to perform a stage isolation performance test to obtain second performance test data of the geometry shader; Inputting the rasterization test load into the rasterization unit decoupling unit to perform stage isolation performance test processing to obtain third performance test data of the rasterization unit; The pixel test load is input into the pixel shader decoupling unit to perform stage isolation performance test processing to obtain fourth performance test data of the pixel shader.

[0008] In combination with the first aspect, in a third implementation of the first aspect of the present invention, inputting the vertex test load into the vertex shader decoupling unit to perform a stage isolation performance test to obtain first performance test data of the vertex shader includes: Generate loads for vertex datasets based on preset geometric complexity gradient parameters to obtain vertex test loads with different vertex densities, vertex attribute complexities, and transformation matrix complexities. Inputting the vertex test load into the first stage performance isolation controller of the vertex shader decoupling unit to perform pipeline load power integral control to obtain a first isolated operating state; Performing vertex throughput monitoring, vertex attribute processing latency monitoring, vertex cache hit rate monitoring, and transformation instruction execution efficiency monitoring on the first isolated operating state to obtain first performance monitoring data; The first performance monitoring data is input into a fractional-order Kalman filter for state estimation and coupling interference elimination to obtain first performance test data of the vertex shader.

[0009] In combination with the first aspect, in a fourth implementation of the first aspect of the present invention, inputting the geometry test load into the geometry shader decoupling unit to perform a stage isolation performance test to obtain second performance test data of the geometry shader includes: Generate multi-level loads for the geometric data set based on preset primitive expansion multiple parameters and geometric subdivision complexity parameters, and obtain geometric test loads containing different primitive expansion ratios, geometric subdivision precisions, and surface subdivision parameters; Inputting the geometric test load into the second stage performance isolation controller of the geometry shader decoupling unit for power integral control to obtain a second isolated operating state; Performing primitive expansion efficiency monitoring, geometric transformation throughput monitoring, surface subdivision performance monitoring, and primitive culling rate monitoring on the second isolated operating state to obtain second performance monitoring data; The second performance monitoring data is input into a fractional-order Kalman filter for dynamic performance tracking and filtering out coupling interference between the previous and next stages to obtain second performance test data of the geometry shader.

[0010] In combination with the first aspect, in a fifth implementation of the first aspect of the present invention, inputting the rasterization test load into the rasterization unit decoupling unit for stage isolation performance test processing to obtain third performance test data of the rasterization unit includes: Generate hierarchical loads for rasterization datasets based on preset pixel fill rate gradient parameters and coverage complexity parameters, and obtain rasterization test loads with different pixel densities, depth test complexities, and coverage variation ranges. Inputting the rasterization test load into the third stage performance isolation controller of the rasterization unit decoupling unit to perform nonlinear power integral control to obtain a third isolation operation state; Performing pixel fill rate monitoring, depth test efficiency monitoring, coverage calculation performance monitoring, and pixel output throughput monitoring on the third isolated operating state to obtain third performance monitoring data; The third performance monitoring data is input into a fractional-order Kalman filter to perform performance data optimization and eliminate coupling interference between the previous and next stages, so as to obtain third performance test data of the rasterization unit.

[0011] In combination with the first aspect, in a sixth implementation of the first aspect of the present invention, inputting the pixel test load into the pixel shader decoupling unit for stage isolation performance test processing to obtain fourth performance test data of the pixel shader includes: Generate multi-dimensional loads for pixel data sets based on preset texture complexity gradient parameters and shading computation complexity parameters, and obtain pixel test loads with different texture sampling densities, shading instruction complexities, and render target output formats. Inputting the pixel test load into the fourth stage performance isolation controller of the pixel shader decoupling unit to perform adaptive power integral control to obtain a fourth isolation operation state; Performing pixel throughput monitoring, texture access efficiency monitoring, shading calculation performance monitoring, and render target write rate monitoring on the fourth isolated operating state to obtain fourth performance monitoring data; The fourth performance monitoring data is input into a fractional-order Kalman filter for pixel-level performance analysis and upstream stage coupling interference suppression to obtain fourth performance test data of the pixel shader.

[0012] In combination with the first aspect, in a seventh implementation of the first aspect of the present invention, the comprehensive analysis of the first performance test data, the second performance test data, the third performance test data, and the fourth performance test data to obtain performance bottleneck location results for each stage of the rendering pipeline includes: Performing multi-dimensional standardization and normalization processing on the first performance test data, the second performance test data, the third performance test data, and the fourth performance test data to obtain a standardized performance data matrix for each stage in the rendering pipeline; Based on the mutual information entropy algorithm, the inter-stage performance correlation calculation and dependency analysis are performed on the standardized performance data matrix to obtain the inter-stage performance correlation matrix; Inputting the inter-stage performance correlation matrix into a multi-objective particle swarm optimization algorithm to identify performance bottlenecks and solve bottleneck weight coefficients, thereby obtaining performance bottleneck weight coefficients for each stage; A rendering pipeline bottleneck location decision tree is constructed based on the performance bottleneck weight coefficients of each stage and bottleneck priorities are sorted to obtain performance bottleneck location results for each stage of the rendering pipeline.

[0013] A second aspect of the present invention provides a performance testing device for a graphics card, the performance testing device for a graphics card comprising: A decoupling module is used to decouple the graphics card's rendering pipeline at the quaternion stage to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit, and a pixel shader decoupling unit; a performance testing module, configured to perform stage-isolated performance tests based on the vertex shader decoupling unit, the geometry shader decoupling unit, the rasterization unit decoupling unit, and the pixel shader decoupling unit, respectively, to obtain first performance test data of the vertex shader, second performance test data of the geometry shader, third performance test data of the rasterization unit, and fourth performance test data of the pixel shader; The comprehensive analysis module is used to comprehensively analyze the first performance test data, the second performance test data, the third performance test data and the fourth performance test data to obtain the performance bottleneck positioning results of each stage of the rendering pipeline.

[0014] A third aspect of the present invention provides an electronic device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory to enable the electronic device to execute the above-mentioned graphics card performance testing method.

[0015] Compared with the existing technology, the present invention has the following advantages: The use of quaternion encoding conversion and decoupling operators can effectively separate the coupling states of each stage of the rendering pipeline, achieving true stage independence. The separation process of each stage is precisely controlled through the quaternion rotation transformation matrix and the stage state selection function, avoiding the information loss problem of traditional decoupling methods. Each decoupling unit is equipped with an adaptive stage performance isolation controller, which can effectively eliminate the mutual influence of upstream and downstream stages and obtain true single-stage performance data. The use of fractional-order Kalman filters for state estimation and interference elimination significantly improves the accuracy and reliability of performance test data. A dedicated monitoring indicator system is designed for different stage characteristics, such as vertex throughput, primitive expansion efficiency, and pixel fill rate, to achieve comprehensive performance evaluation. Through real-time performance monitoring data collection, dynamic performance change characteristics can be captured, providing a rich data foundation for performance analysis. Based on the mutual information entropy algorithm, the performance correlation between stages is analyzed to accurately identify the dependencies and influence of each stage. The multi-objective particle swarm optimization algorithm is used for bottleneck identification, which can simultaneously consider multiple dimensions such as bottleneck severity, duration, and impact range. The bottleneck location decision tree is constructed to achieve priority sorting, providing clear guidance for performance optimization. In addition, multi-level test loads are generated based on preset complexity gradient parameters to ensure the comprehensiveness and pertinence of the test, and improved power integral control processing technology is used to achieve precise adjustment and control of the operating status of each stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which the present invention can be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size should still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and objectives that can be achieved by the present invention.

[0018] Figure 1 1 is a flow chart of a method for testing the performance of a graphics card provided by an embodiment of the present invention; Figure 2 This is a schematic block diagram of the structure of a performance testing device for a graphics card provided by an embodiment of the present invention; Figure 3 It is a schematic block diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0021] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should be further understood that the term "and / or" used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations. Figure 1 , an embodiment of a performance testing method for a graphics card in an embodiment of the present invention includes: Step 100: Decouple the rendering pipeline of the graphics card at the quaternion stage to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit, and a pixel shader decoupling unit; It is understandable that the execution subject of the present invention can be a performance test device for a graphics card, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0023] Specifically, coupled state information reflecting the behavior of each processing stage is extracted from the graphics card rendering pipeline in real time. This information includes multi-dimensional dynamic parameters such as vertex attribute processing behavior, geometry generation path, fragment generation mode, and pixel output load. Because coupled state information is intertwined and mutually influential, it requires a unified data structure to represent it. A quaternion encoding mechanism is introduced to convert the composite state of the entire rendering pipeline into a quaternion Q = (q0, q1, q2, q3), where q0 represents the global base state, q1 represents the substate related to the vertex shader, q2 represents the dynamic state of the geometry processing stage, and q3 represents the information encoding component containing the characteristics of the raster and pixel stages. A mathematical quaternion rotation transformation matrix R(Q) and a stage state selection function S(Q) are constructed. The rotation matrix R(Q) defines the reference direction for state rotation in four-dimensional space, providing a coordinate basis for the mathematical mapping. The state selection function S(Q) extracts features closely related to the target stage based on the set test target. Based on this, the system defines a decoupling operator, which maps and extracts features from each stage in the rotation domain and then projects them back into the original state space, achieving the transition from a coupled state to a stage-by-stage sub-state. The encoded pipeline state quaternion is input into this quaternion decoupling operator, initiating the stage-by-stage state separation process. During this process, each component q1, q2, and q3 is mapped to a corresponding independent stage-by-stage state component. q1 extracts state information such as cache access patterns, attribute transformation density, and matrix operation load during vertex processing. q2 extracts behavioral features such as geometric primitive expansion rate, tessellation level, and culling algorithm complexity. q3 distinguishes between state features related to fragment generation in the rasterization path and state features such as texture sampling behavior, shader instruction distribution, and output bandwidth pressure in the pixel stage. Through the decoupling operator's separation operation, the processing stages of the graphics card rendering pipeline are no longer coupled, but are instead extracted as separate state subsets that mathematically do not interfere with each other and can be independently modeled functionally and logically. These four types of phased decoupled state components are encapsulated as independent units, packaging each phase's decoupled state into structured units according to modularization rules. This encapsulation process not only includes the physical classification of state variables but also generates state-related interface definitions, load injection ports, and performance measurement callback mechanisms. Ultimately, the vertex shader decoupling unit, geometry shader decoupling unit, rasterization unit decoupling unit, and pixel shader decoupling unit are constructed.

[0024] Step 200: Performing stage-isolated performance tests on the vertex shader decoupling unit, the geometry shader decoupling unit, the rasterization unit decoupling unit, and the pixel shader decoupling unit, respectively, to obtain first performance test data of the vertex shader, second performance test data of the geometry shader, third performance test data of the rasterization unit, and fourth performance test data of the pixel shader;Specifically, based on the vertex shader decoupling unit, geometry shader decoupling unit, rasterization unit decoupling unit and pixel shader decoupling unit, standardized test loads with controllable complexity and stage-specificity are injected respectively, thereby realizing stage-by-stage performance isolation measurement. The test process starts from the vertex stage, and vertex data sets of different sizes are constructed through the vertex test load generator. The data set can be adjusted in terms of vertex density, attribute dimension and matrix operation complexity according to the test requirements. The generated test load is directly injected into the vertex shader decoupling unit, so that it can be processed in a physically isolated pipeline environment. At the same time, the cache access mode, attribute processing path and vertex transformation strategy are adjusted in real time through the dynamic performance feedback controller to suppress the adverse effects of other downstream stages such as geometry processing or pixel calculation, thereby obtaining high-purity independent performance measurement results of the vertex stage and outputting the first performance test data, including core indicators such as vertex throughput, attribute processing latency, cache hit rate and instruction execution efficiency. Entering the geometry shader stage, a scalable primitive set is generated using a geometry test load generator. The test covers multiple test dimensions, including primitive expansion ratios ranging from 1:1 to 1:64, number of tessellation planes, and surface smoothness. This load is fed into the geometry shader decoupling unit to independently stimulate the geometry stage's performance. During this process, an ASPI controller is configured to maintain state stability within the geometry pipeline, and a feedback regulation mechanism is employed to isolate vertex input perturbations from the state backpressure caused by subsequent raster processing, ensuring that the geometry stage's processing performance data is truly measurable. The measurement results are output as secondary performance metrics, including primitive expansion efficiency, geometry throughput, tessellation performance, and culling rate, quantifying the geometry stage's computational capabilities under varying complexity conditions. A rasterization test load is fed into the rasterization unit decoupling unit for performance testing. This load consists of multiple rendering resolutions, antialiasing sampling levels, and depth and stencil test complexities, simulating the resolution pressure and fragment generation peaks faced by the rasterizer unit during actual rendering. In this stage, a rasterization-specific adaptive controller is configured to dynamically adjust variables such as viewport settings, depth buffer accuracy, and multi-sampling strategies, so that the test is always carried out under the premise of eliminating upstream and downstream interference, and combined with a fixed-time convergence strategy to ensure that the system can enter a stable measurement state within a specified time range. The test output is the third performance test data, covering key performance indicators such as fragment generation rate, depth test throughput, multi-sampling efficiency, and viewport transformation delay. In the pixel shader stage, a pixel test load consisting of texture sampling complexity, shader instruction combination, PBR material rendering model, and fragment discarding strategy is injected and input into the pixel shader decoupling unit to complete the isolation test task.By deploying the FTASPI controller and interference observation compensation module, the performance impact of input fluctuations from the preceding grating is tracked and suppressed in real time. The controller implements a piecewise-continuous fixed-time control law based on performance errors, ensuring that performance measurements can be completed in a stable state and converge quickly. The resulting fourth performance test data covers key parameters such as pixel fill rate, texture sampling throughput, shader instruction execution efficiency, and output bandwidth utilization, reflecting the pixel stage's processing capabilities in complex computing scenarios.

[0025] Step 300: Comprehensively analyze the first performance test data, the second performance test data, the third performance test data, and the fourth performance test data to obtain performance bottleneck positioning results at each stage of the rendering pipeline.

[0026] Specifically, the first performance test data for the vertex shader, the second performance test data for the geometry shader, the third performance test data for the rasterizer, and the fourth performance test data for the pixel shader were standardized and normalized across multiple dimensions to unify the data scales of each performance metric and eliminate statistical bias caused by different scales. This resulted in a standardized performance data matrix that facilitates cross-stage comparative analysis. Key performance parameters for each stage, such as throughput, processing latency, cache hit rate, computational efficiency, and instruction execution density, were converted into dimensionless values ​​in the interval [0, 1] and then adjusted based on their distribution characteristics. A mutual information entropy algorithm was used to calculate the correlation between the stage metrics in the standardized performance data matrix to quantify the degree of performance interdependence between different rendering stages. This mutual information entropy analysis considers linear correlations between performance metrics and captures potential nonlinear coupling, such as the amplified impact of geometry processing bottlenecks on rasterization performance through primitive complexity, or the potential negative impact of the pixel stage on cache and bandwidth in dense texture sampling scenarios. This analysis generates a performance correlation matrix between stages, in which each element represents the strength of the performance coupling between two stages. The inter-stage performance correlation matrix is ​​fed into a multi-objective particle swarm optimization algorithm. The algorithm uses performance bottleneck identification as its objective function. By assigning multidimensional individual particles representing different bottleneck attribution paths, the algorithm dynamically searches for the dominant bottleneck structure of the current rendering pipeline in real-world scenarios, combining historical optimal values ​​with the swarm's global optimal direction. The algorithm then introduces constraints to limit overfitting and calculates bottleneck weight coefficients for each rendering stage. Larger values ​​indicate a more dominant role for the stage in overall rendering latency and processing bottlenecks. A comprehensive assessment is also made based on characteristic metrics such as performance saturation and utilization proximity. A rendering pipeline bottleneck location decision tree is constructed based on the performance bottleneck weight coefficients for each stage. This decision tree uses weight thresholds, performance imbalance indicators, and stage-level relative deviation as decision nodes. Through a recursive tree path, the specific location and impact of performance bottlenecks are determined, and a prioritized ranking of performance bottlenecks is generated at the output level. This results in performance bottleneck location results for each stage of the rendering pipeline.

[0027] In a specific embodiment, the process of executing step 100 may specifically include the following steps: Obtaining coupling state information of a rendering pipeline in a graphics card, and performing quaternion encoding conversion on the coupling state information to obtain a pipeline state quaternion; Constructing a quaternion rotation transformation matrix and a phase state selection function, and generating a quaternion decoupling operator based on the quaternion rotation transformation matrix and the phase state selection function; Inputting the pipeline state quaternion into the quaternion decoupling operator to perform stage state separation operation processing to obtain a vertex shader separation state component, a geometry shader separation state component, a rasterization unit separation state component, and a pixel shader separation state component; The vertex shader separation state component, the geometry shader separation state component, the rasterization unit separation state component and the pixel shader separation state component are respectively encapsulated into independent units to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit and a pixel shader decoupling unit.

[0028] Specifically, during graphics card operation, coupled state information of the rendering pipeline is collected in real time. This information is derived from the intersecting data streams of processing behavior in the four stages of vertex processing: vertex processing, geometric transformation, primitive rasterization, and pixel shading. This information includes vertex cache access frequency, transformation matrix computation time, primitive expansion and culling ratios, fragment generation rate, texture sampling call density, number of pixel instruction operations, and rendering bandwidth utilization. This state data is highly coupled across time and modules, making it difficult to directly use for single-stage performance modeling. Therefore, a structured transformation is performed based on a unified encoding representation. A quaternion encoding mechanism is introduced to project this coupled state information into a quaternion state space for representation. The main state variables of the vertex, geometry, rasterization, and pixel stages are encoded as the three imaginary components q1, q2, and q3 of the quaternion, respectively. The overall stability state and background conditions of the rendering system are encoded as the real component q0, resulting in the pipeline state quaternion Q = (q0, q1, q2, q3). To extract the state information of each stage implied by the quaternion, a quaternion rotation transformation matrix R(Q) is constructed, and a corresponding stage state selection function S(Q) is designed. The rotation matrix R(Q), based on the rotation tensor constructed from the unit quaternion, essentially maps the quaternion state from the original encoding space to the reference space of each stage, providing the necessary spatial transformation foundation. The state selection function S(Q) sets selection factors based on a preset stage response template, such as selecting a vector group associated with q1 to extract vertex processing behavior or selecting the texture sampling-output mapping path formed by q3 for pixel state extraction. Through the synergistic effect of these two factors, a quaternion decoupling operator is constructed to achieve selective separation of pipeline states. The pipeline state quaternion Q is input into the decoupling operator for separation processing. The system initiates a combined four-dimensional rotation mapping and state selection operation to obtain state feature sets associated with the q1, q2, and q3 components, respectively. This allows the extraction of the vertex shader separation state component, the geometry shader separation state component, the rasterizer separation state component, and the pixel shader separation state component. Each separate state component contains key variables unique to that stage, including timing metrics, load characteristics, instruction complexity labels, and resource utilization data. To ensure that these four separate state components are operationally capable and can independently participate in testing and optimization analysis, they are packaged as independent units. This process includes structural packaging of each state component and the integrated integration of its input and output channels, state feedback paths, test load interfaces, and performance monitoring components.The vertex shader separation state component integrates the vertex attribute scheduler, transformation matrix processor and vertex cache state loop in the encapsulation to generate a vertex shader decoupling unit; the geometry shader separation state component integrates the primitive generation controller, subdivision level adjustment module and culling logic analyzer to form a geometry shader decoupling unit; the rasterization unit separation state component is encapsulated as a rasterization unit decoupling unit in conjunction with the viewport configuration module, depth test controller and sampling rate adjustment mechanism; and the pixel shader separation state component is reconstructed through the texture sampling strategy generator, shading instruction scheduler and output bandwidth evaluation module to finally form a pixel shader decoupling unit.

[0029] In a specific embodiment, the process of executing step 200 may specifically include the following steps: Inputting the vertex test load into the vertex shader decoupling unit to perform a stage isolation performance test to obtain first performance test data of the vertex shader; Inputting the geometry test load into the geometry shader decoupling unit to perform a stage isolation performance test to obtain second performance test data of the geometry shader; Inputting the rasterization test load into the rasterization unit decoupling unit to perform stage isolation performance test processing to obtain third performance test data of the rasterization unit; The pixel test load is input into the pixel shader decoupling unit to perform stage isolation performance test processing to obtain fourth performance test data of the pixel shader.

[0030] Specifically, an independent test logic loop is established within the vertex shader decoupling unit. Based on the quaternion state component q1, this decoupling unit extracts the computation channels, cache channels, and state transition paths associated with the vertex processing stage. A dedicated ASPI controller is deployed to ensure that the test process is unaffected by subsequent geometric transformations or pixel operation feedback. Furthermore, a constructed vertex test load is injected into the decoupling unit. The test load features multi-dimensional gradient control based on the test objectives, covering a variety of typical scenarios such as vertex density, attribute data dimensions, transformation matrix complexity, position coordinate perturbation amplitude, and cross-attribute binding structures. A serialization structure and periodic triggering mechanism ensure repeatability and comparability in the test process. During testing, the ASPI controller adjusts the input structure in real time based on vertex processing deviation to ensure stable load distribution and avoid coupling backflow. During operation, the system monitors multiple performance metrics in parallel, including vertex throughput, cache hit rate, instruction scheduling latency, and transformation path load balance. The RPDQCKF-PS filter is used to estimate state evolution trends, thereby obtaining a vertex stage performance profile and generating the first performance test data. Entering the geometry shader stage, the second phase of testing occurs in the geometry shader decoupling unit. This unit consists of a geometry feature stream derived from the state component q2. It integrates primitive generation logic, tessellation calculation paths, and a culling mechanism identifier. The geometry stage ASPI controller maintains relative stability between processing behavior and the input load. The geometry test workload is constructed using a highly parameterized primitive expansion model, incorporating variables such as primitive expansion ratios (e.g., 1:1, 1:4, 1:16, and 1:64), tessellation levels (e.g., Bezier surfaces and Catmull-Clark meshes), patch reconstruction accuracy control parameters, and culling test conditions (e.g., outside-view frustum culling and backface culling). Discrete sampling is used to cover the entire primitive space. By feeding this workload into the geometry decoupling unit, the system performs a point-by-point analysis of each module in the geometry processing path during execution, extracting characteristic metrics such as primitive throughput, culling success rate, tessellation calculation time, and geometry cache access patterns. The dynamic response to geometry pressure feedback is evaluated using the controller's internal feedback mechanism, generating the second performance test data for the geometry stage. The test process transitions to the rasterization unit stage. The processing logic of this stage is mainly concentrated on the raster part in the state component q3. The rasterization decoupling unit includes a fragment generator, a multi-sampling management module, and a depth and template buffer simulation module, and is coordinated and scheduled by the rasterization ASPI controller.To construct a reasonable rasterization test load, we preset multiple resolution levels (such as 512×512, 1024×1024, 2048×2048, and 4096×4096), anti-aliasing levels (such as 1×, 4×, 8×, and 16× MSAA), viewport coverage ratios, and occlusion control parameters to ensure that the test process covers the rendering task complexity of various real-world scenarios. During the actual injection phase, the test load is loaded into the rasterization decoupling channel through a designated interface. The controller dynamically adjusts state stability through feedback. Simultaneously, the system performs high-frequency sampling and timing analysis on metrics such as fragment generation rate, depth test throughput, multi-sample processing latency, and stencil buffer call count. A fixed-time convergence algorithm is used to ensure measurement accuracy within a specified period, resulting in the third-party performance test data for the rasterization stage. The test flow enters the pixel shader stage. This decoupled unit is constructed based on the pixel processing sub-channels in the state component q3. Its internal modules include a fragment scheduler, texture sampling controller, shader compute core, and bandwidth management unit, all driven by the FTASPI control strategy. The pixel test workload is constructed to cover a variety of texture complexities (single, 4, 8, and 16 layers), a variety of shader programs (from basic lighting models to full PBR pipelines), different sampling modes (such as nearest neighbor, bilinear, and anisotropic), and fragment discard rates (full retention, random occlusion, and high occlusion). A dynamic workload flow is generated through a combination of random perturbations and regular transformations. During the load injection process into the decoupled unit, the FTASPI controller regulates the fragment scheduling rhythm, texture call order, and shader path execution rate to ensure that pixel processing pressure is concentrated and independent of upstream pixel fluctuations. An integrated disturbance observer identifies external influencing factors in real time and provides feed-forward compensation. During the test cycle, the system collects statistics and analyzes multiple indicators such as pixel fill rate, texture sampling efficiency, shader instruction throughput, and rendering output bandwidth utilization, and achieves rapid convergence of performance values ​​within a fixed period under the guarantee of the FTASPI controller, ultimately forming the fourth performance test data of the pixel shader.

[0031] In a specific embodiment, the step of inputting the vertex test load into the vertex shader decoupling unit to perform the stage isolation performance test and obtaining the first performance test data of the vertex shader may specifically include the following steps: Generate loads for vertex datasets based on preset geometric complexity gradient parameters to obtain vertex test loads with different vertex densities, vertex attribute complexities, and transformation matrix complexities. Inputting the vertex test load into the first stage performance isolation controller of the vertex shader decoupling unit to perform pipeline load power integral control to obtain a first isolated operating state; Performing vertex throughput monitoring, vertex attribute processing latency monitoring, vertex cache hit rate monitoring, and transformation instruction execution efficiency monitoring on the first isolated operating state to obtain first performance monitoring data; The first performance monitoring data is input into a fractional-order Kalman filter for state estimation and coupling interference elimination to obtain first performance test data of the vertex shader.

[0032] Specifically, a vertex test workload generation model is constructed using the controllable geometry processing path within the graphics card's rendering architecture as the entry point. Preset geometric complexity gradient parameters are used to establish multi-dimensional load control channels, including three subsystems: vertex density control, attribute complexity control, and transformation matrix complexity control. These channels control the number of vertices processed per frame in the vertex dataset, the types of attributes bound to each vertex (such as normals, tangents, colors, and texture coordinates), and the size and number of matrix operations applied to each vertex's transformation matrix, thereby forming a dynamically adjustable three-dimensional complexity workload space. In practice, using pre-set complexity grading parameters, such as the L1 to L5 density control level, a variety of scenes with vertex counts ranging from 100,000 to 10 million are dynamically constructed. Attribute complexity ranges from simple position coordinates (vec3) to full structures containing multiple vector attributes, while matrix complexity ranges from basic displacement and scaling transformations to high-level, stacked skeletal animation matrix chains. The result is a vertex test workload with multi-dimensional control and adaptability for large-scale workload simulations. Vertex test loads are fed into the vertex shader decoupling unit, where the control logic is taken over by the first-stage performance isolation controller within the unit. This controller is designed based on power-integral control theory. Its control law employs a power function to perform temporally nonlinear weighting of vertex processing errors. The error between actual processing performance and the desired load response is used as the control input. A power integrator is used to construct a nonlinear response adjustment path to achieve a dynamic balance between stability and response speed. Within the controller, multiple adjustable parameters are set for vertex cache access patterns, transform instruction activation frequency, and attribute calculation pipeline scheduling intervals. These parameters are adjusted in real time by the power-integral control loop, gradually stabilizing according to the load response state. This results in a first-stage isolated operating state where vertex processing behavior fully matches the test load and coupling interference is minimized. This state ensures a physically isolated operating environment for the vertex processing stage, unaffected by subsequent geometry shader feedback, pixel shader backpressure, or global resource contention. The first isolated operating state is monitored and sampled. Based on the multi-channel data return module integrated in the vertex decoupling unit, fine-grained and high-frequency sampling is performed on four core performance indicators: vertex throughput, vertex attribute processing latency, vertex cache hit rate, and transformation instruction execution efficiency. Vertex throughput is measured in the number of vertices processed per second, reflecting the maximum capacity boundary of the processing link; attribute processing latency measures the average time from vertex data input to attribute calculation output, which can identify data dependency structures and scheduling bottlenecks; vertex cache hit rate is based on the cache level access success rate, revealing the laws of data reuse and access locality; and transformation instruction execution efficiency statistically evaluates the pipeline behavior of operations such as matrix multiplication and vector rotation, which is used to reflect the hardware utilization and processing granularity distribution of the instruction scheduling module.These monitoring data are organized into a series of dynamic sampling segments along the timeline using a preset structure and organized into the first performance monitoring dataset. During the acquisition process, the system simultaneously records statistical features such as the instantaneous value, mean, standard deviation, and coefficient of variation of each indicator. This first performance monitoring data is fed into a Kalman filter based on a fractional-order model to perform state estimation and coupled interference cancellation. This filter uses an α-order fractional derivative operator to construct the state equation, adaptively modeling and mitigating nonstationary disturbances, cross-cycle trends, and high-frequency noise during state changes. Its state equation models the temporal response structure of GPU vertex processing behavior, while the observation equation quantitatively fits the mapped performance data. Through the filter's prediction-correction iterative mechanism, interfering components such as transient noise, cache perturbations, and thread scheduling jitter during performance evolution are filtered out from the effective state, extracting the true stable processing characteristics of the vertex stage. During the iterative process, the filter constructs three core data structures: the state transfer matrix, the observation noise covariance matrix, and the prediction error covariance matrix. The state estimate is corrected with each frame performance update, and real-time assessment is performed to determine whether the system state has reached steady-state conditions. When the stability and identifiability standards are met, the system outputs the final vertex shader first performance test data, which includes the decoupling values ​​of various performance indicators, the expected response path after filtering, the stable state criteria and the performance evaluation level.

[0033] In a specific embodiment, the step of inputting the geometry test load into the geometry shader decoupling unit to perform the stage isolation performance test and obtaining the second performance test data of the geometry shader may specifically include the following steps: Generate multi-level loads for the geometric data set based on preset primitive expansion multiple parameters and geometric subdivision complexity parameters, and obtain geometric test loads containing different primitive expansion ratios, geometric subdivision precisions, and surface subdivision parameters; Inputting the geometric test load into the second stage performance isolation controller of the geometry shader decoupling unit for power integral control to obtain a second isolated operating state; Performing primitive expansion efficiency monitoring, geometric transformation throughput monitoring, surface subdivision performance monitoring, and primitive culling rate monitoring on the second isolated operating state to obtain second performance monitoring data; The second performance monitoring data is input into a fractional-order Kalman filter for dynamic performance tracking and filtering out coupling interference between the previous and next stages to obtain second performance test data of the geometry shader.

[0034] Specifically, multi-level load generation is performed on geometric datasets based on preset primitive expansion multiplier and geometry subdivision complexity parameters. The primitive expansion multiplier parameter simulates the large-scale primitive proliferation generated by expansion operations in geometry shaders, such as generating multiple output primitives from a single input primitive (e.g., expanding multiple surface segments from a triangle patch). Its set values ​​cover typical expansion ratios such as 1:1, 1:4, 1:16, and even 1:64. The geometry subdivision complexity parameter controls the mathematical interpolation strategy and reconstruction density used for each primitive during subdivision, such as using Bezier curves, B-splines, or the Catmull-Clark subdivision algorithm. Different levels of detail (LODs) and control point densities are set to construct test patch structures with varying computational costs. Furthermore, primitive expansion behavior, patch structure characteristics, and surface smoothness targets are combined to generate a set of standardized geometric test workloads covering low, medium, and high complexity. Each workload is assigned a corresponding task identifier and transformation template, ensuring that it accurately maps to the target computation path upon entering the test channel. The geometry test load is fed into the geometry shader decoupling unit, which has been previously structurally separated via the state component q2 and equipped with a second-stage performance isolation controller to isolate the performance response of the geometry processing stage within a highly coupled rendering pipeline. This isolation controller, based on a power-integral feedback control structure, takes the geometry processing response error signal as input and implements a nonlinear power-integral loop to regulate the output, resulting in a robust, smooth, and dynamic control behavior. During operation, the controller monitors the input pressure after primitive expansion and the geometric complexity of the tessellation surface on the hardware cache bandwidth and processing pipeline in real time. Based on the real-time error state, the controller adjusts the primitive generation rate, tessellation depth, and culling strategy to ensure a stable match between the geometry processing pipeline and the target test load, avoiding critical overflow caused by sudden increases in the upstream load and suppressing the geometry output scale due to feedback from the downstream rasterization module, thereby maintaining a stable second isolated operating state. This second isolated operating state is monitored for primitive expansion efficiency, geometry transformation throughput, tessellation performance, and primitive culling rate. The primitive expansion efficiency reflects the ratio of the number of new primitives actually successfully generated after the input primitives are processed in the geometric stage to the theoretical expansion target, which is used to evaluate the effectiveness of the expansion mechanism and the smoothness of scheduling; the geometric transformation throughput is measured by the number of geometric units processed per unit time, quantifying the degree of matching between the pipeline carrying capacity and the execution load; the surface subdivision performance combines multiple factors such as the complexity of the subdivision algorithm, sampling accuracy, and the actual surface smoothness quality to establish a dual evaluation dimension of time and accuracy; the primitive culling rate evaluates the system's ability to successfully identify and discard invalid primitives (such as back faces or outside the viewing cone) after completing expansion and transformation, reflecting the efficiency of eliminating spatial redundancy.All monitoring indicators establish a serialized sampling stream based on the time axis. Statistical features such as peak values, mean values, and stability coefficients are collected in each control cycle and compared with the preset performance intervals to form the second performance monitoring data. The second performance monitoring data is input into a Kalman filter based on fractional calculus theory to perform dynamic performance tracking and coupled interference filtering. The filter model introduces an α-order fractional derivative operator to construct the system state equation, which enables high-fidelity modeling of slow variable evolution, historically dependent scheduling offsets, and high-order nonlinear fluctuation behaviors in the geometric stage. Its core filter structure consists of a state prediction equation, an observation update equation, a noise covariance matrix, and a state transfer matrix. In each frame data update, a three-stage closed loop of state prior estimation, observation correction, and error convergence is performed to ensure that the output state estimate can truly reflect the independent response capability of the geometric stage under specific load conditions. During operation, the filter uses coupled state feedback signals from previous and subsequent stages to model and analyze existing cross-interference paths. By minimizing observation errors and state prediction residuals, it identifies and eliminates noise sources outside the current stage, resulting in the final output of geometric performance data with good isolation, stability, and dynamic interpretability. The output of the geometry shader's second performance test data includes decoupled values ​​for static indicators such as primitive expansion capability, subdivision surface efficiency, throughput, and culling capability, as well as structural metadata such as dynamic change trends in time series, disturbance response models, and state stability evaluation coefficients.

[0035] In a specific embodiment, the step of inputting the rasterization test load into the rasterization unit decoupling unit for stage isolation performance test processing to obtain third performance test data of the rasterization unit may specifically include the following steps: Generate hierarchical loads for rasterization datasets based on preset pixel fill rate gradient parameters and coverage complexity parameters, and obtain rasterization test loads with different pixel densities, depth test complexities, and coverage variation ranges. Inputting the rasterization test load into the third stage performance isolation controller of the rasterization unit decoupling unit to perform nonlinear power integral control to obtain a third isolation operation state; Performing pixel fill rate monitoring, depth test efficiency monitoring, coverage calculation performance monitoring, and pixel output throughput monitoring on the third isolated operating state to obtain third performance monitoring data; The third performance monitoring data is input into a fractional-order Kalman filter to perform performance data optimization and eliminate coupling interference between the previous and next stages, so as to obtain third performance test data of the rasterization unit.

[0036] Specifically, a multi-dimensional controllable load generation mechanism is established based on the spatial characteristics of pixel fill rate and coverage. The system constructs a pixel density change surface according to the preset pixel fill rate gradient parameters. The surface covers a variety of typical distribution scenarios, ranging from sparse filling (such as 512×512 rendering window, low-complexity geometry) to high-density filling (such as 4096×4096 ultra-high resolution, almost full viewport). At the same time, a primitive overlap ratio model is established in combination with the coverage complexity parameter. The model forms different coverage gradient change conditions by adjusting geometric layout control parameters such as spatial overlap between primitives, view frustum interleaving area, and depth interleaving order. For the depth test complexity parameter, typical depth test modes including Z-buffer forward sorting, reverse order, random depth overlap, and non-uniform occlusion distribution are set. The multi-dimensional rasterization data set generated by combining these parameters constitutes a hierarchical rasterization test load set covering pixel fill rate, coverage variation amplitude, and depth test complexity. The rasterization test load is fed into the third-stage performance isolation controller of the rasterization unit decoupling unit to establish a coupling shielding mechanism during operation. This controller uses a nonlinear power-integral control law as its core feedback mechanism. The exponential term, combined with a sign function, is introduced into its control expression to achieve nonlinear weighting and response compensation for input perturbations, effectively addressing nonstationary load perturbations caused by varying pixel density. During operation, the controller monitors the load response deviation along the rasterization path in real time. Using the pixel filling error term as the control variable, it combines a power-integral response strategy to adjust the internal pixel buffer scheduling, fragment generation and distribution rate, depth-stencil test order, and MSAA sampling process state. This allows the entire rasterization process to suppress feedback loops between previous and subsequent stages while maintaining load input stability, thereby establishing a fully isolated operating state (the third isolated operating state). In this state, any pipeline blocking effects caused by upstream geometric mismatches or downstream pixel shading output backpressure are shielded. The rasterization unit responds only to the current load input and autonomously completes the entire process of fragment generation, depth filtering, coverage calculation, and pixel output, ensuring the single-stage independence and structural stability of the test data. When the isolation state is formed, the rasterization monitoring channel is started to conduct multi-dimensional monitoring of the actual operating performance of this stage, mainly including four major indicators: pixel fill rate monitoring, depth test efficiency monitoring, coverage calculation performance monitoring and pixel output throughput monitoring.Pixel fill rate monitoring assesses the efficiency of successfully converting fragments into writeable pixels after completing the entire rasterization computation process per unit time, a key metric for measuring rasterization processing saturation. Depth test efficiency focuses on the hit, reject, and skip path statistics during the Z-buffer decision phase, reflecting the accuracy and computational time ratio of the fragment culling mechanism. Coverage calculation performance monitoring primarily assesses the regional interleaving load of the current rendering scene based on primitive coverage analysis and screen-space fragment Boolean reconstruction, reflecting the GPU's ability to withstand complex occlusion calculations. Pixel output throughput, measured by the coupling efficiency between fragment conversion rate, viewport write rate, and framebuffer output scheduling, is the ultimate indicator of the completeness of the entire rasterization phase. The system utilizes a timestamp-weighted scheduling method and a ring buffer analysis mechanism to perform high-frequency sampling on each metric. Peak extraction, mean calculation, stability fluctuation analysis, and cross-covariance modeling are performed across multiple load levels and control frame windows to generate tertiary performance monitoring data. This tertiary performance monitoring data is then fed into a fractional-order Kalman filter for performance data optimization and interference elimination between previous and subsequent stages. Leveraging the temporal memory and non-local modeling capabilities of fractional derivative operators, this filter introduces a delay-correlation response factor into the state prediction equation and constructs an enhanced state transition model based on a multi-stage state estimation path. This allows for each filtering iteration to consider not only the observation error of the current frame but also the residual trends and state evolution patterns of the previous N frames into the state update calculation. In its implementation, the filter constructs a disturbance observation matrix using the rasterization stage's own behavior model and the residuals of the previous and subsequent perturbation predictions. The residual threshold drift amplitude is used to determine the presence of external coupling interference and to determine the state correction weight accordingly. This effectively filters out data perturbations and feedback that are not core performance fluctuations of the current stage, ensuring the representativeness and structural consistency of the output state estimate. The filter outputs third-party performance test data for the rasterization unit. This data set includes absolute performance metrics such as pixel fill efficiency, depth test response time, coverage calculation density, and pixel output channel saturation under steady-state conditions. It also includes the dynamic evolution of each metric under different load levels, stability evaluation indicators, estimated variance ranges, and optimized residual determination results.

[0037] In a specific embodiment, the step of inputting the pixel test load into the pixel shader decoupling unit for stage isolation performance test processing to obtain the fourth performance test data of the pixel shader may specifically include the following steps: Generate multi-dimensional loads for pixel data sets based on preset texture complexity gradient parameters and shading computation complexity parameters, and obtain pixel test loads with different texture sampling densities, shading instruction complexities, and render target output formats. Inputting the pixel test load into the fourth stage performance isolation controller of the pixel shader decoupling unit to perform adaptive power integral control to obtain a fourth isolation operation state; Performing pixel throughput monitoring, texture access efficiency monitoring, shading calculation performance monitoring, and render target write rate monitoring on the fourth isolated operating state to obtain fourth performance monitoring data; The fourth performance monitoring data is input into a fractional-order Kalman filter for pixel-level performance analysis and upstream stage coupling interference suppression to obtain fourth performance test data of the pixel shader.

[0038] Specifically, based on the high-frequency calculation and texture access behavior patterns in the graphics card shading path, the system presets a series of texture complexity gradient parameters and shading calculation complexity parameters to control the multi-dimensional load intensity of the test data. In terms of texture complexity gradient, the texture sampling density is controlled by parameters such as the number of texture layers, sampling methods (such as nearest neighbor, bilinear, trilinear, anisotropic, etc.), texture map resolution and hierarchy (such as mipmap level), thereby generating a continuous load level from low-frequency single-layer sampling to high-frequency 16-layer PBR texture mixed sampling. In terms of shading computational complexity, by controlling factors such as the number of operation instruction types in the shader, the number of control flow branch layers, the loop body expansion level and the dependency nesting depth, test paths with different computational intensities are constructed, ranging from simple color mapping, basic lighting, Blinn-Phong model, real-time shadows, PBR materials to screen-space reflections. At the same time, in terms of rendering target output format, multiple output structures such as RGB8, RGBA16F, RGBA32F are set to change the load pressure of the pixel write path, and the frame buffer data format, alignment strategy and anti-aliasing strategy are linked to simulate the output characteristics of actual rendering scenes, thereby forming a pixel test load set with real business characteristics. The pixel test load is injected into the pixel shader decoupling unit via a standard interface. Internally, the decoupling unit implements structural isolation of the pixel processing pathway based on the Q3 component of the quaternion state. A fourth-stage performance isolation controller serves as the core scheduling mechanism. This controller employs an adaptive power-integral control strategy. Its core logic transforms the pixel processing error signal through a nonlinear power-exponential function, then dynamically adjusts the integral-feedback path. This controller adjusts texture sampling thread allocation, shader instruction entry rate, and rendering write cadence in real time. This automatically adjusts controller gains based on the pixel load during runtime to accommodate load spikes, compute bottlenecks, texture access jitter, or write blocking in the pixel processing pipeline, thereby establishing a fourth isolated operating state. In this state, the pixel shader's execution behavior is guided by the test load characteristics, masking fragment generation jitter in the preceding rasterization stage, output density variations in the geometry stage, and deep transform dilation effects in the vertex stage. This ensures that test results reflect the inherent capabilities of the pixel processing rather than incidental behavior introduced by other system modules. Perform multi-dimensional performance monitoring of the pixel shader's execution behavior, mainly covering four major indicators: pixel throughput, texture access efficiency, shading calculation performance, and render target write rate.Pixel throughput measures the overall computational power of the pixel pipeline, using the number of effective pixels processed per unit time as its core metric. Texture access efficiency monitoring records behavioral characteristics such as the hit rate, memory bandwidth consumption, and address reconstruction latency of texture sampling calls at each layer, reflecting the efficiency of GPU texture cache scheduling and multi-layer sampling distribution. Shading compute performance monitoring focuses on ALU occupancy, instruction density, dependency depth, and branch jump frequency within the shader execution thread, assessing the GPU's actual execution capability and scheduling density for high-complexity pixel computation tasks. Render target write rate comprehensively assesses the bandwidth carrying capacity and multi-channel simultaneous write capability of the final data output path through metrics such as output frame buffer write latency, write merge ratio, and memory bandwidth utilization. The system constructs a high-precision, high-temporal-resolution multi-channel monitoring data sequence by sampling on a sub-frame basis within the test cycle. Statistical modeling is then performed on each metric, including mean, variance, peak response time, and sliding window stability, to form a fourth performance monitoring dataset. This fourth performance monitoring data is then fed into a fractional-order Kalman filter for pixel-level performance analysis and upstream coupling interference suppression. This filter utilizes an α-order fractional-order state update mechanism. The filter incorporates a fractional-order differential operator with memory into its state transition equations, cumulatively modeling performance residuals over multiple past moments. It also constructs a co-evolution mechanism between the prediction covariance matrix and the observation update vector. This mechanism comprehensively considers historical dependency trends, perturbation transition probabilities, and currently monitored abnormal behavior in each state update, enabling precise identification and stable tracking of the system state. The filter also incorporates a structural residual detection module to dynamically identify non-pixel-level interference components in observed metrics. The system sets residual tolerance thresholds and drift rate judgment rules to determine whether current performance fluctuations stem from current-stage processing bottlenecks or from upstream-stage interference transfers. The system then adjusts the Kalman gain and state correction step size accordingly, making the output more physically interpretable and meaningful for system positioning. The final pixel shader fourth performance test data output includes decoupled estimates of four core performance metrics, a dynamic evolution trend map, a stability evaluation matrix, and interference component residual analysis results.

[0039] In a specific embodiment, the process of executing step 300 may specifically include the following steps: Performing multi-dimensional standardization and normalization processing on the first performance test data, the second performance test data, the third performance test data, and the fourth performance test data to obtain a standardized performance data matrix for each stage in the rendering pipeline; Based on the mutual information entropy algorithm, the inter-stage performance correlation calculation and dependency analysis are performed on the standardized performance data matrix to obtain the inter-stage performance correlation matrix; Inputting the inter-stage performance correlation matrix into a multi-objective particle swarm optimization algorithm to identify performance bottlenecks and solve bottleneck weight coefficients, thereby obtaining performance bottleneck weight coefficients for each stage; A rendering pipeline bottleneck location decision tree is constructed based on the performance bottleneck weight coefficients of each stage and bottleneck priorities are sorted to obtain performance bottleneck location results for each stage of the rendering pipeline.

[0040] Specifically, the first, second, third, and fourth performance test data were subjected to multi-dimensional standardization and normalization to eliminate analytical bias caused by data scale differences and construct a computable evaluation matrix. Each metric was subjected to maximum-minimum normalization or Z-score normalization. Based on the metric's characteristics, the logical direction of "larger is better" or "smaller is better" was determined. After adjusting the objective function, the data was uniformly mapped to the [0, 1] interval. This eliminated the perturbations of extreme values ​​and pseudo-anomalies on the overall analysis structure. A standardized performance data matrix, such as N×M, was constructed, where N is the number of rendering stages and M is the number of independent performance sub-indicators involved in each stage. The standardized performance data matrix was calculated using the mutual information entropy algorithm to extract the nonlinear coupling relationships and interdependence between performance indicators at different stages. Mutual information entropy, an important information theory tool for measuring the amount of shared information between variables, can quantify the strength of the correlation between two stages in terms of multi-dimensional performance trends. In actual operation, the standardized performance data is discretized, and a joint probability distribution is used to estimate the probability of coordinated changes in various indicator combinations between each pair of stages, thereby calculating their mutual information. The marginal entropy of each stage's performance vector is used as a normalization factor to construct a normalized mutual information entropy matrix. Each element in this matrix represents the strength of performance interaction and the degree of coupling risk between any two stages during the overall operation, resulting in an inter-stage performance correlation matrix. This inter-stage performance correlation matrix is ​​then fed into a multi-objective particle swarm optimization algorithm to identify performance bottlenecks and determine weight coefficients. The algorithm treats each rendering stage as an individual particle to be optimized, embeds initial bottleneck weights in the particle solution vector, and defines a multi-objective function system: the first objective is to minimize the standard deviation of the overall system performance fluctuation; the second objective is to maximize the load ratio of the performance contribution of the key stage; and the third objective is to minimize the overall system response delay or energy cost. All these objectives jointly constrain the update direction of the particle solution. In each round of iteration, particles adjust their speed and position based on the historical optimal solution and the global optimal guidance vector. At the same time, referring to the coupling relationship between stages revealed in the performance correlation matrix, mutual information driving factors are embedded in the update logic to prevent the optimization results from being misled by non-critical stages. By continuously iterating and dynamically adjusting the weight distribution coefficients of each stage, the algorithm gradually converges to the multi-objective Pareto optimal solution set and outputs a stable set of bottleneck weight coefficients. The higher the value of the stage, the greater the possibility and criticality of the bottleneck in the performance structure of the entire pipeline, reflecting the greater its impact on rendering efficiency, energy consumption or resource utilization. A bottleneck location decision tree model is constructed based on the performance bottleneck weight coefficients of each stage to achieve a hierarchical understanding and priority sorting of the overall bottleneck structure of the rendering pipeline.During the construction process, bottleneck weights are used as the basis for root node splitting. For each branch, derived performance indicators such as resource utilization, utilization saturation, volatility variance, and indicator aggregate covariance are used as auxiliary criteria to construct the sub-node partitioning logic. This results in a structured decision tree that reflects the progressive relationship between bottleneck dominance, indicator anomaly, and resource intensity. The tree model optimizes paths using information gain or the GINI coefficient to ensure interpretability and node splitting stability during each stage. Incorporating a redundancy analysis mechanism, it prunes path branches with abnormal indicators but low system sensitivity to improve bottleneck location efficiency and accuracy. The decision tree outputs a prioritized bottleneck list, identifying the most bottlenecking stages in the current test scenario. For example, in high-primitive complexity tests, the geometry shader is identified as the primary bottleneck, while in texture sampling-intensive tasks, the pixel shader is identified as the primary bottleneck. The tree also provides diagnostic explanations for the numerical structure of bottleneck characteristics at each stage, such as determining whether a particular stage's bottleneck is caused by insufficient throughput, reduced cache hit rates, or dense control flow instructions. In addition, the system outputs automated suggestions based on the bottleneck level. For example, when the bottleneck coefficient is greater than a certain threshold, it recommends executing optimization behaviors such as instruction path reconstruction, load downsampling, resource reallocation, or cache strategy adjustment, thus forming a closed loop of performance analysis and strategy feedback.

[0041] The above describes the performance test method of the graphics card in the embodiment of the present invention. The following describes the performance test device of the graphics card in the embodiment of the present invention. Figure 2 , an embodiment of a performance testing device for a graphics card according to an embodiment of the present invention includes: A decoupling module 11 is used to perform quaternion stage decoupling on the rendering pipeline of the graphics card to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit, and a pixel shader decoupling unit; a performance testing module 12, configured to perform stage-isolated performance tests based on the vertex shader decoupling unit, the geometry shader decoupling unit, the rasterization unit decoupling unit, and the pixel shader decoupling unit, respectively, to obtain first performance test data of the vertex shader, second performance test data of the geometry shader, third performance test data of the rasterization unit, and fourth performance test data of the pixel shader; The comprehensive analysis module 13 is used to perform comprehensive analysis on the first performance test data, the second performance test data, the third performance test data and the fourth performance test data to obtain the performance bottleneck positioning results of each stage of the rendering pipeline.

[0042] Through the collaborative efforts of these components, quaternion encoding conversion and decoupling operators effectively separate the coupling states of each rendering pipeline stage, achieving true stage independence. Quaternion rotation transformation matrices and stage state selection functions precisely control the separation process of each stage, avoiding the information loss associated with traditional decoupling methods. Each decoupling unit is equipped with an adaptive stage performance isolation controller, effectively eliminating the mutual influence of upstream and downstream stages and obtaining true single-stage performance data. A fractional-order Kalman filter is used for state estimation and interference elimination, significantly improving the accuracy and reliability of performance test data. A specialized monitoring metric system, such as vertex throughput, primitive expansion efficiency, and pixel fill rate, is designed to address the characteristics of each stage, enabling comprehensive performance evaluation. Real-time performance monitoring data collection captures dynamic performance changes, providing a rich data foundation for performance analysis. The mutual information entropy algorithm analyzes performance correlations between stages, accurately identifying the dependencies and impact of each stage. A multi-objective particle swarm optimization algorithm is used for bottleneck identification, simultaneously considering multiple dimensions such as bottleneck severity, duration, and impact range. A bottleneck location decision tree is constructed to prioritize bottlenecks, providing clear guidance for performance optimization. In addition, multi-level test loads are generated based on preset complexity gradient parameters to ensure the comprehensiveness and pertinence of the test, and improved power integral control processing technology is used to achieve precise adjustment and control of the operating status of each stage.

[0043] See also Figure 3 , Figure 3 This is a schematic block diagram of the structure of an electronic device 300 provided in an embodiment of the present invention. The electronic device 300 includes a processor 301 and a memory 302. The processor 301 and the memory 302 are connected via a device bus 303, wherein the memory 302 may include a non-volatile storage medium and an internal memory.

[0044] The non-volatile storage medium can store a computer program. The computer program includes program instructions. When the program instructions are executed by the processor 301, the processor 301 can execute any of the above-mentioned graphics card performance testing methods.

[0045] The processor 301 is used to provide computing and control capabilities to support the operation of the entire electronic device 300 .

[0046] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor 301, the processor 301 can execute any of the above-mentioned performance testing methods for the graphics card.

[0047] Those skilled in the art will understand that Figure 3The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation on the electronic device 300 involved in the solution of the present invention. The specific electronic device 300 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0048] It should be understood that the processor 301 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0049] It should be noted that those skilled in the art will clearly understand that for the sake of convenience and brevity of description, the specific working process of the electronic device 300 described above can refer to the corresponding process of the aforementioned graphics card performance testing method, which will not be repeated here.

[0050] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0051] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for enabling an electronic device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0052] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A performance testing method for a graphics card, characterized in that: include: Decouple the graphics card's rendering pipeline at the quaternion stage to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit, and a pixel shader decoupling unit; Performing stage-isolated performance tests based on the vertex shader decoupling unit, the geometry shader decoupling unit, the rasterization unit decoupling unit, and the pixel shader decoupling unit, respectively, to obtain first performance test data of the vertex shader, second performance test data of the geometry shader, third performance test data of the rasterization unit, and fourth performance test data of the pixel shader; A comprehensive analysis is performed on the first performance test data, the second performance test data, the third performance test data, and the fourth performance test data to obtain performance bottleneck positioning results at each stage of the rendering pipeline.

2. The performance testing method for a graphics card according to claim 1, wherein: The quaternion stage decoupling of the rendering pipeline of the graphics card is performed to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit and a pixel shader decoupling unit, including: Obtaining coupling state information of a rendering pipeline in a graphics card, and performing quaternion encoding conversion on the coupling state information to obtain a pipeline state quaternion; Constructing a quaternion rotation transformation matrix and a phase state selection function, and generating a quaternion decoupling operator based on the quaternion rotation transformation matrix and the phase state selection function; Inputting the pipeline state quaternion into the quaternion decoupling operator to perform stage state separation operation processing to obtain a vertex shader separation state component, a geometry shader separation state component, a rasterization unit separation state component, and a pixel shader separation state component; The vertex shader separation state component, the geometry shader separation state component, the rasterization unit separation state component and the pixel shader separation state component are respectively encapsulated into independent units to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit and a pixel shader decoupling unit.

3. The performance testing method for a graphics card according to claim 1, wherein: The stage-isolation performance test is performed based on the vertex shader decoupling unit, the geometry shader decoupling unit, the rasterization unit decoupling unit, and the pixel shader decoupling unit, respectively, to obtain first performance test data of the vertex shader, second performance test data of the geometry shader, third performance test data of the rasterization unit, and fourth performance test data of the pixel shader, including: Inputting the vertex test load into the vertex shader decoupling unit to perform a stage isolation performance test to obtain first performance test data of the vertex shader; Inputting the geometry test load into the geometry shader decoupling unit to perform a stage isolation performance test to obtain second performance test data of the geometry shader; Inputting the rasterization test load into the rasterization unit decoupling unit to perform stage isolation performance test processing to obtain third performance test data of the rasterization unit; The pixel test load is input into the pixel shader decoupling unit to perform stage isolation performance test processing to obtain fourth performance test data of the pixel shader.

4. The performance testing method for a graphics card according to claim 3, wherein: Inputting the vertex test load into the vertex shader decoupling unit to perform stage isolation performance testing to obtain first performance test data of the vertex shader includes: Generate loads for vertex datasets based on preset geometric complexity gradient parameters to obtain vertex test loads with different vertex densities, vertex attribute complexities, and transformation matrix complexities. Inputting the vertex test load into the first stage performance isolation controller of the vertex shader decoupling unit to perform pipeline load power integral control to obtain a first isolated operating state; Performing vertex throughput monitoring, vertex attribute processing latency monitoring, vertex cache hit rate monitoring, and transformation instruction execution efficiency monitoring on the first isolated operating state to obtain first performance monitoring data; The first performance monitoring data is input into a fractional-order Kalman filter for state estimation and coupling interference elimination to obtain first performance test data of the vertex shader.

5. The performance testing method for a graphics card according to claim 3, wherein: Inputting the geometry test load into the geometry shader decoupling unit to perform a stage isolation performance test to obtain second performance test data of the geometry shader includes: Generate multi-level loads for the geometric data set based on preset primitive expansion multiple parameters and geometric subdivision complexity parameters, and obtain geometric test loads containing different primitive expansion ratios, geometric subdivision precisions, and surface subdivision parameters; Inputting the geometric test load into the second stage performance isolation controller of the geometry shader decoupling unit for power integral control to obtain a second isolated operating state; Performing primitive expansion efficiency monitoring, geometric transformation throughput monitoring, surface subdivision performance monitoring, and primitive culling rate monitoring on the second isolated operating state to obtain second performance monitoring data; The second performance monitoring data is input into a fractional-order Kalman filter for dynamic performance tracking and filtering out coupling interference between the previous and next stages to obtain second performance test data of the geometry shader.

6. The performance testing method for a graphics card according to claim 3, wherein: Inputting the rasterization test load into the rasterization unit decoupling unit to perform stage isolation performance test processing to obtain third performance test data of the rasterization unit includes: Generate hierarchical loads for rasterization datasets based on preset pixel fill rate gradient parameters and coverage complexity parameters, and obtain rasterization test loads with different pixel densities, depth test complexities, and coverage variation ranges. Inputting the rasterization test load into the third stage performance isolation controller of the rasterization unit decoupling unit to perform nonlinear power integral control to obtain a third isolation operation state; Performing pixel fill rate monitoring, depth test efficiency monitoring, coverage calculation performance monitoring, and pixel output throughput monitoring on the third isolated operating state to obtain third performance monitoring data; The third performance monitoring data is input into a fractional-order Kalman filter to perform performance data optimization and eliminate coupling interference between the previous and next stages, so as to obtain third performance test data of the rasterization unit.

7. The performance testing method for a graphics card according to claim 3, wherein: Inputting the pixel test load into the pixel shader decoupling unit to perform stage isolation performance test processing to obtain fourth performance test data of the pixel shader includes: Generate multi-dimensional loads for pixel data sets based on preset texture complexity gradient parameters and shading computation complexity parameters, and obtain pixel test loads with different texture sampling densities, shading instruction complexities, and render target output formats. Inputting the pixel test load into the fourth stage performance isolation controller of the pixel shader decoupling unit to perform adaptive power integral control to obtain a fourth isolation operation state; Performing pixel throughput monitoring, texture access efficiency monitoring, shading calculation performance monitoring, and render target write rate monitoring on the fourth isolated operating state to obtain fourth performance monitoring data; The fourth performance monitoring data is input into a fractional-order Kalman filter for pixel-level performance analysis and upstream stage coupling interference suppression to obtain fourth performance test data of the pixel shader.

8. The performance testing method of a graphics card according to claim 1, wherein: The comprehensive analysis of the first performance test data, the second performance test data, the third performance test data, and the fourth performance test data to obtain the performance bottleneck location results of each stage of the rendering pipeline includes: Performing multi-dimensional standardization and normalization processing on the first performance test data, the second performance test data, the third performance test data, and the fourth performance test data to obtain a standardized performance data matrix for each stage in the rendering pipeline; Based on the mutual information entropy algorithm, the inter-stage performance correlation calculation and dependency analysis are performed on the standardized performance data matrix to obtain the inter-stage performance correlation matrix; Inputting the inter-stage performance correlation matrix into a multi-objective particle swarm optimization algorithm to identify performance bottlenecks and solve bottleneck weight coefficients, thereby obtaining performance bottleneck weight coefficients for each stage; A rendering pipeline bottleneck location decision tree is constructed based on the performance bottleneck weight coefficients of each stage and bottleneck priorities are sorted to obtain performance bottleneck location results for each stage of the rendering pipeline.

9. A performance testing device for a graphics card, characterized in that: Used to execute the performance testing method for a graphics card according to any one of claims 1 to 8, the performance testing device for a graphics card comprising: A decoupling module is used to decouple the graphics card's rendering pipeline at the quaternion stage to obtain a vertex shader decoupling unit, a geometry shader decoupling unit, a rasterization unit decoupling unit, and a pixel shader decoupling unit; a performance testing module, configured to perform stage-isolated performance tests based on the vertex shader decoupling unit, the geometry shader decoupling unit, the rasterization unit decoupling unit, and the pixel shader decoupling unit, respectively, to obtain first performance test data of the vertex shader, second performance test data of the geometry shader, third performance test data of the rasterization unit, and fourth performance test data of the pixel shader; The comprehensive analysis module is used to comprehensively analyze the first performance test data, the second performance test data, the third performance test data and the fourth performance test data to obtain the performance bottleneck positioning results of each stage of the rendering pipeline.

10. An electronic device, characterized in that: The electronic device comprises: a memory and at least one processor, wherein instructions are stored in the memory; The at least one processor calls the instruction in the memory to enable the electronic device to execute the performance testing method for a graphics card according to any one of claims 1 to 8.

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