Boundary scan test structure and method

Abstract

The invention discloses a boundary scan test structure and method, the boundary scan test structure is used for circuit board card interface interconnection test, and a test platform main control unit and a tested mainboard carry out data interaction only through a JTAG channel; selecting three signal lines from the signal lines of each tested slot as test control and data return channels; and the test control and data return channel is used for customizing a protocol to transmit a test command and a test result. According to the invention, a parallel test scheme that a plurality of back JTAG cables are needed in the prior art is abandoned, and a technical scheme that a command-back bus formed by combining one master control JTAG channel with three signal lines in each slot in a time division multiplexing manner is redesigned, so that hardware connecting lines are replaced by software time sequences, and the number of hardware connecting lines is greatly reduced; and the reliability and the anti-interference performance of the connection in the production test are obviously improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a boundary scan test structure and method. Background Art

[0002] Boundary scan testing developed in the 1990s. With the advent of large-scale integrated circuits (LSIs), printed circuit board (PCB) manufacturing processes evolved towards smaller, thinner, and more compact designs. Traditional ICT testing was no longer sufficient to meet the testing requirements of these products. Due to the large number of chip pins, the small size of components, and the extremely high density of boards, probing was impossible. This led to the emergence of a new testing technology, defined by the Joint Test Action Group (JTAG), as boundary scan testing. Boundary scan is a collection of design rules applied at the integrated circuit level, allowing software to reduce the ever-increasing costs of designing, manufacturing, and testing digital systems. Boundary scan testing primarily tests the interconnections between integrated circuit chips. Using built-in instructions specified by the IEEE 1149.1 / 1149.6 protocols, the ICs in the boundary scan chain enter boundary scan mode. By controlling the input / output states of the IC pins, the inter-chip interconnects are tested for open and short circuit faults. Boundary scan testing can quickly and accurately verify the reliability of connections between multiple chip pins, improving testing efficiency. Due to its short test time and high reliability, boundary scan testing is now widely used in consumer electronics and semiconductor fields.

[0003] When producing and testing circuit boards with high reliability requirements (such as server motherboards), it is necessary to perform boundary scan testing on the plug-in interconnection characteristics of all connector slots on the motherboard under test. A typical test system is as follows: Figure 1 As shown in the figure, the "test platform main control unit" sends a boundary scan test pattern to the CPU unit on the "tested motherboard" through the "test pattern output JTAG" channel, causing the specified test vector levels to be generated on the pins of "Slot 1...Slot N" under test. The "test platform main control unit" then uses the "test data return JTAG" channel to allow the "dummy cards" inserted in each slot to capture the voltage levels received on each pin of the slot and transmit these captured measurement results back to the "test platform main control unit". The "test platform main control unit" can then compare the sent test pattern with the received return test voltage values ​​to determine whether the interconnect characteristics of each pin of each slot on the tested motherboard have passed the test.

[0004] A drawback of existing boundary scan testing technology is that, when the motherboard under test has a large number of slots, multiple JTAG cables are required to transmit test data. In complex production environments, these multiple JTAG cables are prone to unreliable contact and unstable operation due to electromagnetic interference, significantly reducing the reliability of the entire test system and leading to serious consequences such as frequent disconnections on the production line.

[0005] Dummy Card: Also known as Dummy Load or Dummy Board, it is a testing tool that simulates a real chip or load.

[0006] Dummy Card FPGA: Simulates and verifies the onboard FPGA. Summary of the Invention

[0007] The Summary of the Invention introduces a series of simplified concepts, which are simplifications of existing technologies in the field and are further described in detail in the Detailed Description of the Invention. The Summary of the Invention is not intended to define the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0008] The technical problem to be solved by the present invention is to provide a boundary scan test structure that can simplify the lines between the main control unit of the test platform and the motherboard under test and the dummy card, especially save data return lines, and improve the reliability and anti-interference in complex production test environments.

[0009] To solve the above technical problems, the present invention provides a boundary scan test structure, which is used for circuit board card interface interconnection testing. The test platform main control unit and the tested motherboard only exchange data through the JTAG channel;

[0010] Select three signal lines from each tested slot as test control and data return channels;

[0011] The test control and data return channels are used to transmit test commands and test results using custom protocols.

[0012] Optionally, the boundary scan test structure is further improved, wherein the three signal lines are named as the first signal line, the second signal line and the third signal line, and the signals transmitted by them are marked as the first signal, the second signal and the third signal PSYN, PTX and PRX respectively;

[0013] The first signal and the second signal are signals sent by the tested mainboard to the Dummy Card, which are used to assist in time synchronization and send command data to the Dummy Card respectively;

[0014] The third signal is a signal that the Dummy Card replies to the tested mainboard, and is used by the Dummy Card to reply command result data to the tested mainboard.

[0015] To solve the above technical problems, the present invention provides a boundary scan test method, which is implemented based on the boundary scan test structure and includes the following steps:

[0016] S1, performs interconnection test on JTAG channel;

[0017] In step S2, the test platform main control unit generates a test pattern level combination on the remaining signal lines under test that are not assigned to the tested slot through the JTAG channel, and controls the boundary scan chain of the tested motherboard MCU through the JTAG channel to generate level capture and result return commands for the test control and data return channels.

[0018] After receiving the command, the Dummy Card captures the current test signal level and transmits the level capture result back to the CPU boundary scan chain on the motherboard under test through the test control and data return channel;

[0019] In step S4, the main control unit of the test platform reads the returned level capture result through the JTAG channel and compares it with the sent test pattern level combination to complete the interconnection test of each pin of each slot.

[0020] Optionally, the boundary scan test method is further improved by performing a parallel interconnection test on each slot if the third signals selected in different slots correspond to different CPU pins;

[0021] If the third signals selected in different slots correspond to the same pin of the CPU, a serial interconnection test is performed on each slot.

[0022] Optionally, the boundary scan test method may be further improved by replacing step S4 with the following steps:

[0023] The test platform main control unit controls the boundary scan chain of the CPU of the motherboard under test through the JTAG channel, causing the test control and data return channels to generate multiple customized test pattern generation commands. When each test pattern generation command ends, the test platform main control unit directly reads the current level values ​​of each pin captured by the MCU of the motherboard under test through the JTAG channel, and compares them with the test pattern level combination currently generated by the Dummy Card to complete the interconnection test of each pin of each slot.

[0024] The Dummy Card generates test pattern levels under the control of the test platform master unit, and the MCU of the motherboard under test captures the test signal levels. This significantly reduces the amount of level capture result data that needs to be transmitted back, increasing test speed.

[0025] The working principle and technical effects of the present invention are as follows:

[0026] The present invention abandons the existing parallel testing solution that requires multiple return JTAG cables and redesigns it into a technical solution that time-shares a master JTAG channel combined with a "command-return" bus consisting of three signal lines (PSYN / PTX / PRX) per slot, thereby using software timing in exchange for a significant reduction in hardware connections.

[0027] The present invention only retains one JTAG main link between the test platform main control unit and the motherboard under test (the result data is first cached in the Dummy Card FPGA and then read out in time-sharing through the unique master JTAG channel, reducing the number of hardware lines from multiple to one). The Dummy Card in each slot no longer needs to be connected to the return JTAG, greatly simplifying the line connection between the "test platform main control unit" and the "motherboard under test + Dummy Card", and significantly improving the reliability and anti-interference performance of the connection during production testing.

[0028] The key design concept of this invention is to place test result data, which in existing solutions requires multiple cables for transmission, onto the master JTAG channel and transmit it back to the test platform's main control unit in a time-sharing manner. Therefore, this invention is particularly suitable for situations where the number of input and output signals in the interface slot under test is small. Compared with existing solutions, this solution will result in a longer test completion time. The following example uses a test system with a relatively large number of signals in the tested slot to provide an estimate of the overall test time:

[0029] Assume that the JTAG clock frequency on the test platform is 200 kHz (clock cycle 5 μs), the CPU boundary scan chain length is at the level of 1000 registers, and the level capture data of 160 pins on the tested card slot needs to be transmitted back (160 / 8 = 20 bytes). These 20 bytes are split into two 10-byte return data packets. Referring to the typical embodiment provided by the present invention, in the worst case, all level test result data is captured by the dummy card and then transmitted back:

[0030] The level capture command for each data interaction costs 3+4+8+2=17 baud; the result return response for each data interaction costs 3+4+10*8+2=89 baud; the total cost is 106 baud.

[0031] Each baud can be achieved using one JTAG EXTEST instruction cycle. The number of JTAG clock cycles consumed by one JTAG EXTEST instruction cycle roughly matches the length of the JTAG boundary scan chain. Therefore, the duration of one baud is approximately: 1000 x 5µs = 5ms. Therefore, each data exchange command takes approximately: 5ms / baud x 106 baud = 530ms. The total duration of two data packets returned from the tested card slot is approximately: 530ms x 2 = 1.06 seconds.

[0032] It can be seen that the test completion time of a card slot on the tested motherboard is still controlled in seconds. For a tested motherboard with more than a dozen card slots, even if all its card slots need to be tested serially, the complete test time is less than 30 seconds, which will not have a serious impact on production test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings herein are intended to illustrate the general characteristics of methods, structures, and / or materials used in certain exemplary embodiments of the present invention, supplementing the descriptions in the specification. However, the drawings herein are schematic diagrams not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment. The drawings herein should not be interpreted as defining or limiting the range of values ​​or properties encompassed by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0034] Figure 1 This is a schematic diagram of the existing boundary scan test structure.

[0035] Figure 2 It is a schematic diagram of the boundary scan test structure of the present invention.

[0036] Figure 3 This is a schematic diagram of the test control and data return protocol.

[0037] Figure 4 This is a state transition diagram in the Dummy Card FPGA. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can fully understand the other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features therein can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or there can be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element. In all figures, the same figure numbers always represent the same elements.

[0039] First embodiment;

[0040] refer to Figure 2 As shown, the present invention provides a boundary scan test structure, which is used for circuit board card interface interconnection testing, and the test platform main control unit and the tested motherboard only exchange data through the JTAG channel;

[0041] Select three signal lines from each tested slot as test control and data return channels;

[0042] The test control and data return channels are used to transmit test commands and test results using custom protocols;

[0043] Among them, the three signal lines are named as the first signal line, the second signal line and the third signal line, and the signals they transmit are marked as the first signal PSYN, the second signal PTX and the third signal PRX respectively;

[0044] The first signal PSYN and the second signal PTX are signals sent by the tested mainboard to the Dummy Card, which are used to assist in time synchronization and send command data to the Dummy Card respectively;

[0045] The third signal PRX is a signal that the Dummy Card replies to the tested mainboard, and is used by the Dummy Card to reply command result data to the tested mainboard.

[0046] refer to Figure 3As shown, in a typical implementation, three signal lines are used to transmit test commands and test results using a custom protocol. Among them, PSYN is high and PTX jumps from high to low is defined as BUS START; PSYN is high and PTX jumps from low to high is defined as BUS STOP; PSYN maintains a high level and PTX jumps from low to high three times in a row is defined as BUS SYNC; to realize the command transmission from the tested motherboard to the Dummy Card, the test platform main control unit will first send a BUS START waveform, then send a low level on PTX during the low period of PSYN, then send 4 beats of command data byte length information (K=1...15bytes), then send K bytes of command information, and finally send a BUS STOP waveform; to realize the command response from the Dummy Card to the tested motherboard, that is, the return of the action result, the test platform main control unit will first send a BUS START waveform, then send a high level on PTX during the low period of PSYN, then send 4 beats of command response data byte length information (K=1...15bytes), then receive K bytes of command result return information, and finally send a BUS STOP waveform.

[0047] Preferably, multi-bit data in the above definition is transmitted in big-endian format (higher bits are transmitted first, followed by lower bits). It should be noted that this definition of the signal transmission format is only used to illustrate the feasibility of the present invention. Those skilled in the art can make reasonable improvements based on this format according to actual needs, which also fall within the scope of protection claimed in the present invention.

[0048] For the above custom protocol example, Figure 4The figure further illustrates the state transition diagram that should be implemented in the Dummy Card FPGA. As the slave of the 3-wire custom communication protocol, the Dummy Card FPGA is in the idle state before the test begins. Upon receiving the BUS START+PTX low-level waveform, the Dummy Card FPGA enters the "BUS CMD" state, receiving the test command, and receives the 4-bit command length K, followed by the K-byte command. Finally, upon receiving the BUS STOP waveform, the Dummy Card FPGA returns to the idle state. Similarly, upon receiving the BUS START+PTX high-level waveform, the Dummy Card FPGA enters the "BUS RESP" state, feeding back the test result, and receives the 4-bit result return length K. It then feeds K bytes of result information back to the motherboard under test, and finally returns to the idle state upon receiving the BUS STOP waveform. As a remedy for abnormal situations such as bus loss of synchronization, the Dummy Card FPGA enters the BUS SYNC state and then returns to the idle state if it receives three consecutive BUSSTOP waveforms in any state. The test platform main control unit can use this basic implementation and complete the interaction with various custom test commands of all Dummy Cards according to the ideas disclosed in this patent, thereby achieving interconnection test coverage of all interfaces of the tested motherboard.

[0049] Table 1 below further provides a complete definition of a test command set on a typical test platform for the custom protocol example described above. Note that reasonable extensions to this command set (such as adding ADC sampling or frequency estimation commands on specific pins) are also within the scope of protection claimed by the present invention.

[0050] Table 1

[0051]

[0052] In addition, it should be understood that, although the terms "first", "second", etc. may be used herein to describe different elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of exemplary embodiments of the present invention, the first element, component, region, layer or part discussed below may also be referred to as the second element, component, region, layer or part.

[0053] Second embodiment;

[0054] The present invention provides a boundary scan test method, which is implemented based on the boundary scan test structure described in the first embodiment and includes the following steps:

[0055] S1, performs interconnection testing on the JTAG channel; the three selected signal lines in each slot of the tested motherboard are also test objects of the interconnection test; when they are selected as test control and data return channels, it is necessary to ensure that the coverage of the interconnection test is not affected; the interconnection characteristics of these three signal lines should be confirmed using the custom "bus confirmation" command; if the "bus confirmation" fails, it means that the interconnection characteristics of these three signal lines are incorrect, and the subsequent "level capture and result return" command should not be executed;

[0056] In step S2, the test platform main control unit generates a test pattern level combination on the remaining signal lines under test that are not assigned to the tested slot through the JTAG channel, and controls the boundary scan chain of the tested motherboard MCU through the JTAG channel to generate level capture and result return commands for the test control and data return channels.

[0057] After receiving the command, the Dummy Card captures the current test signal level and transmits the level capture result back to the CPU boundary scan chain on the motherboard under test through the test control and data return channel;

[0058] In step S4, the main control unit of the test platform reads the returned level capture result through the JTAG channel and compares it with the sent test pattern level combination to complete the interconnection test of each pin of each slot.

[0059] Furthermore, if the PRX signals selected in different slots correspond to the same CPU pin, before executing the "bus confirmation" and "level capture and result return" operations, a "Slot Select" command is sent to the relevant slots to select one of the tested slots, and the other tested slots enter an idle standby state. In this way, each tested slot is selected one by one, and the interconnection test of each slot is completed serially;

[0060] If the third signals selected in different slots correspond to different pins of the CPU, a parallel interconnection test is performed on each slot;

[0061] Third embodiment;

[0062] The present invention provides a boundary scan test method, which is based on the boundary scan test method described in the second embodiment. The same parts are not repeated here. When implementing step S4, the following steps are used instead:

[0063] The test platform main control unit controls the boundary scan chain of the CPU of the motherboard under test through the JTAG channel, causing the test control and data return channels to generate multiple customized test pattern generation commands. Exemplary test pattern sets include: an all-one sequence, an all-zero sequence, a sequence obtained by writing zeros at each offset position of the all-one sequence (a zero sequence), and a sequence obtained by writing 1s at each offset position of the all-zero sequence (a 1 sequence). At the end of each test pattern generation command, the test platform main control unit directly reads the current level values ​​of each pin captured by the MCU of the motherboard under test through the JTAG channel, and compares them with the test pattern level combination currently generated by the dummy card to complete the interconnection test of each pin of each slot.

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, rather than being interpreted in an idealized or overly formal sense.

[0065] The present invention has been described in detail above by way of specific embodiments and examples, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered within the scope of protection of the present invention.

Claims

1. A boundary scan test structure for testing circuit board card interfaces, characterized in that: The test platform main control unit and the motherboard under test only exchange data through the JTAG channel; Select three signal lines from each tested slot as test control and data return channels; The test control and data return channels are used to transmit test commands and test results using custom protocols.

2. The boundary scan test structure according to claim 1, wherein: The three signal lines are named as the first signal line, the second signal line and the third signal line, and the signals they transmit are marked as the first signal, the second signal and the third signal respectively; The first signal and the second signal are signals sent by the tested mainboard to the Dummy Card, which are used to assist in time synchronization and send command data to the Dummy Card respectively; The third signal is a signal that the Dummy Card replies to the tested mainboard, and is used by the Dummy Card to reply command result data to the tested mainboard.

3. A boundary scan test method, which is implemented based on the boundary scan test structure according to claim 2, characterized in that: The following steps are involved: S1, performs interconnection test on JTAG channel; In step S2, the test platform main control unit generates a test pattern level combination on the remaining signal lines under test that are not assigned to the tested slot through the JTAG channel, and controls the boundary scan chain of the MCU of the tested mainboard through the JTAG channel to generate level capture and result return commands for the test control and data return channels. After receiving the command, the Dummy Card captures the current test signal level and transmits the level capture result back to the CPU boundary scan chain on the motherboard under test through the test control and data return channel; In step S4, the main control unit of the test platform reads the returned level capture result through the JTAG channel and compares it with the sent test pattern level combination to complete the interconnection test of each pin of each slot.

4. The boundary scan test method according to claim 3, wherein: Implementing step S2 includes: Use the custom bus confirmation command to confirm the interconnection of the three signal lines that constitute the JTAG channel; If the bus confirmation fails, it is confirmed that the JTAG channel interconnection is incorrect and subsequent tests are not performed.

5. The boundary scan test method according to claim 4, wherein: If the third signals selected in different slots correspond to different pins of the CPU, a parallel interconnection test is performed on each slot; If the third signals selected in different slots correspond to the same pin of the CPU, a serial interconnection test is performed on each slot.

6. The boundary scan test method according to claim 4, wherein: When implementing step S4, the following steps are used instead: The test platform main control unit controls the boundary scan chain of the CPU of the motherboard under test through the JTAG channel, causing the test control and data return channels to generate multiple customized test pattern generation commands. When each test pattern generation command ends, the test platform main control unit directly reads the current level values ​​of each pin captured by the MCU of the motherboard under test through the JTAG channel, and compares them with the test pattern level combination currently generated by the Dummy Card to complete the interconnection test of each pin of each slot.

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