Circuit board testing method and related device

Abstract

The invention discloses a circuit board test method and a related device, and the method comprises the steps: sequentially applying a power pulse sequence to a plurality of power supply rails under a control condition, and collecting the reference data of a differential link before triggering; collecting frequency change data, bit error rate data and phase change data at the same time in the pulse action period to obtain a multi-physical-quantity response sequence; performing time synchronization processing based on the pulse triggering time and extracting a multi-scale feature vector; combining the feature vectors into a feature tensor with time, frequency and response type dimensions, and identifying a time interval with coupling energy exceeding a threshold value as an abnormal window; and comparing the abnormal window characteristics with reference data, generating a standardized defect index, and outputting test judgment in combination with a dynamic judgment threshold. According to the technical scheme, the multi-physical-quantity coupling response of the differential link can be accurately captured under the multi-interference condition, and stable detection and judgment of fine defects are achieved.

Description

Technical Field

[0001] This invention relates to the field of circuit board signal integrity detection and fault diagnosis technology, and in particular to a circuit board testing method and related apparatus. Background Technology

[0002] Laptop motherboards are multilayer rigid printed circuit boards used to implement power distribution, signal interconnection, and device support within a limited space for a computing platform. Their basic structure consists of alternating conductive and dielectric layers, with cross-layer connections established through vias, buried vias, and blind vias. Functionally, they support BGA (Ball Grid Array) packaged devices, including the central processing unit, graphics processing unit, and power management integrated circuits, and feature differential traces and reference planes for high-speed data transmission to maintain specified characteristic impedances and clock synchronization. Simultaneously, the motherboard is typically coupled to the overall system structure through positioning components and heat dissipation / support components to meet the assembly, heat dissipation, and reliability requirements of the entire system.

[0003] Current motherboard testing processes typically employ a step-by-step, environment-specific approach: high-speed interface compliance and bit error rate (BER) testing is performed under constant or gradually varying temperature conditions to obtain repeatable eye diagrams and BER data; thermal reliability and stress code verification are then performed in independent thermal cycling or environmental stress equipment to assess the resilience of component solder joints and board structure. The advantages of this approach are mature testing technology, strong equipment versatility, good data comparability, and ease of standardization and cost control in mass production scenarios. However, this process suffers from a disconnect between the timeline and boundary conditions and actual operating conditions: high-speed link quality assessment and structural / thermal stress loading do not occur within the same time window, and the transient coupling of thermo-mechanical responses is not observed synchronously; simultaneously, the fixtures and gradually varying temperature conditions struggle to reproduce the rapid power consumption transitions and resulting board deformation and impedance drift under actual loads. The resulting technical contradiction is that conventional step-by-step testing can provide stable single-dimensional indicators, but it is difficult to capture transient failure symptoms caused by the superposition of thermal, mechanical, and electrical pulses in a short period of time under real working conditions. Therefore, how to synchronously characterize the impact of board-level thermal-mechanical-electric coupling on high-speed differential links and key interconnects within a millisecond-level power consumption transition time window and use it for mass production judgment is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The main objective of this invention is to establish a joint testing and interpretation mechanism based on a unified time reference for actual power consumption transition time windows, so as to identify transient anomalies caused by thermo-mechanical-electric coupling in a repeatable manner and form objective test judgment results accordingly.

[0005] To achieve the above objectives, embodiments of this application provide a method for testing a circuit board, including: Under controlled conditions, a sequence of power consumption pulses is applied sequentially to multiple power supply rails of the circuit board, and reference data reflecting the electrical state of the differential link is collected before the power consumption pulses are triggered. During the power pulse, frequency change data, bit error rate data, and phase change data of the differential link are simultaneously collected to obtain a multi-physical quantity response sequence. Based on the power consumption pulse triggering time, the multi-physical quantity response sequence is time-synchronized and multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect are extracted. The multi-scale feature vectors are combined into a feature tensor with time, frequency and response type dimensions, and the time intervals in which the coupling energy exceeds the threshold are identified as abnormal windows. The features within the anomaly window are compared with the baseline data to generate standardized defect indicators, and a test judgment is output based on the comparison result of the indicators and the dynamic judgment threshold.

[0006] To achieve the above objectives, embodiments of this application also propose a circuit board testing apparatus, comprising: The reference acquisition module is used to sequentially apply a power consumption pulse sequence to multiple power supply rails of the circuit board under control conditions, and to acquire reference data reflecting the electrical state of the differential link before the power consumption pulses are triggered. The response acquisition module is used to simultaneously acquire frequency change data, bit error rate data, and phase change data of the differential link during the power consumption pulse to obtain a multi-physical quantity response sequence. The synchronization processing module is used to perform time synchronization processing on the multi-physical quantity response sequence based on the power consumption pulse trigger time, and extract multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect. The tensor recognition module is used to combine the multi-scale feature vectors into a feature tensor with time, frequency and response type dimensions, and identify the time interval in which the coupling energy exceeds the threshold as an abnormal window. The judgment output module is used to compare the features within the abnormal window with the benchmark data, generate standardized defect indicators, and output test judgments based on the comparison results of the indicators and dynamic judgment thresholds.

[0007] To achieve the above objectives, this application also proposes a circuit board testing device, comprising: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a circuit; the at least one processor invokes the instructions in the memory to cause the circuit board testing device to execute the steps of the circuit board testing method described above.

[0008] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the steps of the circuit board testing method described above.

[0009] The technical solution provided in this application applies a series of power consumption pulses sequentially to multiple power supply rails of a circuit board under controlled conditions. Before the pulses are triggered, reference data reflecting the electrical state of the differential link is acquired, enabling subsequent observations to be comparable to the initial health state of the circuit board. The power consumption pulses cause rapid changes in local temperature rise, mechanical stress, and power ripple within milliseconds. These changes simultaneously affect the transmission characteristics of the high-speed differential link. Therefore, by synchronously acquiring frequency changes, bit error rate, and phase change data during the pulse application, the instantaneous response of the link performance under thermal, mechanical, and electrical pulse coupling can be obtained within the same timeframe. This process avoids the disconnect between thermal stress and signal quality observations in traditional testing, and can directly capture the dynamic degradation characteristics of the high-speed link under actual transient load conditions.

[0010] The acquired multi-physical response data is time-aligned with the power consumption pulse trigger time as a reference and synchronized through a unified sampling benchmark, preserving the correlation between different physical quantities. Subsequently, multi-scale feature vectors reflecting thermo-mechanical-electrical interactions are extracted from the synchronized data. These features are combined into a feature tensor that simultaneously includes time, frequency, and response type dimensions, facilitating the analysis of the distribution and evolution of coupling energy in a multi-dimensional space. When the coupling energy in a certain time interval of the tensor exceeds a set threshold, that interval is marked as an abnormal window. Within this window, the current feature is compared one by one with the benchmark data before the pulse trigger to obtain a standardized defect index after eliminating dimensional differences. Finally, this index is compared with a dynamic judgment threshold calculated considering external operating conditions such as ambient temperature and power supply ripple, achieving mass-production-level judgment of link reliability under transient coupling stress. Through these continuous steps, the testing process can accurately and synchronously characterize the impact of multi-field coupling of thermal, mechanical, and electrical fields on high-speed signal interconnects within the critical time window of actual load fluctuations, and transform it into a judgment standard that can be used for batch testing, thus solving the problem of difficulty in obtaining transient failure symptoms of high-speed differential links under short-time power consumption transitions. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of one embodiment of the circuit board testing method according to the present invention; Figure 2 This is a schematic diagram of one embodiment of the circuit board testing device according to the present invention; Figure 3 This is a schematic diagram of one embodiment of the testing equipment for the circuit board in this invention.

[0013] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0015] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0016] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the term "and / or" throughout the text includes three solutions; taking A and / or B as an example, it includes technical solution A, technical solution B, and a technical solution that simultaneously satisfies A and B. Furthermore, the technical solutions of various embodiments can be combined with each other, provided that they are feasible for those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0017] The circuit boards targeted by this solution can include multilayer rigid printed circuit boards such as laptop motherboards, server motherboards, and industrial control boards. These circuit boards are typically formed by alternating conductive and dielectric layers, with cross-layer connectivity achieved through vias, buried vias, and blind vias, and housing large-scale BGA packaged devices such as central processing units, graphics processors, and power management chips within a limited space. Simultaneously, to achieve high-speed data transmission, differential traces with specific impedance control and reference planes are laid on the board, coupled to the overall frame through mechanical fasteners and heat dissipation structures. While this structure meets the performance and assembly requirements of the entire system, during operation, the signal integrity of the high-speed link and the structural reliability of solder joints and board layers are simultaneously affected by various transient stresses, including thermal, mechanical, and electrical stresses.

[0018] Existing testing methods typically separate signal integrity testing from environmental stress loading. For example, high-speed interface compliance and bit error rate testing are performed under isothermal or gradually changing temperature conditions, while structural reliability is verified in independent thermal cycling equipment or stress platforms. Although this approach is mature and provides good data comparability, it fails to capture performance fluctuations and potential failure symptoms caused by multi-physics coupling under transient conditions because high-speed link testing and thermal / mechanical stress loading do not occur in the same time window. Furthermore, fixed fixtures and gradually changing temperature conditions cannot simulate the rapid temperature rise, board-level deformation, and impedance drift caused by millisecond-level power consumption transitions in actual loads. Therefore, this solution proposes to simultaneously observe multiple electrical parameters of the differential link during power consumption pulses and combine time alignment and characteristic analysis methods to directly evaluate link reliability in a real transient stress field, thereby solving the problem of the disconnect between test conditions and actual operating conditions in existing methods.

[0019] Specifically, one embodiment of this application provides a method for testing a circuit board. Figure 1 A flowchart illustrating a circuit board testing method according to an embodiment of this application. In this embodiment, the method includes: Please see Figure 1 Under controlled conditions, a power consumption pulse sequence is applied sequentially to multiple power supply rails of the circuit board, and reference data reflecting the electrical state of the differential link is collected before the power consumption pulses are triggered. In one embodiment of the present invention, the step of sequentially applying a power consumption pulse sequence to multiple power supply rails of the circuit board under controlled conditions, and acquiring reference data reflecting the electrical state of the differential link before the power consumption pulses are triggered, includes: The contour parameters characterizing the power consumption change are analyzed to obtain pulse configuration information including power consumption peak, rise time rate, duration and power supply rail sequence, and a power consumption pulse sequence triggered sequentially is generated based on the configuration information. Before emitting the power pulse sequence, a low-amplitude power cycle is applied to preheat the circuit board, and multiple temperature samples are monitored until the temperature difference meets the steady-state condition. Multiple sets of impedance, phase, and bit error rate samples are collected at the same time reference before the power consumption pulse is triggered. These samples are then differentially compensated with the data collected during the preheating stage to obtain the reference data.

[0020] The following is a detailed description of the steps involved in the above embodiments: When analyzing power profile parameters characterizing power consumption changes and generating a sequentially triggered power pulse sequence, the power profile parameters refer to four quantities for a single power consumption event: peak power consumption, rise rate, duration, and power rail sequence. Peak power consumption is measured in watts and can be obtained by multiplying the nominal voltage of the target power rail by the peak current; the rise rate is measured in watts per millisecond or amperes per millisecond, one of which must be used and specified in the configuration information; duration is measured in milliseconds; and the power rail sequence is determined by the order in which the rails to be excited are arranged on the time axis. Parameters come from three sources: design power timing tables and budgets (providing peak values ​​and desired slopes), telemetry logs from the on-board power management integrated circuit (PMIC) (providing the current envelope of the actual load), and short-time calibration tests (determining the selectable range of slope and duration within a safe margin). The test control terminal uses a unified trigger marker as the time base, writing the trigger time, amplitude, rise slope, and duration for each rail. The interval between adjacent pulses is set to be no less than the greater of "the shortest measurement window length for subsequent frequency estimation and the bit error rate statistical integration time," thus preventing cross-rail responses from entering the same sampling window. After the configuration information is sent via the synchronization line or control bus, the power rails are triggered sequentially, forming a power pulse sequence that matches the actual load wake-up. An equivalent implementation involves the PMIC controlling the load switch to generate power pulses with the same amplitude, slope, and duration, with the trigger time aligned to the unified time base, resulting in the same sequential triggering behavior as the external source.

[0021] Before emitting the power pulse sequence, a low-amplitude power cycle is applied to preheat the circuit board, and steady-state conditions are determined using multi-point temperature sampling values. The low amplitude is taken as a fixed proportion of the peak power consumption of each power rail, allowing the device and board layer temperatures to rise slowly without introducing strong stress. Temperature sampling points are placed near the processor area, graphics chip area, power supply module, and structural fixed boundaries, forming multi-point temperature sampling values. After each low-amplitude cycle, the maximum temperature difference between sampling points and the rate of temperature change at each sampling point are calculated. When the maximum temperature difference and rate of change are simultaneously below a pre-set threshold for several consecutive sampling periods, the steady-state condition is considered met. The threshold can be given by prototype statistics or thermal design specifications, for example, the maximum temperature difference is limited to a certain number of degrees Celsius and the rate of change is less than a certain number of degrees Celsius per second, and this is maintained continuously for several sampling periods. This process eliminates the slow drift caused by initial thermal non-uniformity in impedance, phase, and bit error rate, making subsequent baselines comparable. An equivalent implementation method is to maintain a constant low-amplitude power until the steady-state condition is met, or to use duty cycle closed-loop regulation to bring the maximum temperature difference and rate of change to within the threshold. Both methods are feasible in this scenario.

[0022] Multiple sets of impedance, phase, and bit error rate samples are acquired at the same time reference before the power pulse trigger, and differential compensation is performed to obtain reference data. A unified trigger marker is used as the reference timestamp. At a fixed offset time before triggering, three types of sampling are started simultaneously. Impedance samples are estimated from the reflection or echo measurement of the differential port at a fixed frequency (e.g., converted to equivalent characteristic impedance by echo readings from mass production fixtures or reflection coefficient readings from onboard calibration channels). Phase samples refer to the offset of the transmission phase relative to the historical reference at a fixed frequency or within a small frequency band (which can be read from the transceiver's phase estimation register or phase measurement channel). Bit error rate samples are read from the link's bit error statistics register within a specified integration time. To suppress outliers, multiple sets of samples are acquired within a short time window, and outlier removal and statistical averaging are performed to obtain pre-trigger statistics. The corresponding statistical values ​​recorded in the preheating steady-state interval are then subtracted element-by-element from the pre-trigger statistical values ​​to form a differential compensation value. This differential compensation value is used to correct the pre-trigger statistical values, outputting compensated impedance, phase, and bit error rate reference data, which is then bound to the trigger time as a comparison reference for subsequent multi-physical quantity response sequences. This anchors the reference to the actual thermal state just before the pulse triggers, avoiding reference distortion caused by slight drift in the short period between the end of preheating and the trigger. An equivalent implementation is to replace the statistical average with the median or truncated average, or to replace the preheating steady-state interval statistics with fixed-length steady-state sliding window statistics; under the premise of a unified time reference and differential compensation process, the function of the reference data remains consistent.

[0023] Please continue reading Figure 1 During the power consumption pulse, frequency change data, bit error rate data, and phase change data of the differential link are collected simultaneously to obtain a multi-physical quantity response sequence. In one embodiment of the present invention, the step of simultaneously acquiring frequency change data, bit error rate data, and phase change data of the differential link during the power consumption pulse to obtain a multi-physical quantity response sequence includes: Based on the current change rate of the power consumption pulse, the pulse duration is divided into a high-slope measurement window and a low-slope measurement window. Within the high-slope measurement window, a coverage-based frequency domain estimation is performed on the resonance-related frequency characteristics of the differential link. Within the low-slope measurement window, a tracking-based frequency domain estimation is performed based on the frequency measurements of the previous window in the neighborhood of the center frequency point. At the center of each measurement window, the acquisition channel is triggered uniformly, and the bit error rate of the transmitted data stream of the differential link is statistically analyzed. The difference between the phase corresponding to the current frequency measurement value and the phase in the reference data is calculated to obtain the phase change. The frequency change data, bit error rate data, and phase change data obtained in each measurement window are used to establish a unified time index according to the power consumption pulse trigger time, forming a multi-physical quantity response sequence.

[0024] The following is a detailed description of the steps involved in the above embodiments: In this scheme, the current change rate of the power consumption pulse refers to the slope (in amperes per second) of the current change over time during the application of the power consumption pulse. By sampling the pulse waveform, its instantaneous change rate is calculated and compared with a preset slope threshold. Periods with rates higher than the threshold are defined as high-slope measurement windows, and periods with rates lower than the threshold are defined as low-slope measurement windows. This division is to employ matched measurement strategies at different stages of power consumption transitions: in the high-slope stage, signal disturbances are large, requiring full-range scanning to acquire frequency characteristics; in the low-slope stage, signal changes are slow, allowing for fine tracking within the neighborhood of the center frequency point measured in the previous stage. Equivalently, the slope threshold can be set based on the proportion of the pulse peak current (e.g., 10%~20%) to balance noise suppression and response capture capabilities.

[0025] Within the high-slope measurement window, comprehensive frequency domain estimation is performed on the resonant-related frequency characteristics of the differential link. This involves frequency scanning and power spectrum analysis across the entire target frequency band at predetermined steps, ensuring the capture of frequency drift that may be caused by rapid thermal-mechanical coupling. Within the low-slope measurement window, the center frequency obtained in the previous window is used as a reference, and bidirectional scanning is performed within its upper and lower frequency ranges at preset step values, achieving tracking-style frequency domain estimation within the neighborhood. This switching strategy reduces measurement time during low-change phases while maintaining sensitive capture of critical frequency drifts. In practical applications, the step value can be set as an integer multiple of the system frequency resolution to avoid frequency quantization errors.

[0026] At the center of each measurement window, a unified trigger signal simultaneously activates multiple acquisition channels: first, it acquires the spectral data of the differential link at that moment for frequency measurement; second, it uses PRBS (Pseudo Random Binary Sequence) code to perform bit error statistics on the differential link and calculates the bit error rate; third, it calculates the phase of the signal corresponding to the current frequency measurement value and performs a difference operation with the phase in the reference data to obtain the phase change. The purpose of synchronous triggering is to ensure strict temporal alignment of the three types of data for subsequent fusion analysis. Equivalently, the trigger can be generated using an external timing pulse or edge detection based on a power pulse.

[0027] Frequency variation data, bit error rate data, and phase variation data obtained from each measurement window are indexed using a unified time index based on the power consumption pulse trigger time, generating a multi-physical quantity response sequence. In this sequence, the time index serves as the primary reference axis for all measurement data, with each index point corresponding to one of the three types of data, forming a multi-dimensional time-series signal directly applicable to thermo-mechanical-electric coupling analysis. This unified index structure avoids alignment errors introduced by asynchronous acquisition, improving data comparability and analytical accuracy. Equivalently, the time index can be established based on a high-precision hardware clock or through interpolation alignment in the sampled data using post-processing software.

[0028] Please continue reading Figure 1 Based on the power consumption pulse triggering time, the multi-physical quantity response sequence is time-synchronized and multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect are extracted. In one embodiment of the present invention, the step of performing time synchronization processing on the multi-physical quantity response sequence based on the power consumption pulse trigger time and extracting a multi-scale feature vector reflecting the thermo-mechanical-electric coupling effect includes: Using the power consumption pulse trigger time as time zero, the multi-physical quantity response sequences are time-aligned at time zero, and resampling is performed according to the sampling period relationship of each sequence to obtain a synchronization sequence with a unified time reference. Risk weights are calculated based on the interconnection layout characteristics of the circuit board, and the risk weights are applied to the synchronization sequence to obtain a risk-weighted sequence; Multi-resolution decomposition is performed on the risk-weighted sequence to extract coefficient vectors at different time scales, which serve as multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect.

[0029] The following is a detailed description of the steps involved in the above embodiments: In this embodiment, the multi-physical quantity response sequence refers to frequency change data, bit error rate data, and phase change data obtained based on differential link testing. These data are all recorded in time series form, but their sampling periods may differ. Taking the power pulse trigger moment as time zero, i.e., the starting point of the power pulse application, as the common time reference point for all measurement data, the time offset of each sequence is calculated to align them at time zero. After alignment, to ensure that the three types of data can be directly compared under the same time reference, resampling is performed according to their original sampling period relationships. For example, through linear interpolation or sample-holding methods, all sequences are unified to a preset sampling period (e.g., 1 µs). This ensures that the data at each time point in subsequent analysis corresponds one-to-one, avoiding phase or amplitude errors introduced due to asynchronous sampling. Equivalently, this step can also use a real-time acquisition method based on hardware clock synchronization to directly generate data with a unified sampling period, thus eliminating the need for resampling.

[0030] In this embodiment, risk weights are parameters that quantify the importance or vulnerability of different signal paths based on the interconnect layout characteristics of the circuit board. For example, based on factors such as the wiring length of high-speed differential links, the number of layers spanned, proximity to heat sources, and the distribution of nearby sensitive devices, weight values ​​in the range of 0 to 1 can be assigned to different measurement channels using a preset weighting rule. After calculation, the risk weight is applied to the data points corresponding to the synchronization sequence channel by channel, that is, the amplitude is scaled according to the channel weight for the entire time series of that channel. This process enhances the focus of analysis on high-risk interconnect paths, making subsequent feature extraction more sensitive to changes in these paths. In an equivalent implementation, risk weights can also be dynamically adjusted through an online adaptive algorithm, for example, increasing the weight of relevant channels when a local temperature rise or increase in mechanical stress is detected, to reflect the real-time risk distribution.

[0031] After obtaining the risk-weighted sequence, multi-resolution decomposition is performed to break down the original time-series signal into components at multiple time scales (e.g., milliseconds, microseconds, and microseconds). Signal processing methods such as wavelet decomposition or empirical mode decomposition can be used to decompose the risk-weighted sequence into several sub-sequences, each retaining signal components at a specific frequency band or time resolution. Subsequently, the corresponding coefficient vectors are calculated at each time scale. These vectors, as multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect, can reveal the link parameter variation patterns caused by power consumption pulses at different time granularities. For example, millisecond-level components may reflect thermal effects, while microsecond-level components may reflect mechanical vibrations or transient electrical disturbances. Equivalently, this step can also employ methods such as short-time Fourier transform to achieve multi-time-scale analysis, as long as feature vectors corresponding to different time resolutions can be output.

[0032] In one embodiment of the present invention, the step of calculating risk weights based on circuit board interconnection layout characteristics and applying the risk weights to the synchronization sequence to obtain a risk-weighted sequence includes: Using the circuit board layout coordinates as a reference, the input parameters for weight calculation are determined based on the spatial proximity of differential traces to power rails, main heat-generating components and fixed boundaries, as well as cross-layer connectivity density. The input parameters are normalized in amplitude and weight allocation coefficients are determined according to response type. The normalized weights are multiplied by the allocation coefficients to obtain the channel weights corresponding to frequency change data, bit error rate data and phase change data. During the power consumption pulse, when the changes in the multi-point temperature sampling values ​​exceed the preset stable range, the channel weights are updated within the current measurement window, and the updated channel weights are applied element by element to the time-synchronized multi-physical quantity response sequence to obtain the risk-weighted sequence.

[0033] The following is a detailed description of the steps involved in the above embodiments: In this scheme, the circuit board layout coordinates refer to a two-dimensional or three-dimensional coordinate system established with the physical plane of the circuit board as the reference frame, used to describe the spatial positional relationships of components, wiring, and boundaries on the board. The positional information of differential traces, power rails, major heat-generating devices, and fixed boundaries can be directly obtained from the circuit board's wiring design files (such as Gerber files or CAD layout data). Input parameters include: the minimum distance between differential traces and power rails; the distance between differential traces and the center point of major heat-generating devices (such as the CPU or GPU); the distance between differential traces and fixed boundaries (such as metal supports or chassis connections); and the number of layers or via density (i.e., cross-layer connectivity density) crossed by the differential traces. These parameters reflect the potential risk level of differential links due to electrical, thermal, and mechanical interference. In practical implementation, the above parameters can be calculated in batches using computer scripts by parsing network identifiers and positional information in the CAD files, ensuring accurate and repeatable calculation results. Equivalently, if a ranging or temperature sensor array is already deployed on the board, equivalent spatial proximity relationships can also be deduced based on measured data, achieving the same parameter acquisition effect.

[0034] To eliminate differences in the dimensions and numerical ranges of different input parameters, amplitude normalization processing needs to be performed on each parameter. For example, each type of parameter can be linearly mapped to the [0,1] interval according to the minimum and maximum values ​​of all its channels. This ensures that different types of parameters can be directly compared and superimposed in subsequent weight calculations. Based on the response type (i.e., frequency variation data, bit error rate data, and phase variation data), different weight allocation coefficients are pre-set to reflect the relative importance of each response type in risk assessment. For example, bit error rate variation has a significant impact on data integrity and can be assigned a higher coefficient; phase variation is sensitive in reflecting mechanical stress and its coefficient can be increased in specific applications. Multiplying the normalized parameters element-wise with the corresponding allocation coefficients yields the initial channel weights for each response type. In engineering applications, these allocation coefficients can be optimized and adjusted based on historical failure analysis data to improve the accuracy of risk assessment. Equivalently, allocation coefficients can also be automatically generated through expert experience or statistical feature selection methods to achieve the same risk differentiation effect.

[0035] During the power pulse, the system continuously collects temperature samples from multiple points on the board. When changes in these samples exceed a preset stable range (e.g., exceeding a threshold of ±2℃), it indicates a significant change in the heat distribution within the board, potentially affecting the stress and electrical state of different channels. In this case, the channel weights are updated within the current measurement window to reflect the new risk conditions. The update method can be either recalculating the input parameters based on the real-time temperature gradient or directly adjusting the scaling factor of the existing weights. The updated channel weights are applied element-wise to a time-synchronized multi-physical quantity response sequence; that is, the weight is multiplied by each time point of the channel's frequency change data, bit error rate data, and phase change data to obtain a risk-weighted sequence. This risk-weighted sequence makes subsequent analysis more sensitive to changes in high-risk channels under the current thermo-mechanical environment, thereby improving the reliability of anomaly detection. Equivalently, dynamic weight updates can also be triggered based on other real-time sensor signals (such as strain gauge or power ripple monitoring results) to adapt to the detection requirements of different board-level environmental stresses.

[0036] Please continue reading Figure 1 The multi-scale feature vectors are combined into a feature tensor with time, frequency and response type dimensions, and the time intervals in which the coupling energy exceeds the threshold are identified as abnormal windows. In one embodiment of the present invention, the step of combining the multi-scale feature vectors into a feature tensor having time, frequency, and response type dimensions, and identifying time intervals where the coupling energy exceeds a threshold as anomaly windows, includes: The multi-scale feature vectors are arranged and stacked in an ordered manner according to the time index, frequency index, and response type index to generate a three-dimensional feature tensor. Perform matrix decomposition on the three-dimensional feature tensor using overlapping time sliding windows to obtain the energy distribution sequence corresponding to each time window; The cumulative energy of the energy distribution sequence is calculated and compared with a preset energy threshold. When the cumulative energy within a continuous time index exceeds the preset energy threshold, the corresponding time index interval is determined as an abnormal window.

[0037] The following is a detailed description of the steps involved in the above embodiments: Specifically, a three-dimensional feature tensor is a three-dimensional data structure formed by arranging and stacking multi-scale feature vectors in a certain order using time index, frequency index, and response type index as three-dimensional coordinate axes. It is used to simultaneously express the distribution of multiple physical quantities across different time, frequency, and type dimensions. The time index reflects the temporal position of the acquisition point during the power pulse process; the frequency index corresponds to the analysis results of different frequency components; and the response type index distinguishes between three categories: frequency change data, bit error rate data, and phase change data. In implementation, the multi-scale feature vectors can be sorted by time index first, and then stacked in a fixed order by frequency index and response type index at each time point to generate a three-dimensional array that can be directly input into subsequent data processing modules. In this scenario, the above arrangement and stacking process can typically be implemented using numerical computing libraries that support matrix and tensor operations (such as NumPy in Python or the MATLAB platform), and the data structure is adapted to high-speed matrix factorization operations. Equivalently, the three-dimensional tensor can also be expanded into a two-dimensional matrix according to specific rules, but the index mapping relationship must be preserved so that subsequent sliding window analysis can accurately locate the original time and frequency positions.

[0038] Overlapping time sliding windows refer to sequentially extracting data segments along the time axis with fixed steps, allowing for partial temporal overlap between adjacent windows to ensure smooth transitions and continuous analysis. Matrix decomposition can employ practical algorithms such as Singular Value Decomposition (SVD) and Non-negative Matrix Factorization (NMF) to expand the three-dimensional feature tensor into a matrix within each time window according to frequency and response type indices, and decompose it into components representing the main modes and their corresponding energy values. The energy values ​​can be calculated from the singular values ​​or component amplitudes in the decomposition results, reflecting the overall intensity of changes in multiple physical quantities within that time window. In the high-speed differential link thermal-mechanical-electrical coupling analysis scenario of this scheme, this decomposition method can effectively distinguish between background noise and anomalous disturbances, and reduces the risk of missed detections caused by short-term signal abrupt changes through continuous analysis of overlapping windows. Equivalently, a multi-scale decomposition method based on wavelet packet energy distribution can also be used to obtain the same time window energy distribution results.

[0039] Accumulated energy refers to the total energy within a given time index interval by summing the energy values ​​of the corresponding energy distribution sequence. Comparing the accumulated energy with a preset energy threshold aims to determine if any abnormal events significantly exceed the normal energy range within that interval. The energy threshold can be determined based on the statistical distribution of historical normal operation data, such as adding a certain number of standard deviations to the normal energy mean to balance the false alarm and false positive rates. When accumulated energy consistently exceeds the threshold within a continuous time index interval, that time period is marked as an "abnormal window" for subsequent analysis and judgment. In this scheme, this judgment mechanism effectively captures the transient impact of thermal-mechanical-electrical coupling anomalies under power consumption pulses on link performance, rather than relying solely on single-point instantaneous values. Equivalently, the accumulated energy calculation can also be updated in real-time using a sliding integral method, which reduces latency in online monitoring systems and decreases processing burden while maintaining sensitivity.

[0040] Please continue reading Figure 1 The features within the abnormal window are compared with the benchmark data to generate standardized defect indicators, and a test judgment is output based on the comparison result of the indicators and the dynamic judgment threshold.

[0041] In one embodiment of the present invention, the step of comparing the features within the abnormal window with the benchmark data to generate a standardized defect index, and outputting a test judgment based on the comparison result of the index and the dynamic judgment threshold, includes: Within the anomaly window, the multi-physical quantity response features are compared element-by-element with the features of the corresponding time index in the benchmark data to obtain a difference vector; The difference vector is normalized to eliminate the differences in units and numerical ranges between different response types, thus obtaining a standardized defect index. The dynamic judgment threshold is calculated based on the external parameters of ambient temperature and power ripple collected in real time. The standardized defect index is compared with the dynamic judgment threshold. When the index value exceeds the threshold, an abnormal judgment is output; otherwise, a normal judgment is output.

[0042] The following is a detailed description of the steps involved in the above embodiments: In this embodiment, the difference vector refers to the vector obtained by subtracting the multi-physical quantity response features within the anomaly window from the multi-physical quantity response features at the corresponding time index position in the benchmark data element by element. Each element represents the deviation of the response type from the benchmark state at a certain frequency point and time point. The multi-physical quantity response features include frequency change data, bit error rate data, and phase change data. The benchmark data is usually collected from samples of the same batch or historically stable performance under the same test conditions and stored in a database. In specific implementation, the corresponding time period in the benchmark data can be located first according to the time index of the anomaly window, and then element-by-element calculation can be performed according to the index order to ensure that each element of the difference vector corresponds one-to-one. In the differential link thermal-mechanical-electrical coupling test scenario of this scheme, such element-by-element comparison can accurately capture the small offset between the abnormal state and the normal state, rather than relying solely on the overall trend judgment. Equivalently, if the benchmark data is a continuous curve fitted by a function, the benchmark value at the same time index can also be calculated by interpolation, and then the element-by-element comparison can be performed.

[0043] The purpose of normalization is to eliminate differences in units and numerical ranges between different response types, enabling frequency variation data (unit: Hz), bit error rate data (dimensionless probability value), and phase variation data (unit: ° or radians) to be compared on the same scale. Linear normalization can be used, for example, dividing the difference value for each response type by the standard deviation or range of that type in the baseline data, resulting in a dimensionless vector with a consistent numerical range. This normalized vector is the "standardized defect index," which has the same number of elements as the difference vector but is adapted to a unified judgment threshold standard. In this scenario, this process ensures that the contribution of different physical quantities to the final judgment is not unreasonably amplified or weakened due to differences in the original numerical ranges. Equivalently, Z-score normalization (mean 0, standard deviation 1) can achieve the same effect, suitable for scenarios with relatively stable baseline data distribution.

[0044] The dynamic threshold is a judgment benchmark that is dynamically adjusted based on real-time acquired external environmental parameters (including ambient temperature and power supply ripple). Ambient temperature is acquired by temperature sensors distributed throughout the test environment, and power supply ripple can be measured on the power rail using an oscilloscope or a high-precision sampling module. These external parameters affect the transient response of the differential link and circuit board; for example, high temperatures may lead to increased phase drift, and increased power supply ripple may cause sudden changes in the bit error rate. Therefore, the dynamic threshold calculation multiplies or adds the base threshold to the correction coefficients of the external parameters, thereby automatically adjusting the sensitivity under different operating conditions. In implementation, each element of the standardized defect index is compared with the corresponding dynamic threshold. When any index value exceeds the threshold, the abnormal window is judged as abnormal; otherwise, it is considered normal. This avoids false alarms or missed alarms caused by fixed thresholds under environmental changes while maintaining high sensitivity to actual failure risks. Equivalently, the dynamic threshold calculation can also be embedded in an adaptive control algorithm, allowing it to update in real time according to external conditions.

[0045] In one embodiment of the present invention, the step of calculating a dynamic judgment threshold based on external parameters of real-time acquired ambient temperature and power ripple, and comparing the standardized defect index with the dynamic judgment threshold, outputting an anomaly judgment when the index value exceeds the threshold, and outputting a normal judgment otherwise, includes: The ambient temperature, power ripple, and power rail activity within the corresponding abnormal window are collected during the test period. The parameters are weighted and fused according to the preset sensitivity coefficient to obtain the threshold correction amount. Smoothing filtering is performed on the threshold correction amount within the rolling time window to suppress drastic threshold changes caused by transient disturbances and generate a smoothed dynamic judgment threshold. When the rate of change of the threshold correction amount within a continuous sampling period is lower than the steady-state rate threshold, the dynamic judgment threshold is compared with the latest standardized defect index and the judgment result is output; when the rate of change exceeds the steady-state rate threshold, the threshold is frozen and updated and the previous dynamic judgment threshold is used for comparison.

[0046] The following is a detailed description of the steps involved in the above embodiments: In this embodiment, power rail activity refers to the dynamic fluctuation of the power rail voltage or current under the action of power consumption pulses, reflecting the transient load changes of the power supply system. It can be measured in real time using a high-speed sampling module (e.g., a voltage / current sampler with a bandwidth ≥ 10MHz). During the test cycle, the ambient temperature is collected by temperature sensors (such as thermocouples or digital thermometers) placed in the test area; power ripple is collected at the power rail by a high-bandwidth oscilloscope or power quality analyzer. After data acquisition, the three types of parameters are weighted and fused according to preset sensitivity coefficients (set based on historical experiments and engineering experience to reflect the influence weight of each parameter on threshold adjustment), and the threshold correction is output. The significance of this processing is that it can simultaneously consider the comprehensive impact of external environmental factors (temperature, power ripple) and internal electrical activity characteristics (power rail activity) on system stability, thereby dynamically adjusting the judgment criteria. An equivalent method is to re-weight the parameters after normalization to reduce the impact of dimensional differences on the fusion result.

[0047] To prevent sharp fluctuations in the threshold correction due to transient interference (such as the switching action of test equipment, electromagnetic pulses, etc.), smoothing filtering needs to be performed within a rolling time window. Specifically, methods such as moving average filtering, weighted moving average, or first-order low-pass filtering can be used, covering multiple sampling periods (e.g., 5-10 sampling points) within the time window length, thereby smoothing out high-frequency interference components. The smoothed output is the dynamic judgment threshold, which serves as a real-time benchmark for judging anomalies. It can be slowly adjusted as external conditions gradually change, without significant fluctuations due to short-term anomalies. In the differential link thermal-mechanical-electrical coupling test scenario of this invention, this approach can significantly reduce misjudgments caused by transient noise. Equivalently, if the system has sufficient computational resources, Kalman filtering can also be used to achieve smoothing and prediction functions, improving stability in fluctuating environments.

[0048] After generating the dynamic threshold, the system needs to determine whether the current external parameters are in a steady state. The steady-state rate threshold refers to the condition where the rate of change of the threshold correction is lower than a certain set value, usually based on the absolute rate of change or the variance of change. For example, if the change amplitude within N consecutive sampling periods is less than a preset threshold, it is determined that the system has entered a steady state. In the steady state, the latest dynamic judgment threshold is compared with the latest standardized defect index, and the judgment result is output. If the rate of change exceeds the steady-state rate threshold (indicating that the external conditions are in a state of rapid fluctuation or disturbance), the threshold update is frozen, and the dynamic judgment threshold of the previous period is used to avoid threshold distortion in a short period of time. In this scheme, this design can effectively prevent threshold instability and misjudgment caused by sudden environmental changes. Equivalently, the trajectory of external parameter changes can be recorded at the same time as the threshold is frozen for post-event diagnosis and fault tracing.

[0049] The testing method for the circuit board in the embodiments of the present invention has been described above. The testing apparatus for the circuit board in the embodiments of the present invention will be described below. Please refer to [link / reference]. Figure 2 One embodiment of the circuit board testing apparatus of the present invention includes: The reference acquisition module 101 is used to sequentially apply a power consumption pulse sequence to multiple power supply rails of the circuit board under control conditions, and to acquire reference data reflecting the electrical state of the differential link before the power consumption pulses are triggered. The response acquisition module 102 is used to simultaneously acquire the frequency change data, bit error rate data and phase change data of the differential link during the power consumption pulse to obtain a multi-physical quantity response sequence. The synchronization processing module 103 is used to perform time synchronization processing on the multi-physical quantity response sequence based on the power consumption pulse trigger time, and extract multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect. Tensor recognition module 104 is used to combine the multi-scale feature vectors into feature tensors with time, frequency and response type dimensions, and identify the time interval in which the coupling energy exceeds the threshold as an abnormal window. The judgment output module 105 is used to compare the features within the abnormal window with the benchmark data, generate standardized defect indicators, and output test judgments based on the comparison results of the indicators and dynamic judgment thresholds.

[0050] above Figure 2 The testing device for the circuit board in the embodiments of the present invention will be described in detail from the perspective of modular functional entities. The testing equipment for the circuit board in the embodiments of the present invention will be described in detail from the perspective of hardware processing.

[0051] Figure 3 This is a schematic diagram of a circuit board testing device 200 provided in an embodiment of the present invention. The testing device 200 can vary significantly due to different configurations or performance characteristics. It may include one or more processors 210 (e.g., one or more processors) and a memory 220, and one or more storage media 230 (e.g., one or more mass storage devices) for storing application programs 233 or data 232. The memory 220 and storage media 230 can be temporary or persistent storage. The program stored in the storage media 230 may include one or more modules (not shown in the diagram), each module including a series of instruction operations on the circuit board testing device 200. Furthermore, the processor 210 may be configured to communicate with the storage media 230 and execute the series of instruction operations in the storage media 230 on the circuit board testing device 200 to implement the steps of the circuit board testing method described above.

[0052] The circuit board testing equipment 200 may also include one or more power supplies 240, one or more wired or wireless network interfaces 250, one or more input / output interfaces 260, and / or one or more operating systems 231, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will understand that... Figure 3 The test equipment structure of the circuit board shown does not constitute a limitation on the test equipment for the circuit board provided by the present invention. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0053] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the steps of the test method for the circuit board.

[0054] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system, device, or unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0055] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0056] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for testing a circuit board, characterized in that, include: Under controlled conditions, a sequence of power consumption pulses is applied sequentially to multiple power supply rails of the circuit board, and reference data reflecting the electrical state of the differential link is collected before the power consumption pulses are triggered. During the power pulse, frequency change data, bit error rate data, and phase change data of the differential link are simultaneously collected to obtain a multi-physical quantity response sequence. Based on the power consumption pulse triggering time, the multi-physical quantity response sequence is time-synchronized and multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect are extracted. The multi-scale feature vectors are combined into a feature tensor with time, frequency and response type dimensions, and the time intervals in which the coupling energy exceeds the threshold are identified as abnormal windows. The features within the anomaly window are compared with the baseline data to generate standardized defect indicators, and a test judgment is output based on the comparison result of the indicators and the dynamic judgment threshold.

2. The circuit board testing method according to claim 1, characterized in that, The process of sequentially applying a power consumption pulse sequence to multiple power supply rails of the circuit board under controlled conditions, and acquiring reference data reflecting the electrical state of the differential link before the power consumption pulses are triggered, includes: The contour parameters characterizing the power consumption change are analyzed to obtain pulse configuration information including power consumption peak, rise time rate, duration and power supply rail sequence, and a power consumption pulse sequence triggered sequentially is generated based on the configuration information. Before emitting the power pulse sequence, a low-amplitude power cycle is applied to preheat the circuit board, and multiple temperature samples are monitored until the temperature difference meets the steady-state condition. Multiple sets of impedance, phase, and bit error rate samples are collected at the same time reference before the power consumption pulse is triggered. These samples are then differentially compensated with the data collected during the preheating stage to obtain the reference data.

3. The circuit board testing method according to claim 1, characterized in that, During the power pulse, frequency change data, bit error rate data, and phase change data of the differential link are simultaneously acquired to obtain a multi-physical quantity response sequence, including: Based on the current change rate of the power consumption pulse, the pulse duration is divided into a high-slope measurement window and a low-slope measurement window. Within the high-slope measurement window, a coverage-based frequency domain estimation is performed on the resonance-related frequency characteristics of the differential link. Within the low-slope measurement window, a tracking-based frequency domain estimation is performed based on the frequency measurements of the previous window in the neighborhood of the center frequency point. At the center of each measurement window, the acquisition channel is triggered uniformly, and the bit error rate of the transmitted data stream of the differential link is statistically analyzed. The difference between the phase corresponding to the current frequency measurement value and the phase in the reference data is calculated to obtain the phase change. The frequency change data, bit error rate data, and phase change data obtained in each measurement window are used to establish a unified time index according to the power consumption pulse trigger time, forming a multi-physical quantity response sequence.

4. The circuit board testing method according to claim 1, characterized in that, Based on the power consumption pulse triggering time, the multi-physical quantity response sequence is time-synchronized, and a multi-scale feature vector reflecting the thermo-mechanical-electric coupling effect is extracted, including: Using the power consumption pulse trigger time as time zero, the multi-physical quantity response sequences are time-aligned at time zero, and resampling is performed according to the sampling period relationship of each sequence to obtain a synchronization sequence with a unified time reference. Risk weights are calculated based on the interconnection layout characteristics of the circuit board, and the risk weights are applied to the synchronization sequence to obtain a risk-weighted sequence; Multi-resolution decomposition is performed on the risk-weighted sequence to extract coefficient vectors at different time scales, which serve as multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect.

5. The circuit board testing method according to claim 4, characterized in that, The step of calculating risk weights based on circuit board interconnection layout characteristics and applying the risk weights to the synchronization sequence to obtain a risk-weighted sequence includes: Using the circuit board layout coordinates as a reference, the input parameters for weight calculation are determined based on the spatial proximity of differential traces to power rails, main heat-generating components and fixed boundaries, as well as cross-layer connectivity density. The input parameters are normalized in amplitude and weight allocation coefficients are determined according to response type. The normalized weights are multiplied by the allocation coefficients to obtain the channel weights corresponding to frequency change data, bit error rate data and phase change data. During the power consumption pulse, when the changes in the multi-point temperature sampling values ​​exceed the preset stable range, the channel weights are updated within the current measurement window, and the updated channel weights are applied element by element to the time-synchronized multi-physical quantity response sequence to obtain the risk-weighted sequence.

6. The circuit board testing method according to claim 1, characterized in that, The step of combining the multi-scale feature vectors into a feature tensor with time, frequency, and response type dimensions, and identifying time intervals where the coupling energy exceeds a threshold as anomaly windows, includes: The multi-scale feature vectors are arranged and stacked in an ordered manner according to the time index, frequency index, and response type index to generate a three-dimensional feature tensor. Perform matrix decomposition on the three-dimensional feature tensor using overlapping time sliding windows to obtain the energy distribution sequence corresponding to each time window; The cumulative energy of the energy distribution sequence is calculated and compared with a preset energy threshold. When the cumulative energy within a continuous time index exceeds the preset energy threshold, the corresponding time index interval is determined as an abnormal window.

7. The circuit board testing method according to claim 1, characterized in that, The step of comparing the features within the anomaly window with the benchmark data to generate standardized defect indicators, and outputting a test judgment based on the comparison result of the indicators and the dynamic judgment threshold, includes: Within the anomaly window, the multi-physical quantity response features are compared element-by-element with the features of the corresponding time index in the benchmark data to obtain a difference vector; The difference vector is normalized to eliminate the differences in units and numerical ranges between different response types, thus obtaining a standardized defect index. The dynamic judgment threshold is calculated based on the external parameters of ambient temperature and power ripple collected in real time. The standardized defect index is compared with the dynamic judgment threshold. When the index value exceeds the threshold, an abnormal judgment is output; otherwise, a normal judgment is output.

8. The circuit board testing method according to claim 7, characterized in that, The dynamic judgment threshold is calculated based on external parameters such as real-time collected ambient temperature and power ripple. The standardized defect index is compared with the dynamic judgment threshold. When the index value exceeds the threshold, an abnormal judgment is output; otherwise, a normal judgment is output. This includes: The ambient temperature, power ripple, and power rail activity within the corresponding abnormal window are collected during the test period. The parameters are weighted and fused according to the preset sensitivity coefficient to obtain the threshold correction amount. Smoothing filtering is performed on the threshold correction amount within the rolling time window to suppress drastic threshold changes caused by transient disturbances and generate a smoothed dynamic judgment threshold. When the rate of change of the threshold correction amount within a continuous sampling period is lower than the steady-state rate threshold, the dynamic judgment threshold is compared with the latest standardized defect index and the judgment result is output; when the rate of change exceeds the steady-state rate threshold, the threshold is frozen and updated and the previous dynamic judgment threshold is used for comparison.

9. A testing device for a circuit board, characterized in that, include: The reference acquisition module is used to sequentially apply a power consumption pulse sequence to multiple power supply rails of the circuit board under control conditions, and to acquire reference data reflecting the electrical state of the differential link before the power consumption pulses are triggered. The response acquisition module is used to simultaneously acquire frequency change data, bit error rate data, and phase change data of the differential link during the power consumption pulse to obtain a multi-physical quantity response sequence. The synchronization processing module is used to perform time synchronization processing on the multi-physical quantity response sequence based on the power consumption pulse trigger time, and extract multi-scale feature vectors reflecting the thermo-mechanical-electric coupling effect. The tensor recognition module is used to combine the multi-scale feature vectors into a feature tensor with time, frequency and response type dimensions, and identify the time interval in which the coupling energy exceeds the threshold as an abnormal window. The judgment output module is used to compare the features within the abnormal window with the benchmark data, generate standardized defect indicators, and output test judgments based on the comparison results of the indicators and dynamic judgment thresholds.

10. A testing device for circuit boards, characterized in that, The testing equipment for the circuit board includes: a memory and at least one processor, wherein the memory stores instructions; The at least one processor invokes the instructions in the memory to cause the test equipment of the circuit board to perform the steps of the test method for the circuit board as described in any one of claims 1 to 8.

Images