Display device of hybrid thin film transistor

Abstract

The invention provides a display device of a hybrid thin film transistor, which belongs to the technical field of display, and comprises a plurality of thin film transistors formed on the same semiconductor substrate, the thin film transistors comprise a first thin film transistor and a second thin film transistor, the first thin film transistor is a low-temperature polycrystalline silicon thin film transistor, and the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor. The second thin film transistor is an oxide semiconductor thin film transistor; the shielding layer is located below the active layer of the first thin film transistor and on the projection perpendicular to the semiconductor substrate, and the shielding layer at least partially covers the active layer of the first thin film transistor and completely covers the channel region of the first thin film transistor; and the shading layer is located below the active layer of the second thin film transistor and on the projection perpendicular to the semiconductor substrate, and the shading layer at least completely covers the active layer of the second thin film transistor. The invention has the beneficial effects that the advantages of the low-temperature polycrystalline silicon thin film transistor and the oxide semiconductor thin film transistor are fully combined, the display effect is ensured while low power consumption is realized, and the device reliability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a hybrid thin film transistor display device. BACKGROUND

[0002] With the development of information technology era, flat panel display has rapidly become the mainstream product in display field due to its advantages of light and thin, energy saving and so on. Among them, organic light emitting diode (OLED) has become the next generation display technology with self-luminous characteristics, which has the advantages of large viewing angle, high contrast, fast response, low power consumption, light and thin, flexible and so on.

[0003] The OLED display includes an organic light emitting device for displaying an image, a pixel circuit for driving the organic light emitting device, and a circuit in a non-display area. Among them, the pixel circuit contains a plurality of thin film transistors (TFTs), and the thin film transistors can be divided into various types according to different active layer materials. Among them, low temperature poly-silicon thin film transistor (LTPS-TFT) and oxide semiconductor thin film transistor (Oxide TFT) are the two most widely used types at present.

[0004] LTPS-TFT is widely used in pixel circuit, gate driver circuit (GEOA) and multiplexer (Mux) circuit of display due to its high mobility (100 cm2 / Vs or above), low power consumption and high reliability, and can be used as a driving TFT in the pixel circuit. Oxide semiconductor thin film transistor, such as indium gallium zinc oxide thin film transistor (IGZO-TFT), has a larger band gap than silicon material, so that it is difficult for electrons to cross the band gap in the off state, resulting in a lower off current. Therefore, the oxide semiconductor thin film transistor as a switching TFT is suitable for application scenarios with shorter on time and longer off time.

[0005] Due to the limitation of battery capacity, reducing the power consumption of the display becomes one of the key problems to be solved in the display technology field. In order to reduce the power consumption, one of the solutions is to use pixel circuit for low refresh rate driving. However, in some application scenarios with high requirements for display effect, such as games, video playing and the like, users have a strong demand trend for high refresh rate driving (usually as high as 120Hz or even higher). However, due to the large leakage current of LTPS-TFT, it is difficult to realize low refresh rate driving. In contrast, IGZO-TFT has lower leakage current during the off state, and can be suitable for low refresh rate display, so as to realize low power consumption while ensuring display effect.

[0006] In recent years, in order to fully exert the respective advantages of LTPS-TFT and IGZO-TFT, researchers have begun to develop a display device integrating LTPS-TFT and IGZO-TFT on the same substrate, i.e. Low Temperature Polycrystalline Oxide (LTPO) backplane technology. However, the process of the LTPO device is relatively complex and has poor reliability. SUMMARY

[0007] In order to solve the above technical problems, the application provides a display device of a hybrid thin film transistor.

[0008] The technical problems solved by the application can be implemented by the following technical solutions:

[0009] A display device of a hybrid thin film transistor, comprising a plurality of thin film transistors formed on the same semiconductor substrate, wherein the plurality of thin film transistors comprises a first thin film transistor and a second thin film transistor, the first thin film transistor is a low temperature polycrystalline silicon thin film transistor, and the second thin film transistor is an oxide semiconductor thin film transistor.

[0010] Further comprising:

[0011] A shielding layer located below the active layer of the first thin film transistor, and in the projection perpendicular to the semiconductor substrate, the shielding layer at least partially covers the active layer of the first thin film transistor, and completely covers the channel region of the first thin film transistor.

[0012] An optical shielding layer located below the active layer of the second thin film transistor, and in the projection perpendicular to the semiconductor substrate, the optical shielding layer at least completely covers the active layer of the second thin film transistor.

[0013] Preferably, further comprising:

[0014] A capacitor is formed on the semiconductor substrate, the capacitor comprising a first plate and a second plate, the first plate being in the same layer as the shielding layer, and the second plate being in the same layer as the gate of the first thin film transistor.

[0015] Preferably, the channel region of the first thin film transistor comprises a lightly doped drain region between the source region and the drain region.

[0016] In a projection perpendicular to the semiconductor substrate, the shielding layer covers at least half of the width of the lightly doped drain region, and the edge of the shielding layer does not exceed the edge of the drain region of the first thin film transistor.

[0017] Preferably, the light shielding layer is in the same layer as one of the shielding layer and the gate of the first thin film transistor.

[0018] Preferably, the edge of the light shielding layer exceeds the edge of the active layer of the second thin film transistor by a predetermined distance.

[0019] Preferably, the predetermined distance is 1.5 microns to 3.0 microns.

[0020] Preferably, the semiconductor substrate further comprises:

[0021] A buffer layer is formed on the semiconductor substrate, and the shielding layer is in the buffer layer.

[0022] A first gate insulating layer is formed on the buffer layer, and the active layer of the first thin film transistor is in the first gate insulating layer.

[0023] A first interlayer insulating layer is formed on the first gate insulating layer, and the gate of the first thin film transistor is in the first interlayer insulating layer.

[0024] A second gate insulating layer is formed on the first interlayer insulating layer, and the active layer of the second thin film transistor is in the second gate insulating layer.

[0025] A second interlayer insulating layer is formed on the second gate insulating layer, and the top gate of the second thin film transistor is in the second interlayer insulating layer.

[0026] A planarization layer is formed on the second interlayer insulating layer, the first source trace and the first drain trace of the first thin film transistor and the second source trace and the second drain trace of the second thin film transistor are located in the planarization layer respectively, and the first source trace, the first drain trace, the second source trace and the second drain trace respectively extend downward from the upper surface of the planarization layer to the contact of the first source trace with the source region of the first thin film transistor, the contact of the first drain trace with the drain region of the first thin film transistor, the contact of the second source trace with the source region of the second thin film transistor and the contact of the second drain trace with the drain region of the second thin film transistor, and the upper surface of the planarization layer is formed with an anode which extends downward from the upper surface of the planarization layer to contact the first source trace of the first thin film transistor;

[0027] A pixel definition layer is formed on the planarization layer, and a pixel opening is formed in the pixel definition layer to expose the anode.

[0028] Preferably, the first gate insulating layer is formed on the buffer layer as a whole, and simultaneously as the gate insulating layer of the first thin film transistor and the buffer layer of the second thin film transistor; or

[0029] The first gate insulating layer is a patterned first gate insulating layer.

[0030] Preferably, the second gate insulating layer is formed on the first interlayer insulating layer as a whole, and simultaneously as the interlayer insulating layer of the first thin film transistor and the gate insulating layer of the second thin film transistor; or

[0031] The second gate insulating layer is a patterned second gate insulating layer.

[0032] Preferably, the buffer layer comprises:

[0033] A first buffer layer is formed on the semiconductor substrate.

[0034] A second buffer layer is formed on the first buffer layer, and the shielding layer is located in the second buffer layer.

[0035] The technical scheme of the present application has the following advantages or beneficial effects:

[0036] The application integrates low-temperature polysilicon thin film transistor and oxide semiconductor thin film transistor on the same semiconductor substrate, fully combines the advantages of both, realizes low power consumption while ensuring display effect; at the same time, a shielding layer is arranged below the active layer of the low-temperature polysilicon thin film transistor, the shielding layer at least partially covers the active layer and completely covers the channel region, and a light shielding layer is arranged below the active layer of the second thin film transistor, the light shielding layer at least completely covers the active layer, which can prevent hydrogen from diffusing into the channel of the oxide semiconductor thin film transistor, thereby improving the reliability of the LTPO device and enhancing the user experience. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 For the preferred embodiment 1 of the application, the structure schematic diagram of the display device of the hybrid thin film transistor is shown in the figure.

[0038] Figures 2A-2O For the preferred embodiment 1 of the application, the structure schematic diagram of the display device of the hybrid thin film transistor is shown in the figure.

[0039] Figure 3 For the preferred embodiment 2 of the application, the structure schematic diagram of the display device of the hybrid thin film transistor is shown in the figure.

[0040] Figure 4 For the preferred embodiment 3 of the application, the structure schematic diagram of the display device of the hybrid thin film transistor is shown in the figure. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0042] It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other without conflict.

[0043] The application will be further described below with reference to the drawings and specific embodiments, but is not limited to the application.

[0044] Embodiment 1

[0045] Reference Figure 1In a preferred embodiment of the present application, in view of the above problems existing in the prior art, a hybrid thin film transistor display device is provided, comprising a plurality of thin film transistors formed on the same semiconductor substrate 1, the plurality of thin film transistors comprising a first thin film transistor 2 and a second thin film transistor 3, the first thin film transistor 2 being a low temperature poly-silicon thin film transistor (LTPS-TFT), and the second thin film transistor 3 being an oxide semiconductor thin film transistor, such as an indium gallium zinc oxide thin film transistor (IGZO-TFT).

[0046] In the present embodiment, the LTPS-TFT and the IGZO-TFT are integrated on the same semiconductor substrate 1, so that the advantages of the two types of thin film transistors can be fully combined, thereby achieving low power consumption while ensuring the display effect of the display device.

[0047] The active layer of the first thin film transistor 2 comprises a first source region 212, a first channel region 211 and a first drain region 213, and the active layer of the second thin film transistor 3 comprises a second source region 312, a second channel region 311 and a second drain region 313.

[0048] For ease of description and understanding, the active layer of the first thin film transistor 2 can also be referred to as the first active layer 21 in the text, but in fact they represent the same component. By analogy, the source region of the first thin film transistor 2 can also be referred to as the first source region 212, the channel region of the first thin film transistor 2 can also be referred to as the first channel region 211, and the drain region of the first thin film transistor 2 can also be referred to as the first drain region 213. Similarly, the active layer of the second thin film transistor 3 can also be referred to as the second active layer 31 in the text, the source region of the second thin film transistor 3 can also be referred to as the second source region 312, the channel region of the second thin film transistor 3 can also be referred to as the second channel region 311, and the drain region of the second thin film transistor 3 can also be referred to as the second drain region 313.

[0049] The display device further comprises:

[0050] The shielding layer 4 is located below the active layer of the first thin film transistor 2, and in a projection perpendicular to the semiconductor substrate 1, the shielding layer 4 at least partially covers the active layer of the first thin film transistor 2, and completely covers the channel region of the first thin film transistor 2.

[0051] The light shielding layer 5 is located below the active layer of the second thin film transistor 2, and in a projection perpendicular to the semiconductor substrate 1, the light shielding layer 5 at least completely covers the active layer of the second thin film transistor 2.

[0052] In the field of display technology, the pursuit of high resolution and low power consumption constantly drives the device size towards miniaturization. However, the short channel poly-silicon thin film transistor (TFT) is limited by the manufacturing process, and its channel length is difficult to further reduce, which exacerbates the kink effect problem.

[0053] The so-called kink effect of TFT refers to the phenomenon that the drain current of poly-silicon thin film transistor (p-Si TFT) unexpectedly increases after pinch-off voltage under short channel conditions, resulting in the upward warping of the output characteristic curve in the high drain-source voltage (Vds) region. This phenomenon is mainly caused by the following effects:

[0054] Firstly, impact ionization effect. When the channel length is shortened, the lateral electric field will be significantly enhanced. In a high electric field environment, carriers (such as electrons) will be accelerated and gain enough energy, and then collide with lattice atoms to generate electron-hole pairs. The newly generated carriers will further participate in the conduction process, forming additional current, thereby causing the drain current to suddenly increase after pinch-off voltage.

[0055] Secondly, floating body effect. The substrate of poly-silicon TFT usually adopts insulating materials (such as glass), which is different from the conductive silicon substrate of MOSFET. The holes generated by impact ionization cannot be quickly conducted out, but will gather near the base, changing the local potential (body potential). This potential change will in turn affect the channel carrier concentration, further exacerbating the non-linear growth of the drain current.

[0056] Thirdly, drain-induced grain boundary lowering (DIGBL) effect. There are grain boundaries in poly-silicon materials, and the height of the grain boundary barrier will affect the current transmission. In a short channel device, the high voltage of the drain will cause the band tilt, reduce the grain boundary barrier, and make the carriers more easily cross the barrier, thereby causing abnormal increase of current.

[0057] In OLED display applications, driving TFT needs to work in the saturation region, and ideally the drain current should only be controlled by the gate voltage (Vgs). However, the kink effect causes the current to change with Vds, which destroys the linear relationship between current and Vgs, and further leads to unstable driving current, causing uneven pixel brightness. The current fluctuation caused by the kink effect will directly reflect as brightness change and gray scale distortion, reducing the display quality. In addition, long-term current fluctuation may also accelerate device aging, shorten the service life of the display panel, and cause reliability problems.

[0058] In the embodiment, by arranging the shielding layer 4 under the first active layer 21 of the low-temperature polysilicon thin-film transistor (LTPS-TFT), the potential generated on the surface of the substrate and the external incident light can be blocked. The shielding layer 4 covers the channel region of the LTPS-TFT in vertical projection, and when a constant voltage is applied to the shielding layer 4, the influence of the electric charges flowing through the channel of the driving pixel LTPS TFT can be minimized to avoid causing the kink effect, thereby avoiding the phenomenon of unexpected increase of the drain current of the LTPS-TFT after pinch-off voltage under the short channel condition of the LTPS-TFT, improving the stability and reliability of the LTPS-TFT, and further improving the overall performance of the display device.

[0059] Meanwhile, the light shielding layer 5 is arranged under the second active layer 31 of the indium gallium zinc oxide thin-film transistor (IGZO-TFT), and the light shielding layer 5 at least completely covers the second active layer 31 of the IGZO-TFT in vertical projection, which can block the influence of external light on the reliability of the IGZO TFT, and prevent hydrogen from diffusing into the channel of the IGZO-TFT, thereby avoiding the abnormal increase of the carrier concentration and the shift of the threshold voltage caused by the combination of hydrogen and oxygen in the IGZO material to form a defect state, and further improving the electrical performance, stability and reliability of the display device.

[0060] In a preferred embodiment of the present application, the display device further comprises:

[0061] The capacitor 6 is formed on the semiconductor substrate 1, and the capacitor 6 includes a first plate 61 and a second plate 62, the first plate 61 is located in the same layer as the shielding layer 4, and the second plate 62 is located in the same layer as the gate 22 of the first thin-film transistor 2.

[0062] Specifically, the capacitor 6 is integrated on the same semiconductor substrate 1 together with the LTPS-TFT and the IGZO-TFT. The capacitor 6 can reduce pixel voltage fluctuation, maintain pixel voltage stability, suppress leakage current, support dynamic refresh rate switching, and optimize display performance and power consumption.

[0063] Specifically, although the LTPS-TFT has high mobility, the off-state current is relatively high, which can cause pixel voltage fluctuation. The off-state current of the IGZO-TFT is extremely low, but there is still a small leakage. The capacitor 6 stores electric charges to compensate for the voltage drop caused by leakage, ensures that the pixel voltage remains constant within the frame refresh interval, thereby improving display uniformity and reducing flicker.

[0064] In the hybrid driving system, the capacitor 6 realizes seamless switching of refresh rate by adjusting the charging and discharging path, and reduces power consumption. In the high frequency mode (such as 120Hz), the LTPS-TFT dominates the driving, and the capacitor 6 cooperates with the LTPS-TFT. The capacitor 6 matches the high frequency signal by fast charging and discharging, accelerates the OLED light emitting response, and shortens the response time. In the low frequency mode (such as 1Hz), the IGZO-TFT dominates the driving, and the capacitor 6 stores charges. The IGZO-TFT cooperates with the capacitor 6 to reduce the charging frequency and prolong the device endurance.

[0065] The capacitor 6 is mainly composed of two metal layer plates. In the traditional semiconductor manufacturing process, a special mask is used for patterning each layer, which increases the manufacturing cost and the complexity of the preparation process. In the embodiment, one of the two plates of the capacitor 6 is arranged on the same layer as the shielding layer 4, and the other plate is arranged on the same layer as the gate 22 of the LTPS-TFT. The manufacturing of multiple structures can be completed at the same time in one mask process, reducing the number of masks used, reducing the manufacturing cost, and simplifying the overall preparation process.

[0066] In the preferred embodiment of the present application, as shown in Figure 2H , the channel region of the first thin film transistor 2 includes a lightly doped drain (LDD) region 214 between the source region and the drain region;

[0067] In the projection perpendicular to the semiconductor substrate 1, the shielding layer 4 covers at least half of the width of the lightly doped drain region 214, and the edge of the shielding layer 4 does not exceed the edge of the drain region of the first thin film transistor 2.

[0068] Specifically, in the embodiment, the shielding layer 4 covers the channel region of the LTPS TFT, including covering more than half of the width of the lightly doped drain (LDD) region 214. When a constant voltage is applied to the shielding layer 4 (such as the source region of the LTPS TFT is connected to one end of the shielding layer 4, and the width of this end of the shielding layer 4 exceeds the source region of the LTPS TFT and is connected to the source region, which is not marked in the figure), the other end of the shielding layer 4 does not exceed the drain region of the LTPS TFT, so as to avoid causing unnecessary kink effect, improve the stability and reliability of the LTPS-TFT, and further improve the overall performance of the display device.

[0069] It should be noted that the present application only shows the region where the lightly doped drain (LDD) region 214 is located in Figure 2H , in fact, although Figure 1 and other structure diagrams do not explicitly show it, the structure presented in the figure also has an LDD region.

[0070] In the preferred embodiment of the present application, the light shielding layer 5 and the shielding layer 4 are located in the same layer.

[0071] Specifically, since the first plate 61 of the aforementioned capacitor 6 and the shielding layer 4 are located in the same layer, i.e., the light shielding layer 5, the capacitor 6 and the shielding layer 4 are located in the same layer, the number of masks used in the process is reduced, and the manufacturing process is simplified.

[0072] In the preferred embodiment of the present application, the edge of the light shielding layer 5 exceeds the edge of the active layer of the second thin film transistor 3 by a predetermined distance, and the predetermined distance is 1.5 microns to 3.0 microns.

[0073] Specifically, the light shielding layer 5 covers the second active layer 31 of the IGZO TFT, and the width of the light shielding layer 5 exceeds the edge of the active layer of the IGZO TFT by a distance of about 1.5 microns to 3.0 microns, which can effectively prevent hydrogen from diffusing into the channel region of the active layer of the IGZO TFT, and improve the reliability of the display device.

[0074] In the preferred embodiment of the present application, the display device further comprises:

[0075] The first buffer layer 7 is formed on the semiconductor substrate 1.

[0076] The second buffer layer 8 is formed on the first buffer layer 7, and the shielding layer 4 is located in the second buffer layer 8.

[0077] The first gate insulating layer 9 is formed on the second buffer layer 8, and the active layer of the first thin film transistor 2 is located in the first gate insulating layer 9.

[0078] The first interlayer insulating layer 10 is formed on the first gate insulating layer 9, and the gate of the first thin film transistor 2 is located in the first interlayer insulating layer 10.

[0079] The second gate insulating layer 11 is formed on the first interlayer insulating layer 10, and the active layer of the second thin film transistor 3 is located in the second gate insulating layer 11.

[0080] The second interlayer insulating layer 12 is formed on the second gate insulating layer 11, and the top gate 32 of the second thin film transistor 3 is located in the second interlayer insulating layer 12.

[0081] A planarization layer 13 is formed on the second interlayer insulating layer 12. The first source line 25 and the first drain line 24 of the first thin film transistor 2, and the second source line 33 and the second drain line 34 of the second thin film transistor 3 are respectively located in the planarization layer 13. The first source line 25, the first drain line 24, the second source line 33 and the second drain line 34 extend downward from the upper surface of the planarization layer 13, until the first source line 25 contacts the source region of the first thin film transistor 2, the first drain line 24 contacts the drain region of the first thin film transistor 2, the second source line 33 contacts the source region of the second thin film transistor 3, and the second drain line 34 contacts the drain region of the second thin film transistor 3. An anode 20 is formed on the upper surface of the planarization layer 13, and the anode 20 extends downward from the upper surface of the planarization layer 13 to contact the first source line 25 of the first thin film transistor 2.

[0082] A pixel definition layer 14 is formed on the planarization layer 13, and a pixel opening 141 is provided in the pixel definition layer 14 to expose the anode 20.

[0083] In a preferred embodiment of the present invention, the first gate insulating layer 9 is formed on the entire surface of the second buffer layer 8, and the first gate insulating layer 9 serves as both the gate insulating layer of the first thin film transistor 2 and the buffer layer of the second thin film transistor 3.

[0084] In a preferred embodiment of the present invention, the second gate insulating layer 11 is formed on the entire surface of the first interlayer insulating layer 10, and the second gate insulating layer 11 serves as both the interlayer insulating layer of the first thin film transistor 2 and the gate insulating layer of the second thin film transistor 3.

[0085] Factors affecting the reliability of TFTs include: the thickness of the active layer, the gate insulating layer, the buffer layer, and the interlayer insulating layer. In the LTPO structure, the first gate insulating layer 9 serves as both the gate insulating layer of the LTPS and the buffer layer of the IGZO, while the second gate insulating layer 11 serves as both the gate insulating layer of the IGZO and the interlayer insulating layer of the LTPS.

[0086] In this embodiment, the manufacturing process of the above-mentioned display device includes the following steps:

[0087] Step 1: Deposit the first buffer layer 7 and the metal layer, and pattern the metal layer;

[0088] like Figure 2A As shown, firstly, a substrate is provided as a semiconductor substrate 1. The substrate can be made of a rigid glass or a flexible material such as flexible polyimide (PI) to meet the flexibility requirements of display devices in different application scenarios.

[0089] Then, a first buffer layer 7 is deposited on the semiconductor substrate 1. The first buffer layer 7 can be a single layer or a multi-layer stack of SiOx, SiNx, etc. to effectively block the diffusion of metal ions due to subsequent high-temperature processes, thereby ensuring the performance stability of the display device.

[0090] Then, a metal layer is deposited on the first buffer layer 7.

[0091] Then, the metal layer is patterned as a shielding layer 4 of the LTPS TFT, a first plate 61 of the capacitor 6, and a light shielding layer 5 of the IGZO TFT. The metal layer can be made of a metal material such as molybdenum (Mo) or a doped amorphous silicon (a-Si) material. The shielding layer 4, the light shielding layer 5, and the first plate 61 of the capacitor 6 can be formed in the same layer using the same mask, greatly simplifying the preparation process.

[0092] Step 2: Forming a second buffer layer 8 and a poly-Si layer, and patterning the poly-Si layer;

[0093] As shown in Figure 2B , the second buffer layer 8 is deposited on the shielding layer 4, the first plate 61 of the capacitor 6, and the light shielding layer 5. The structure of the second buffer layer 8 is similar to that of the first buffer layer 7, and can be a single layer or a multi-layer stack of silicon oxide (SiOx) or silicon nitride (SiNx).

[0094] Then, an amorphous silicon layer is deposited on the second buffer layer 8, and then a dehydrogenation process is performed. This is because the subsequent process will undergo a high-temperature stage. If dehydrogenation is not performed, hydrogen explosion may occur due to the mixing of elements, affecting the success rate of preparation and the performance of the display device.

[0095] Then, the amorphous silicon is dissolved using a xenon chloride (XeCl) laser with a wavelength of 308 nm, and then cooled, solidified, and crystallized to form a Poly-Si layer.

[0096] Then, the Poly-Si layer is patterned.

[0097] Step 3: Forming the source and drain regions of the LTPS-TFT;

[0098] As shown in Figure 2C , light doping is performed in the patterned Poly-Si layer, and the doping element is boron ions.

[0099] As shown in Figure 2D , a photoresist 16 is formed on the patterned Poly-Si layer through a photolithography process,

[0100] As shown in Figure 2EAs shown, photoresist 16 is used as a blocking layer, and heavy doping is performed on the patterned Poly-Si layer, with boron ions as the doping element.

[0101] like Figure 2F As shown, the light obstruction is removed.

[0102] Step 4: Form the gate insulating layer and the second metal layer of the LTPS-TFT, and pattern the second metal layer;

[0103] like Figure 2G As shown, the first gate insulating layer 9 is formed by plasma-enhanced chemical vapor deposition (PECVD). The first gate insulating layer 9 can be a SiOx monolayer structure or a SiOx / SiNx multilayer structure.

[0104] Next, a second metal layer is deposited on the first gate insulating layer 9 by physical vapor deposition (PVD). The metal layer can be made of a metal such as molybdenum (Mo).

[0105] Next, the second metal layer is patterned to serve as the gate of the LTPS TFT and the second electrode 62 of the capacitor 6.

[0106] At the same time, such as Figure 2H As shown, the active layer of the LTPS TFT is complex-doped to generate a lightly doped drain (LDD) region 214, thereby reducing leakage current and improving the electrical characteristics of the LTPS TFT. The shielding layer 4 covers more than half the width of the LTPS TFT LDD region. When a constant voltage is applied to the shielding layer 4, one end of the shielding layer 4 extends beyond the source region of the LTPS TFT and is connected to it, while the other end does not extend beyond the drain region of the LTPS TFT, to avoid causing unnecessary kinking effects.

[0107] Step 5: Pattern the active layer of the IGZOTFT;

[0108] like Figure 2I As shown, a first interlayer insulating layer 10 is deposited on the first gate insulating layer 9, the gate of the LTPS TFT, and the second electrode 62 of the capacitor 6. This insulating layer can be a single layer of SiOx or SiNx, or a multilayer stacked structure of SiNx / SiOx.

[0109] An IGZO TFT active layer is deposited and patterned on the first interlayer insulating layer 10, and then the patterned IGZO TFT active layer is heat-treated to make the IGZO more stable and improve its reliability.

[0110] The light-shielding layer 5 covers the active layer of the IGZO TFT and its width exceeds the edge of the active layer of the IGZO TFT by approximately 1.5 μm to 3.0 μm to effectively prevent hydrogen diffusion into the channel of the IGZO TFT.

[0111] Step 6: Pattern the third metal layer;

[0112] like Figure 2J As shown, the second gate insulating layer 11 of the IGZO TFT is formed by PECVD. The second gate insulating layer 11 can be a single SiOx layer or a SiOx / SiNx multilayer structure.

[0113] Next, a third metal layer is deposited on the second gate insulating layer 11 by PVD.

[0114] Next, the third metal layer is patterned to make the exposed portion of the active layer of the IGZO TFT conductive, thereby defining the source and drain regions of the IGZO TFT. This third metal layer serves as the top gate of the IGZO TFT.

[0115] After forming the second gate insulating layer 11 of the IGZO TFT, the active layer of the LTPS TFT needs to be activated and hydrogenated.

[0116] Activation treatment involves placing impurities within the silicon (Si) lattice, which can repair damaged silicon (Si).

[0117] Hydrogenation is performed because vacancies in polysilicon can lead to performance degradation. A thermal treatment process diffuses hydrogen into the interlayer insulating layer of the LTPS TFT, hydrogenating the active layer of the LTPS TFT to fill the vacancies in the polysilicon and stabilize the LTPS active layer.

[0118] Prior to hydrogenation, a hydrogen plasma pretreatment process can be performed to supply hydrogen to the polysilicon layer of the LTPS TFT, enabling more stable filling of vacancies in the polysilicon with hydrogen. This step can be performed after the formation of the LTPS active layer and after the formation of the first gate insulating layer 9 of the LTPS TFT.

[0119] Step 7: Form contact holes;

[0120] like Figure 2K As shown, a second interlayer insulating layer 12 is formed by PECVD, and contact holes are formed in the second interlayer insulating layer 12, including a first contact hole 17a, a second contact hole 17b, a third contact hole 17c, and a fourth contact hole 17d, so that the signal of the gate driving MOS can be transmitted to the data trace, and the data trace is electrically connected to the source and drain regions of the TFT through the contact holes.

[0121] Step 8: Pattern the fourth metal layer;

[0122] like Figure 2LAs shown, a fourth metal layer is formed using physical vapor deposition (PVD) and patterned to form data traces and ELVDD traces (not shown in the figure). The data traces include the first source trace 25 and the first drain trace 24 of the first thin-film transistor 2, and the second source trace 33 and the second drain trace 34 of the second thin-film transistor 3, which electrically connect the data traces to the source and drain regions of the TFT through contact holes.

[0123] The fourth metal layer can be made of Ti / Al / Ti structure, where Al has low resistivity, making it very suitable for large-screen, high-definition displays. The surface of the Al film is uneven and has hillocks. Depositing a high-melting-point metal Ti film can limit the appearance of hillocks and ensure the performance and stability of the display device.

[0124] Step 9: Form the anode contact hole;

[0125] like Figure 2M As shown, a planarization layer 13 is formed on the fourth metal layer. The organic planarization layer can make the ITO of the anode flat, thereby making the OLED flat, while protecting the completed circuit and avoiding the generation of parasitic capacitance.

[0126] After planarization, anode contact holes 19 are formed on the planarization layer 13 to connect the data traces and the OLED anode 20.

[0127] Step 10: Patterning the anode;

[0128] like Figure 2N As shown, a metal layer is deposited and patterned on top of the planarization layer 13 to serve as the OLED anode 20.

[0129] The anode has an ITO / Ag / ITO structure. The bottom ITO layer prevents diffusion caused by the planarization module contacting Ag, which could lead to abnormal resistance. Ag serves as the OLED reflective layer, while the top ITO layer acts as the anode.

[0130] Step 11: Form the pixel definition area;

[0131] like Figure 2O As shown, an organic photoresist layer is coated as a pixel definition layer 14 to define the size and position of the R / G / B light-emitting material pixels, thereby completing the precise layout of the display device pixels.

[0132] Meanwhile, a pixel opening 141 is provided in the pixel definition layer 14 to expose the anode 20.

[0133] Example 2

[0134] SeeFigure 3 In a preferred embodiment of the present application, a hybrid thin film transistor display device is provided, which is different from the embodiment 1 in that the light shielding layer 5 and the gate 22 of the first thin film transistor 2 are located in the same layer. The other structures of the display device are the same as those of the embodiment 1, and thus will not be described here again.

[0135] Since the second plate 62 of the capacitor 6 and the gate 22 of the first thin film transistor 2 are also located in the same layer, i.e., the light shielding layer 5, the second plate 62 of the capacitor 6, the gate 22 of the first thin film transistor 2 and the light shielding layer 5 are located in the same layer, the number of masks used in the process is reduced, and the manufacturing process is simplified.

[0136] Embodiment 3

[0137] Referring to Figure 4 In a preferred embodiment of the present application, a hybrid thin film transistor display device is provided, which is different from the embodiment 1 in that the gate insulating layer is patterned.

[0138] The other structures of the display device are the same as those of the embodiment 1, and thus will not be described here again.

[0139] In the embodiment, the first gate insulating layer 9 is a patterned first gate insulating layer, which includes a first patterned gate insulating layer 9a located below the gate of the LTPS TFT and a second patterned gate insulating layer 9b located below the first plate 61 of the capacitor 6.

[0140] The second gate insulating layer 10 is a patterned second gate insulating layer, i.e., a third patterned gate insulating layer 10a located below the top gate of the IGZO TFT. The first gate insulating layer 9 simultaneously serves as the gate insulating layer of the first thin film transistor 2 and the buffer layer of the second thin film transistor 3; and the second gate insulating layer 11 simultaneously serves as the interlayer insulating layer of the first thin film transistor 2 and the gate insulating layer of the second thin film transistor 3.

[0141] By patterning the first gate insulating layer 9 and the second gate insulating layer 10, the total thickness of the buffer layer of the second thin film transistor 3 and the total thickness of the interlayer insulating layer of the first thin film transistor 2 are simultaneously controlled, so that the electrical properties and reliability of the TFTs are adjusted.

[0142] The advantages or beneficial effects of the above technical solution are as follows: the present application integrates low-temperature polysilicon thin film transistor and oxide semiconductor thin film transistor on the same semiconductor substrate, fully combines the advantages of both, realizes low power consumption while ensuring display effect; at the same time, a shielding layer is arranged below the active layer of the low-temperature polysilicon thin film transistor, the shielding layer at least partially covers the active layer and completely covers the channel region, and a light shielding layer is arranged below the active layer of the second thin film transistor, the light shielding layer at least completely covers the active layer, which can prevent hydrogen from diffusing into the channel of the oxide semiconductor thin film transistor, thereby improving the reliability of the LTPO device and improving the user experience.

[0143] The above is only the preferred embodiment of the present application, and does not limit the implementation and protection scope of the present application. Those skilled in the art should be able to realize that any equivalent replacement and obvious change made by applying the content of the present application and drawings should be included in the protection scope of the present application.

Claims

1. A hybrid thin film transistor display device, characterized by comprising: The plurality of thin film transistors formed on the same semiconductor substrate includes a first thin film transistor and a second thin film transistor, the first thin film transistor is a low-temperature polysilicon thin film transistor, and the second thin film transistor is an oxide semiconductor thin film transistor; Further comprising: A shielding layer is located below the active layer of the first thin film transistor, and in the projection perpendicular to the semiconductor substrate, the shielding layer at least partially covers the active layer of the first thin film transistor, and completely covers the channel region of the first thin film transistor; An optical shielding layer is located below the active layer of the second thin film transistor, and in the projection perpendicular to the semiconductor substrate, the optical shielding layer at least completely covers the active layer of the second thin film transistor.

2. The hybrid thin film transistor display device according to claim 1, wherein Further comprising: A capacitor is formed on the semiconductor substrate, the capacitor includes a first plate and a second plate, the first plate is located in the same layer as the shielding layer, and the second plate is located in the same layer as the gate of the first thin film transistor.

3. The hybrid thin film transistor display device according to claim 1 or 2, wherein The channel region of the first thin film transistor includes a lightly doped drain region between the source region and the drain region; In the projection perpendicular to the semiconductor substrate, the shielding layer covers at least half of the width of the lightly doped drain region, and the edge of the shielding layer does not exceed the edge of the drain region of the first thin film transistor.

4. The hybrid thin film transistor display device according to claim 1 or 2, wherein The optical shielding layer is located in the same layer as one of the shielding layer and the gate of the first thin film transistor.

5. The hybrid thin film transistor display device according to claim 1 or 2, wherein The edge of the optical shielding layer exceeds the edge of the active layer of the second thin film transistor by a predetermined distance.

6. The hybrid thin film transistor display device according to claim 5, wherein The predetermined distance is 1.5 microns to 3.0 microns.

7. The hybrid thin film transistor display device according to claim 1 or 2, wherein Further comprising: A buffer layer is formed on the semiconductor substrate, and the shielding layer is located in the buffer layer; A first gate insulating layer is formed on the buffer layer, and the active layer of the first thin film transistor is located in the first gate insulating layer; A first interlayer insulating layer is formed on the first gate insulating layer, and the gate of the first thin film transistor is located in the first interlayer insulating layer; A second gate insulating layer is formed on the first interlayer insulating layer, and the active layer of the second thin film transistor is located in the second gate insulating layer; A second interlayer insulating layer is formed on the second gate insulating layer, and the top gate of the second thin film transistor is located in the second interlayer insulating layer; A planarization layer is formed on the second interlayer insulating layer, the first source and drain wirings of the first thin film transistor and the second source and drain wirings of the second thin film transistor are located in the planarization layer respectively, and the first source and drain wirings, the second source and drain wirings extend downward from the upper surface of the planarization layer respectively, to contact the source and drain regions of the first thin film transistor, the second thin film transistor respectively, the upper surface of the planarization layer is formed with an anode, and the anode extends downward from the upper surface of the planarization layer to contact the first source wiring of the first thin film transistor; A pixel definition layer is formed on the planarization layer, and a pixel opening is formed in the pixel definition layer to expose the anode.

8. The hybrid thin film transistor display device according to claim 7, wherein The first gate insulating layer is formed on the buffer layer as a whole, and simultaneously as the gate insulating layer of the first thin film transistor and the buffer layer of the second thin film transistor; or The first gate insulating layer is a patterned first gate insulating layer.

9. The hybrid thin film transistor display device according to claim 7, wherein The second gate insulating layer is formed on the first interlayer insulating layer as a whole, and simultaneously as the interlayer insulating layer of the first thin film transistor and the gate insulating layer of the second thin film transistor; or The second gate insulating layer is a patterned second gate insulating layer.

10. The hybrid thin film transistor display device according to claim 7, wherein The buffer layer comprises: A first buffer layer is formed on the semiconductor substrate; A second buffer layer is formed on the first buffer layer, and the shielding layer is located in the second buffer layer.

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