Display panel and driving method thereof

Abstract

The invention discloses a display panel and a driving method thereof, the display panel comprises a plurality of first switches and a plurality of second switches, N columns of pixels are arranged in a first display area, and M columns of pixels are arranged in a second display area; the first scanning line is connected with N columns of pixels in the first display area and M columns of pixels in the second display area, the second scanning line is connected with the N columns of pixels in the first display area, and each first switch is connected with two data lines corresponding to sub-pixels with the same color in the first display area and the second display area; each second switch is connected with a data driving chip and a data line corresponding to a pixel in the first display area; wherein N and M are natural numbers greater than or equal to 2. The two data lines corresponding to the sub-pixels with the same color in the first display area and the second display area respectively receive the same data signal or different data signals to realize display in different display modes by switching on or switching off the first switch and the second switch, so that insufficient charging under a high refresh rate is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and its driving method. Background Technology

[0002] Liquid Crystal Displays (LCDs) have many advantages, such as thinness, energy saving, and no radiation, and have been widely used. In the LCD display industry, in order to reduce costs, a dual rate driver (DRD) driving method can be used. When using the DRD driving method, two sets of scanning signals are used to drive the pixels in the same row. In the first row of pixels, two adjacent signals are used to drive the pixels. Products using the DRD driving method can reduce the number of data lines and the number of COF (Chip On Film), thereby achieving the goal of reducing costs. Therefore, the DRD design is currently being used more and more.

[0003] DRD design addresses adjacent pixels by using different scan lines instead of a single data line, thus halving the number of data lines. However, this also halves the pixel charging time due to the doubled scan lines, leading to insufficient charging at higher refresh rates. As display panels become more high-resolution and high-refresh-rate, display abnormalities caused by insufficient charging become more pronounced. Summary of the Invention

[0004] The purpose of this application is to provide a display panel and its driving method to improve the display abnormalities caused by insufficient charging of the DRD display panel at high refresh rates.

[0005] This application discloses a display panel, which includes a first switching circuit and a second switching circuit. The first switching circuit includes a plurality of first switches, and the second switching circuit includes a plurality of second switches. Along the extension direction of the scan lines, the display area of ​​the display panel is divided into a first display area and a second display area. Each first display area has N columns of sub-pixels, and each second display area has M columns of sub-pixels. Along the extension direction of the data lines, the display panel is divided into multiple rows of sub-pixels. Each row of sub-pixels corresponds to two scan lines, which are a first scan line and a second scan line. The first scan line connects the N columns of pixels in the first display area and the M columns of sub-pixels in the second display area, and the second scan line connects the N columns of sub-pixels in the first display area. Each of the first switches is connected to two data lines corresponding to the same color sub-pixels in the first and second display areas, and each of the second switches is connected to the data driver chip and the data line corresponding to the pixel in the first display area; Wherein, N and M are natural numbers greater than or equal to 2. By controlling the conduction or disconnection of the first switch and the second switch, the two data lines corresponding to the same color sub-pixels in the first display area and the second display area receive the same data signal or different data signals respectively, thereby realizing the display of different display modes.

[0006] Optionally, the display panel includes a refresh rate detection module, which is connected to the first switch circuit and the second switch circuit respectively. The refresh rate detection module detects the refresh rate of the next frame and outputs a first level signal and a second level signal to the first switch or the second switch according to the refresh rate of the next frame. If the refresh rate of the next frame is less than the preset refresh rate, a first level signal is output to the first switch to control the first switch to be turned on, and a second level signal is output to the second switch to control the second switch to be turned off. The two data lines corresponding to the sub-pixels of the same color in the first display area and the second display area receive the same data signal. The first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area. If the refresh rate of the next frame is greater than or equal to the preset refresh rate, a second level signal is output to the first switch to control the first switch to turn off, and a first level signal is output to the second switch to control the second switch to turn on. The two data lines corresponding to the same color sub-pixels in the first display area and the second display area receive different data signals, and the first scan line is turned on to charge the pixels in the first display area and the second display area.

[0007] Optionally, each sub-pixel of the first display area is provided with a first thin-film transistor and a second thin-film transistor. The control terminal of the first thin-film transistor is connected to a third level signal output terminal, the input terminal is connected to a first scan line, and the output terminal is connected to the control terminal of the second thin-film transistor. The control terminal of the second thin-film transistor is connected to a second scan line, the input terminal is connected to a data line, and the output terminal is connected to a pixel electrode. Each pixel of the second display area is provided with a third thin-film transistor. The control terminal of the third thin-film transistor is connected to the first scan line, the input terminal is connected to a data line, and the output terminal is connected to a pixel electrode. The first switch circuit is turned on, and the second switch circuit is turned off. Two data lines corresponding to sub-pixels of the same color in the first and second display areas receive the same data signal. The first scan line activates the third thin-film transistor of the sub-pixel in the second display area to charge the pixel. The third level signal turns off the first thin-film transistor of the sub-pixel in the first display area, and the second scan line activates the second thin-film transistor of the sub-pixel in the first display area to charge the pixel, thus realizing the display of the first display mode. The first switch circuit is turned off, the second switch circuit is turned on, and the two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals. The first scan line is turned on to charge the sub-pixels in the first and second display areas, and the second scan line is turned off to turn off the second thin-film transistors of the sub-pixels in the first display area, thereby realizing the display of the second display mode.

[0008] Optionally, both the first display area and the second display area are provided with multiple [various types of displays]. The control terminals of all the first switches are connected to the same control signal line and receive the same control signal. The control terminals of all the second switches are connected to the same control signal line and receive the same control signal. The values ​​of N and M in each display area are equal, and the values ​​of N and M are multiples of 3. The gate driving units connected to the scan lines of odd-numbered rows are cascaded, and the gate driving units connected to the scan lines of even-numbered rows are cascaded. When the first switching circuit is on, the second switching circuit is off. The two data lines corresponding to the same color sub-pixels in the first and second display areas receive the same data signal. Odd-numbered scan lines are turned on to charge the image in the second display area, and even-numbered scan lines are turned on to charge the pixels in the first display area. When the first switching circuit is off, the second switching circuit is on. The two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals. Odd-numbered scan lines are turned on to charge the sub-pixels in the first and second display areas, and even-numbered scan lines are turned off.

[0009] Optionally, the display panel further includes a third switch circuit, which is disposed on the side of the data line away from the data driver chip. The third switch circuit includes multiple third switches, each of which connects two data lines corresponding to sub-pixels of the same color in the first and second display areas. The two data lines connected by the third switch and the two data lines connected by the first switch are the same two data lines. When the first switch is turned on, the third switch is turned on, and the first switch, the third switch, and the two connected data lines form a loop.

[0010] Optionally, the first switch circuit, the second switch circuit, and the third switch circuit are disposed in the non-display area of ​​the display panel, and the first switch, the second switch, and the third switch are formed on the glass substrate in the same process.

[0011] Optionally, along the extension direction of the data line, each row of subpixels includes multiple subpixels, which are red subpixels, green subpixels and blue subpixels respectively, and in each row of subpixels, the red subpixels, green subpixels and blue subpixels are arranged in sequence; The two scan lines corresponding to each row of sub-pixels are respectively set above and below each row of sub-pixels; or the two scan lines corresponding to each row of sub-pixels are both set above or below each row of sub-pixels.

[0012] Optionally, both the first display area and the second display area are provided with multiple control terminals. The control terminals of all the first switches are connected to the same control signal line and receive the same control signal. The control terminals of all the second switches corresponding to the data lines of each first display area are connected to different control signal lines and receive different control signals.

[0013] This application also discloses a driving method for a display panel, used to drive any of the display panels described above, the driving method comprising the steps of: The first switch circuit is turned on, and the second switch circuit is turned off. Two data lines corresponding to sub-pixels of the same color in both the first and second display areas receive the same data signal. The first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area, thus achieving the display of the first display mode. The first switch circuit is turned off and the second switch circuit is turned on. The two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals. The first scan line is turned on to charge the sub-pixels in the first and second display areas, thereby realizing the display of the second display mode. The refresh rate of the first display mode is different from that of the second display mode.

[0014] Optionally, the display panel includes a refresh rate detection module, which is connected to the first switching circuit and the second switching circuit respectively; The steps for controlling the first switch circuit to be turned on and the second switch circuit to be turned off, so that the two data lines corresponding to the same color sub-pixels in the first and second display areas receive the same data signal, the first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area, thereby realizing the display of the first display mode, include: The refresh rate detection module detects the refresh rate of the next frame and generates a first level signal and a second level signal based on the refresh rate of the next frame. If the refresh rate of the next frame is less than the preset refresh rate, a first level signal is output to the first switch to control the first switch to be turned on, and a second level signal is output to the second switch to control the second switch to be turned off. The two data lines corresponding to the sub-pixels of the same color in the first display area and the second display area receive the same data signal. The first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area. The steps for controlling the first switch circuit to be disconnected and the second switch circuit to be connected, so that the two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals, and the first scan line to be turned on to charge the sub-pixels in the first and second display areas, thereby realizing the display of the second display mode, include: The refresh rate detection module detects the refresh rate of the next frame and generates a first level signal and a second level signal based on the refresh rate of the next frame. If the refresh rate of the next frame is greater than or equal to the preset refresh rate, a second level signal is output to the first switch to control the first switch to turn off, and a first level signal is output to the second switch to control the second switch to turn on. The two data lines corresponding to the same color sub-pixels in the first display area and the second display area receive different data signals, and the first scan line is turned on to charge the sub-pixels in the first display area and the second display area.

[0015] Compared to DRD display panels without switching circuits, this application provides a novel DRD display panel. The display panel includes two switching circuits, each of which includes multiple switches, namely a first switch and a second switch. Each first switch is connected to two data lines corresponding to sub-pixels of the same color in the first and second display areas. Each second switch is connected to a data driver chip and the data lines corresponding to pixels in the first display area. At high refresh rates, by controlling the first switch to turn off and the second switch to turn on, the two data lines corresponding to sub-pixels of the same color in the first and second display areas receive different data signals to achieve display, thus improving the problem of insufficient charging in DRD mode. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without any creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of the display panel according to the first embodiment of this application; Figure 2 This is a schematic diagram of the display panel structure according to the second embodiment of this application; Figure 3 This is a schematic diagram of the cascaded gate driving circuit structure of the display panel according to the second embodiment of this application; Figure 4 This is a schematic diagram of the clock signal waveform according to the third embodiment of this application; Figure 5This is a pixel structure diagram of the first display area of ​​the display panel according to the third embodiment of this application; Figure 6 This is a pixel structure diagram of the second display area of ​​the display panel according to the third embodiment of this application; Figure 7 This is a schematic diagram of the structure of the display panel according to the fourth embodiment of this application; Figure 8a This is a schematic diagram of the structure of the display panel according to the fifth embodiment of this application; Figure 8b This is a color diagram of the structure of the display panel according to the fifth embodiment of this application; Figure 9a This is a color diagram of the structure of another display panel according to the fifth embodiment of this application; Figure 9b This is a schematic diagram of the structure of another display panel according to the fifth embodiment of this application; Figure 10 This is a schematic flowchart of the driving method for the display panel according to the sixth embodiment of this application; Figure 11 This is a schematic flowchart of the driving method for the display panel according to the seventh embodiment of this application.

[0017] Among them, 100 is the display panel; 101 is the display area; 1011 is the first display area; 1012 is the second display area; 102 is the non-display area; 110 is the sub-pixel; 120 is the scan line; 130 is the data line; 140 is the first switch circuit; 150 is the second switch circuit; 160 is the refresh rate detection module; 170 is the control signal line; 180 is the gate driving unit; 190 is the third switch circuit; 200 is the data driving chip; G1 is the first scan line; G2 is the second scan line; S1 is the first switch; S2 is the second switch; S3 is the third switch; T1 is the first thin-film transistor; T2 is the second thin-film transistor; T3 is the third thin-film transistor. Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0020] like Figure 1As shown, as a first embodiment of this application, a display panel 100 is disclosed. The display panel 100 includes a first switching circuit 140 and a second switching circuit 150. The first switching circuit 140 includes a plurality of first switches S1, and the second switching circuit 150 includes a plurality of second switches S2. Along the extension direction of the scan line 120, the display area 101 of the display panel 100 is divided into a first display area 1011 and a second display area 1012. Generally, m data lines are provided in the display area 101, and N columns of sub-pixels 110 are provided in each first display area 1011. The second display area 1012 has M columns of sub-pixels 110. Generally, both the first display area 1011 and the second display area 1012 have multiple sub-pixels 110, which are spaced apart. Both the first display area 1011 and the second display area 1012 have 3 data lines. Counting starts from the first data line D1. The three data lines corresponding to the first display area 1011 are D1, D2, and D3; the three data lines corresponding to the second display area 1012 are D4, D5, and D6; and the three data lines corresponding to the last first display area 1011 are Dm-5, Dm-4, and Dm-3. The last second display area 101... The three data lines corresponding to 2 are Dm-2, Dm-1, and Dm; along the extension direction of the data line 130, the display panel 100 is divided into multiple rows of sub-pixels 110, each row of sub-pixels 110 is provided with two scan lines 120, the two scan lines 120 are the first scan line G1 and the second scan line G2, the first scan line G1 connects the N columns of pixels in the first display area 1011 and the M columns of sub-pixels 110 in the second display area 1012, the second scan line G2 connects the N columns of sub-pixels 110 in the first display area 1011; each of the first switches S1 is connected to the first display... Two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 are connected to the data driver chip 200 and the data lines 130 corresponding to the pixels in the first display area 1011, respectively, by controlling the first switch S1 and the second switch S2 to make the two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive the same data signal or different data signals respectively to achieve different display modes.

[0021] In this embodiment, the display panel 100 is provided with a first switching circuit 140 and a second switching circuit 150. The first switching circuit 140 includes a plurality of first switches S1, and the second switching circuit 150 includes a plurality of second switches S2. By controlling the first switching circuit 140 to be turned on and the second switching circuit 150 to be turned off, the two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive the same data signal. The first scan line G1 is turned on to charge the sub-pixels 110 in the second display area 1012, and the second scan line G2 is turned on to charge the sub-pixels 110 in the first display area 1011, thereby realizing the display of the first display mode. The display mode is DRD mode. Under high refresh rate conditions, the first switch circuit 140 is turned off and the second switch circuit 150 is turned on. The two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive different data signals. The first scan line G1 is turned on to charge the sub-pixels 110 in the first display area 1011 and the second display area 1012, thereby realizing the display of the second display mode, namely 1G1D mode, to avoid uneven charging of the DRD display panel 100. The solution of this application can be switched to DRD mode, and DLG mode (dual grid line drive mode) can be switched between 1G1D and DRD modes.

[0022] The second embodiment of this application is a further refinement of the first embodiment described above, as referred to in the following text. Figure 2 and Figure 3As shown, the display panel 100 includes a refresh rate detection module 160, which is connected to the first switch circuit 140 and the second switch circuit 150 respectively. The refresh rate detection module 160 detects the refresh rate of the next frame and outputs a first level signal and a second level signal to the first switch S1 or the second switch S2 according to the refresh rate of the next frame. The first level signal is generally a high level signal (DG), and the second level signal is generally a low level signal (DL). Before switching modes, the refresh rate of the next frame is detected and compared with a preset refresh rate. If the refresh rate of the next frame is less than the preset refresh rate, the first level signal is output to the first switch S1 to turn on the first switch S1, and the second level signal is output to the second switch S2 to turn on the second switch S2. When the display is off, the two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive the same data signal. The first scan line G1 is turned on to charge the sub-pixels 110 in the second display area 1012, and the second scan line G2 is turned on to charge the sub-pixels 110 in the first display area 1011. If the refresh rate of the next frame is greater than or equal to the preset refresh rate, a second level signal is output to the first switch S1 to control the first switch S1 to turn off, and a first level signal is output to the second switch S2 to control the second switch S2 to turn on. The two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive different data signals, and the first scan line G1 is turned on to charge the pixels in the first display area 1011 and the second display area 1012.

[0023] Before switching modes, the refresh rate of the next frame is detected and compared with the preset refresh rate. If the refresh rate of the next frame is greater than or equal to the preset refresh rate, the next frame is determined to be a high refresh rate frame. When the DRD display panel is at a high refresh rate of 100%, there is insufficient charging. Therefore, the 1G1D display mode is automatically switched to solve the problem of insufficient charging. When the refresh rate is low, that is, if the refresh rate of the next frame is less than the preset refresh rate, the DRD display mode is used. This application can freely switch between DRD and 1G1D, displaying multiple modes on one screen, thereby improving product competitiveness.

[0024] Generally, the preset refresh rate is between 60-90Hz. For example, when the preset refresh rate is 60Hz, a refresh rate greater than or equal to 60Hz is considered high. Similarly, when the preset refresh rate is 90Hz, a refresh rate greater than or equal to 90Hz is considered high. The refresh rate can be adjusted as needed. Furthermore, the refresh rate is not fixed for the same display panel. For instance, within the first year or two after the display panel is manufactured, a refresh rate greater than the preset 90Hz is selected. As the years of use increase, the preset refresh rate gradually decreases. The first display area 1011 and the second display area 1012 each have multiple first switches S1. All first switches S1 are connected to the same control signal line 170 and receive the same control signal. All second switches S2 are also connected to the same control signal line 170 and receive the same control signal. The values ​​of N and M in each display area 101 are equal and are multiples of 3. Gate driving units 180 connected to the scan lines 120 in odd-numbered rows are cascaded, and gate driving units 180 connected to the scan lines 120 in even-numbered rows are cascaded. Taking N and M equal to 3 as an example, each of the first display area 1011 and the second display area 1012 has 3 columns of pixels. The first switch circuit 140 has 3 first switches S1. The first first switch S1 is connected to the data line 130 corresponding to the first column of sub-pixels 110 in the first display area 1011 and the data line 130 corresponding to the first column of sub-pixels 110 in the second display area 1012. A data line 130 corresponding to a column of sub-pixels 110 is connected to a second first switch S1, which is connected to the data line 130 corresponding to the second column of sub-pixels 110 in the first display area 1011 and the data line 130 corresponding to the second column of sub-pixels 110 in the second display area 1012. Multiple first display areas 1011 and second display areas 1012 are provided and spaced apart. Each first display area 1011 and each second display area 1012 has three data lines. Starting from the first data line D1, the three data lines corresponding to the first first display area 1011 are D1, D2, and D3; the three data lines corresponding to the first second display area 1012 are D4, D5, and D6; the three data lines corresponding to the last first display area 1011 are Dm-5, Dm-4, and Dm-3; and the three data lines corresponding to the last second display area 1012 are Dm-2, Dm-1, and Dm.

[0025] When the first switching circuit 140 is turned on, the second switching circuit 150 is turned off. The two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive the same data signal. The odd-numbered row scan lines 120 are turned on to charge the image in the second display area 1012, and the even-numbered row scan lines 120 are turned on to charge the pixels in the first display area 1011. When the first switching circuit 140 is turned off, the second switching circuit 150 is turned on. The two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive different data signals. The odd-numbered row scan lines 120 are turned on to charge the sub-pixels 110 in the first display area 1011 and the second display area 1012, and the even-numbered row scan lines 120 are turned off.

[0026] Furthermore, the gate drive unit 180 (GOA) connected to scan line 120 is designed to be cascaded with odd numbers and even numbers. The output of the first gate unit serves as the input of the third gate drive unit, and the output of the second gate drive unit serves as the input of the fourth gate drive unit. The first and second gate drive units simultaneously receive the frame start signal STV. In this way, the odd-numbered scan lines 120 and even-numbered scan lines 120 can be controlled and operate independently. Timing can be used to control the switching of even-numbered lines. When an even-numbered line needs to be turned on, the CK of the even-numbered line is given a corresponding high-level timing sequence. When an even-numbered line needs to be turned off, the CK of the even-numbered line is not given a timing sequence or is given a low-level timing sequence. Adjusting the phase of the CK of the odd-numbered line does not affect the output of the odd-numbered line while the even-numbered line is in a closed state.

[0027] Generally, there are multiple first display areas 1011 and second display areas 1012. The control terminals of all first switches S1 are connected to the same control signal line 170 and receive the same control signal, such as simultaneously receiving a first level signal or a second level signal. The control terminals of all second switches S2 corresponding to the data lines 130 of each first display area 1011 are connected to different control signal lines 170 and receive different control signals, or connected to the same control signal line 170 and receive the same control signal. The settings can be selected as needed.

[0028] As a third embodiment of this application, it further limits and improves upon any of the above embodiments, see reference. Figures 2 to 6 As shown, each sub-pixel 110 of the first display area 1011 is provided with a first thin-film transistor T1 and a second thin-film transistor T2, as shown in the figure. Figure 5As shown, the control terminal of the first thin-film transistor T1 is connected to the third-level signal output terminal. The third-level signal output terminal and the control terminal of the first switch receive the same level signal (DG). The input terminal is connected to the first scan line G1, and the output terminal is connected to the control terminal of the second thin-film transistor T2. The control terminal of the second thin-film transistor T2 is connected to the second scan line G2. The input terminal is connected to the data line 130, and the output terminal is connected to the pixel electrode. Each pixel of the second display area 1012 is provided with a corresponding third thin-film transistor T3, such as... Figure 6 As shown, the control terminal of the third thin-film transistor T3 is connected to the first scan line G1, the input terminal is connected to the data line 130, and the output terminal is connected to the pixel electrode.

[0029] Generally, when displaying a low refresh rate screen, the first switch circuit 140 is turned on and the second switch circuit 150 is turned off. The two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive the same data signal. The first scan line G1 turns on the third thin-film transistor T3 of the sub-pixel 110 in the second display area 1012 to charge the pixel in the second display area 1012. The third level signal turns off the first thin-film transistor T1 of the sub-pixel 110 in the first display area 1011, and the second scan line G2 turns on the second thin-film transistor T2 of the sub-pixel 110 in the first display area 1011 to charge the pixel in the first display area 1011, thus realizing the first display mode, i.e., DRD display. In high refresh rate display mode, the first switch circuit 140 is turned off and the second switch circuit 150 is turned on. The two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive different data signals. The first scan line G1 is turned on to charge the sub-pixels 110 in the first display area 1011 and the second display area 1012. The second scan line G2 turns off the second thin film transistor T2 of the sub-pixels 110 in the first display area 1011, realizing the display of the second display mode, namely the 1G1D display mode. DRD and 1G1D can be switched freely, and multiple modes can be displayed on one screen. This can avoid the situation where the sub-pixels 110 are not charged enough when using the DRD mode at high refresh rates.

[0030] like Figure 7 As shown, this fourth embodiment of the present application is a further improvement on any of the above embodiments. (Refer to...) Figures 5 to 7As shown, the display panel 100 also includes a third switch circuit 190. The third switch circuit 190 is disposed on the side of the data line 130 away from the data driver chip 200. The third switch circuit 190 includes a plurality of third switches S3. Each third switch S3 is connected to two data lines 130 corresponding to sub-pixels 110 of the same color in the first display area 1011 and the second display area 1012. The two data lines 130 connected by the third switch S3 are the same two data lines 130 as the two data lines 130 connected by the first switch S1. When the first switch S1 is turned on, the third switch S3 is turned on. The first switch S1, the third switch S3 and the two connected data lines 130 form a loop.

[0031] The first switch circuit 140, the second switch circuit 150 and the third switch circuit 190 are disposed in the non-display area 102 of the display panel 100 to avoid affecting the aperture ratio of the display panel 100. The first switch S1, the second switch S2 and the third switch S3 are formed on the glass substrate in the same process to avoid using different types of switches, which would complicate the process and increase costs.

[0032] This embodiment adds a third switch circuit 190. Taking the third embodiment as an example, when displaying a screen at a low refresh rate, the first switch circuit 140 and the third switch circuit 190 are turned on, and the second switch circuit 150 is turned off. The two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive the same data signal. The first switch S1, the third switch S3, and the two data lines 130 connected to the switch S1 form a loop to avoid different voltages on the two data lines 130, which would lead to uneven charging. At the same time, the first scan line G1 turns on the first thin film transistor T1 of the sub-pixel 110 in the second display area 1012 to charge the pixel in the second display area 1012. The third level signal turns off the first thin film transistor T1 of the sub-pixel 110 in the first display area 1011, and the second scan line G2 turns on the second thin film transistor T2 of the sub-pixel 110 in the first display area 1011 to charge the pixel in the first display area 1011, thus realizing the display of the first display mode, namely the DRD display mode, and avoiding insufficient charging.

[0033] As a fifth embodiment of this application, a display panel 100 is disclosed, which is a further refinement of any of the above embodiments. It mainly defines the arrangement of sub-pixels 110 and the setting of scan lines 120. Along the extension direction of the data line 130, each row of sub-pixels 110 includes multiple sub-pixels 110, which are red sub-pixels 110, green sub-pixels 110, and blue sub-pixels 110, respectively. In each row of sub-pixels 110, red sub-pixels R, green sub-pixels G, and blue sub-pixels B are arranged sequentially. The two scan lines 120 corresponding to each row of sub-pixels 110 are respectively set above and below each row of sub-pixels 110, such as... Figure 8a and Figure 8b As shown; or, the two scan lines 120 corresponding to each row of sub-pixels 110 are both set below each row of sub-pixels 110, as shown. Figure 9a and Figure 9b As shown, or both scan lines 120 corresponding to each row of sub-pixels 110 can be set below each row of sub-pixels 110.

[0034] In this embodiment, in each row of sub-pixels 110, the red sub-pixels, green sub-pixels, and blue sub-pixels are arranged sequentially, such as RGBRGB. For details, please refer to [reference needed]. Figure 8a and Figure 8b As shown, taking N and M equal to 6 as an example, the first display area 1011 and the second display area 1012 are each provided with 6 columns of pixels. The first switch circuit 140 is provided with 6 first switches S1. The first first switch S1 is connected to the data line 130 corresponding to the first column of red sub-pixels 110 in the first display area 1011 and the data line 130 corresponding to the first column of red sub-pixels 110 in the second display area 1012. The second first switch S1 is connected to the data line 130 corresponding to the first column of green sub-pixels 110 in the first display area 1011 and the data line 130 corresponding to the first column of green sub-pixels 110 in the second display area 1012.

[0035] When displaying a high refresh rate screen, the control terminals of the first switch circuit 140 and the third switch circuit 190 receive the first level signal DL, controlling the first switch S1 and the third switch S3 to turn off. The second switch circuit 150 receives the second level signal, controlling the second switch S2 to turn on. The two data lines 130 corresponding to the same color sub-pixels 110 in the first display area 1011 and the second display area 1012 receive different data signals. At the same time, the first scan line G1 turns on the third thin-film transistor T3 of the sub-pixel 110 in the second display area 1012 to charge the pixel in the second display area 1012, and the second scan line G2 turns on the first thin-film transistor T1 and the second thin-film transistor T2 of the sub-pixel 110 in the first display area 1011 to charge the pixel in the first display area 1011, realizing the display of the second display mode, namely the 1G1D display mode, and avoiding insufficient charging. When displaying a low refresh rate screen, the first switch circuit 140 and the third switch circuit 190 are connected... The control signal line 170 receives the second level signal DG and is turned on. The control signal line 170 of the second switch circuit 150 receives the first level signal DL and is turned off. The two data lines 130 corresponding to the sub-pixels 110 of the same color in the first display area 1011 and the second display area 1012 receive the same data signal. The first switch S1, the third switch S3 and the two connected data lines 130 form a loop to avoid uneven charging caused by different voltages on the two data lines 130. At the same time, the first scan line G1 turns on the third thin film transistor T3 of the sub-pixel 110 in the second display area 1012 to charge the pixel in the second display area 1012. The third level signal turns off the first thin film transistor T1 of the sub-pixel 110 in the first display area 1011. The second scan line G2 turns on the second thin film transistor T2 of the sub-pixel 110 in the first display area 1011 to charge the pixel in the first display area 1011, thus realizing the display of the first display mode, namely the DRD display mode.

[0036] like Figure 10 As shown, as the sixth embodiment of this application, a driving method for a display panel is disclosed. The driving method is used to drive the display panel as described in any of the above embodiments, and the driving method includes the following steps: S1: Controls the first switching circuit to be turned on and the second switching circuit to be turned off. The two data lines corresponding to the same color sub-pixels in the first and second display areas receive the same data signal. The first scan line opens to charge the sub-pixels in the second display area, and the second scan line opens to charge the sub-pixels in the first display area, thus realizing the display of the first display mode; and S2: The first switch circuit is turned off and the second switch circuit is turned on. The two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals. The first scan line is turned on to charge the sub-pixels in the first and second display areas, thereby realizing the display of the second display mode.

[0037] Because the charging time of DRD display panels is relatively short at high refresh rates, two switching circuits are set up. By controlling the conduction or disconnection of the first and second switches, the two data lines corresponding to the same color sub-pixels in the first and second display areas receive the same or different data signals respectively, so as to realize different display modes. When the DRD display panel has a high refresh rate, it automatically switches to the 1G1D display mode to solve the problem of insufficient charging. When the refresh rate is low, that is, if the refresh rate of the next frame is less than the preset refresh rate, the DRD display mode is used, so that multiple modes can be displayed on one screen.

[0038] Further reference Figure 11 As shown, the sixth embodiment of this application is a further refinement of the fifth embodiment described above. (Refer to...) Figures 2 to 11 As shown, the display panel includes a refresh rate detection module, which is connected to the first switching circuit and the second switching circuit respectively; Step S1 includes: S11: The refresh rate detection module detects the refresh rate of the next frame and generates a first level signal and a second level signal based on the refresh rate of the next frame; and S12: If the refresh rate of the next frame is less than the preset refresh rate, output a first level signal to the first switch to control the first switch to be turned on, output a second level signal to the second switch to control the second switch to be turned off, the two data lines corresponding to the sub-pixels of the same color in the first display area and the second display area receive the same data signal, the first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area. Step S2 includes: S21: The refresh rate detection module detects the refresh rate of the next frame and generates a first level signal and a second level signal based on the refresh rate of the next frame; and S22: If the refresh rate of the next frame is greater than or equal to the preset refresh rate, then output a second level signal to the first switch to control the first switch to turn off, output a first level signal to the second switch to control the second switch to turn on, and the two data lines corresponding to the same color sub-pixels in the first display area and the second display area receive different data signals. The first scan line is turned on to charge the sub-pixels in the first display area and the second display area.

[0039] In this embodiment, the refresh rate detection module generates a first level signal and a second level signal based on the comparison result between the refresh rate of the next frame and the preset refresh rate. Under different comparison results, it outputs different signals to the corresponding switches, which can change the refresh rate and realize the free switching between DRD mode and 1G1D mode, thereby improving the problem of insufficient charging of DRD display panel at high refresh rates.

[0040] Furthermore, if a third switch circuit is added, when displaying in DRD mode, at the same time the first switch is turned on, the corresponding level signal will be input to the control terminal of the third switch to control the third switch to turn on, so that the first switch, the third switch and the two connected data lines form a loop.

[0041] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0042] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0043] The technical solution of this application can be widely used in driving circuits of various display panels, such as driving circuits of TN (Twisted Nematic) display panels, driving circuits of IPS (In-Plane Switching) display panels, driving circuits of VA (Vertical Alignment) display panels, and driving circuits of MVA (Multi-Domain Vertical Alignment) display panels. Of course, it can also be used for driving circuits of other types of display panels, such as driving circuits of OLED (Organic Light-Emitting Diode) display panels, and the above solution is applicable to all of them.

[0044] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A display panel, characterized in that, The display panel includes a first switch circuit and a second switch circuit. The first switch circuit includes a plurality of first switches, and the second switch circuit includes a plurality of second switches. Along the extension direction of the scan lines, the display area of ​​the display panel is divided into a first display area and a second display area. Each first display area has N columns of sub-pixels, and each second display area has M columns of sub-pixels. Along the extension direction of the data lines, the display panel is divided into multiple rows of sub-pixels. Each row of sub-pixels corresponds to two scan lines, which are a first scan line and a second scan line. The first scan line connects the N columns of pixels in the first display area and the M columns of sub-pixels in the second display area, and the second scan line connects the N columns of sub-pixels in the first display area. Each of the first switches is connected to two data lines corresponding to the same color sub-pixels in the first and second display areas, and each of the second switches is connected to the data driver chip and the data line corresponding to the pixel in the first display area; Wherein, N and M are natural numbers greater than or equal to 2. By controlling the conduction or disconnection of the first switch and the second switch, the two data lines corresponding to the same color sub-pixels in the first display area and the second display area receive the same data signal or different data signals respectively, thereby realizing the display of different display modes.

2. The display panel as described in claim 1, characterized in that, The display panel includes a refresh rate detection module, which is connected to the first switch circuit and the second switch circuit respectively. The refresh rate detection module detects the refresh rate of the next frame and outputs a first level signal and a second level signal to the first switch or the second switch according to the refresh rate of the next frame. If the refresh rate of the next frame is less than the preset refresh rate, a first level signal is output to the first switch to control the first switch to be turned on, and a second level signal is output to the second switch to control the second switch to be turned off. The two data lines corresponding to the sub-pixels of the same color in the first display area and the second display area receive the same data signal. The first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area. If the refresh rate of the next frame is greater than or equal to the preset refresh rate, a second level signal is output to the first switch to control the first switch to turn off, and a first level signal is output to the second switch to control the second switch to turn on. The two data lines corresponding to the same color sub-pixels in the first display area and the second display area receive different data signals, and the first scan line is turned on to charge the pixels in the first display area and the second display area.

3. The display panel as described in claim 1, characterized in that, Each sub-pixel in the first display area is provided with a first thin-film transistor and a second thin-film transistor. The control terminal of the first thin-film transistor is connected to a third level signal output terminal, the input terminal is connected to a first scan line, and the output terminal is connected to the control terminal of the second thin-film transistor. The control terminal of the second thin-film transistor is connected to a second scan line, the input terminal is connected to a data line, and the output terminal is connected to a pixel electrode. Each pixel in the second display area is provided with a third thin-film transistor. The control terminal of the third thin-film transistor is connected to the first scan line, the input terminal is connected to a data line, and the output terminal is connected to a pixel electrode. The first switch circuit is turned on and the second switch circuit is turned off. The two data lines corresponding to the sub-pixels of the same color in the first and second display areas receive the same data signal. The first scan line turns on the third thin-film transistor of the sub-pixel in the second display area to charge the pixel in the second display area. The third level signal turns off the first thin-film transistor of the sub-pixel in the first display area. The second scan line turns on the second thin-film transistor of the sub-pixel in the first display area to charge the pixel in the first display area, thereby realizing the display of the first display mode. as well as The first switch circuit is turned off, the second switch circuit is turned on, and the two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals. The first scan line is turned on to charge the sub-pixels in the first and second display areas, and the second scan line is turned off to turn off the second thin-film transistors of the sub-pixels in the first display area, thereby realizing the display of the second display mode.

4. The display panel as described in claim 1, characterized in that, Both the first display area and the second display area are provided with multiple [various types of displays]. The control terminals of all the first switches are connected to the same control signal line and receive the same control signal. The control terminals of all the second switches are connected to the same control signal line and receive the same control signal. The values ​​of N and M in each display area are equal, and the values ​​of N and M are multiples of 3. The gate driving units connected to the scan lines of odd-numbered rows are cascaded, and the gate driving units connected to the scan lines of even-numbered rows are cascaded. When the first switching circuit is on, the second switching circuit is off. The two data lines corresponding to the same color sub-pixels in the first and second display areas receive the same data signal. Odd-numbered scan lines are turned on to charge the image in the second display area, and even-numbered scan lines are turned on to charge the pixels in the first display area. When the first switching circuit is off, the second switching circuit is on. The two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals. Odd-numbered scan lines are turned on to charge the sub-pixels in the first and second display areas, and even-numbered scan lines are turned off.

5. The display panel as described in any one of claims 1-4, characterized in that, The display panel further includes a third switch circuit, which is located on the side of the data line away from the data driver chip. The third switch circuit includes multiple third switches, each of which connects two data lines corresponding to sub-pixels of the same color in the first and second display areas. The two data lines connected by the third switch and the two data lines connected by the first switch are the same two data lines. When the first switch is turned on, the third switch is turned on, and the first switch, the third switch, and the two connected data lines form a loop.

6. The display panel as described in claim 5, characterized in that, The first switch circuit, the second switch circuit, and the third switch circuit are disposed in the non-display area of ​​the display panel, and the first switch, the second switch, and the third switch are formed on the glass substrate in the same process.

7. The display panel as described in claim 5, characterized in that, Along the extension direction of the data line, each row of sub-pixels includes multiple sub-pixels, which are red sub-pixels, green sub-pixels and blue sub-pixels respectively. In each row of sub-pixels, the red sub-pixels, green sub-pixels and blue sub-pixels are arranged in sequence. The two scan lines corresponding to each row of sub-pixels are respectively set above and below each row of sub-pixels; or the two scan lines corresponding to each row of sub-pixels are both set above or below each row of sub-pixels.

8. The display panel as described in claim 1, characterized in that, Both the first display area and the second display area are provided with multiple control terminals. The control terminals of all the first switches are connected to the same control signal line and receive the same control signal. The control terminals of all the second switches corresponding to the data lines of each first display area are connected to different control signal lines and receive different control signals.

9. A driving method for a display panel, used to drive the display panel as described in any one of claims 1-8, characterized in that, The driving method includes the following steps: The first switch circuit is turned on, and the second switch circuit is turned off. Two data lines corresponding to sub-pixels of the same color in both the first and second display areas receive the same data signal. The first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area, thus achieving the display of the first display mode. The first switch circuit is turned off and the second switch circuit is turned on. The two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals. The first scan line is turned on to charge the sub-pixels in the first and second display areas, thereby realizing the display of the second display mode.

10. The driving method for a display panel as described in claim 9, characterized in that, The display panel includes a refresh rate detection module, which is connected to the first switching circuit and the second switching circuit respectively. The steps for controlling the first switch circuit to be turned on and the second switch circuit to be turned off, so that the two data lines corresponding to the same color sub-pixels in the first and second display areas receive the same data signal, the first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area, thereby realizing the display of the first display mode, include: The refresh rate detection module detects the refresh rate of the next frame and generates a first level signal and a second level signal based on the refresh rate of the next frame. If the refresh rate of the next frame is less than the preset refresh rate, a first level signal is output to the first switch to control the first switch to be turned on, and a second level signal is output to the second switch to control the second switch to be turned off. The two data lines corresponding to the sub-pixels of the same color in the first display area and the second display area receive the same data signal. The first scan line is turned on to charge the sub-pixels in the second display area, and the second scan line is turned on to charge the sub-pixels in the first display area. The steps for controlling the first switch circuit to be disconnected and the second switch circuit to be connected, so that the two data lines corresponding to the same color sub-pixels in the first and second display areas receive different data signals, and the first scan line to be turned on to charge the sub-pixels in the first and second display areas, thereby realizing the display of the second display mode, include: The refresh rate detection module detects the refresh rate of the next frame and generates a first level signal and a second level signal based on the refresh rate of the next frame. If the refresh rate of the next frame is greater than or equal to the preset refresh rate, a second level signal is output to the first switch to control the first switch to turn off, and a first level signal is output to the second switch to control the second switch to turn on. The two data lines corresponding to the same color sub-pixels in the first display area and the second display area receive different data signals, and the first scan line is turned on to charge the sub-pixels in the first display area and the second display area.

Images