Array substrate and electronic paper display device

Abstract

The application provides an array substrate and an electronic paper display device, and relates to the field of display. The array substrate comprises a substrate, a plurality of scan lines and a plurality of data lines are arranged on the substrate, the plurality of scan lines and the plurality of data lines cross and form a plurality of pixel units, and the pixel unit comprises a pixel electrode and a first thin film transistor. The pixel electrode is arranged opposite to the substrate. The first thin film transistor comprises a gate, a semiconductor layer, a source and a drain. The gate is connected with the scan line, the source is connected with the data line, the drain is electrically connected with the source, the gate comprises a top gate, a bottom gate and a connecting layer, the top gate and the bottom gate are arranged on opposite sides of the semiconductor layer in the thickness direction of the array substrate, and the top gate and the bottom gate are electrically connected through the connecting layer. The application can effectively improve the working stability of the electronic paper display device.

Description

Technical Field

[0001] This application relates to the field of display, and more particularly to an array substrate and an electronic paper display device. Background Technology

[0002] Electronic paper is a type of display that forms pixel patterns by coating electronic ink onto a plastic film and attaching the film to an array substrate with thin-film transistor circuitry, controlled by a driver IC.

[0003] In commonly used electronic paper products, such as MED displays based on Micro Electric-Chamber Display technology and EPD displays based on Electrophoretic Display technology, thin-film transistors are usually fabricated using IGZO or a-Si processes. In existing technologies, thin-film transistors generally adopt a single-gate or dual-gate series design (i.e., two gates connected in the same metal layer). This structure has insufficient stability, and thin-film transistors are prone to malfunctions. When a thin-film transistor malfunctions, its corresponding pixel unit cannot work properly, resulting in pixel defects in the displayed image and affecting the display effect.

[0004] Therefore, improving the operational stability of electronic paper display devices has become an urgent problem to be solved. Utility Model Content

[0005] The main objective of this application is to provide an array substrate and an electronic paper display device that can effectively improve the operational stability of the electronic paper display device.

[0006] In a first aspect, this application provides an array substrate, including a substrate, on which multiple scan lines and data lines are disposed, the multiple scan lines and data lines intersecting to form multiple pixel units, the pixel units including:

[0007] Pixel electrodes are disposed opposite to the substrate.

[0008] A first thin-film transistor includes a gate, a semiconductor layer, a source, and a drain. The gate is connected to the scan line, the source is connected to the data line, and the drain is electrically connected to the source. The gate includes a top gate, a bottom gate, and a connection layer. In the thickness direction of the array substrate, the top gate and the bottom gate are disposed on opposite sides of the semiconductor layer, and the top gate and the bottom gate are electrically connected through the connection layer.

[0009] Secondly, this application provides an electronic paper display device, including a top substrate, an electrophoretic layer, and an array substrate as described in any embodiment of this application.

[0010] This application provides an array substrate and an electronic paper display device. By applying an enable voltage to a scan line connected to the gate of a first thin-film transistor (TFT), a conduction voltage is formed between the gate and source of the TFT in the pixel unit, thereby switching the TFT from an off state to a conduction state. Since the top and bottom gates of the TFT in the pixel unit are electrically connected through a connection layer, when the bottom gate malfunctions, such as a broken wire, the enable voltage received by the bottom gate can be transmitted to the top gate through the connection layer, forming a conduction voltage between the top gate and the source, thus enabling the TFT to remain in a conduction state. The first thin-film transistor maintains a conducting state, ensuring the normal operation of the pixel unit. When the top gate malfunctions, such as a broken wire, the bottom gate receives an on-state voltage, forming a conduction voltage between the bottom gate and the source, thus ensuring the pixel unit can operate normally. Compared to the existing thin-film transistor design using a single-gate or dual-gate series connection, in this application, when either the bottom gate or the top gate malfunctions, the conductive channel can be completed by driving another backup gate, improving the working stability of the thin-film transistor and thus effectively enhancing the working stability of the electronic paper display device. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A plan view of an array substrate provided in an embodiment of this application;

[0013] Figure 2 An embodiment provided in this application Figure 1 Cross-sectional view in direction B;

[0014] Figure 3 An embodiment provided in this application Figure 1 Cross-sectional view in direction A;

[0015] Figure 4 A plan view of another array substrate provided in an embodiment of this application;

[0016] Figure 5 An embodiment provided in this application Figure 4 Cross-sectional view in direction C;

[0017] Figure 6 This is a schematic diagram of the display area of ​​an electronic paper display device provided in an embodiment of this application;

[0018] Figure 7 This is a schematic diagram of the structure of an electronic paper display device provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0021] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should be understood that, in order to clearly describe the technical solutions of the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. For example, the first callback function and the second callback function are only used to distinguish different callback functions and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" do not necessarily mean they must be different.

[0023] It should also be understood that the term "and / or" as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] In commonly used electronic paper products, such as MED displays based on Micro Electric-Chamber Display technology and EPD displays based on Electrophoretic Display technology, thin-film transistors are usually fabricated using IGZO or a-Si processes. In existing technologies, thin-film transistors generally adopt a single-gate or dual-gate series design (i.e., two gates connected in the same metal layer). This structure has insufficient stability, and thin-film transistors are prone to malfunctions. When a thin-film transistor malfunctions, its corresponding pixel unit cannot work properly, resulting in pixel defects in the displayed image and affecting the display effect.

[0026] To address the aforementioned issues, this application provides an array substrate and an electronic paper display device, which can effectively improve the operational stability of the electronic paper display device.

[0027] Firstly, referring to Figures 1-6 This application provides an array substrate 1, including a substrate 100. Multiple scan lines 200 and data lines 300 are disposed on the substrate 100. The multiple scan lines 200 and data lines 300 intersect and form multiple pixel units. Each pixel unit includes a pixel electrode 11 and a first thin-film transistor 400. The pixel electrode 11 is disposed opposite to the substrate 100. The first thin-film transistor 400 includes a gate 12, a semiconductor layer 13, a source 14, and a drain 15. The gate 12 is connected to the scan lines 200, the source 14 is connected to the data lines 300, and the drain 15 is electrically connected to the source 14. The gate 12 includes a top gate 121, a bottom gate 122, and a connection layer 123. In the thickness direction of the array substrate 1, the top gate 121 and the bottom gate 122 are disposed on opposite sides of the semiconductor layer 13, and the top gate 121 and the bottom gate 122 are electrically connected through the connection layer 123.

[0028] Preferably, the scan line 200 is electrically connected to the bottom gate 122 in the gate 12.

[0029] Preferably, the bottom gate 122, source 14, drain 15 and top gate 121 can all be metal layer structures made of aluminum, molybdenum, titanium, nickel, copper, silver or chromium.

[0030] For example, the connection layer 123 can be a metal via or a conductive connection structure. In this application, the structure of the connection layer 123 is not limited in too much.

[0031] For example, the material of the substrate 100 can be glass, or it can be acrylic sheet, polyethylene terephthalate (PET), polyethylene aphthalate (PEN), or polyimide film, etc. This application does not impose too many restrictions on the material of the substrate 100.

[0032] According to an embodiment of this application, an array substrate 1 is provided, with reference to... Figure 1-3 The projection of the top gate 121 on the substrate 100 covers the projection of the semiconductor layer 13 on the substrate 100.

[0033] It should be noted that the display light source of electronic paper products comes from the external light at the user end. A small portion of this light passes through the electronic paper film and illuminates the thin-film transistor. The brighter the external light, the more light illuminates the thin-film transistor. In the existing technology, the thin-film transistor of electronic paper products is generally designed as a single-gate or dual-gate series structure, with the gate of the thin-film transistor at the bottom. For this type of structure, when external light passes through the electronic paper film and reaches the thin-film transistor, it will illuminate the semiconductor layer. The light will affect the current of the semiconductor layer. When the illumination light is strong, the leakage current of the product will increase significantly, causing display abnormalities.

[0034] It is understandable that, since the projection of the top gate 121 on the substrate 100 covers the projection of the semiconductor layer 13 on the substrate 100, the top gate 121 can not only serve as a backup gate 12, but also act as a light shielding layer to block light from passing through and shining on the semiconductor layer 13 of the first thin film transistor 400, thereby preventing leakage, improving the anti-lighting effect, and thus improving the product yield.

[0035] According to an embodiment of this application, an array substrate 1 is provided, with reference to... Figure 2-3 The pixel unit also includes a first insulating layer 16 and a second insulating layer 17, which are stacked and disposed between the top gate 121 and the bottom gate 122. The connecting layer 123 is used to penetrate the first insulating layer 16 and the second insulating layer 17 to realize the electrical connection between the top gate 121 and the bottom gate 122.

[0036] It should be noted that the first insulating layer 16 is disposed on the side of the source 14 and drain 15 away from the substrate 100. The top gate 121 is completely isolated from the source 14 and drain 15 through the first insulating layer 16. The semiconductor layer 13 is disposed on the side of the source 14 and drain 15 close to the substrate 100. The second insulating layer 17 is disposed between the semiconductor layer 13 and the bottom gate 122. The connecting layer 123 is used to penetrate the first insulating layer 16 and the second insulating layer 17. That is, the connecting layer 123 is disposed in the stacked area of ​​the first insulating layer 16 and the second insulating layer 17. The connecting layer 123 can avoid penetrating the semiconductor layer 13, the source 14 and the drain 15. The surrounding material is insulating material (stable dielectric constant and non-conductive). It will hardly form additional coupling with the semiconductor layer 13, the source 14 or the drain 15, which can significantly reduce parasitic capacitance and leakage current, and ensure that the drive signal is efficiently transmitted from the bottom gate 122 to the top gate 121.

[0037] According to an embodiment of this application, an array substrate 1 is provided, with reference to... Figure 2-3 The pixel unit also includes a protective layer 18, which is disposed between the first insulating layer 16 and the pixel electrode 11.

[0038] It should be noted that the protective layer 18 covers the side of the top gate 121 away from the substrate 100 and extends to cover the side of the first insulating layer 16 away from the substrate 100. The pixel electrode 11 covers the side of the protective layer 18 away from the substrate 100. On the one hand, the protective layer 18 covering the side of the top gate 121 away from the substrate 100 can increase the physical distance between the conductive layer of the top gate 121 and the conductive layer of the pixel electrode 11, thereby reducing the parasitic capacitance between the conductive layer of the top gate 121 and the conductive layer of the pixel electrode 11, ensuring that the voltage of the pixel electrode 11 can accurately reflect the driving signal and guarantee the display effect. On the other hand, the source electrode 14 and the drain electrode 15 are disposed on the side of the first insulating layer 16 close to the substrate 100. If the surface of the first insulating layer 16 is not smooth, the protective layer... The protective layer 18 extends and covers the side of the first insulating layer 16 away from the substrate 100, which can increase the physical distance between the two conductive layers of the source electrode 14 and the drain electrode 15 and the conductive layer of the pixel electrode 11, thereby reducing the parasitic capacitance between the two conductive layers of the source electrode 14 and the drain electrode 15 and the conductive layer of the pixel electrode 11, ensuring that the voltage of the pixel electrode 11 can accurately reflect the driving signal and guarantee the display effect. On the other hand, if the surface of the first insulating layer 16 and the surface of the top gate 121 are not flat, directly setting the pixel electrode 11 on the uneven surface can easily lead to uneven film thickness and inconsistent resistance distribution of the pixel electrode 11. Therefore, by setting the protective layer 18, it is beneficial to flatten the surface of the first thin film transistor 400 in contact with the pixel electrode 11 and optimize the film formation quality of the pixel electrode 11.

[0039] According to an embodiment of this application, an array substrate 1 is provided, with reference to... Figure 3 The pixel electrode 11 is provided with a connection hole 111, which is used to penetrate the first insulating layer 16 and the protective layer 18 to realize the electrical connection between the pixel electrode 11 and the drain electrode 15.

[0040] It should be noted that by applying an on-state voltage to the scan line 200 on the substrate 100, a conduction voltage is formed between the gate 12 and the source 14 of the first thin film transistor 400 in the pixel unit, thereby causing the first thin film transistor 400 to switch from the off state to the on state. The drain 15 can transmit the voltage to the pixel electrode 11 through the connection hole 111, so that the pixel electrode 11 can work normally.

[0041] It is understood that the connection hole 111 is used to penetrate the first insulating layer 16 and the protective layer 18, that is, the connection hole 111 is set in the stacked area of ​​the first insulating layer 16 and the protective layer 18. The connection hole 111 can avoid passing through the top gate 121, which can significantly reduce parasitic capacitance and leakage current, and ensure that the drive signal is efficiently transmitted from the drain 15 to the pixel electrode 11.

[0042] According to an embodiment of this application, an array substrate 1 is provided, with reference to... Figure 4 , Figure 5 The pixel unit also includes at least one second thin-film transistor 500, which has the same structural parameters as the first thin-film transistor 400, and is connected in parallel with the first thin-film transistor 400.

[0043] It should be noted that the second thin film transistor 500 has the same structural parameters as the first thin film transistor 400. In the thickness direction of the array substrate 1, the top gate 121 and bottom gate 122 of each second thin film transistor 500 are disposed on opposite sides of the semiconductor layer 13, and the top gate 121 and bottom gate 122 of each second thin film transistor 500 are electrically connected through the connection layer 123.

[0044] It should be noted that the top gate 121 of the second thin-film transistor 500 and the top gate 121 of the first thin-film transistor 400 are located on the same metal layer, the source 14 and drain 15 of the second thin-film transistor 500 and the source 14 and drain 15 of the first thin-film transistor 400 are located on the same metal layer, the bottom gate 122 of the second thin-film transistor 500 and the bottom gate 122 of the first thin-film transistor 400 are located on the same metal layer, and the first thin-film transistor 400 and the second thin-film transistor 500 share the semiconductor layer 13.

[0045] It should be noted that by applying an enable voltage to the scan line 200 connected to the gate 12 of the first thin-film transistor 400 and the gate 12 of the second thin-film transistor 500, a conduction voltage is formed between the gate 12 and the source 14 of the first thin-film transistor 400 and the second thin-film transistor 500, thereby switching the first thin-film transistor 400 and the second thin-film transistor 500 from the off state to the on state; since the top gate 121 and the bottom gate 122 of the first thin-film transistor 400 are electrically connected through the connection layer 123 and the top gate 121 and the bottom gate 122 of the second thin-film transistor 500 are electrically connected through the connection layer 123, when the bottom gate 122... When an anomaly occurs, such as a broken wire in the bottom gate 122, the turn-on voltage received by the bottom gate 122 can be transmitted to the top gate 121 through the connection layer 123. A conduction voltage is formed between the top gate 121 and the source 14, so that the first thin-film transistor 400 and the second thin-film transistor 500 can remain in the conducting state, thereby ensuring that the pixel unit can work normally. When an anomaly occurs in the top gate 121, such as a broken wire in the top gate 121, the bottom gate 122 receives the turn-on voltage, and a conduction voltage is formed between the bottom gate 122 and the source 14, so that the first thin-film transistor 400 and the second thin-film transistor 500 can remain in the conducting state, thereby ensuring that the pixel unit can work normally.

[0046] Furthermore, since the second thin-film transistor 500 is connected in parallel with the first thin-film transistor 400, when both the top gate 121 and the bottom gate 122 of the first thin-film transistor 400 malfunction, such as both the top gate 121 and the bottom gate 122 being disconnected, the second thin-film transistor 500 can still maintain its conduction function; when both the top gate 121 and the bottom gate 122 of the second thin-film transistor 500 malfunction, such as both the top gate 121 and the bottom gate 122 being disconnected, the first thin-film transistor 400 can still maintain its conduction function. This redundant design of adding at least one second thin-film transistor 500 can significantly improve product yield and service life.

[0047] According to an embodiment of this application, an array substrate 1 is provided, with reference to... Figure 5 The projections of the top gate 121 of the first thin film transistor 400 and the top gate 121 of the second thin film transistor 500 onto the substrate 100 cover the projection of the semiconductor layer 13 onto the substrate 100.

[0048] It should be noted that the top gate 121 of the second thin-film transistor 500 and the top gate 121 of the first thin-film transistor 400 are located on the same metal layer, and the top gate 121 of the second thin-film transistor 500 is in contact with the top gate 121 of the first thin-film transistor 400. Since the projections of the top gates 121 of the first thin-film transistor 400 and the top gates 121 of the second thin-film transistor 500 on the substrate 100 cover the projection of the semiconductor layer 13 on the substrate 100, the top gates 121 of the first thin-film transistor 400 and the top gates 121 of the second thin-film transistor 500 can not only serve as a backup gate 12, but also as a light-shielding layer to block light from passing through and shining onto the semiconductor layer 13, thus preventing leakage and improving the anti-lighting effect, thereby improving the product yield.

[0049] In some embodiments, refer to Figure 5 The pixel unit also includes a first insulating layer 16 and a second insulating layer 17, which are stacked and disposed between the top gate 121 and the bottom gate 122 of the first thin film transistor 400 and the second thin film transistor 500. The connection layer 123 of the first thin film transistor 400 and the second thin film transistor 500 is used to penetrate the first insulating layer 16 and the second insulating layer 17 to realize the electrical connection between the top gate 121 and the bottom gate 122.

[0050] In some embodiments, refer to Figure 5 The pixel unit also includes a protective layer 18, which is disposed between the first insulating layer 16 and the pixel electrode 11. The pixel electrode 11 is provided with a connection hole 111, which is used to penetrate the first insulating layer 16 and the protective layer 18 to realize the electrical connection between the pixel electrode 11 and the drain 15 of the second thin film transistor 500.

[0051] It should be noted that the source 14 and drain 15 of the second thin film transistor 500 are located on the same metal layer as the source 14 and drain 15 of the first thin film transistor 400, and the source 14 of the second thin film transistor 500 is in contact with the drain 15 of the first thin film transistor 400.

[0052] According to an embodiment of this application, an array substrate 1 is provided, and the pixel electrode 11 is made of indium tin oxide.

[0053] According to an embodiment of this application, an array substrate 1 is provided, wherein the semiconductor layer 13 is made of amorphous silicon or indium gallium zinc oxide.

[0054] Secondly, referring to Figure 7 This application provides an electronic paper display device, including a top substrate 3, an electrophoretic layer 2, and an array substrate 1 as described in any embodiment of this application.

[0055] For example, the electronic paper display device provided in this application can be a micro-cavity electronic paper display (MED) or other electronic paper display devices, without any specific limitation.

[0056] Among them, microcavity electronic paper display (MED) is a display that uses a dam structure to surround each pixel unit on the surface of a thin film transistor (TFT) and uses electronic paste as display particles. Combined with a glass plate, it forms a microcavity structure. The color change of the particles in the paste is controlled by an electric field, and the display effect of high contrast, high reflection and high color gamut is achieved by the reflection of light by the particles.

[0057] For example, the top substrate 3 and the pixel electrode 11 can be disposed correspondingly in a first direction, which can be a vertical direction, i.e., the thickness direction of the array substrate 1, and the electrophoretic layer 2 is disposed between the array substrate 1 and the top substrate 3.

[0058] It should be noted that the array substrate 1 serves as a driving board to drive the movement of particles within the electrophoretic layer 2. Specifically, when the first thin-film transistor 400 in the pixel unit is turned on, the voltage of the data line 300 is applied to the pixel electrode 11 through the first thin-film transistor 400, forming an electric field with the common electrode 600, thereby driving the movement of particles within the electrophoretic layer 2.

[0059] For example, the electrophoretic layer 2 forms a sealed cavity containing a filling liquid and black and white particles distributed within the filling liquid. The black and white particles have different electrical charges; for example, white particles may be negatively charged and black particles positively charged, or vice versa. The black and white particles can undergo electrophoresis under voltage, controlling their positional distribution within the electrophoretic layer 2, thus creating different grayscale levels on the screen surface. Utilizing the principle of attraction between positive and negative charges, when an electric field is applied, the corresponding black or white particles move to the top of the electrophoretic layer 2, allowing the user to see black or white within that area (pixel unit). Applying different voltages to the same electrophoretic layer 2 will result in a half-black, half-white appearance at the top, allowing the user to see gray within that area (pixel unit).

[0060] According to the array substrate 1 and electronic paper display device provided in this application, by applying an enable voltage to the scan line 200 connected to the gate 12 of the first thin-film transistor 400, a conduction voltage is formed between the gate 12 and the source 14 of the first thin-film transistor 400 in the pixel unit, thereby causing the first thin-film transistor 400 to switch from an off state to a conduction state. Since the top gate 121 and the bottom gate 122 of the first thin-film transistor 400 in the pixel unit are electrically connected through the connection layer 123, when the bottom gate 122 malfunctions, such as a broken wire in the bottom gate 122, the enable voltage received by the bottom gate 122 can be transmitted to the top gate 121 through the connection layer 123, and a conduction voltage is formed between the top gate 121 and the source 14, thus enabling the first thin-film transistor 400 to switch from an off state to a conduction state. The first thin-film transistor 400 can remain in the conducting state, thereby ensuring that the pixel unit can work normally. When the top gate 121 malfunctions, such as a broken wire in the top gate 121, the bottom gate 122 receives the turn-on voltage, and a conduction voltage is formed between the bottom gate 122 and the source 14, so that the first thin-film transistor 400 can remain in the conducting state, thereby ensuring that the pixel unit can work normally. Compared with the existing thin-film transistors using a single-gate or dual-gate series structure design, in this application, when either the bottom gate 122 or the top gate 121 malfunctions, the conductive channel can be completed by driving another spare gate 12, which improves the stability of the thin-film transistor and thus effectively improves the working stability of the electronic paper display device.

[0061] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. They can refer to a mechanical connection or an electrical connection. They can refer to a direct connection or an indirect connection through an intermediate medium, and they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0062] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0063] The foregoing disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0064] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0065] The above embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of protection of this application. Any non-substantial changes and substitutions made by those skilled in the art based on this application shall fall within the scope of protection claimed by this application.

Claims

1. An array substrate, characterized in that, The substrate includes a substrate on which multiple scan lines and data lines are disposed. The multiple scan lines and data lines intersect to form multiple pixel units, wherein the pixel unit includes: Pixel electrodes are disposed opposite to the substrate. A first thin-film transistor includes a gate, a semiconductor layer, a source, and a drain. The gate is connected to the scan line, the source is connected to the data line, and the drain is electrically connected to the source. The gate includes a top gate, a bottom gate, and a connection layer. In the thickness direction of the array substrate, the top gate and the bottom gate are disposed on opposite sides of the semiconductor layer, and the top gate and the bottom gate are electrically connected through the connection layer.

2. The array substrate according to claim 1, characterized in that, The projection of the top gate on the substrate covers the projection of the semiconductor layer on the substrate.

3. The array substrate according to claim 1, characterized in that, The pixel unit further includes a first insulating layer and a second insulating layer, which are stacked and disposed between the top gate and the bottom gate. The connecting layer is used to penetrate the first insulating layer and the second insulating layer to realize the electrical connection between the top gate and the bottom gate.

4. The array substrate according to claim 3, characterized in that, The pixel unit further includes a protective layer disposed between the first insulating layer and the pixel electrode.

5. The array substrate according to claim 4, wherein the pixel electrode is provided with a connection hole, the connection hole being used to penetrate the first insulating layer and the protective layer to realize the electrical connection between the pixel electrode and the drain electrode.

6. The array substrate according to claim 1, characterized in that, The pixel unit further includes at least one second thin-film transistor, which has the same structural parameters as the first thin-film transistor and is connected in parallel with the first thin-film transistor.

7. The array substrate according to claim 6, characterized in that, The projections of the top gate of the first thin-film transistor and the top gate of the second thin-film transistor on the substrate cover the projection of the semiconductor layer on the substrate.

8. The array substrate according to claim 1, characterized in that, The pixel electrode is made of indium tin oxide.

9. The array substrate according to claim 1, characterized in that, The semiconductor layer is made of amorphous silicon or indium gallium zinc oxide.

10. An electronic paper display device, characterized in that, It includes a top substrate, an electrophoretic layer, and an array substrate as described in any one of claims 1-9.

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