Display panel motherboard and display panel

Abstract

This invention discloses a display panel motherboard, comprising a display panel disposed at one of the four corners of the motherboard. The display panel has a display area and a peripheral area. The peripheral area has a dummy pixel area surrounding the display area. The display panel includes a dummy pixel group disposed at one of the four corners of the dummy pixel area. The dummy pixel group includes a scan line, a data line, first and second output lines, first and second thin-film transistors, and a virtual center line. The data line is disposed between the first and second output lines. The first and second thin-film transistors are electrically connected to the data line and respectively electrically connected to the first and second output lines. The virtual center line is located between the first and second thin-film transistors and is perpendicular to the scan line. The first and second thin-film transistors are mirror-symmetrical about the virtual center line. The aforementioned display panel motherboard can effectively detect the misalignment of the thin-film transistor layers, thereby improving product yield and maintaining or reducing manufacturing costs.

Description

Technical Field

[0001] The present invention relates to a display panel motherboard, and more particularly to a display panel motherboard comprising a dummy pixel group with thin-film transistors in mirror symmetry. Background Technology

[0002] Active matrix (AM) type display panels contain pixel driving elements, which may include thin-film transistors (TFTs). Therefore, the alignment of the TFT layers significantly impacts display quality. For example, misalignment of the light-shielding layer can cause leakage in the TFTs, thus affecting display quality. However, array testing primarily focuses on functional testing and cannot effectively detect light-shielding layer misalignment. It is only after the circuit board or driver chip is bonded that poor display quality leads to rejection, resulting in decreased product yield and increased manufacturing costs. Summary of the Invention

[0003] At least one embodiment of the present invention provides a display panel motherboard that can effectively detect the misalignment of thin-film transistor layers, thereby improving product yield and maintaining or reducing manufacturing costs.

[0004] At least one other embodiment of the present invention provides a display panel that can effectively detect the misalignment of thin-film transistor layers, thereby improving product yield and maintaining or reducing manufacturing costs.

[0005] At least one embodiment of the present invention provides a display panel motherboard comprising a plurality of display panels arranged in an array. These display panels include a first display panel disposed at one of the four corners of the motherboard and having a display area and a peripheral area, the peripheral area having a dummy pixel area surrounding the display area. The first display panel includes a dummy pixel group disposed at one of the four corners of the dummy pixel area. The dummy pixel group includes a scan line, a data line, a first output line, a second output line, a first thin-film transistor (TFT), a second TFT, and a dummy center line. The scan line extends along a first direction, the data line extends along a second direction not parallel to the first direction, the first output line extends along the second direction, and the second output line extends along the second direction, with the data line disposed between the first and second output lines. The first TFT is electrically connected to the data line and the first output line, and the second TFT is electrically connected to the data line and the second output line. The dummy center line is located between the first and second TFTs and perpendicular to the scan line, and the first and second TFTs are mirror-symmetrical about the dummy center line.

[0006] In at least one embodiment of the present invention, the first thin-film transistor and the second thin-film transistor each include a light-shielding layer, an active layer, a gate, a source, and a drain. The active layer is disposed on the light-shielding layer. The gate is disposed on the active layer and electrically connected to the scan line. The source is disposed on the gate and electrically connected to the active layer and the data line. The drain is disposed on the gate and electrically connected to the active layer and the first output line or the second output line.

[0007] In at least one embodiment of the present invention, the first display panel further includes a substrate, and the light-shielding layer is disposed on the substrate, and the light-shielding layer overlaps with the active layer along the normal line of the substrate.

[0008] In at least one embodiment of the present invention, the source of the first thin-film transistor and the source of the second thin-film transistor are located between the drain of the first thin-film transistor and the drain of the second thin-film transistor.

[0009] In at least one embodiment of the present invention, the active layer is made of polycrystalline silicon.

[0010] In at least one embodiment of the present invention, the first display panel includes four dummy pixel groups, which are respectively disposed at the four corners of the dummy pixel area.

[0011] In at least one embodiment of the present invention, the plurality of display panels includes four first display panels, which are respectively disposed at the four corners of the mother plate of the display panel mother plate.

[0012] In at least one embodiment of the present invention, the four first display panels each include four dummy pixel groups, and the four dummy pixel groups are respectively disposed at the four corners of the dummy pixel area.

[0013] At least one other embodiment of the present invention provides a display panel having a display area and a peripheral area, the peripheral area having a dummy pixel area surrounding the display area. The display panel includes a dummy pixel group disposed at one of the four corners of the dummy pixel area. The dummy pixel group includes a scan line, a data line, a first output line, a second output line, a first thin-film transistor (TFT), a second TFT, and a dummy center line. The scan line extends along a first direction, the data line extends along a second direction not parallel to the first direction, the first output line extends along the second direction, and the second output line extends along the second direction, with the data line disposed between the first and second output lines. The first TFT is electrically connected to the data line and the first output line, and the second TFT is electrically connected to the data line and the second output line. The dummy center line is located between the first and second TFTs and is perpendicular to the scan line; the first and second TFTs are mirror-symmetrical about the dummy center line.

[0014] In at least another embodiment of the present invention, the first thin-film transistor and the second thin-film transistor each include a light-shielding layer, an active layer, a gate, a source, and a drain. The active layer is disposed on the light-shielding layer. The gate is disposed on the active layer and electrically connected to the scan line. The source is disposed on the gate and electrically connected to the active layer and the data line. The drain is disposed on the gate and electrically connected to the active layer and the first output line or the second output line.

[0015] Based on the above, the display panel motherboard and display panel disclosed in the above embodiments include a group of dummy pixels disposed in the corner of the dummy pixel area and with the thin film transistors being mirror-symmetrical, which can effectively detect the offset of the thin film transistor film layer, thereby improving product yield and maintaining or reducing manufacturing costs. Attached Figure Description

[0016] Figure 1 This is a top view schematic diagram of a display panel motherboard according to at least one embodiment of the present invention.

[0017] Figure 2 This is a top view schematic diagram of a display panel according to at least one embodiment of the present invention.

[0018] Figure 3A This is a simplified layout diagram of the dummy pixel group according to at least one embodiment of the present invention.

[0019] Figure 3B yes Figure 3A A magnified view of region A in the middle.

[0020] Figure 3C yes Figure 3B A schematic cross-sectional view drawn along line a-a'.

[0021] In the attached figures, the following labels are used:

[0022] 1: Display panel motherboard

[0023] 10: Display Panel

[0024] 10': First display panel

[0025] 100:Substrate

[0026] 101: Scan line

[0027] 102: Data cable

[0028] 103: First Output Line

[0029] 104: Second Output Line

[0030] A: Area

[0031] a-a': line

[0032] AA: Display area

[0033] AL: Active Layer

[0034] CH: Passage Area

[0035] C1: Motherboard corner

[0036] C2: Corner

[0037] DA: Virtual pixel area

[0038] DC: Drive circuit

[0039] DE: Drain

[0040] DP: Dummy pixel group

[0041] DR: Drain Contact Area

[0042] D1: First Direction

[0043] D2: Second Direction

[0044] FA: Wiring Area

[0045] GE: Gate

[0046] LDR: Lightly Doped Drain Region

[0047] LSR: Lightly Doped Source Region

[0048] IL1: First insulating layer

[0049] IL2: Second insulating layer

[0050] IL3: Third insulating layer

[0051] IL4: Fourth insulating layer

[0052] O1: First perforation

[0053] O2: Second perforation

[0054] PA: Surrounding Area

[0055] SE: Source

[0056] SL: Light-shielding layer

[0057] SR: Source Contact Region

[0058] T1: First thin-film transistor

[0059] T2: Second thin-film transistor

[0060] VL: Virtual Midline Detailed Implementation

[0061] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0062] In the following text, to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally, and the number of some elements may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings or the size and shape of the elements, but should cover deviations in size, shape, and both caused by actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings of the present invention are primarily for illustration and are not intended to precisely depict the actual shape of the elements, nor are they intended to limit the claims of the present invention.

[0063] Secondly, the terms "approximately," "about," or "substantially" used in this invention not only cover explicitly stated numerical values ​​and ranges, but also the permissible deviation range understandable to those skilled in the art to which this invention pertains. This deviation range can be determined by errors generated during measurement, which may arise from limitations of the measurement system or process conditions, for example. For instance, two objects (e.g., planes or traces of a substrate) are "substantially parallel" or "substantially perpendicular," where "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects can include non-parallelism and non-perpendicularity caused by permissible deviation ranges.

[0064] Furthermore, "approximately" can indicate that the value is within one or more standard deviations, such as ±30%, ±20%, ±10%, or ±5%. The terms "approximately," "approximately," or "substantially" used in this invention can be selected based on the optical, etching, mechanical, or other properties to determine an acceptable range of deviations or standard deviations, and are not applied to all optical, etching, mechanical, and other properties using a single standard deviation.

[0065] The spatial relative terms used in this invention, such as "below," "under," "above," and "above," are for the convenience of describing the relative relationship between one element or feature and another, as illustrated in the figures. The true meaning of these spatial relative terms includes other orientations. For example, when the illustration is rotated 180 degrees vertically, the relationship between one element and another may change from "below" or "under" to "above" or "above." Furthermore, the spatial relative descriptions used in this invention should be interpreted in the same way.

[0066] It should be understood that although the present invention may use terms such as "first," "second," and "third" to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are primarily used to distinguish one element from another, or one signal from another. Furthermore, the term "or" as used in this invention may, depending on the specific circumstances, include any combination of one or more of the associated listed items.

[0067] Furthermore, the present invention can be implemented or applied through other different specific embodiments, and the details of the present invention can also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

[0068] Figure 1 This is a top view schematic diagram of a display panel motherboard according to at least one embodiment of the present invention. Figure 2 This is a top view schematic diagram of a display panel according to at least one embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The display panel motherboard 1 includes a plurality of display panels 10, 10' arranged in an array. These display panels 10, 10' include a first display panel 10', which is located at one of the four corners C1 of the display panel motherboard 1 and has a display area AA and a peripheral area PA. The peripheral area PA has a dummy pixel area DA surrounding the display area AA. The first display panel 10' includes a dummy pixel group DP located at one of the four corners C2 of the dummy pixel area DA.

[0069] Figure 3A This is a simplified layout illustration of a dummy pixel group according to at least one embodiment of the present invention. Please refer to... Figure 3A The virtual pixel group DP includes a scan line 101, a data line 102, a first output line 103, a second output line 104, a first thin-film transistor T1, a second thin-film transistor T2, and a virtual center line VL. The scan line 101 extends along a first direction D1, the data line 102 extends along a second direction D2 that is not parallel to the first direction D1, the first output line 103 extends along the second direction D2, and the second output line 104 extends along the second direction D2. The data line 102 is located between the first output line 103 and the second output line 104.

[0070] like Figure 3A As shown, the first thin-film transistor T1 is electrically connected to the data line 102 and the first output line 103, and the second thin-film transistor T2 is electrically connected to the data line 102 and the second output line 104. The virtual center line VL is located between the first thin-film transistor T1 and the second thin-film transistor T2 and is perpendicular to the scan line 101. The first thin-film transistor T1 and the second thin-film transistor T2 are mirror-symmetrical about the virtual center line VL.

[0071] Since the first display panel 10' located at corner C1 of the motherboard 1 contains the aforementioned dummy pixel group DP, the first thin-film transistor T1 and the second thin-film transistor T2 of the dummy pixel group DP are mirror-symmetrical about the virtual center line VL as the axis of symmetry. The first thin-film transistor T1 and the second thin-film transistor T2 can receive the signal provided by the same data line 102. The output signals of the first output line 103 and the second output line 104 can help determine the alignment of the thin-film transistor layers in each pixel of the multiple display panels 10 and 10' of the motherboard 1.

[0072] For example, if the difference between the output signal value of the first output line 103 and the output signal value of the second output line 104 exceeds 0.02, it indicates that the film layer of the thin-film transistor may have shifted. If it does not exceed 0.02, it indicates that the film layer of the thin-film transistor may not have shifted.

[0073] Therefore, through the above structural design and measurement method, the misalignment of the thin-film transistor layer can be effectively detected before the circuit board or driver chip is bonded, thereby improving product yield and maintaining or reducing manufacturing costs.

[0074] Please continue reading. Figure 2 The first display panel 10' includes a driving circuit DC, which is disposed in a peripheral area PA. Specifically, the peripheral area PA has a routing area FA surrounding a dummy pixel area DA. The driving circuit DC is disposed in the routing area FA, and the routing traces (not shown) of the routing area FA are electrically connected to the driving circuit DC. In some embodiments, the routing traces of the routing area FA are electrically connected to the driving circuit DC and the pixels (not shown) of the display area AA and the dummy pixel group DP of the dummy pixel area DA, such that the driving circuit DC drives the pixels of the display area AA and the dummy pixel group DP of the dummy pixel area DA.

[0075] Please continue reading. Figure 3A The scan line 101 and data line 102 intersect. The scan line 101 extends along a first direction D1, while the data line 102 extends along a second direction D2. The first direction D1 and the second direction D2 are not parallel, meaning there is an angle between them greater than 0 degrees and less than 180 degrees. In this embodiment, the first direction D1 and the second direction D2 are perpendicular to each other, meaning there is a 90-degree angle between them. However, the invention is not limited to this; in other embodiments, there may be other angles between the first direction D1 and the second direction D2. Furthermore, for the sake of brevity, Figure 3A The common electrode and pixel electrode are omitted from the drawing.

[0076] Figure 3B yes Figure 3A A magnified view of region A in the middle. Figure 3C yes Figure 3B A schematic cross-sectional view along line a-a'. Please refer to [link / reference]. Figure 3B and Figure 3C The first thin-film transistor T1 and the second thin-film transistor T2 each include a light-shielding layer SL, an active layer AL, a gate GE, a source SE, and a drain DE. The active layer AL is disposed on the light-shielding layer SL. The gate GE is disposed on the active layer AL and electrically connected to the scan line 101. The source SE is disposed on the gate GE and electrically connected to the active layer AL and the data line 102. The drain DE is disposed on the gate GE and electrically connected to the active layer AL and either the first output line 103 or the second output line 104.

[0077] In detail, such as Figure 3A and Figure 3B As shown, scan line 101 includes the gate GE of the first thin-film transistor T1 and the gate GE of the second thin-film transistor T2. That is, the portions of scan line 101 that overlap with the active layer AL of the first thin-film transistor T1 and the active layer AL of the second thin-film transistor T2 are respectively the gate GE of the first thin-film transistor T1 and the gate GE of the second thin-film transistor T2. In addition, the source SE of the first thin-film transistor T1 and the source SE of the second thin-film transistor T2 are located between the drain DE of the first thin-film transistor T1 and the drain DE of the second thin-film transistor T2.

[0078] Specifically, the source SE of the first thin film transistor T1 and the source SE of the second thin film transistor T2 are connected to each other in the first direction D1 through the data line 102, and the source SE of the first thin film transistor T1 and the source SE of the second thin film transistor T2 are electrically connected to one end of the active layer AL of the first thin film transistor T1 and one end of the active layer AL of the second thin film transistor T2 through the first through hole O1, respectively.

[0079] The drain DE of the first thin-film transistor T1 extends from the first output line 103 to the data line 102 and is electrically connected to the other end of the active layer AL of the first thin-film transistor T1 through the second through-hole O2, while the drain DE of the second thin-film transistor T2 extends from the second output line 104 to the data line 102 and is electrically connected to the other end of the active layer AL of the second thin-film transistor T2 through the second through-hole O2.

[0080] Please continue reading. Figure 3CThe first display panel 10' further includes a substrate 100. A light-shielding layer SL for the first thin-film transistor T1 and a light-shielding layer SL for the second thin-film transistor T2 are disposed on the substrate 100. On the normal line of the substrate 100, the light-shielding layers SL of the first thin-film transistor T1 and the second thin-film transistor T2 overlap with the active layer AL of the first thin-film transistor T1 and the active layer AL of the second thin-film transistor T2, respectively. Therefore, if the light-shielding layer SL is offset, it will cause leakage in the first thin-film transistor T1 and / or the second thin-film transistor T2, causing the ratio of the difference between the output signals of the first output line 103 and the second output line 104 to the output signal of the first output line 103 and / or the second output line 104 to exceed 0.02. Thus, the offset of the thin-film transistor layers can be detected.

[0081] like Figure 3C As shown, the first display panel 10' further includes a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, and a fourth insulating layer IL4. The first insulating layer IL1 is disposed on the light-shielding layer SL, the second insulating layer IL2 is disposed on the active layer AL, the third insulating layer IL3 is disposed on the gate GE, and the fourth insulating layer IL4 is disposed on the source SE and the drain DE.

[0082] The active layer AL includes a channel region CH, a lightly doped source region LSR, a lightly doped drain region LDR, a source contact region SR, and a drain contact region DR. The lightly doped source region LSR is located between the source contact region SR and the channel region CH, and the lightly doped drain region LDR is located between the channel region CH and the drain contact region DR. The gate GE overlaps with the channel region CH of the active layer AL, but the present invention is not limited thereto. In other embodiments, the active layer AL may only include the source contact region SR, the channel region CH, and the drain contact region DR.

[0083] Furthermore, the source SE of the first thin-film transistor T1 and the source SE of the second thin-film transistor T2 are electrically connected to the source contact region SR of the active layer AL of the first thin-film transistor T1 and the source contact region SR of the active layer AL of the second thin-film transistor T2 through the first through-hole O1 through the third insulating layer IL3 and the second insulating layer IL2, respectively. The drain DE of the first thin-film transistor T1 and the drain DE of the second thin-film transistor T2 are electrically connected to the drain contact region DR of the active layer AL of the first thin-film transistor T1 and the drain contact region DR of the active layer AL of the second thin-film transistor T2 through the second through-hole O2 through the third insulating layer IL3 and the second insulating layer IL2, respectively.

[0084] In some embodiments, the substrate 100 may be a transparent substrate, and the material of the substrate 100 may be quartz, glass, polymer material, or other suitable material. In some embodiments, the material of the active layer AL may include silicon semiconductor materials (e.g., polycrystalline silicon, amorphous silicon, etc.), oxide semiconductor materials, organic semiconductor materials, other suitable materials, or a single layer, multiple layers, or combination of the foregoing materials. In this embodiment, the material of the active layer AL includes polycrystalline silicon, such as low-temperature polycrystalline silicon.

[0085] In some embodiments, the materials of scan line 101, data line 102, first output line 103, second output line 104, gate GE, source SE, and drain DE may include metals, alloys, transparent conductive materials, other suitable materials, or single layers, multiple layers, or combinations of the aforementioned materials. Metals include, for example, aluminum, molybdenum, titanium, copper, or silver; alloys include alloys of the aforementioned metals; and transparent conductive materials include, for example, indium tin oxide, indium zinc oxide, indium gallium zinc oxide, or aluminum zinc oxide. In this embodiment, the materials of scan line 101, data line 102, first output line 103, second output line 104, light-shielding layer SL, gate GE, source SE, and drain DE comprise metals or alloys, which may have better conductivity, but the present invention is not limited thereto.

[0086] In some embodiments, the materials of the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 may include transparent insulating materials, such as transparent inorganic insulating materials, organic insulating materials, other suitable materials, or single layers, multiple layers, or combinations of the aforementioned materials. Inorganic insulating materials include silicon oxide, silicon nitride, silicon oxynitride, etc., and organic insulating materials include polymethyl methacrylate, siloxane, polyimide, epoxy resin, etc.

[0087] In some embodiments, with Figure 1 For example, multiple display panels 10, 10' may include four first display panels 10', with the four first display panels 10' respectively disposed at the four corners C1 of the motherboard 1. Figure 2 For example, the first display panel 10' may include four dummy pixel groups DP, which are respectively located at the four corners C2 of the dummy pixel area DA. Furthermore, multiple display panels 10, 10' may include four first display panels 10', which are respectively located at the four motherboard corners C1 of the display panel motherboard 1. Each of the four first display panels 10' may include four dummy pixel groups DP, which are respectively located at the four corners C2 of the dummy pixel area DA. Through the aforementioned configuration, the offset of the thin-film transistor layer can be further effectively detected.

[0088] In summary, in the display panel motherboard and display panel of at least one embodiment of the present invention, since the display panel disposed at the corner of the display panel motherboard includes a dummy pixel group, the first and second thin-film transistors of the dummy pixel group are mirror-symmetrical about the virtual center line, and the first and second thin-film transistors can receive signals provided by the same data line. Furthermore, the output signals of the first and second output lines can help determine the alignment of the thin-film transistor film layers in each pixel of the multiple display panels of the display panel motherboard. Therefore, the misalignment of the thin-film transistor film layers can be effectively detected, thereby improving product yield and maintaining or reducing manufacturing costs.

[0089] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A display panel motherboard, characterized in that, include: A plurality of display panels arranged in an array, including a first display panel, the first display panel being disposed at one of the four corners of the motherboard of the display panel, and having a display area and a peripheral area, wherein the peripheral area has a dummy pixel area surrounding the display area, and the first display panel including a dummy pixel group disposed at one of the four corners of the dummy pixel area, wherein the dummy pixel group includes: A scan line extends along a first direction; A data line extends along a second direction that is not parallel to the first direction; A first output line extends along the second direction; A second output line extends along the second direction, wherein the data line is disposed between the first output line and the second output line; A first thin-film transistor is electrically connected to the data line and the first output line; A second thin-film transistor, electrically connected to the data line and the second output line; and A virtual center line is located between the first thin-film transistor and the second thin-film transistor and is perpendicular to the scan line, wherein the first thin-film transistor and the second thin-film transistor are mirror-symmetrical about the virtual center line.

2. The display panel motherboard as described in claim 1, characterized in that, The first thin-film transistor and the second thin-film transistor each include: A light-blocking layer; An active layer is disposed on the light-shielding layer; A gate is disposed on the active layer and electrically connected to the scan line; A source electrode is disposed on the gate electrode and electrically connected to the active layer and the data line; and A drain electrode is disposed on the gate and electrically connected to the active layer and the first output line or the second output line.

3. The display panel motherboard as described in claim 2, characterized in that, It further includes a substrate, wherein the light-shielding layer is disposed on the substrate, and the light-shielding layer overlaps with the active layer along a normal line of the substrate.

4. The display panel motherboard as described in claim 2, characterized in that, The source of the first thin-film transistor and the source of the second thin-film transistor are located between the drain of the first thin-film transistor and the drain of the second thin-film transistor.

5. The display panel motherboard as described in claim 2, characterized in that, The active layer is made of polycrystalline silicon.

6. The display panel motherboard as described in claim 1, characterized in that, The first display panel includes four dummy pixel groups, which are respectively disposed at the four corners of the dummy pixel area.

7. The display panel motherboard as described in claim 1, characterized in that, The plurality of display panels includes four first display panels, which are respectively disposed at the four corners of the motherboard of the display panel motherboard.

8. The display panel motherboard as described in claim 7, characterized in that, Each of the first display panels includes four dummy pixel groups, which are respectively disposed at the four corners of the dummy pixel area.

9. A display panel, characterized in that, The display panel includes a display area and a peripheral area, wherein the peripheral area has a dummy pixel area surrounding the display area. A dummy pixel group is disposed at one of the four corners of the dummy pixel area, and includes: A scan line extends along a first direction; A data line extends along a second direction that is not parallel to the first direction; A first output line extends along the second direction; A second output line extends along the second direction, wherein the data line is disposed between the first output line and the second output line; A first thin-film transistor is electrically connected to the data line and the first output line; A second thin-film transistor, electrically connected to the data line and the second output line; and A virtual center line is located between the first thin-film transistor and the second thin-film transistor and is perpendicular to the scan line, wherein the first thin-film transistor and the second thin-film transistor are mirror-symmetrical about the virtual center line.

10. The display panel as claimed in claim 9, characterized in that, The first thin-film transistor and the second thin-film transistor each include: A light-blocking layer; An active layer is disposed on the light-shielding layer; A gate is disposed on the active layer and electrically connected to the scan line; A source electrode is disposed on the gate electrode and electrically connected to the active layer and the data line; and A drain electrode is disposed on the gate and electrically connected to the active layer and the first output line or the second output line.

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