Display panel and display device

Abstract

A display panel (PNL) and a display device. The display panel (PNL) comprises at least two sub-panels (SPNL) sequentially tiled in a column direction; any sub-panel (SPNL) comprises sub-pixels (PIX) distributed in an array and scan lines (GL) in one-to-one correspondence to sub-pixel rows; and the sub-panel (SPNL) is provided with a plurality of gate drive circuits (GOA) for driving the scan lines (GL), wherein among two adjacent sub-panels (SPNL), the timing of a start signal of the gate drive circuit (GOA) electrically connected to the last row of scan line (GL) of the preceding sub-panel (SPNL) is the same as the timing of a start signal of the gate drive circuit (GOA) electrically connected to the first row of scan line (GL) of the subsequent sub-panel (SPNL). The problem of screen tearing of the tiled display panels (PNL) can be solved.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Currently, AM (Active AM) Mini / Micro LED (miniature light-emitting diode or micro-light-emitting diode) video wall displays use a GOA (Gate of Area) scanning method where each video wall module scans simultaneously. This results in a time difference of one scan cycle (1 frame) between the scanning times of the two rows of pixels at the seam between the upper and lower modules (the last row of pixels in the upper module and the first row of pixels in the lower module). Consequently, the time difference in image display between the two rows of pixels at the seam between the upper and lower modules is also one scan cycle. When displaying fast-moving images, this can easily lead to screen tearing (image desynchronization) between the upper and lower modules, affecting display quality.

[0003] Understandably, a frame consists of one scan cycle (1 Frame) and one blank cycle (1 blank). Specifically, 1 Frame is the time it takes for the module's gate drive circuit (GOA) to scan from the first row to the last row.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device to solve the problem of screen tearing in spliced ​​display panels.

[0007] According to one aspect of this disclosure, a display panel is provided, comprising at least two sub-panels sequentially joined along a column direction;

[0008] Each of the sub-panels includes an array of sub-pixels and scan lines that correspond one-to-one with each row of sub-pixels;

[0009] The sub-panel has multiple gate drive circuits for driving each of the scan lines;

[0010] In two adjacent sub-panels, the start signal of the gate drive circuit electrically connected to the last row of scan lines of the preceding sub-panel is at the same time as the start signal of the gate drive circuit electrically connected to the first row of scan lines of the following sub-panel.

[0011] In one embodiment of this disclosure, the display panel includes two sub-panels.

[0012] In one embodiment of this disclosure, the sub-panel includes two gate drive circuits.

[0013] In one embodiment of this disclosure, m gate driving circuits are disposed on the sub-panel; m is a positive integer greater than 1;

[0014] The scan line is divided into multiple sequentially adjacent scan line groups, and each scan line group includes m sequentially adjacent scan lines.

[0015] Each of the m scan lines in the same scan line group is driven by one of the m gate drive circuits.

[0016] In one embodiment of this disclosure, each gate driving circuit includes a plurality of shift registers cascaded in sequence;

[0017] The j-th scan line in the i-th scan line group is electrically connected to the i-th shift register of the j-th gate drive circuit; j is a positive integer between 1 and m.

[0018] In one embodiment of this disclosure, the gate drive circuit includes a plurality of shift registers cascaded in sequence;

[0019] The first reference gate driving circuit of the sub-panel is a gate driving circuit that drives the last row of scan lines of the sub-panel; the second reference gate driving circuit of the sub-panel is a gate driving circuit that drives the first row of scan lines of the sub-panel.

[0020] In two adjacent sub-panels, the input of the first-stage shift register of the first reference gate drive circuit of the preceding sub-panel is electrically connected to the input of the first-stage shift register of the second reference gate drive circuit of the following sub-panel.

[0021] In one embodiment of this disclosure, the display panel includes a first sub-panel and a second sub-panel sequentially spliced ​​along a column direction;

[0022] The first sub-panel has a first gate driving circuit and a second gate driving circuit for driving each of the scan lines; the first gate driving circuit is used to drive the odd-numbered scan lines of the first sub-panel, and the second gate driving circuit is used to drive the even-numbered scan lines of the first sub-panel.

[0023] The second sub-panel has a third gate driving circuit and a fourth gate driving circuit for driving each of the scan lines; the third gate driving circuit is used to drive the odd-numbered scan lines of the second sub-panel, and the fourth gate driving circuit is used to drive the even-numbered scan lines of the second sub-panel.

[0024] In one embodiment of this disclosure, the number of scan lines of the sub-panel is even; the start signal of the second gate driving circuit of the first sub-panel is at the same time as the start signal of the third gate driving circuit of the second sub-panel.

[0025] In one embodiment of this disclosure, the number of scan lines of the sub-panel is odd; the start signal of the first gate driving circuit of the first sub-panel is at the same time as the start signal of the third gate driving circuit of the second sub-panel.

[0026] In one embodiment of this disclosure, the start time of the start signal of the first gate driving circuit is one-half a scan cycle earlier than the start time of the start signal of the second gate driving circuit.

[0027] In one embodiment of this disclosure, the sub-panel has light emission control traces that correspond one-to-one with each sub-pixel row, and the light emission control traces are used to load light emission control signals to the pixel driving circuit.

[0028] All of the aforementioned light-emitting control traces are electrically connected to each other.

[0029] In one embodiment of this disclosure, the display panel is a Mini LED display panel, a Micro LED display panel, an OLED display panel, a QLED display panel, or an LCD display panel.

[0030] According to another aspect of this disclosure, a display device is also provided, including the display panel described above.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0033] Figure 1 is a schematic diagram of a display panel in one embodiment of this disclosure.

[0034] Figure 2 is a schematic diagram of a sub-panel in one embodiment of this disclosure.

[0035] Figure 3 is a schematic diagram of the film layer of the sub-panel in one embodiment of this disclosure.

[0036] Figure 4 is a schematic diagram of the film layer of the sub-panel in one embodiment of this disclosure.

[0037] Figure 5 is a schematic diagram of the film layer of a sub-pixel in one embodiment of this disclosure.

[0038] Figure 6 is a schematic diagram of the film layer of a sub-pixel in one embodiment of this disclosure.

[0039] Figure 7 is a schematic diagram of the film layer of a sub-pixel in one embodiment of this disclosure.

[0040] Figure 8 is a schematic diagram of the film layer of a sub-pixel in one embodiment of this disclosure.

[0041] Figure 9 is a schematic diagram of the structure of the display panel in one embodiment of this disclosure.

[0042] Figure 10 is a timing diagram of the scan lines corresponding to each sub-pixel row of the display panel in Figure 9, according to one embodiment of the present disclosure.

[0043] Figure 11 is a schematic diagram of the structure of the display panel in one embodiment of this disclosure.

[0044] Figure 12 is a timing diagram corresponding to the scan lines of each sub-pixel row of the display panel in Figure 11 in one embodiment of the present disclosure.

[0045] Figure 13 is a timing diagram of the start signal in one embodiment of this disclosure.

[0046] Figure 14 is a timing diagram of the simultaneous loading of light emission control signals on each sub-pixel row in one embodiment of the present disclosure.

[0047] Figure reference numerals: AA, Display area; BB, Peripheral area; Buff, Inorganic buffer layer; CFL, Color filter layer; CGL, Charge generation layer; COML, Common electrode layer; CVD1, First inorganic encapsulation layer; CVD2, Second inorganic encapsulation layer; DBP, Driving backplane; DH, Horizontal direction; DL, Data line; DRL, Driving layer; DV, Columnar array; EBL, Electron blocking layer; EFL, Light-emitting functional layer; EFU, Light-emitting functional unit; EIL, Electron injection layer; ELS, Light-emitting stack structure; EML, Organic light-emitting layer; ETL, Electron transport layer; GI, Gate insulating layer; GL, Scan line; GL1, First scan line; GL2, Second scan line; GLS, Scan line group; GOA, Gate driving circuit; GOA1, First gate driving circuit; GOA2, Second gate driving circuit; GOA3, Third gate driving circuit; GOA4, Fourth gate driving circuit; GT, Gate layer; HBL, Hole blocking layer; HI L, Hole injection layer; HTL, Hole transport layer; IJP, Organic encapsulation layer; ILD, Interlayer dielectric layer; PDC, Pixel driver circuit; PDL, Pixel definition layer; PE, Pixel electrode; PEL, Pixel electrode layer; PIX, Subpixel; PIXL, Pixel layer; PLN, Planarization layer; PNL, Display panel; QDL, Quantum dot layer; SBT, Substrate; SCL, Semiconductor layer; SD, Source / drain metal layer; SPNL, Sub-panel; SPNL1, First sub-panel; SPNL2, Second sub-panel; SR, Shift register; TFE, Thin film encapsulation layer; TFT, Thin film transistor; TSL, Touch function layer; SR1, First shift register; SR2, Second shift register; SR3, Third shift register; SR89, ​​Eighty-ninth shift register; SR90, Ninetieth shift register; Detailed Implementation

[0048] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0049] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0050] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0051] In this embodiment, a transistor is a device that includes at least three terminals: a gate, a source, and a drain. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the area through which current primarily flows. In this embodiment, when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged; that is, the "source" and "drain" can be interchanged. In this embodiment, for any transistor, one of the "source" and "drain" is referred to as the first terminal of the transistor, and the other is referred to as the second terminal of the transistor, and the gate is referred to as the control terminal of the transistor. In this embodiment, at least a portion of the signal has a high level and a low level; one of the high level and the low level can serve as the on-level of the signal, which enables the controlled transistor to conduct; the other of the high level and the low level can serve as the off-level of the signal, which enables the controlled transistor to turn off. For example, for a signal controlling a P-type transistor (which can be applied to the control terminal of the P-type transistor), its on-level is low and its off-level is high. As another example, for a signal controlling an N-type transistor (which can be applied to the control terminal of the N-type transistor), its on-level is high and its off-level is low.

[0052] Structural layer A is located on the side of structural layer B that faces away from the substrate SBT. This can be understood as structural layer A being formed on the side of structural layer B that faces away from the substrate SBT. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or at a lower physical height than structural layer B, where the substrate SBT serves as the height reference.

[0053] This disclosure provides a display device, including a display panel PNL. The display device can be any product or component with display functionality, such as a TV, an all-in-one conference machine, or an advertising screen. In one example, the display panel PNL is a display panel PNL with a display size of not less than 80 inches, and particularly not less than 100 inches. Of course, the display panel PNL can also be a small-to-medium-sized display panel PNL, such as a direct-display Mini LED display panel or a direct-display Micro LED display panel.

[0054] In this embodiment of the disclosure, referring to FIG1, the display panel PNL includes at least two sub-panels SPNL sequentially spliced ​​along the column direction. Thus, a larger display panel PNL can be formed using smaller sub-panels SPNL, thereby reducing the cost of the display panel PNL.

[0055] In one embodiment of this disclosure, referring to FIG2, the sub-panel SPNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the sub-panel SPNL is provided with an array of display units, each display unit including a sub-pixel PIX and a pixel driving circuit PDC that drives the sub-pixel PIX. The sub-panel SPNL does not have display units in the peripheral area BB, or the display units provided are not used for displaying images.

[0056] Referring to Figure 2, the sub-panel SPNL has multiple scan lines GL extending along the row direction DH in the display area AA, with each scan line GL corresponding to a row of display units. The pixel driving circuit PDC of each display unit in each row is electrically connected to its corresponding scan line GL. The sub-panel SPNL also has multiple data lines DL extending along the column square DV in the display area AA, with each data line DL corresponding to a column of display units. The pixel driving circuit PDC of each display unit in each column is electrically connected to its corresponding data line DL. Thus, each display unit's pixel driving circuit PDC is connected to one scan line GL and one data line DL. When a scan signal is applied to the scan line GL, the driving voltage applied to the data line DL is written into the pixel driving circuit PDC, thereby causing the sub-pixel PIX to emit light.

[0057] Optionally, the pixel driving circuit PDC includes at least a data writing transistor, a driving transistor, and a storage capacitor. The control terminal of the driving transistor can be electrically connected to one electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data line DL, and the control terminal of the data writing transistor can be electrically connected to the scan line GL. The pixel driving circuit PDC is configured such that when a scan signal is applied to the scan line GL, the data writing transistor is turned on, thereby causing the driving voltage on the data line DL to be written to the control terminal of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage at its control terminal. It is understood that the pixel driving circuit PDC of this disclosure embodiment may also include other transistors or capacitors to give the pixel driving circuit PDC better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors TFTs and one storage capacitor), an 8T1C (8 thin film transistors TFTs and one storage capacitor), or a pixel driving circuit with other architectures.

[0058] Optionally, the sub-pixel PIX can be a current-driven self-emissive element, such as any one of OLED, QLED, Micro LED, Mini LED, etc. In this embodiment, the sub-pixel PIX can include multiple sub-pixel PIXs of different colors, such as a red sub-pixel for emitting red light, a blue sub-pixel for emitting green light, and a green sub-pixel for emitting green light. It is understood that in other embodiments of this disclosure, the sub-pixel PIX in the display area AA may also have sub-pixel PIXs of other colors (e.g., a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0059] In one embodiment of this disclosure, referring to FIG3, the sub-panel SPNL may include a substrate SBT, a driving layer DRL, and a pixel layer PIXL stacked sequentially. The pixel layer PIXL contains sub-pixels PIX, and the driving layer DRL contains a pixel driving circuit PDC for driving the sub-pixels PIX; each sub-pixel PIX can emit light under the drive of the pixel driving circuit PDC to display an image. In the example of FIG3, the sub-pixel PIX is a thin-film self-emissive element, such as an OLED, QLED, or PLED. In this example of FIG3, the sub-panel SPNL also includes an encapsulation layer located on the side of the pixel layer PIXL away from the substrate SBT, which can encapsulate and protect the pixel layer PIXL. In one example, the encapsulation layer is a thin-film encapsulation layer TFE.

[0060] It is understood that, in the embodiments of this disclosure, the display panel PNL can also be other types of panels. For example, the display panel PNL can also be a Mini LED display panel, a Micro LED display panel, or other display panels. In this display panel PNL, the film layer structure of the sub-panel SPNL can be different from the example in FIG3. The PNL can also be an LCD display panel; in this LCD display panel PNL, the structure of the sub-panel SPNL is also different from the example in FIG3.

[0061] The following example illustrates the film structure and distance of the sub-panel SPNL, using the sub-pixel PIX of the display panel PNL as a thin-film self-emissive element.

[0062] In this example, the substrate SBT can be an inorganic material substrate SBT or an organic material substrate SBT; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrate SBTs. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate SBT; for example, the material of the substrate SBT may include polyimide.

[0063] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a thin-film transistor (TFT) and a storage capacitor. Further, the TFT can be selected from top-gate TFTs, bottom-gate TFTs, or dual-gate TFTs; the active layer material of the TFT can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the TFT can be an N-type TFT or a P-type TFT.

[0064] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. Exemplarily, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon (LTPS) semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor (MODS) semiconductor material. In some embodiments of this disclosure, the thin-film transistor (TFT) is a LPS transistor. In other embodiments of this disclosure, some TFTs are LPS transistors and some TFTs are MODS transistors.

[0065] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN, stacked between the substrate SBT and the pixel layer PIXL. Each thin-film transistor (TFT) and storage capacitor can be formed from the semiconductor layer SCL, gate insulating layer GI, gate layer GT, interlayer dielectric layer ILD, and source / drain metal layer SD. The positional relationship of each layer can be determined based on the thin-film transistor TFT's layer structure. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form partial traces or conductive structures if necessary. The gate layer can be used to form one or more gate layer traces such as scan traces, reset control traces, and light emission control traces, or it can be used to form the control terminal of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer can be used to form data traces, drive power supply voltage traces, or other source / drain metal layer traces, or it can be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of this disclosure, the driving layer DRL may also include other film layers as needed, such as a light-shielding layer located between the semiconductor layer SCL and the substrate SBT. As needed, any one of the above-mentioned semiconductor layer SCL, gate layer GT, source / drain metal layer SD may be multiple layers. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate layers GT. Correspondingly, the insulating film layers in the driving layer DRL (such as gate insulating layer GI, interlayer dielectric layer ILD, planarization layer PLN, etc.) may be increased or decreased adaptively, or new insulating film layers may be added as needed.

[0066] Optionally, the driving layer DRL may also include a passivation layer, which may be disposed on the surface of the source / drain metal layer SD away from the substrate SBT, in order to protect the source / drain metal layer SD.

[0067] As an example, referring to Figure 3, the driving layer DRL may include an inorganic buffer layer Buff, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN stacked sequentially, so that the thin film transistor TFT formed is a top-gate thin film transistor TFT.

[0068] In one embodiment of this disclosure, referring to Figures 4 and 5, the sub-pixel PIX in the pixel layer PIXL is a thin-film light-emitting element, which may include two electrodes stacked together and a light-emitting functional unit EFU sandwiched between the two electrodes.

[0069] For example, referring to Figure 4, the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes PE in the display area of ​​the sub-panel SPNL; the portion of the light-emitting functional layer EFL connected to the pixel electrodes PE serves as the light-emitting functional unit EFU of the sub-pixel PIX; and the common electrode layer COML serves as a common electrode electrically connected to the light-emitting functional units EFU of each sub-pixel PIX.

[0070] Furthermore, the pixel layer PIXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has multiple through-hole pixel openings corresponding one-to-one with the multiple pixel electrodes PE, with each pixel opening exposing at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal region of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective region of the pixel electrode PE (the region directly connected to the light-emitting functional unit EFU), thereby defining the light-emitting region and light-emitting area of ​​the sub-pixel PIX. The light-emitting functional layer EFL at least covers the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting functional layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide electrons, holes, and other charge carriers to the light-emitting functional layer EFL, causing the light-emitting functional layer EFL to emit light. The portion of the light-emitting functional layer EFL located between the pixel electrode PE and the common electrode layer COML can serve as the light-emitting functional unit EFU. A pixel electrode (PE), a common electrode layer (COML), and a light-emitting functional unit (EFU) form a sub-pixel (PIX). One of the pixel electrode (PE) and the common electrode layer (COML) serves as the anode of the sub-pixel (PIX), and the other serves as the cathode.

[0071] In one example, the pixel electrode PE serves as the anode of the sub-pixel PIX, and the common electrode layer COML serves as the cathode of the sub-pixel PIX.

[0072] It is understandable that different types of light-emitting elements result in different materials and films for the light-emitting functional unit (EFU).

[0073] For example, referring to Figure 5, when the light-emitting element is an OLED, the light-emitting functional unit (EFU) may include an organic light-emitting layer (EML), and may include one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the organic light-emitting layer (EML) may include a host material and a guest material, where the guest material can be a fluorescent dopant or a phosphorescent dopant, particularly a thermally activated delayed fluorescence material. Referring to Figure 6, when the OLED adopts a stacked structure, a charge generation layer (CGL) may also be provided in the EFL.

[0074] For example, referring to Figure 7, when the light-emitting element is a QLED, the light-emitting functional unit (EFU) may include a quantum dot layer (QDL) and one or more of the following: a hole injection layer (HIL), an electron transport layer (ETL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the quantum dot layer (QDL) may have quantum dot particles, which can be interconnected through surface-modified groups. Referring to Figure 8, when the QLED adopts a stacked structure, the light-emitting functional unit (EFU) may also include a charge generation layer (CGL).

[0075] In this embodiment of the disclosure, referring to Figures 5 to 8, the light-emitting functional unit (EFU) may include a single-layer light-emitting stacked structure (ELS) or multiple layers of light-emitting stacked structures (ELS). When the EFU includes multiple layers of light-emitting stacked structures (ELS), a charge-generating layer (CGL) may be disposed between adjacent layers of light-emitting stacked structures (ELS). Each layer of light-emitting stacked structure (ELS) is provided with one or more light-emitting layers, which may be either an organic light-emitting layer (EML) or a quantum dot layer (QDL).

[0076] Referring to Figure 3, the thin-film encapsulation layer TFE can be disposed on the surface of the pixel layer PIXL away from the substrate SBT, and it can include alternately stacked inorganic encapsulation layers and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing material aging in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked on the side of the pixel layer PIXL away from the substrate SBT. Of course, in other embodiments of this disclosure, the sub-panel SPNL may not have a thin-film encapsulation layer, but may use other methods to encapsulate and protect the pixel layer.

[0077] In some embodiments of this disclosure, referring to FIG3, the sub-panel SPNL may further include a touch function layer TSL, which may be disposed on the side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the sub-panel SPNL has touch function.

[0078] In some embodiments of this disclosure, referring to FIG3, the sub-panel SPNL may further include a color filter layer CFL, which may be disposed on the side of the thin film encapsulation layer TFE away from the driving backplane DBP to reduce reflection of ambient light and improve display quality.

[0079] In one embodiment of this disclosure, referring to FIG9, the display panel PNL includes at least two sub-panels SPNL sequentially arranged along a column direction. Each sub-panel SPNL includes an array of sub-pixels PIX and scan lines GL corresponding one-to-one with each row of sub-pixels. Each sub-pixel PIX is provided with the aforementioned pixel driving circuit PDC, which drives the sub-pixel PIX. The sub-panel SPNL has multiple gate driving circuits GOA for driving each scan line GL. Specifically, in two adjacent sub-panels SPNL, the start signal of the gate driving circuit GOA electrically connected to the last row of scan lines GL of the preceding sub-panel SPNL is at the same time as the start signal of the gate driving circuit GOA electrically connected to the first row of scan lines GL of the following sub-panel SPNL.

[0080] It is understood that in this embodiment, "previous" and "next" refer to their vertical position relative to each other in two adjacent sub-panels SPNL. For example, the "previous" sub-panel SPNL could be the one positioned higher up, and the "next" sub-panel SPNL could be the one positioned lower down, with the two sub-panels SPNL being joined sequentially. In one example, the simultaneous timing of the start signals could mean that the inputs of the two gate drive circuits GOA share the same start signal, or that the inputs of the two gate drive circuits GOA are connected to the same start signal at the same time.

[0081] In two adjacent sub-panels SPNL, by setting the start signal of the gate drive circuit GOA electrically connected to the last scan line GL of the preceding sub-panel SPNL and the start signal of the gate drive circuit GOA electrically connected to the first scan line GL of the following sub-panel SPNL to be at the same time, when driving the scan lines GL of the two adjacent sub-panels SPNL, the odd and even scan lines GL of the sub-panel SPNL can be driven separately. This reduces the scanning time difference between the last scan line GL of the preceding sub-panel SPNL and the first scan line GL of the following sub-panel SPNL, which helps to solve the screen tearing phenomenon of splicing display panels PNL, thereby improving display quality and facilitating its application in display products with customizable splicing sizes.

[0082] In one embodiment of this disclosure, referring to FIG9, the display panel PNL includes two sub-panels SPNL. In other words, the two sub-panels SPNL spliced ​​along the column direction together constitute the display panel PNL of this embodiment.

[0083] In one embodiment of this disclosure, referring to FIG9, the sub-panel SPNL includes two gate drive circuits GOA, which drive the scan line GL, facilitating separate scanning of the odd and even rows of the scan line GL of the sub-panel SPNL.

[0084] In one embodiment of this disclosure, m gate drive circuits GOA are provided on the sub-panel SPNL; m is a positive integer greater than 1, for example, m can be a positive integer such as 2, 3, 4, etc.; the scan line GL is divided into multiple sequentially adjacent scan line groups GLS, and the scan line group GLS includes m sequentially adjacent scan lines GL; the m scan lines GL in the same scan line group GLS are driven by m gate drive circuits GOA respectively.

[0085] Optionally, the number of gate drive circuits (GOAs) on the same sub-panel SPNL can be two, three, four, etc.

[0086] In one example, referring to Figures 9 and 10, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially arranged along the column direction. Both the first sub-panel SPNL1 and the second sub-panel SPNL2 have 180 scan lines GL, with the first sub-panel SPNL1 located above the second sub-panel SPNL2. The first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, both the first sub-panel SPNL1 and the second sub-panel SPNL2 have two gate drive circuits GOA. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS. Each scan line group GLS includes two sequentially adjacent scan lines GL; in other words, each scan line group GLS includes a sequentially adjacent first scan line GL1 and a sequentially adjacent second scan line GL2. In this design, two scan lines GL within the same scan line group GLS are driven by two gate drive circuits GOA. Specifically, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2. In the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the third gate drive circuit GOA3, and the second scan line GL2 in the same scan line group GLS is driven by the fourth gate drive circuit GOA4. This allows for separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL through the two gate drive circuits GOA, ensuring that the scanning time difference between the 180th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half the scanning cycle of the sub-panel SPNL. This helps to solve the screen tearing phenomenon in spliced ​​display panels PNL and improves display quality.

[0087] In another example, referring to Figures 11 and 12, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially arranged along the column direction. Both the first sub-panel SPNL1 and the second sub-panel SPNL2 have 179 scan lines GL, with the first sub-panel SPNL1 positioned above the second sub-panel SPNL2. The first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, both the first sub-panel SPNL1 and the second sub-panel SPNL2 have two gate drive circuits GOA. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS. The first 89 scan line groups GLS include two sequentially adjacent scan lines GL, in other words, the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2 that are sequentially adjacent. The 90th scan line group GLS includes one scan line GL, in other words, the 90th scan line group GLS includes a first scan line GL1. Except for the 90th scan line group GLS, the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA. That is, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2. Driven by the third gate drive circuit GOA3, the second scan line GL2 in the same scan line group GLS is driven by the fourth gate drive circuit GOA4; while in the first sub-panel SPNL1, the first scan line GL1 in the 90th scan line group GLS is driven by the first gate drive circuit GOA1; in the second sub-panel SPNL2, the first scan line GL1 in the 90th scan line group GLS is driven by the third gate drive circuit GOA3, so that the odd and even row scan lines GL of the same sub-panel SPNL can be scanned separately through the two gate drive circuits GOA, so that the scanning time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning cycle of the sub-panel SPNL, which helps to solve the screen tearing phenomenon of spliced ​​display panels PNL and improve display quality.

[0088] In other examples, similarly, m can be 3. In this case, three gate drive circuits (GOA) can be used to achieve separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL. That is, each scan line group GLS includes three scan lines GL, and the three scan lines GL are driven by three gate drive circuits (GOA) respectively. This makes the scan time difference between the last scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 one-third of the sub-panel SPNL scan cycle. m can be 4. In this case, four gate drive circuits (GOA) can be used to achieve separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL. This makes the scan time difference between the last scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 one-quarter of the sub-panel SPNL scan cycle.

[0089] In one embodiment of this disclosure, each gate drive circuit (GOA) includes multiple shift registers (SR) cascaded sequentially. The j-th scan line (GL) in the i-th scan line group (GLS) is electrically connected to the i-th shift register (SR) of the j-th gate drive circuit (GOA); i is a positive integer, for example, i can be a positive integer such as 1, 2, 3, etc.; j is a positive integer between 1 and m, for example, j can be a positive integer such as 1, 2, 3, ..., m. The multiple gate drive circuits (GOA) on the sub-panel (SPNL) operate sequentially according to a preset order; wherein, the output terminal of the last shift register (SR) of the gate drive circuit (GOA) that operates first is connected to the input terminal of the first shift register (SR) of the gate drive circuit (GOA) that operates subsequently.

[0090] In one example, referring to Figures 9 and 10, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially arranged along the column direction. Both the first sub-panel SPNL1 and the second sub-panel SPNL2 have 180 scan lines GL, with the first sub-panel SPNL1 positioned above the second sub-panel SPNL2. The first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, both the first sub-panel SPNL1 and the second sub-panel SPNL2 have two gate drive circuits GOA. Each gate drive circuit GOA includes 90 cascaded shift registers SR, i.e., each gate drive circuit GOA includes a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90, all cascaded together. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS. Each scan line group GLS includes two sequentially adjacent scan lines GL; in other words, each scan line group GLS includes a first scan line GL1 and a second scan line GL2 that are sequentially adjacent. The two scan lines GL within the same scan line group GLS are driven by two gate drive circuits GOA. Specifically, in the first sub-panel SPNL1, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1, and the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2. Similarly, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1, and the second scan line GL2 in the second scan line group GLS is electrically connected to the second gate drive circuit GOA2. The second shift register SR2 of the gate drive circuit GOA2 is electrically connected. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1. The second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2. ... The first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the first gate drive circuit GOA1. The second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the second gate drive circuit GOA2.In the second sub-panel SPNL2, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3; the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4; the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3; and the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3; the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4; ..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the third gate drive circuit GOA3; and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the fourth gate drive circuit GOA4. This allows for separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL through two gate drive circuits GOA, ensuring that the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half the scanning cycle of the sub-panel SPNL. This helps to solve the screen tearing phenomenon in spliced ​​display panels PNL, thereby improving display quality.

[0091] In another example, referring to Figures 11 and 12, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially arranged along the column direction. Both the first sub-panel SPNL1 and the second sub-panel SPNL2 have 179 scan lines GL, with the first sub-panel SPNL1 positioned above the second sub-panel SPNL2. The first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, both the first sub-panel SPNL1 and the second sub-panel SPNL2 have two gate drive circuits GOA.Both the first gate drive circuit GOA1 and the third gate drive circuit GOA3 include 90 cascaded shift registers SR, namely, the first shift register SR1, the second shift register SR2, the third shift register SR3, ..., the 90th shift register SR90 are cascaded in sequence. Conversely, both the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 include 89 cascaded shift registers SR, namely, the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 include 89 cascaded shift registers SR, namely, the first shift register SR1, the second shift register SR2, the third shift register SR3, ..., the 90th shift register SR90 are cascaded in sequence. Register SR1, second shift register SR2, third shift register SR3, ..., eighty-ninth shift register SR89; the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS. The first 89 scan line groups GLS include two sequentially adjacent scan lines GL, in other words, the first 89 scan line groups GLS include a sequentially adjacent first scan line GL1 and a second scan line GL2; the 90th scan line group GLS includes one scan line GL, in other words, the 90th scan line group GLS includes the first scan line GL1; its In the first sub-panel SPNL1, except for the 90th scan line group GLS, the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA. In other words, in the first scan line group SPNL1, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2, and the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR1 of the first gate drive circuit GOA1. The register SR2 is electrically connected. The second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1. The second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2. ... The first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the first gate drive circuit GOA1.In the second sub-panel SPNL2, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3; the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4; the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3; the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4; the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3; the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4; ..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the third gate drive circuit GOA3. This allows for separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL through two gate drive circuits GOA, ensuring that the scanning time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the sub-panel SPNL scanning cycle. This helps to solve the screen tearing phenomenon of spliced ​​display panels PNL and improve display quality.

[0092] In one embodiment of this disclosure, the gate driving circuit GOA includes a plurality of shift registers SR cascaded in sequence; in two adjacent sub-panels SPNL, the input terminal of the first-stage shift register SR of the first reference gate driving circuit of the preceding sub-panel SPNL is electrically connected to the input terminal of the first-stage shift register SR of the second reference gate driving circuit of the following sub-panel SPNL; the first reference gate driving circuit of the sub-panel SPNL is the gate driving circuit GOA that drives the last scan line GL of the sub-panel SPNL; the second reference gate driving circuit of the sub-panel SPNL is the gate driving circuit GOA that drives the first scan line GL of the sub-panel SPNL.

[0093] In one example, the first reference gate driving circuit is the second gate driving circuit GOA2, and the second reference gate driving circuit is the third gate driving circuit GOA3. The input terminal of the first shift register SR1 of the second gate driving circuit GOA2 is electrically connected to the input terminal of the first shift register SR1 of the third gate driving circuit GOA3, so that the start signal of the second gate driving circuit GOA2 is multiplexed as the start signal of the third gate driving circuit GOA3. Compared with loading the start signal separately in the third gate driving circuit GOA3, the number of traces is reduced, thereby enabling the odd-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 to be scanned simultaneously, and the even-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 to be scanned simultaneously. This makes the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 half of the scanning cycle of the sub-panel SPNL, which helps to solve the screen tearing phenomenon of the splicing display panel PNL and improves the display quality.

[0094] In another example, the first reference gate driving circuit is the first gate driving circuit GOA1, and the second reference gate driving circuit is the third gate driving circuit GOA3. The input terminal of the first shift register SR1 of the first gate driving circuit GOA1 is electrically connected to the input terminal of the first shift register SR1 of the third gate driving circuit GOA3, so that the start signal of the first gate driving circuit GOA1 is multiplexed as the start signal of the third gate driving circuit GOA3. Compared with loading the start signal separately in the third gate driving circuit GOA3, the number of traces is reduced, so that the odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, and the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously. This makes the scanning time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 half of the scanning cycle of the sub-panel SPNL, which helps to solve the screen tearing phenomenon of the splicing display panel PNL and improves the display quality.

[0095] In one embodiment of this disclosure, referring to Figures 9 and 11, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially spliced ​​along the column direction; the first sub-panel SPNL1 has a first gate driving circuit GOA1 and a second gate driving circuit GOA2 for driving each of the scan lines GL; the first gate driving circuit GOA1 is used to drive the odd-numbered scan lines GL of the first sub-panel SPNL1, and the second gate driving circuit GOA2 is used to drive the even-numbered scan lines GL of the first sub-panel SPNL1; the second sub-panel SPNL2 has a third gate driving circuit GOA3 and a fourth gate driving circuit GOA4 for driving each of the scan lines GL; the third gate driving circuit GOA3 is used to drive the odd-numbered scan lines GL of the second sub-panel SPNL2, and the fourth gate driving circuit GOA4 is used to drive the even-numbered scan lines GL of the second sub-panel SPNL2.

[0096] In one example, referring to Figures 9 and 10, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially arranged along the column direction. Both the first sub-panel SPNL1 and the second sub-panel SPNL2 have 180 scan lines GL, with the first sub-panel SPNL1 located above the second sub-panel SPNL2. The first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS. Each scan line group GLS includes two sequentially adjacent scan lines GL; in other words, each scan line group GLS includes a sequentially adjacent first scan line GL1 and a sequentially adjacent second scan line GL2. Specifically, the two scan lines GL in the same scan line group GLS are driven by two gate driving circuits GOA respectively. That is, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate driving circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate driving circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the third gate driving circuit GOA3, and the second scan line GL2 in the same scan line group GLS is driven by the fourth gate driving circuit GOA4.

[0097] In another example, referring to Figures 11 and 12, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially arranged along the column direction. Both the first sub-panel SPNL1 and the second sub-panel SPNL2 have 179 scan lines GL, with the first sub-panel SPNL1 located above the second sub-panel SPNL2. The first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS. The first 89 scan line groups GLS include two sequentially adjacent scan lines GL; in other words, the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2, and the 90th scan line group GLS includes one scan line GL; in other words, the 90th scan line group GLS includes a first scan line GL1. Specifically, except for the 90th scan line group GLS, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the third gate drive circuit GOA3, and the second scan line GL2 in the same scan line group GLS is driven by the fourth gate drive circuit GOA4; while in the first sub-panel SPNL1, the first scan line GL1 in the 90th scan line group GLS is driven by the first gate drive circuit GOA1; and in the second sub-panel SPNL2, the first scan line GL1 in the 90th scan line group GLS is driven by the third gate drive circuit GOA3.

[0098] In one embodiment of this disclosure, the number of scan lines GL is an even number, for example, the number of scan lines GL can be 2, 4, 100, 180, etc. The start signal of the second gate drive circuit GOA2 of the first sub-panel SPNL1 is at the same time as the start signal of the third gate drive circuit GOA3 of the second sub-panel SPNL2.

[0099] In one example, referring to Figures 9 and 10, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially arranged along the column direction. Both the first sub-panel SPNL1 and the second sub-panel SPNL2 have 180 scan lines GL, with the first sub-panel SPNL1 positioned above the second sub-panel SPNL2. The first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, both the first sub-panel SPNL1 and the second sub-panel SPNL2 have two gate drive circuits GOA. Each gate drive circuit (GOA) includes 90 cascaded shift registers (SR), i.e., each gate drive circuit (GOA) includes a first shift register (SR1), a second shift register (SR2), a third shift register (SR3), ..., a ninetieth shift register (SR90) cascaded in sequence; the scan lines (GL) of the first sub-panel (SPNL1) and the second sub-panel (SPNL2) are each divided into 90 sequentially adjacent scan line groups (GLS). Each scan line group (GLS) includes two sequentially adjacent scan lines (GL), in other words, each scan line group (GLS) includes a sequentially adjacent first scan line (GL1) and a sequentially adjacent second scan line (GL2). In this configuration, two scan lines GL within the same scan line group GLS are driven by two separate gate drive circuits GOA. In other words, in the first sub-panel SPNL1, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1, and the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2. Similarly, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1, and the second scan line GL2 in the second scan line group GLS is electrically connected to the second... The second shift register SR2 of the gate drive circuit GOA2 is electrically connected. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1. The second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2. ... The first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the first gate drive circuit GOA1. The second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the second gate drive circuit GOA2.In the second sub-panel SPNL2, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3; the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4; the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3; and the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4, ..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the third gate drive circuit GOA3, and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the fourth gate drive circuit GOA4. The input terminal of the first shift register SR1 of the first gate drive circuit GOA1 is electrically connected to the input terminal of the first shift register SR1 of the fourth gate drive circuit GOA4, so that the first shift register SR1 of the first gate drive circuit GOA1 and the first shift register SR1 of the fourth gate drive circuit GOA4 are loaded with the start signal at the same time. This causes the odd-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 to be scanned simultaneously, taking half a scan cycle. Then, the even-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, which also takes half a scan cycle. In short, the scanning time difference from the 180th scan line GL of the first sub-panel SPNL1 to the first scan line GL of the second sub-panel SPNL2 is half a scan cycle. This allows for separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL through two gate drive circuits GOA, ensuring that the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the sub-panel SPNL scanning cycle. This helps to solve the screen tearing phenomenon of spliced ​​display panels PNL and improve display quality.

[0100] In another example, the even-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously. Then, the odd-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously. This allows the two gate drive circuits GOA to achieve separate scanning of the odd and even-numbered scan lines GL of the same sub-panel SPNL. This makes the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 half of the scanning cycle of the sub-panel SPNL. This helps to solve the screen tearing phenomenon of the spliced ​​display panel PNL and improve the display quality.

[0101] Referring to Figures 9 and 13, the input of the first shift register SR1 of the first gate driving circuit GOA1 is loaded with the first start signal GSTV1; the input of the first shift register SR1 of the second gate driving circuit GOA2 is loaded with the second start signal GSTV2; the input of the first shift register SR1 of the third gate driving circuit GOA3 is loaded with the second start signal GSTV2; and the input of the first shift register SR1 of the fourth gate driving circuit GOA4 is loaded with the first start signal GSTV1. The on-state of the first start signal GSTV1 begins 1 / 2 scan cycle earlier than the on-state of the second start signal GSTV2. In this embodiment, the on-state of both the first start signal GSTV1 and the second start signal GSTV2 is low, and the off-state is high. In other embodiments of this disclosure, the on-state of both the first start signal GSTV1 and the second start signal GSTV2 is high, and the off-state is low.

[0102] In one embodiment of this disclosure, the number of scan lines GL is odd; the start signal of the first gate drive circuit GOA1 of the first sub-panel SPNL1 is at the same time as the start signal of the third gate drive circuit GOA3 of the second sub-panel SPNL2.

[0103] In one example, referring to Figures 11 and 12, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially arranged along the column direction. Both the first sub-panel SPNL1 and the second sub-panel SPNL2 have 179 scan lines GL, with the first sub-panel SPNL1 positioned above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2. The second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, both the first sub-panel SPNL1 and the second sub-panel SPNL2 are provided with two gate drive circuits GOA. The first gate drive circuit GOA1 and the third gate drive circuit GOA3 each include 90 shift registers SR in sequence, that is, the first gate drive circuit GOA1 and the third gate drive circuit GOA3 each include the first shift register SR1, the second shift register SR2, the third shift register SR3, ..., the ninetieth shift register SR90 in sequence. The second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 each include 89 shift registers SR in sequence, that is, the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 each include the first shift register SR1, the second shift register SR2, the third shift register SR3, ..., the eighty-ninth shift register SR89 in sequence. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS. The first 89 scan line groups GLS include two sequentially adjacent scan lines GL. In other words, the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2 that are sequentially adjacent. The 90th scan line group GLS includes one scan line GL. In other words, the 90th scan line group GLS includes a first scan line GL1.Except for the 90th scan line group GLS, the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively. In other words, in the first sub-panel SPNL1, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1, and the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2. The first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1, and the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1, and the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2, and so on, until the first scan line GL1 in the 90th scan line group GLS is connected to the first scan line GL1. The first scan line GL1 in the first scan line group GLS is electrically connected to the 90th shift register SR90 of the first gate drive circuit GOA1; in the second sub-panel SPNL2, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3; the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4; the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3; the second scan line GL1... The second scan line GL2 in the GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4. The first scan line GL1 in the third scan line GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3. The second scan line GL2 in the third scan line GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4, and so on. The first scan line GL1 in the 90th scan line GLS is electrically connected to the 90th shift register SR90 of the third gate drive circuit GOA3. The input terminal of the first shift register SR1 of the first gate drive circuit GOA1 is electrically connected to the input terminal of the first shift register SR1 of the third gate drive circuit GOA3, so that the first shift register SR1 of the first gate drive circuit GOA1 and the first shift register SR1 of the third gate drive circuit GOA3 are loaded with the same start signal at the same time.The odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, consuming half a scan cycle. Then, the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, also consuming only half a scan cycle. In short, the scan time difference from the 179th scan line GL of the first sub-panel SPNL1 to the first scan line GL of the second sub-panel SPNL2 is half a scan cycle. This allows for separate scanning of the odd and even scan lines GL of the same sub-panel SPNL through two gate drive circuits GOA, ensuring that the scan time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half the scan cycle of the sub-panel SPNL. This helps to solve the screen tearing phenomenon in spliced ​​display panels PNL, thereby improving display quality.

[0104] In another example, the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously. Then, the odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously. This allows for separate scanning of the odd and even-numbered scan lines GL of the same sub-panel SPNL through two gate drive circuits GOA. This ensures that the scanning time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning cycle of the sub-panel SPNL. This helps to solve the screen tearing phenomenon of spliced ​​display panels PNL and improves display quality.

[0105] Referring to Figures 11 and 13, the input of the first shift register SR1 of the first gate driving circuit GOA1 is loaded with the first start signal GSTV1; the input of the first shift register SR1 of the second gate driving circuit GOA2 is loaded with the second start signal GSTV2; the input of the first shift register SR1 of the third gate driving circuit GOA3 is loaded with the first start signal GSTV1; and the input of the first shift register SR1 of the fourth gate driving circuit GOA4 is loaded with the second start signal GSTV2. The on-state of the first start signal GSTV1 begins 1 / 2 scan cycle earlier than the on-state of the second start signal GSTV2. In this embodiment, the on-state of both the first start signal GSTV1 and the second start signal GSTV2 is low, and the off-state is high. In other embodiments of this disclosure, the on-state of both the first start signal GSTV1 and the second start signal GSTV2 is high, and the off-state is low.

[0106] In one embodiment of this disclosure, the display panel PNL is a Mini LED display panel, a Micro LED display panel, an OLED display panel, a QLED display panel, or an LCD display panel. In one example, the display panel PNL is a Mini LED. In another example, the display panel PNL is a Micro LED.

[0107] In one embodiment of this disclosure, the sub-panel SPNL has light emission control traces that correspond one-to-one with each sub-pixel row. The light emission control traces are used to load light emission control signals EM to the pixel driving circuit PDC. Each of the light emission control traces is electrically connected to the others.

[0108] Specifically, referring to Figure 14, the on-state of the light emission control signal EM takes effect after all scan lines GL of all rows have been scanned. In other words, the on-state of the light emission control signal EM takes effect after all gate driving circuits GOA have been scanned. That is, the on-state of the light emission control signal EM takes effect after the first gate driving circuit GOA1, the second gate driving circuit GOA2, the third gate driving circuit GOA3, and the fourth gate driving circuit GOA4 have been scanned, so that each sub-pixel PIX emits light simultaneously. It should be noted that, in this embodiment, the first gate driving circuit GOA1, the second gate driving circuit GOA2, the third gate driving circuit GOA3, and the fourth gate driving circuit GOA4 shown in Figure 14 are the gate driving circuits GOA corresponding to the four sub-panels SPNL one-to-one. For example, the first sub-panel SPNL corresponds to the first gate drive circuit GOA1, the second sub-panel SPNL corresponds to the second gate drive circuit GOA2, the third sub-panel SPNL corresponds to the third gate drive circuit GOA3, and the fourth sub-panel SPNL corresponds to the fourth gate drive circuit GOA4. After all the gate drive circuits GOA of the entire display panel PNL have been scanned, the light emission control signal EM will simultaneously light up all the sub-pixels PIX of the display panel PNL. The on level of the light emission control signal EM is low, and the off level is high.

[0109] In one example, after the 180 scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are scanned, the conduction level of the light emission control signal EM is started, thereby illuminating all the sub-pixels PIX. In this way, there is no lighting time difference between the 180th row of the first sub-panel SPNL1 and the first row of the second sub-panel SPNL2, which can effectively solve the screen tearing phenomenon.

[0110] In another example, after the 179th scan line GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 is scanned, the conduction level of the light emission control signal EM is started, thereby illuminating all the sub-pixels PIX. In this way, there is no lighting time difference between the sub-pixels of the 179th row of the first sub-panel SPNL1 and the first row of the second sub-panel SPNL2, which can effectively solve the screen tearing phenomenon.

[0111] It should be noted that the method of controlling the PIX illumination time needs to be used when the scanning frequency is high, that is, when the display panel PNL is scanning quickly, such as a scanning frequency of 120Hz or 144Hz, to avoid the screen flickering that can be perceived by the human eye due to the excessively long off time of each sub-panel SPNL for each frame.

[0112] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel comprising at least two sub-panels sequentially joined along a column direction; Each of the sub-panels includes an array of sub-pixels and scan lines that correspond one-to-one with each row of sub-pixels; The sub-panel has multiple gate drive circuits for driving each of the scan lines; in, In two adjacent sub-panels, the start signal of the gate drive circuit electrically connected to the last row of scan lines of the preceding sub-panel is at the same time as the start signal of the gate drive circuit electrically connected to the first row of scan lines of the following sub-panel.

2. The display panel according to claim 1, wherein, The display panel includes two sub-panels.

3. The display panel according to claim 1, wherein, The sub-panel includes two gate drive circuits.

4. The display panel according to claim 1, wherein, The sub-panel is provided with m gate driving circuits; m is a positive integer greater than 1; The scan line is divided into multiple sequentially adjacent scan line groups, and each scan line group includes m sequentially adjacent scan lines. Each of the m scan lines in the same scan line group is driven by one of the m gate drive circuits.

5. The display panel according to claim 4, wherein, Each of the gate drive circuits includes multiple shift registers cascaded in sequence; The j-th scan line in the i-th scan line group is electrically connected to the i-th shift register of the j-th gate drive circuit; j is a positive integer between 1 and m.

6. The display panel according to claim 1, wherein, The gate drive circuit includes multiple shift registers cascaded in sequence; The first reference gate driving circuit of the sub-panel is a gate driving circuit that drives the last row of scan lines of the sub-panel; the second reference gate driving circuit of the sub-panel is a gate driving circuit that drives the first row of scan lines of the sub-panel. In two adjacent sub-panels, the input terminal of the first-stage shift register of the first reference gate drive circuit of the preceding sub-panel is connected to the second reference gate drive circuit of the following sub-panel. The input terminal of the first-stage shift register of the dynamic circuit is electrically connected.

7. The display panel according to claim 1, wherein, The display panel includes a first sub-panel and a second sub-panel that are sequentially spliced ​​along the column direction; The first sub-panel has a first gate driving circuit and a second gate driving circuit for driving each of the scan lines; the first gate driving circuit is used to drive the odd-numbered scan lines of the first sub-panel, and the second gate driving circuit is used to drive the even-numbered scan lines of the first sub-panel. The second sub-panel has a third gate driving circuit and a fourth gate driving circuit for driving each of the scan lines; the third gate driving circuit is used to drive the odd-numbered scan lines of the second sub-panel, and the fourth gate driving circuit is used to drive the even-numbered scan lines of the second sub-panel.

8. The display panel according to claim 7, wherein, The number of scan lines in the sub-panel is even; the start signal of the second gate driving circuit of the first sub-panel is at the same time as the start signal of the third gate driving circuit of the second sub-panel.

9. The display panel according to claim 7, wherein, The number of scan lines in the sub-panel is odd; the start signal of the first gate driving circuit of the first sub-panel is at the same time as the start signal of the third gate driving circuit of the second sub-panel.

10. The display panel according to any one of claims 8 to 9, wherein, The start time of the start signal of the first gate driving circuit is one-half a scan cycle earlier than the start time of the start signal of the second gate driving circuit.

11. The display panel according to any one of claims 1 to 9, wherein, The sub-panel has light emission control traces that correspond one-to-one with each sub-pixel row, and the light emission control traces are used to load light emission control signals to the pixel driving circuit. All of the aforementioned light-emitting control traces are electrically connected to each other.

12. The display panel according to any one of claims 1 to 9, wherein, The display panel is a Mini LED display panel, a Micro LED display panel, an OLED display panel, a QLED display panel, or an LCD display panel.

13. A display device, wherein, Includes the display panel as described in any one of claims 1 to 12.

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